TLV62065 www.ti.com SLVSAC4 – NOVEMBER 2010 3-MHz 2A Step Down Converter in 2x2 SON Package Check for Samples: TLV62065 FEATURES 1 • • • • • • • • • 2 DESCRIPTION VIN Range from 2.9V to 5.5V Up to 97% Efficiency Power Save Mode / 3MHz Fixed PWM Mode Output Voltage Accuracy in PWM Mode ±2.0% Output Capacitor Discharge Function Typical 18 µA Quiescent Current 100% Duty Cycle for Lowest Dropout For Improved Feature Set See TPS62065 Available in a 2x2x0.75mm SON The TLV62065 is a high efficient synchronous step down DC-DC converter. It provides up to 2.0A output current. With an input voltage range of 2.9V to 5.5V the device is a perfect fit for power conversion from a 5V or 3.3V system supply rail. The TLV62065 operates at 3MHz fixed frequency and enters Power Save Mode operation at light load currents to maintain high efficiency over the entire load current range. For low noise applications, TLV62065 can be forced into fixed frequency PWM mode by pulling the MODE pin high. APPLICATIONS • • • • In the shutdown mode, the current consumption is reduced to less than 1µA and an internal circuit discharges the output capacitor. Point Of Load (POL) Notebooks, Pocket PCs Portable Media Players Set Top Box TLV62065 operates with a 1.0µH inductor and 10µF output capacitor. The TLV62065 is available in a small 2x2x0.75mm 8pin SON package. 100 TYPICAL APPLICATION CIRCUIT VIN = 3.7 V 95 90 TLV62065 PVIN L 1.0 mH SW AVIN CIN 10 mF EN MODE AGND PGND VOUT 1.8 V 2 A R1 360 kW FB R2 180 kW Cff 22 pF COUT 10 mF VIN = 4.2 V 85 Efficiency - % VIN = 2.9 V to 5.5 V VIN = 5 V 80 75 70 65 L = 1.2 mH (NRG4026T 1R2), COUT = 22 mF (0603 size), VOUT = 3.3 V, Mode: Auto PFM/PWM 60 55 50 0 0.25 0.5 0.75 1 1.25 1.5 IL - Load Current - A 1.75 2 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TLV62065 SLVSAC4 – NOVEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) PART NUMBER OUTPUT VOLTAGE MAXIMUM OUTPUT CURRENT PACKAGE DESIGNATOR ORDERING (2) PACKAGE MARKING TLV62065 Adjustable 2.0 A DSG TLV62065DSG QVB For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The DSG (SON-8) packages is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Voltage Range (2) AVIN, PVIN EN, MODE, FB SW Current (source) UNIT MIN MAX –0.3 7 –0.3 to VIN +0.3 < 7 –0.3 7 Peak output Internally limited A Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A) (3) 2 Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01) 1 Electrostatic Discharge (Machine model) Temperature (1) (2) (3) V kV 200 V TJ –40 125 °C Tstg –65 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin. THERMAL INFORMATION TLV62065 THERMAL METRIC (1) DSG UNITS 8 PINS qJA Junction-to-ambient thermal resistance 65.2 qJC(top) Junction-to-case(top) thermal resistance 93.3 qJB Junction-to-board thermal resistance 30.1 yJT Junction-to-top characterization parameter 0.5 yJB Junction-to-board characterization parameter 47.4 qJC(bottom) Junction-to-case(bottom) thermal resistance 7.2 (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 TLV62065 www.ti.com SLVSAC4 – NOVEMBER 2010 RECOMMENDED OPERATING CONDITIONS MIN AVIN , PVIN Supply voltage NOM 2.9 MAX 5.5 Output current capability 2000 UNIT V mA Output voltage range for adjustable voltage 0.8 VIN V L Effective Inductance Range 0.7 1.0 1.6 µH COUT Effective Output Capacitance Range 4.5 10 22 µF –40 85 °C –40 125 °C TA Operating ambient temperature TJ Operating junction temperature (1) (1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (qJA), as given by the following equation: TA(max)= TJ(max)–(qJA X PD(max)) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 3 TLV62065 SLVSAC4 – NOVEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for condition VIN = EN = 3.6V. External components CIN = 10mF 0603, COUT = 10mF 0603, L = 1.0mH, see the parameter measurement information. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input voltage range 2.9 IQ Operating quiescent current IOUT = 0 mA, device operating in PFM mode and not device not switching ISD Shutdown current EN = GND, current into AVIN and PVIN combined VUVLO Undervoltage lockout threshold 5.5 18 V mA 0.1 1 Falling 1.73 1.78 1.83 Rising 1.9 1.95 1.99 mA V ENABLE, MODE VIH High level input voltage 2.9V ≤ VIN ≤ 5.5V 1.0 5.5 V VIL Low level input voltage 2.9V ≤ VIN ≤ 5.5V 0 0.4 V IIN Input bias current EN, Mode tied to GND or AVIN 0.01 1 mA POWER SWITCH VIN = 3.6V (1) 120 180 (1) 95 150 VIN = 3.6V (1) 90 130 VIN = 5.0V (1) 75 100 RDS(on) High-side MOSFET on-resistance RDS(on) Low-side MOSFET on-resistance ILIMF Forward current limit MOSFET high-side and low-side 3V ≤ VIN ≤ 3.6V Thermal shutdown Increasing junction temperature 150 Thermal shutdown hysteresis Decreasing junction temperature 10 TSD VIN = 5.0V 2300 2750 mΩ mΩ mA °C OSCILLATOR fSW Oscillator frequency 2.9V ≤ VIN ≤ 5.5V 2.6 3 3.4 MHz OUTPUT Vref Reference voltage VFB(PWM) Feedback voltage PWM Mode VFB(PFM) Feedback voltage PFM mode, Voltage Positioning 600 PWM operation, MODE = VIN , 2.9V ≤ VIN ≤ 5.5V, 0 mA load –2.0 1 -0.5 %/A 0 %/V Line regulation R(Discharge) Internal discharge resistor Activated with EN = GND, 2.9V ≤ VIN≤ 5.5V, 0.8 ≤ VOUT≤ 3.6V 200 tSTART Start-up time Time from active EN to reach 95% of VOUT 500 (1) (2) 4 2.0 % device in PFM mode, voltage positioning active (2) Load regulation VFB 0 mV Ω ms Maximum value applies for TJ = 85°C In PFM mode, the internal reference voltage is set to typ. 1.01×Vref. See the parameter measurement information. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 TLV62065 www.ti.com SLVSAC4 – NOVEMBER 2010 PIN ASSIGNMENTS TERMINAL FUNCTIONS TERMINAL NO. SON 2x2-8 I/O PGND 1 PWR GND supply pin for the output stage. SW 2 OUT This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor between this terminal and the output capacitor. AGND 3 IN Analog GND supply pin for the control circuit. FB 4 IN Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin. In case of fixed output voltage option, connect this pin directly to the output capacitor EN 5 IN This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling this pin to high enables the device. This pin must be terminated MODE 6 IN MODE pin = high forces the device to operate in fixed frequency PWM mode. MODE pin = low enables the Power Save Mode with automatic transition from PFM mode to fixed frequency PWM mode. This pin must be terminated. AVIN 7 IN Analog VIN power supply for the control circuit. Need to be connected to PVIN and input capacitor. PVIN 8 PWR NAME Power PAD DESCRIPTION VIN power supply pin for the output stage. For good thermal performance, this PAD must be soldered to the land pattern on the pcb. This PAD should be used as device GND. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 5 TLV62065 SLVSAC4 – NOVEMBER 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM AVIN PVIN Current Limit Comparator Undervoltage Lockout 1.8V Thermal Shutdown Limit High Side PFM Comparator Reference 0.6V VREF FB VREF Softstart VOUT RAMP CONTROL Gate Driver Anti Shoot-Through Control Stage Error Amp. VREF SW Integrator FB Zero-Pole AMP. PWM Comp. Limit Low Side Sawtooth Generator 3MHz Clock Current Limit Comparator MODE RDischarge EN AGND PGND Vertical spacer Vertical spacer PARAMETER MEASUREMENT INFORMATION VIN = 2.9 V to 5.5 V PVIN CIN 10 µF L 1.0 µH/1.2 µH TLV62065 AVIN EN MODE SW R1 FB AGND PGND Cff VOUT up to 2.0 A COUT 10 µF R2 L: LQH44PN1R0NP0, L = 1.0 mH,Murata, NRG4026T1R2, L = 1.2 mH, Taiyo Yuden CIN/COUT: GRM188R60J106U, Murata 0603 size 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 TLV62065 www.ti.com SLVSAC4 – NOVEMBER 2010 TYPICAL CHARACTERISTICS Table 1. Table of Graphs FIGURE h Efficiency Output Voltage Accuracy Load Current, VOUT = 1.2 V, Auto PF//PWM Mode, Linear Scale Figure 1 Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode, Linear Scale Figure 2 Load Current, VOUT = 3.3 V, PFM/PWM Mode, Linear Scale Figure 3 Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode vs. Forced PWM Mode, Logarithmic Scale Figure 4 Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode Figure 5 Load Current, VOUT = 1.8 V, Forced PWM Mode Figure 6 Shutdown Current Input Voltage and Ambient Temperature Figure 7 Quiescent Current Input Voltage Figure 8 Oscillator Frequency Input Voltage Figure 9 Static Drain-Source On-State Resistance Input Voltage, Low-Side Switch Figure 10 Input Voltage, High-Side Switch Figure 11 RDISCHARGE Input Voltage vs. VOUT Figure 12 PWM Mode, VIN = 3.6 V, VOUT = 1.8 V, 500 mA, L = 1.2 mH, COUT = 10mF Figure 13 PFM Mode, VIN = 3.6 V, VOUT = 1.8 V, 20 mA, L = 1.2 mH, COUT = 10mF Figure 14 PWM Mode, VIN = 3.6 V, VOUT = 1.2 V, 0.2 mA to 1 A Figure 15 PFM Mode, VIN = 3.6 V, VOUT = 1.2 V, 20 mA to 250 mA Figure 16 VIN = 3.6 V, VOUT = 1.8 V, 200 mA to 1500 mA Figure 17 PWM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA Figure 18 Typical Operation Load Transient Line Transient PFM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA Figure 19 Startup into Load VIN = 3.6 V, VOUT = 1.8 V, Load = 2.2-Ω Figure 20 Output Discharge VIN = 3.6 V, VOUT = 1.8 V, No Load Figure 21 EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 100 100 95 95 90 80 VIN = 3 V 75 VIN = 3.3 V VIN = 3.6 V 70 VIN = 5 V 85 VIN = 4.2 V Efficiency - % Efficiency - % 85 65 VIN = 3 V 80 VIN = 3.3 V 75 VIN = 3.6 V 70 65 L = 1.2 mH (NRG4026T 1R2), COUT = 10 mF (0603 size), VOUT = 1.2 V, Mode: Auto PFM/PWM 60 55 50 0 VIN = 4.2 V 90 VIN = 5 V 0.25 0.5 0.75 1 1.25 1.5 IL - Load Current - A 1.75 Figure 1. VOUT = 1.2V, Auto PFM/PWM Mode, Linear Scale L = 1.2 mH (NRG4026T 1R2), COUT = 10 mF (0603 size), VOUT = 1.8 V, Mode: Auto PFM/PWM 60 55 2 50 0 0.25 0.5 0.75 1 1.25 1.5 IL - Load Current - A 1.75 2 Figure 2. VOUT = 1.8V, Auto PFM/PWM Mode, Linear Scale Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 7 TLV62065 SLVSAC4 – NOVEMBER 2010 www.ti.com EFFICIENCY vs LOAD CURRENT 100 EFFICIENCY vs LOAD CURRENT 100 VIN = 3.7 V Auto PFM/PWM Mode 95 90 90 VIN = 4.2 V 80 VIN = 5 V 70 Efficiency - % Efficiency - % 85 80 75 70 L = 1.2 mH (NRG4026T 1R2), COUT = 22 mF (0603 size), VOUT = 3.3 V, Mode: Auto PFM/PWM 60 55 VIN = 3.3 V VIN = 3.6 V VIN = 4.2 V VIN = 5 V 50 40 0.25 0.5 0.75 1 1.25 1.5 IL - Load Current - A 1.75 20 0 0.001 2 0.01 0.1 IL - Load Current - A 1 10 Figure 3. VOUT = 3.3V, Auto PFM/PWM Mode, Linear Scale Figure 4. Auto PFM/PWM Mode vs. Forced PWM Mode, Logarithmic Scale OUTPUT VOLTAGE ACCURACY vs LOAD CURRENT OUTPUT VOLTAGE ACCURACY vs LOAD CURRENT 1.890 1.890 1.872 1.872 1.854 Voltage Positioning PFM Mode 1.854 1.836 1.818 PWM Mode VIN = 3.3 V 1.800 VIN = 3.6 V VIN = 4.2 V 1.782 1.764 L = 1.2 mH (NRG4026T 1R2), COUT = 10 mF (0603 size), VOUT = 1.8 V 10 VO - Output Voltage DC - V VO - Output Voltage DC - V 0 VIN = 5 V L = 1 mH, COUT = 10 mF, VOUT = 1.8 V, Mode: Auto PFM/PWM 1.746 1.728 1.710 0.001 0.01 0.1 IL - Load Current - A 1 L = 1 mH, COUT = 10 mF, VOUT = 1.8 V, Mode: Forced PWM 1.836 1.818 1.800 VIN = 3.3 V 1.782 VIN = 3.6 V VIN = 4.2 V 1.764 VIN = 5 V 1.746 1.728 10 1.710 0.001 Figure 5. Auto PFM/PWM Mode 8 Forced PWM Mode 60 30 65 50 VIN = 3.3 V VIN = 3.6 V VIN = 4.2 V VIN = 5 V Submit Documentation Feedback 0.01 0.1 IL - Load Current - A 1 10 Figure 6. Forced PWM Mode Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 TLV62065 www.ti.com SLVSAC4 – NOVEMBER 2010 SHUTDOWN CURRENT vs INPUT VOLTAGE AND AMBIENT TEMPERATURE QUIESCENT CURRENT vs INPUT VOLTAGE 25 TA = 85°C TA = 85°C 20 0.75 Iq - Quiesent Current - mA ISHDN - Shutdown Current - mA 1 0.50 TA = 25°C 0.25 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 TA = -40°C 10 0 2.5 6 3 3.5 4 4.5 5 VI - Input Voltage - V 6 Figure 8. OSCILLATOR FREQUENCY vs INPUT VOLTAGE STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE 0.12 TA = 85°C 3.05 0.1 TJ = 85°C TA = 25°C TJ = 25°C 3 RDSON - W 0.08 2.95 TA = -40°C 0.04 2.85 0.02 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 TJ = -40°C 0.06 2.9 2.8 2.5 5.5 Figure 7. 3.1 fOSC - Oscillator Frequency - MHz 15 5 TA = -40°C 0 2.5 TA = 25°C 0 2.5 Figure 9. 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 Figure 10. Low-Side Switch Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 9 TLV62065 SLVSAC4 – NOVEMBER 2010 www.ti.com STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE RDISCHARGE vs INPUT VOLTAGE 0.2 600 0.18 500 0.16 400 TJ = 25°C 0.12 RDischarge - W RDSON - W VO = 3.3 V TJ = 85°C 0.14 TJ = -40°C 0.1 0.08 VO = 1.8 V 300 200 0.06 VO = 1.2 V 0.04 100 0.02 0 2.5 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 0 2.5 3 Figure 11. High-Side Switch 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 Figure 12. VOUT 50mV/Div VOUT 50mV/Div VIN = 3.6 V VOUT = 1.8 V IOUT = 20 mA MODE = GND L = 1.2 mH COUT = 10 mF SW 2V/Div SW 2V/Div ICOIL 500mA/Div MODE = GND VIN = 3.6 V L = 1.2 mH VOUT = 1.8 V IOUT = 500 mA COUT = 10 mF ICOIL 200mA/Div Time Base - 4ms/Div Time Base - 100ns/Div Figure 13. Typical Operation (PWM Mode) 10 Figure 14. Typical Operation (PFM Mode) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 TLV62065 www.ti.com SLVSAC4 – NOVEMBER 2010 VOUT100 mV/Div VOUT100 mV/Div SW 2V/Div SW 2V/Div ICOIL1A/Div ICOIL1A/Div VIN = 3.6 V, VOUT = 1.2 V, IOUT = 0.2 A to 1 A MODE = VIN ILOAD500 mA/Div VIN = 3.6 V, VOUT = 1.2 V, IOUT = 20 mA to 250 mA ILOAD500 mA/Div Time Base - 10 µs/Div Time Base - 10 µs/Div Figure 15. Load Transient Response PWM Mode 0.2A To 1A Figure 16. Load Transient PFM Mode 20 mA to 250mA VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, IOUT = 500 mA L = 1.2 mH, 200 mV/Div 500 mV/Div 2A/Div VIN = 3.6 V, VOUT = 1.8 V, 1A/Div 50 mV/Div L = 1.2 mH COUT = 10 mF IOUT 200 mA to 1500 mA Time Base - 100 ms/Div Time Base - 100ms/Div Figure 17. Load Transient Response 200 mA To 1500 mA Figure 18. Line Transient Response PWM Mode Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 11 TLV62065 SLVSAC4 – NOVEMBER 2010 www.ti.com 2 V/Div 500 mV/Div 1 V/Div 2 A/Div 500 mA/Div VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, IOUT = 50 mA, 50 mV/Div L = 1.2 mH, COUT = 10 mF 500 mA/Div Time Base - 100 ms/Div Time Base - 100 ms/Div Figure 19. Line Transient PFM Mode EN 1 V/Div VIN = 3.6 V, L = 1.2 mH, VOUT = 1.8 V, COUT = 10 mF Load = 2R2 Figure 20. Startup Into Load – VOUT 1.8V VIN = 3.6 V, VOUT = 1.8 V, COUT = 10 mF, No Load SW 2 V/Div VOUT 1 V/Div Time Base - 2ms/Div Figure 21. Output Discharge 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 TLV62065 www.ti.com SLVSAC4 – NOVEMBER 2010 DETAILED DESCRIPTION OPERATION The TLV62065 step down converter operates with typically 3MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the converter can automatically enter Power Save Mode and operates then in PFM (Pulse Frequency Mode) mode. During PWM operation the converter use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the High Side MOSFET switch is turned on. The current flows now from the input capacitor via the High Side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic will turn off the switch. The current limit comparator will also turn off the switch in case the current limit of the High Side MOSFET switch is exceeded. After a dead time preventing shoot through current, the Low Side MOSFET rectifier is turned on and the inductor current ramps down. The current flows now from the inductor to the output capacitor and to the load. It returns back to the inductor through the Low Side MOSFET rectifier. The next cycle will be initiated by the clock signal again turning off the Low Side MOSFET rectifier and turning on the High Side MOSFET switch. POWER SAVE MODE At TLV62065 pulling the Mode pin low enables Power Save Mode. If the load current decreases, the converter enters Power Save Mode operation automatically. During Power Save Mode the converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage typically +1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The transition from PWM mode to PFM mode occurs once the inductor current in the Low Side MOSFET switch becomes zero, which indicates discontinuous conduction mode. During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUTnominal +1%, the device starts a PFM current pulse. For this the High Side MOSFET switch will turn on and the inductor current ramps up. After the On-time expires the switch will be turned off and the Low Side MOSFET switch will be turned on until the inductor current becomes zero. The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered current the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold, the device stops switching and enters a sleep mode with typ. 18µA current consumption. In case the output voltage is still below the PFM comparator threshold, further PFM current pulses will be generated until the PFM comparator threshold is reached. The converter starts switching again once the output voltage drops below the PFM comparator threshold due to the load current. The PFM mode is exited and PWM mode entered in case the output current can no longer be supported in PFM mode. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 13 TLV62065 SLVSAC4 – NOVEMBER 2010 www.ti.com Output voltage Voltage Positioning Vout +1% PFM Comparator threshold Light load PFM Mode Vout (PWM) moderate to heavy load PWM Mode Figure 22. Power Save Mode Operation with automatic Mode transition 100% Duty Cycle Low Dropout Operation The device starts to enter 100% duty cycle mode as the input voltage comes close to the nominal output voltage. In order to maintain the output voltage, the High-Side MOSFET switch is turned on 100% for one or more cycles. With further decreasing VIN the High-Side MOSFET switch is turned on completely. In this case the converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: VINmin = VOmax + IOmax × (RDS(on)max + RL) With: IOmax = maximum output current RDS(on)max = maximum P-channel switch RDS(on). RL = DC resistance of the inductor VOmax = nominal output voltage plus maximum output voltage tolerance Undervoltage Lockout The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the output stage of the converter once the falling VIN trips the under-voltage lockout threshold VUVLO. The under-voltage lockout threshold VUVLO for falling VIN is typically 1.78V. The device starts operation once the rising VIN trips under-voltage lockout threshold VUVLO again at typically 1.95V. Output Capacitor Discharge With EN = GND, the device enters shutdown mode and all internal circuits are disabled. The SW pin is connected to PGND via an internal resistor to discharge the output capacitor. This feature ensures a startup in a discharged output capacitor once the converter is enabled again and prevents "floating" charge on the output capacitor. The output voltage ramps up monotonic starting from 0V. MODE SELECTION The MODE pin allows mode selection between forced PWM mode and Power Save Mode. 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 TLV62065 www.ti.com SLVSAC4 – NOVEMBER 2010 Connecting this pin to GND enables the Power Save Mode with automatic transition between PWM and PFM mode. Pulling the MODE pin high forces the converter to operate in fixed frequency PWM mode even at light load currents. This allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads. The condition of the MODE pin can be changed during operation and allows efficient power management by adjusting the operation mode of the converter to the specific system requirements. ENABLE The device is enabled by setting EN pin to high. At first, the internal reference is activated and the internal analog circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output voltages reaches 95% of its nominal value within tSTARTof typically 500 µs after the device has been enabled. The EN input can be used to control power sequencing in a system with various DC/DC converters. The EN pin can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply rails. With EN = GND, the device enters shutdown mode. In this mode, all circuits are disabled and the SW pin is connected to PGND via an internal resistor to discharge the output. SOFT START The TLV62065 has an internal soft start circuit that controls the ramp up of the output voltage. Once the converter is enabled and the input voltage is above the undervoltage lockout threshold VUVLOthe output voltage ramps up from 5% to 95% of its nominal value within tRamp of typ. 250µs. This limits the inrush current in the converter during start up and prevents possible input voltage drops when a battery or high impedance power source is used. During soft start, the switch current limit is reduced to 1/3 of its nominal value ILIMF until the output voltage reaches 1/3 of its nominal value. Once the output voltage trips this threshold, the device operates with its nominal current limit ILIMF. INTERNAL CURRENT LIMIT / FOLD-BACK CURRENT LIMIT FOR SHORT-CIRCUIT PROTECTION During normal operation the High-Side and Low-Side MOSFET switches are protected by its current limits ILIMF. Once the High-Side MOSFET switch reaches its current limit, it is turned off and the Low-Side MOSFET switch is turned on. The High-Side MOSFET switch can only turn on again, once the current in the Low -Side MOSFET switch decreases below its current limit ILIMF. The device is capable to provide peak inductor currents up to its internal current limit ILIMF.. As soon as the switch current limits are hit and the output voltage falls below 1/3 of the nominal output voltage due to overload or short circuit condition, the foldback current limit is enabled. In this case the switch current limit is reduced to 1/3 of the nominal value ILIMF. Due to the short-circuit protection is enabled during start-up, the device does not deliver more than 1/3 of its nominal current limit ILIMF until the output voltage exceeds 1/3 of the nominal output voltage. This needs to be considered when a load is connected to the output of the converter, which acts as a current sink. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this mode, the High-Side and Low-Side MOSFETs are turned off. The device continues its operation with a softstart once the junction temperature falls below the thermal shutdown hysteresis. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 15 TLV62065 SLVSAC4 – NOVEMBER 2010 www.ti.com APPLICATION INFORMATION VIN = 2.9 V to 5.5 V TLV62065 PVIN CIN 10 µF VOUT = 1.8 V up to 2 A SW R1 360 kΩ AVIN EN MODE AGND PGND L 1.0 mH FB Cff 22 pF COUT 10 µF R2 180 kΩ Figure 23. TLV62065 1.8V Adjustable Output Voltage Configuration OUTPUT VOLTAGE SETTING The output voltage can be calculated to: V OUT + VREF ǒ R 1) 1 R2 Ǔ with an internal reference voltage VREF typically 0.6V. To minimize the current through the feedback divider network, R2 should be within the range of 120 kΩ to 360 kΩ. The sum of R1 and R2 should not exceed ~1MΩ, to keep the network robust against noise. An external feedforward capacitor Cff is required for optimum regulation performance. Lower resistor values can be used. R1 and Cff places a zero in the loop. The right value for Cff can be calculated as: fc = 1 = 35kHz 2 ´ p ´ R2 ´ Cff Cff = 16 1 2 ´ p ´ R2 ´ 35kHz Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 TLV62065 www.ti.com SLVSAC4 – NOVEMBER 2010 OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) The internal compensation network of TLV62065 is optimized for a LC output filter with a corner frequency of: fc = 1 2 ´ p ´ (1μH ´ 10μF) = 50kHz The part operates with nominal inductors of 1.0µH to 1.2 µH and with 10µF to 22µF small X5R and X7R ceramic capacitors. Please refer to the lists of inductors and capacitors. The part is optimized for a 1.0µH inductor and 10µF output capacitor. Inductor Selection The inductor value has a direct effect on the ripple current. The selected inductor has to be rated for its dc resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO. Equation 1 calculates the maximum inductor current in PWM mode under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 2. This is recommended because during heavy load transient the inductor current rises above the calculated value. DI L + Vout 1 * Vout Vin L I Lmax + I outmax ) ƒ (1) DI L 2 (2) With: f = Switching Frequency (3MHz typical) L = Inductor Value ΔIL = Peak-to-Peak inductor ripple current ILmax = Maximum Inductor current A more conservative approach is to select the inductor current rating just for the switch current limit ILIMFof the converter. The total losses of the coil have a strong impact on the efficiency of the DC/DC conversion and consist of both the losses in the dc resistance R(DC) and the following frequency-dependent components: • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) • Additional losses in the conductor from the skin effect (current displacement at high frequencies) • Magnetic field losses of the neighboring windings (proximity effect) • Radiation losses Table 2. List of Inductors 3 DIMENSIONS [mm ] INDUCTANCE mH INDUCTOR TYPE SUPPLIER 3.2 x 2.5 x 1.0 max 1.0 LQM32PN (MLCC) Murata 3.7 x 4 x 1.8 max 1.0 LQH44 (wire wound) Murata 4.0 x 4.0 x 2.6 max 1.2 NRG4026T (wire wound) Taiyo Yuden 3.5 x 3.7 x 1.8 max 1.2 DE3518 (wire wound) TOKO Output Capacitor Selection The advanced fast-response voltage mode control scheme of the TLV62065 allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies and may not be used. For most applications a nominal 10µF or 22µF capacitor is suitable. At small ceramic capacitors, the DC-bias effect decreases the effective capacitance. Therefore a 22µF capacitor can be used for output voltages higher than 2V, see list of capacitors. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 17 TLV62065 SLVSAC4 – NOVEMBER 2010 www.ti.com In case additional ceramic capacitors in the supplied system are connected to the output of the DC/DC converter, the output capacitor COUT need to be decreased in order not to exceed the recommended effective capacitance range. In this case a loop stability analysis must be performed as described later. At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as: I RMSCout + Vout 1 * Vout 1 Vin L ƒ 2 Ǹ3 (3) Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications a 10µF ceramic capacitor is recommended. The input capacitor can be increased without any limit for better input voltage filtering. Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on the input can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings. Table 3. List of Capacitors TYPE SIZE [ mm3] SUPPLIER 10mF GRM188R60J106M 0603: 1.6 x 0.8 x 0.8 Murata 22mF GRM188R60G226M 0603: 1.6 x 0.8 x 0.8 Murata 22µF CL10A226MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung 10µF CL10A106MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung CAPACITANCE CHECKING LOOP STABILITY The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signal • Switching node, SW • Inductor current, IL • Output ripple voltage, VOUT(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or wrong L-C output filter combinations. As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge CO generating a feedback error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted when the device operates in PWM mode at medium to high load currents. During this recovery time, VOUT can be monitored for settling time, overshoot, or ringing; that helps evaluate stability of the converter. Without any ringing, the loop has usually more than 45° of phase margin. 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 TLV62065 www.ti.com SLVSAC4 – NOVEMBER 2010 Mode Enable LAYOUT CONSIDERATIONS VIN GND CIN COUT R2 R1 CFF GND L VOUT Figure 24. PCB Layout As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as EMI and thermal problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Connect the AGND and PGND Pins of the device to the PowerPAD™ land of the PCB and use this pad as a star point. Use a common Power PGND node and a different node for the Signal AGND to minimize the effects of ground noise. The FB divider network should be connected right to the output capacitor and the FB line must be routed away from noisy components and traces (e.g., SW line). Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. For good thermal performance a four or more Layer PCB design is recommended. The PowerPAD of the IC must be soldered on the power pad area on the PCB to achieve proper thermal connection. Additionally, for good thermal performance, the PowerPAD on the PCB needs to be connected to an inner GND plane with sufficient via connections. See the documentation of the evaluation kit. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TLV62065 19 PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TLV62065DSGR ACTIVE WSON DSG 8 3000 TBD Call TI Call TI Purchase Samples TLV62065DSGT ACTIVE WSON DSG 8 250 TBD Call TI Call TI Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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