TI TPS62650-Q1

CSP-9
TPS62650-Q1
www.ti.com
SLVSB62A – MARCH 2012 – REVISED MARCH 2012
800-mA, 6-MHz High-Efficiency Step-Down Converter
With I2C™ Compatible Interface in Chip-Scale Packaging
Check for Samples: TPS62650-Q1
FEATURES
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APPLICATIONS
1
23
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Qualified for Automotive Applications
AEC-Q100 Qualified with the Following
Results:
– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
86% Efficiency at 6-MHz Operation
38-μA Quiescent Current
Wide VIN Range From 2.3 V to 5.5 V
6MHz Regulated Frequency Operation
Best-In-Class Load and Line Transient
±2% PWM DC Voltage Accuracy
Automatic PFM/PWM Mode Switching
Low-Ripple Light-Load PFM
I2C Compatible Interface up to 3.4 Mbps
Pin-Selectable Output Voltage (VSEL)
Internal Soft-Start, <150-μs Start-Up Time
Current Overload and Thermal Shutdown
Protection
Three Surface-Mount External Components
Required (One MLCC Inductor, Two Ceramic
Capacitors)
Complete Sub 1-mm Component Profile
Solution
Total Solution Size <13 mm2
•
•
•
•
Available in a 9-Pin NanoFree™ (CSP) Package
SmartReflex™ Compliant Power Supply
OMAP™ Application Processor Core Supply
Cell Phones, Smart-Phones
Micro DC-DC Converter Modules
DESCRIPTION
The TPS62650-Q1 device is a high-frequency
synchronous step-down dc-dc converter optimized for
battery-powered portable applications. Intended for
low-power applications, the TPS62650-Q1 supports
up to 800mA load current and allows the use of
small, low cost inductors and capacitors.
The device is ideal for mobile phones and similar
portable applications powered by a single-cell Li-Ion
battery. With an output voltage range adjustable via
I2C interface down to 0.75V, the device supports lowvoltage DSPs and processors core power supplies in
smart-phones and handheld computers.
The TPS62650-Q1 operates at a regulated 6MHz
switching frequency and enters the efficiency
optimized power-save mode operation at light load
currents to maintain high efficiency over the entire
load current range. In the shutdown mode, the
current consumption is reduced to less than 3.5μA.
Description continued on next page.
spacer
spacer
spacer
100
TPS62650
C1
2.3 V .. 5.5 V
FB
SW
4.7mF
GND
VO
L1
0.47 mH
EN
VO = Roof
VO = Floor
I2C Bus
up to 3.4 Mbips
VSEL
SDA
SCL
Figure 1. Typical Application
C2
4.7mF
Efficiency − %
VIN
VI
90
80
70
60
50
40
30
20
10
0
VO = 1.2V
VI = 2.7V
PFM/PWM Operation
VI = 3.6V
PFM/PWM Operation
VI = 4.2V
PFM/PWM Operation
0.1
VI = 3.6V
Forced PWM Operation
1
10
100
IO − Load Current − mA
1000
Figure 2. Efficiency vs Load Control
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree, SmartReflex, OMAP are trademarks of Texas Instruments.
I2C is a trademark of Philips Semiconductors.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS62650-Q1
SLVSB62A – MARCH 2012 – REVISED MARCH 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
spacer
The serial interface is compatible with Standard, Fast/Fast Plus and High-Speed mode I2C specification allowing
transfers at up to 3.4 Mbps. This communication interface is used for dynamic voltage scaling with voltage steps
down to 12.5mV, for setting the output voltage or reprogramming the mode of operation (PFM/PWM or Forced
PWM) for instance.
ORDERING INFORMATION
(1)
PART
NUMBER
OUTPUT VOLTAGE
RANGE
TPS62650Q1 (1)
0.75 V to 1.4375 V
DEFAULT
OUTPUT VOLTAGE
I2C ADDRESS BITS
VSEL0
VSEL1
A2
A1
1.05 V
1.2 V
0
1
PACKAGE
ORDERING
PACKAGE
MARKING
(CC)
YFF-9
TPS62650TYFFRQ1
Q1
The following registers bits are set by internal hardware logic and not user programmable through I2C:
(a) VSEL0[7] = 1
(b) VSEL1[7] = 1
(c) CONTROL1[3:2] = 00
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
at VIN, SW (2)
Input Voltage
at FB
(2)
at EN, VSEL, SCL, SDA
(2)
Power dissipation
MAX
–0.3
7
V
–0.3
3.6
V
–0.3
VI + 0.3
V
Internally limited
Operating junction temperature, TA
(3)
–40
Maximum operating junction Temperature, TA
Storage temperature range, Tstg
ESD rating (4)
(1)
(2)
(3)
(4)
2
UNIT
MIN
–65
105
°C
150
°C
150
°C
Human-body model (HBM) AEC-Q100 Classification Level H2
2
kV
Charged-device model (CDM) AEC-Q100 Classification Level
C3B
750
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 105°C.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
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SLVSB62A – MARCH 2012 – REVISED MARCH 2012
THERMAL INFORMATION
TPS62650-Q1
THERMAL METRIC (1)
YFF
UNITS
9 PINS
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
0.9
θJB
Junction-to-board thermal resistance
18.1
ψJT
Junction-to-top characterization parameter
4.0
ψJB
Junction-to-board characterization parameter
18.0
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
107.0
°C/W
spacer
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
Minimum and maximum values are at VI = 2.3V to 5.5V, VO = 1.2 V, EN = 1.8V, EN_DCDC bit = 1, AUTO mode and
TA = -40°C to 105°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at
VI = 3.6V, VO = 1.2 V, EN = 1.8V, EN_DCDC bit = 1, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VI
IQ
Input voltage range
Operating quiescent current
I(SD)
Shutdown current
UVLO
Undervoltage lockout threshold
2.3
VI = 3.6 V, IO = 0 mA, -40°C ≤ TA≤ 105°C. Device not switching
38
VI = 3.6 V, IO = 0 mA. PWM mode
5.5
V
80
μA
5.35
mA
VI = 3.6 V, EN = GND, EN_DCDC bit = X, -40°C ≤ TA≤ 105°C
0.5
10
μA
VI = 3.6 V, EN = VI, EN_DCDC bit = 0, -40°C ≤ TA≤ 105°C
0.5
10
μA
2.05
2.15
V
Falling
ENABLE, VSEL, SDA, SCL
VIH
High-level input voltage
VIL
Low-level input voltage
Ilkg
Input leakage current
0.9
V
Input tied to GND or VI, -40°C ≤ TA≤ 105°C
0.01
VI = V(GS) = 3.6 V
255
VI = V(GS) = 2.5 V
335
0.4
V
0.7
μA
POWER SWITCH
rDS(on)
P-channel MOSFET on resistance
Ilkg
P-channel leakage current, PMOS
rDS(on)
N-channel MOSFET on resistance
Ilkg
N-channel leakage current, NMOS
rDIS
Discharge resistor for power-down
sequence
V(DS) = 5.5 V, -40°C ≤ TA≤ 105°C
1
VI = V(GS) = 3.6 V
140
VI = V(GS) = 2.5 V
200
V(DS) = 5.5 V, -40°C ≤ TA≤ 105°C
P-MOS current limit
2.3 V ≤ VI ≤ 4.8 V. Open loop
Input current limit under short-circuit
conditions
VO = 0 V
mΩ
1200
Thermal shutdown
Thermal shutdown hysteresis
μA
mΩ
1
μA
15
50
Ω
1500
1850
mA
11
mA
140
°C
15
°C
OSCILLATOR
fSW
Oscillator frequency
IO = 0 mA. PWM mode, TA= 25°C
5.4
6
6.6
IO = 0 mA. PWM mode, -40°C ≤ TA≤ 105°C
5.2
6
6.8
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MHz
3
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ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum values are at VI = 2.3V to 5.5V, VO = 1.2 V, EN = 1.8V, EN_DCDC bit = 1, AUTO mode and
TA = -40°C to 105°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at
VI = 3.6V, VO = 1.2 V, EN = 1.8V, EN_DCDC bit = 1, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Regulated DC output
voltage accuracy
TPS62650Q1/1
VO
2.3 V ≤ VI ≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA
VO = 0.75 V, 1.05 V, 1.20 V, 1.4375 V (TPS62650-Q1)
PWM operation
–4%
4%
TA= 85°C
2.3 V ≤ VI ≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA
VO = 0.75 V, 1.05 V, 1.20 V, 1.4375 V (TPS62650-Q1)
PWM operation
–2%
2%
2.3 V ≤ VI ≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA
VO = 0.75 V, 1.05 V, 1.20 V, 1.4375 V (TPS62650-Q1)
PFM/PWM Operation
–4%
4%
-0.5%
+0.5%
Regulated DC output
voltage temperature drift
VI = 3.6 V, VO = 1.20 V, IO(DC) = 50 mA
-40°C ≤ TA ≤ 105°C. PWM operation
Line regulation
VI = VO + 0.5 V (min 2.3 V) to 5.5 V, IO(DC) = 200 mA
Load regulation
IO(DC) = 0 mA to 800 mA
0.13
Feedback input resistance
ΔVO
Power-save mode ripple voltage
%/V
–0.00046
%/mA
480
kΩ
VO = 1.05 V, VSEL = GND, IO(DC) = 1 mA
PFM operation
16
mVPP
VO = 1.20 V, VSEL = VI, IO(DC) = 1 mA
PFM operation
16
mVPP
DAC
Resolution
TPS62650Q1
Differential nonlinearity
6
Bits
Specified monotonic by design
±0.4
LSB
TIMING
VO
Setup Time Between
Rising EN and Start of
I2C Stream
TPS62650Q1/1
Output voltage settling
time
TPS62650Q1/1
Start-up time
TPS62650Q1/1
μs
50
From min to max output voltage,
IO(DC) = 500 mA, VSEL = VI, PWM operation
μs
12
Time from active EN to VO
VO = 1.2 V, IO = 0 mA, PWM operation
125
Time from active EN to VO
VO = 1.05 V, IO = 0 mA, PFM operation
120
μs
I2C INTERFACE TIMING CHARACTERISTICS (1)
PARAMETER
TEST CONDITIONS
MAX
UNIT
Standard mode
MIN
100
kHz
Fast mode
400
kHz
1
MHz
High-speed mode (write operation), CB – 100 pF max
3.4
MHz
High-speed mode (read operation), CB – 100 pF max
3.4
MHz
High-speed mode (write operation), CB – 400 pF max
1.7
MHz
1.7
MHz
Fast mode plus
f(SCL)
SCL Clock Frequency
High-speed mode (read operation), CB – 400 pF max
Bus Free Time Between a STOP and
START Condition
tBUF
tHD, tSTA
(1)
4
Hold Time (Repeated) START
Condition
Standard mode
4.7
μs
Fast mode
1.3
μs
Fast mode plus
0.5
μs
Standard mode
4
μs
Fast mode
600
ns
Fast mode plus
260
ns
High-speed mode
160
ns
Specified by design. Not tested in production.
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I2C INTERFACE TIMING CHARACTERISTICS (continued)
PARAMETER
tLOW
LOW Period of the SCL Clock
TEST CONDITIONS
MIN
Standard mode
4.7
μs
Fast mode
1.3
μs
Fast mode plus
0.5
μs
High-speed mode, CB – 100 pF max
160
ns
High-speed mode, CB – 400 pF max
320
ns
4
μs
Standard mode
tHIGH
tSU, tSTA
HIGH Period of the SCL Clock
Setup Time for a Repeated START
Condition
tSU, tDAT Data Setup Time
tHD, tDAT Data Hold Time
tRCL
tRCL1
tFCL
tRDA
Rise Time of SCL Signal
Rise Time of SCL Signal After a
Repeated START Condition and After
an Acknowledge BIT
Fall Time of SCL Signal
Rise Time of SDA Signal
MAX
UNIT
Fast mode
600
ns
Fast mode plus
260
ns
High-speed mode, CB – 100 pF max
60
ns
High-speed mode, CB – 400 pF max
120
ns
Standard mode
4.7
μs
Fast mode
600
ns
Fast mode plus
260
ns
High-speed mode
160
ns
Standard mode
250
ns
Fast mode
100
ns
ns
Fast mode plus
50
High-speed mode
10
Standard mode
0
3.45
μs
0.9
μs
ns
Fast mode
0
Fast mode plus
0
High-speed mode, CB – 100 pF max
0
70
ns
High-speed mode, CB – 400 pF max
0
150
ns
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
120
ns
Fast mode plus
μs
High-speed mode, CB – 100 pF max
10
40
ns
High-speed mode, CB – 400 pF max
20
80
ns
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
120
ns
Fast mode plus
High-speed mode, CB – 100 pF max
10
80
ns
High-speed mode, CB – 400 pF max
20
160
ns
Standard mode
20 + 0.1 CB
300
ns
Fast mode
20 + 0.1 CB
300
ns
120
ns
Fast mode plus
High-speed mode, CB – 100 pF max
10
40
ns
High-speed mode, CB – 400 pF max
20
80
ns
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
120
ns
Fast mode plus
High-speed mode, CB – 100 pF max
10
80
ns
High-speed mode, CB – 400 pF max
20
160
ns
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I2C INTERFACE TIMING CHARACTERISTICS (continued)
PARAMETER
tFDA
Fall Time of SDA Signal
tSU, tSTO Setup Time of STOP Condition
CB
6
Capacitive Load for SDA and SCL
TEST CONDITIONS
MIN
MAX
UNIT
Standard mode
20 + 0.1 CB
300
ns
Fast mode
20 + 0.1 CB
300
ns
120
ns
ns
Fast mode plus
High-speed mode, CB – 100 pF max
10
80
High-speed mode, CB – 400 pF max
20
160
Standard mode
4
μs
ns
Fast mode
600
ns
Fast mode plus
260
ns
High-Speed mode
160
ns
Standard mode
400
pF
Fast mode
400
pF
Fast mode plus
550
pF
High-Speed mode
400
pF
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SLVSB62A – MARCH 2012 – REVISED MARCH 2012
I2C TIMING DIAGRAMS
SDA
tf
tLOW
tsu;DAT
tr
tf
tBUF
tr
thd;STA
SCL
S
thd;STA
thd;DAT
tsu;STA
tsu;STO
HIGH
Sr
P
S
Figure 3. Serial Interface Timing Diagram for Standard-, Fast-, Fast-Mode Plus
Sr
Sr P
tfDA
trDA
SDAH
tsu;STA
thd;DAT
thd;STA
tsu;STO
tsu;DAT
SCLH
tfCL
trCL1
See Note A
trCL1
trCL
tHIGH
tLOW
tLOW
tHIGH
See Note A
= MCS Current Source Pull-Up
= R(P) Resistor Pull-Up
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
Figure 4. Serial Interface Timing Diagram for HS-Mode
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PIN ASSIGNMENTS
TPS6265x
CSP−9
(TOP VIEW)
TPS6265x
CSP−9
(BOTTOM VIEW)
A1
A2
A3
A3
A2
A1
B1
B2
B3
B3
B2
B1
C1
C2
C3
C3
C2
C1
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
VIN
A2
I
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
EN
B3
I
This is the enable pin of the device. Connect this pin to ground forces the device into
shutdown mode. Pulling this pin to VI enables the device. On the rising edge of the enable
pin, all the registers are reset with their default values. This pin must not be left floating and
must be terminated.
VSEL
A1
I
VSEL signal is primarily used to scale the output voltage and to set the TPS62650-Q1
operation between active mode (VSEL=HIGH) and sleep mode (VSEL=LOW). The mode of
operation can also be adapted by I2C settings. This pin must not be left floating and must be
terminated.
SDA
A3
I/O
SCL
B2
I
Serial interface clock line.
FB
C1
I
Output feedback sense input. Connect FB to the converter output.
GND
Serial interface address/data line.
C2, C3
SW
Ground.
B1
This is the switch pin of the converter and connected to the drain of the internal power
MOSFETs.
I/O
FUNCTIONAL BLOCK DIAGRAM
EN
VIN
Undervoltage
Lockout
Bias Supply
Bandgap
Soft-Start
V REF = 0.75 V
VIN
Negative Inductor
Current Detect
Power Save Mode
Switching Logic
Thermal
Shutdown
Current Limit
Detect
Frequency
Control
FB
Gate Driver
Anti
Shoot-Through
SW
+
SDA
SCL
2
I C I/F
Control
Logic
Registers
6-Bit
DAC
VDAC
GND
VSEL
8
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PARAMETER MEASUREMENT INFORMATION
TPS62650
VI
VIN
FB
C1
VO
SW
L1
GND
GND
C2
EN
VO = Roof
VO = Floor
I2C Bus
up to 3.4 Mbps
VSEL
L = muRata LQM21PN1R0NGR
C1 = muRata GRM155R60J475M (4.7mF, 6.3V, 0402, X5R)
C2 = muRata GRM155R60J475M (4.7mF, 6.3V, 0402, X5R)
SDA
SCL
Note: The internal registers are set to their default values
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
η
Efficiency
Peak-to-peak output ripple
voltage
VO
DC output voltage
Measured output voltage
vs Output current
vs Input voltage
5, 6, 7, 8
9
vs Output Current
10, 11, 12, 13
vs Output current
14, 15, 16, 17
vs Ambient temperature
vs DAC target output voltage
PFM/PWM Boundaries
18, 19
20
21
IQ
Quiescent current
vs Input voltage
22
ISD
Shutdown current
vs Input voltage
23
fS
Switching frequency
vs Input voltage
24
P-channel MOSFET rDS(on)
vs Input voltage
25
N-channel MOSFET rDS(on)
vs Input voltage
rDS(on)
Load transient response
26
27 - 38
Line transient PWM operation
39
Combined line and load transient
response
40
PWM operation
41
Power-save mode operation
42
Dynamic voltage management
43, 44
Output voltage ramp control
45
Start-up
46, 47
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
100
100
90
90
80
80
70
VI = 3.6 V
PFM/PWM
60
Efficiency - %
Efficiency - %
70
50
40
VI = 4.2 V
PFM/PWM
VI = 3.6 V
Forced PWM
20
1
10
100
IO - Output Current - mA
1
Figure 6.
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
1000
100
VO = 0.75 V
90
80
VI = 2.7 V
PFM/PWM
VI = 3.6 V
PFM/PWM
70
Efficiency - %
60
50
VI = 4.2 V
PFM/PWM
50
40
30
20
20
10
10
10
100
IO - Output Current - mA
1000
VI = 3.6 V
PFM/PWM
60
30
1
VI = 2.7 V
PFM/PWM
0
0.1
Figure 7.
10
10
100
IO - Output Current - mA
Figure 5.
VO = 1.4375 V
70
Efficiency - %
40
0
0.1
1000
80
0
0.1
VI = 4.2 V
PFM/PWM
50
10
100
40
60
20
10
90
VI = 3.6 V
PFM/PWM
30
30
0
0.1
VI = 2.7 V
PFM/PWM
VO = 1.05 V
VO = 1.20 V
VI = 2.7 V
PFM/PWM
VI = 4.2 V
PFM/PWM
1
10
100
IO - Output Current - mA
1000
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
INPUT VOLTAGE
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
OUTPUT CURRENT
100
24
96
VO - Peak-to-Peak Output Ripple Voltage - mV
VO = 1.2 V
PFM/PWM
98
94
92
IO = 100 mA
Efficiency - %
90
88
IO = 300 mA
86
IO = 10 mA
84
82
80
78
IO = 1 mA
76
74
72
70
2.3
3.1
3.5
3.9
4.3
4.7
VI - Input Voltage - V
5.1
VI = 3.6 V
14
VI = 2.5 V
12
10
8
6
4
2
0
100
200 300 400 500 600
IO - Load Current - mA
700
Figure 10.
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
OUTPUT CURRENT
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
OUTPUT CURRENT
800
24
VO = 1.05 V
VO - Peak-to-Peak Output Ripple Voltage - mV
VO - Peak-to-Peak Output Ripple Voltage - mV
16
Figure 9.
20
VI = 4.8 V
18
16
VI = 3.6 V
14
VI = 2.5 V
12
10
8
6
4
2
0
0
VI = 4.8 V
18
5.5
24
22
20
0
2.7
VO = 1.2 V
22
100
200 300 400 500 600
IO - Load Current - mA
700
800
VO = 0.75 V
22
20
VI = 4.8 V
18
16
VI = 3.6 V
14
VI = 2.5 V
12
10
8
6
4
2
0
0
100
Figure 11.
200 300 400 500 600
IO - Load Current - mA
700
800
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
OUTPUT CURRENT
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.224
VO = 1.2 V
VO = 1.4375 V
22
20
VI = 4.8 V
18
16
1.212
VO - Output Voltage - V
VO - Peak-to-Peak Output Ripple Voltage - mV
24
VI = 3.6 V
14
VI = 2.5 V
12
10
8
VI = 4.8 V
PFM/PWM
VI = 3.6 V
PWM Operation
1.2
VI = 2.5 V
PFM/PWM
VI = 3.6 V
PFM/PWM
1.188
6
4
2
1.176
0.1
0
0
100
200 300 400 500 600
IO - Load Current - mA
700
800
1
10
100
IO - Output Current - mA
Figure 13.
Figure 14.
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0.765
1.071
VO = 0.75 V
VO = 1.05 V
VI = 4.8 V
PFM/PWM
VI = 4.8 V
PFM/PWM
0.758
VI = 3.6 V
PFM/PWM
VO - Output Voltage - V
VO - Output Voltage - V
1.061
1.05
VI = 2.5 V
PFM/PWM
1.04
1.029
0.1
1
10
100
IO - Output Current - mA
1000
0.75
VI = 3.6 V
PFM/PWM
VI = 2.5 V
PFM/PWM
0.743
0.735
0.1
Figure 15.
12
1000
1
10
100
IO - Output Current - mA
1000
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
DC OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE
1.466
1.212
VO = 1.4375 V
VO = 1.2 V,
IO = 250 mA,
PWM Operation
1.209
VI = 4.8 V
PFM/PWM
1.206
VI = 3.6 V
PWM Operation
VO - Output Voltage - V
VO - Output Voltage - V
1.452
1.438
VI = 2.5 V
PFM/PWM
VI = 3.6 V
PFM/PWM
1.423
VI = 4.2 V
VI = 3.6 V
1.203
1.2
VI = 2.7 V
1.197
1.194
1.191
1.409
0.1
1
10
100
IO - Output Current - mA
1000
1.188
-40
Figure 18.
DC OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE
MEASURED OUTPUT VOLTAGE
vs
DAC TARGET OUTPUT VOLTAGE
100
4
VO = 1.05 V,
IO = 250 mA,
PWM Operation
3
Measured Output Voltage DAC Target Output Voltage - mV
VI = 4.2 V
1.058
VI = 3.6 V
1.055
VO - Output Voltage - V
0
20
40
60
80
TA - Ambient Temperature - °C
Figure 17.
1.061
VI = 2.7 V
1.053
1.05
1.047
1.045
VI = 3.6 V,
IO = 100 mA,
PWM Operation
2
-20
0
20
40
60
80
TA - Ambient Temperature - °C
100
TA = 85°C
TA = 25°C
1
0
-1
-2
1.042
1.04
-40
-20
-3
0.75
TA = -40°C
0.85 0.95 1.05 1.15 1.25 1.35
VO - DAC Target Output Voltage - V
Figure 19.
1.45
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
QUIESCENT CURRENT
vs
INPUT VOLTAGE
55
50
o
TA = 85 C
45
IQ − Quiescent Current − mA
IO − Load Current − mA
PFM/PWM BOUNDARIES
220
210 V = 1.2 V
O
200
Always PWM
190
180
170
160
150
140
130
PFM to PWM
120
Mode Change
110
100
90
80
The switching mode
70
changes at these borders
60
50
PWM to PFM
40
Mode Change
30
20
Always PFM
10
0
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
o
TA = 25 C
40
35
30
25
TA = -40oC
20
15
10
5
0
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VI − Input Voltage − V
VI − Input Voltage − V
Figure 21.
Figure 22.
SHUTDOWN CURRENT
vs
INPUT VOLTAGE
SWITCHING FREQUENCY
vs
INPUT VOLTAGE
2500
IO = 50 mA
6.5
2000
fs - Switching Frequency - MHz
I(SD) − Shutdown Current − nA
2250
7
TA = 85oC
1750
1500
1250
1000
TA = 25oC
750
500
250
IO = 150 mA
5.5
IO = 300 mA
5
IO = 400 mA
IO = 500 mA
IO = 600 mA
IO = 700 mA
4.5
IO = 800 mA
4
3.5
o
TA = -40 C
0
6
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
3
2.3
2.7
VI − Input Voltage − V
Figure 23.
14
3.1
3.5
3.9
4.3
4.7
VI - Input Voltage - V
5.1
5.5
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
rDS(on) P-MOSFET
vs
INPUT VOLTAGE
rDS(on) N-MOSFET
vs
INPUT VOLTAGE
rDS(on) - Static Drain-Source On-Resistance - mW
PWM Mode Operation
425
400
TA = 85°C
375
350
TA = 25°C
325
300
275
250
225
200
175
TA = -40°C
150
125
2.5
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
5.3
PWM Mode Operation
275
250
TA = 85°C
225
200
TA = 25°C
175
150
125
100
TA = -40°C
75
50
2.5
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
Figure 26.
LOAD TRANSIENT: 50 mA / 400 mA / 50 mA
PWM OPERATION
LOAD TRANSIENT: 50 mA / 400 mA
PWM OPERATION
IO
200 mA/div
5.3
VI = 3.6 V
VO = 1.35 V
VO
20 mV/div - 1.20-V Offset
VO
20 mV/div - 1.20-V Offset
4.9
300
Figure 25.
IO
200 mA/div
rDS(on) - Static Drain-Source On-Resistance - mW
450
VI = 3.6 V
VO = 1.20 V
t − Time = 5 ms/div
t − Time = 1 ms/div
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
VO
20 mV/div - 1.20-V Offset
VO
20 mV/div - 1.20-V Offset
IO
200 mA/div
VI = 3.6 V
VO = 1.20 V
LOAD TRANSIENT: 50 mA / 400 mA / 50 mA
PFM/PWM OPERATION
IO
200 mA/div
LOAD TRANSIENT: 400 mA / 50 mA
PWM OPERATION
VI = 3.6 V
VO = 1.20 V
t − Time = 10 ms/div
Figure 29.
Figure 30.
LOAD TRANSIENT: 50 mA / 400 mA
PFM/PWM OPERATION
LOAD TRANSIENT: 400 mA / 50 mA
PFM/PWM OPERATION
VO
20 mV/div - 1.20-V Offset
t − Time = 1 ms/div
t − Time = 1 ms/div
Figure 31.
16
VI = 3.6 V
VO = 1.20 V
IO
200 mA/div
VI = 3.6 V
VO = 1.20 V
VO
20 mV/div - 1.20-V Offset
IO
200 mA/div
t − Time = 1 ms/div
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
IO
200 mA/div - 400 mA Offset
VO
LOAD TRANSIENT: 400 mA / 750 mA
PWM OPERATION
20 mV/div - 1.20-V Offset
IO
VO
20 mV/div - 1.20-V Offset
200 mA/div - 400 mA Offset
LOAD TRANSIENT: 400 mA / 750 mA / 400 mA
PWM OPERATION
VI = 3.6 V
VO = 1.20 V
VI = 3.6 V
VO = 1.20 V
t − Time = 1 ms/div
Figure 33.
Figure 34.
LOAD TRANSIENT: 750 mA / 400 mA
PWM OPERATION
LOAD TRANSIENT: 5 mA / 100 mA / 5 mA
PFM/PWM OPERATION
VI = 3.6 V
VO = 1.05 V
IO
50 mA/div
VO
VI = 3.6 V
VO = 1.20 V
10 mV/div - 1.05-V Offset
IO
200 mA/div - 400 mA Offset
VO
20 mV/div - 1.20-V Offset
t − Time = 5 ms/div
t − Time = 1 ms/div
t − Time = 250 ms/div
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT: 100 mA / 5 mA
PFM/PWM OPERATION
IO
IL
200 mA/div
VO
10 mV/div - 1.05-V Offset
t − Time = 2.5 ms/div
t − Time = 2.5 ms/div
Figure 37.
Figure 38.
LINE TRANSIENT
PWM OPERATION
COMBINED LINE/LOAD TRANSIENT
(3.3 V TO 3.9 V, 400 mA TO 800 mA)
PWM OPERATION
VO = 1.20 V, IO = 50mA
PWM Mode
t − Time = 50 ms/div
Figure 39.
18
VI = 3.6 V
VO = 1.05 V
100 mA/div
VI = 3.6 V
VO = 1.05 V
VI
VO
20 mV/div - 1.20-V Offset 500 mV/div - 3.3-V Offset
IO
IL
200 mA/div
VO
VI
VO
10 mV/div - 1.20-V Offset 500 mV/div - 3.3-V Offset
10 mV/div - 1.05-V Offset
100 mA/div
LOAD TRANSIENT: 5 mA / 100 mA
PFM/PWM OPERATION
IO
500 mA/div
VI
500 mV/div
VO = 1.20 V
PWM Mode
t − Time = 25 ms/div
Figure 40.
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TYPICAL CHARACTERISTICS (continued)
IL
100 mA/div
VO
10 mV/div - 1.20-V Offset
VI = 3.6 V
VO = 1.20 V
IO = 30 mA
t − Time = 500 ns/div
t − Time = 40 ns/div
Figure 41.
Figure 42.
DYNAMIC VOLTAGE MANAGEMENT
DYNAMIC VOLTAGE MANAGEMENT
VI = 3.6 V
VO = 1.05 V (PFM) / 1.20 V (PWM)
VSEL
2 V/div
IL
SW
2 V/div
VO
POWER SAVE MODE OPERATION
VI = 3.6 V, VO = 1.20 V
IO = 200 mA
VSEL
2 V/div
10 mV/div - 1.20-V Offset
100 mA/div
PWM OPERATION
VO = 1.20 V
VO
VO = 1.05 V
IL
PFM
VI = 3.6 V
VO = 1.05 V (PFM) / 1.20 V (PWM)
RL = 5 W
50 mV/div - 1.05-V Offset
PWM
PWM
VO = 1.05 V
PFM
200 mA/div
VO
IL
200 mA/div
50 mV/div - 1.05-V Offset
VO = 1.20 V
t − Time = 5 ms/div
RL = 270 W
t − Time = 25 ms/div
Figure 43.
Figure 44.
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TYPICAL CHARACTERISTICS (continued)
VO
VO
200 mV/div - 0.75-V Offset
VO = 1.4375 V
500 mV/div
VI = 3.6 V
VO = 0.75 V / 1.4375 V (PWM)
IO = 0 mA
IL
EN
2 V/div
START UP
100 mA/div
VSEL
2 V/div
OUTPUT VOLTAGE
RAMP CONTROL
VI = 3.6 V
VO = 1.05 V (PFM)
IO = 0 mA
Slew Rate = 4.8 mV/ms
VO = 0.75 V
t − Time = 50 ms/div
t − Time = 20 ms/div
Figure 45.
Figure 46.
EN
2 V/div
START UP
VI = 3.6 V
VO = 1.20 V (PWM)
VO
500 mV/div
IL
200 mA/div
RL = 5 W
t − Time = 20 ms/div
Figure 47.
20
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DETAILED DESCRIPTION
Operation
The TPS62650-Q1 is a synchronous step-down converter typically operates at a regulated 6-MHz frequency
pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS62650-Q1
converter operates in power-save mode with pulse frequency modulation (PFM) and automatic transition into
PWM operation when the load current increases.
The TPS62650-Q1 integrates an I2C compatible interface allowing transfers up to 3.4 Mbps. This communication
interface can be used for dynamic voltage scaling with voltage steps down to 12.5 mV, for reprogramming the
mode of operation (PFM or forced PWM) or disable/enabling the output voltage for instance. For more details,
see the I2C interface and register description section.
The converter uses a unique frequency locked ring oscillating modulator to achieve best-in-class load and line
response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of
each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up rising the
output voltage until the main comparator trips, then the control logic turns off the switch.
One key advantage of the non-linear architecture is that there is no traditional feed-back loop. The loop response
to change in VO is essentially instantaneous, which explains its extraordinary transient response. The absence of
a traditional, high-gain compensated linear loop means that the TPS62650-Q1 is inherently stable over a range
of small L and CO.
Although this type of operation normally results in a switching frequency that varies with input voltage and load
current, an internal frequency lock loop (FLL) holds the switching frequency constant over a large range of
operating conditions.
Combined with best in class load and line transient response characteristics, the low quiescent current of the
device (ca. 38μA) allows to maintain high efficiency at light load, while preserving fast transient response for
applications requiring tight output regulation.
SWITCHING FREQUENCY
The magnitude of the internal ramp, which is generated from the duty cycle, reduces for duty cycles either set of
50%. Thus, there is less overdrive on the main comparator inputs which tends to slow the conversion down. The
intrinsic maximum operating frequency of the converter is about 10MHz to 12MHz, which is controlled to circa.
6MHz by a frequency locked loop.
When high or low duty cycles are encountered, the loop runs out of range and the conversion frequency falls
below 6MHz. The tendency is for the converter to operate more towards a "constant inductor peak current" rather
than a "constant frequency". In addition to this behavior which is observed at high duty cycles, it is also noted at
low duty cycles.
When the converter is required to operate towards the 6MHz nominal at extreme duty cycles, the application can
be assisted by decreasing the ratio of inductance (L) to the output capacitor's equivalent serial inductance (ESL).
This increases the ESL step seen at the main comparator's feed-back input thus decreasing its propagation
delay, hence increasing the switching frequency.
POWER-SAVE MODE
If the load current decreases, the converter will enter Power Save Mode operation automatically. During powersave mode the converter operates in discontinous current (DCM) single-pulse PFM mode, which produces low
output ripple compared with other PFM architectures.
When in power-save mode, the converter resumes its operation when the output voltage trips below the nominal
voltage. It ramps up the output voltage with a minimum of one pulse and goes into power-save mode when the
inductor current has returned to a zero steady state. The PFN on-time varies inversely proportional to the input
voltage and proportional to the output voltage giving the regulated switching frequency when is steady-state.
PFM mode is left and PWM operation is entered as the output current can no longer be supported in PFM mode.
As a consequence, the DC output voltage is typically positioned ca 0.5% above the nominal output voltage and
the transition between PFM and PWM is seamless.
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PFM Mode at Light Load
PFM Ripple
Nominal DC Output Voltage
PWM Mode at Heavy Load
Figure 48. Operation in PFM Mode and Transfer to PWM Mode
MODE SELECTION
Depending on the settings of CONTROL1 register the device can be operated in either the regulated frequency
PWM mode or in the automatic PWM and power-save mode. In this mode, the converter operates in a regulated
frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, which maintains high
efficiency over a wide load current range. For more details, see the CONTROL1 register description.
The regulated frequency PWM mode has the tightest regulation and the best line/load transient performance.
Furthermore, this mode of operation allows simple filtering of the switching frequency for noise-sensitive
applications. In forced PWM mode, the efficiency is lower compared to the power-save mode during light loads.
It is possible to switch from power-save mode (PFM) to forced PWM mode during operation either via the VSEL
signal or by re-programming the CONTROL1 register. This allows adjustments to the converters operation to
match the specific system requirements leading to more efficient and flexible power management.
ENABLE
The device starts operation when EN pin is set high and starts up with the soft start. This signal is gated by the
EN_DCDC bit defined in register VSEL0 and VSEL1. On rising edge of the EN pin, all the registers are reset with
their default values. Enabling the converter's operation via the EN_DCDC bit does not affect internal register
settings. This allows the output voltage to be programmed to other values than the default voltage before starting
up the converter. For more details, see the VSEL0/1 register description.
Pulling the EN pin, VSEL0[6] bit or VSEL1[6] bit low forces the device into shutdown, with a shutdown current as
defined in the electrical characteristics table. In this mode, the P and N-channel MOSFETs are turned off, the
internal resistor feedback divider is disconnected, and the entire internal-control circuitry is switched off. For
proper operation, the EN pin must be terminated and must not be left floating.
In addition, depending on the setting of CONTROL2[6] bit, the device can actively discharge the output capacitor
when it turns off. The integrated discharge resistor has a typical resistance of 15 Ω. The required time to
discharge the output capacitor at VO depends on load current and the output capacitance value.
SOFT START
The TPS62650-Q1 has an internal soft-start circuit that limits the inrush current during start-up. This limits input
voltage drops when a battery or a high-impedance power source is connected to the input of the converter.
The soft-start system progressively increases the on-time from a minimum pulse-width of 35ns as a function of
the output voltage. This mode of operation continues for c.a. 100μs after enable. Should the output voltage not
have reached its target value by this time, such as in the case of heavy load, the soft-start transitions to a second
mode of operation.
The converter will then operate in a current limit mode, specifically the P-MOS current limit is set to half the
nominal limit and the N-channel MOSET remains on until the inductor current has reset. After a further 100 μs,
the device ramps up to full current limit operation providing that the output voltage has risen above 0.5V
(approximately). Therefore, the start-up time depends on the output capacitor and load current.
22
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UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the
converter from turning on the switch or rectifier MOSFET under undefined conditions. The TPS62650-Q1 device
have a UVLO threshold set to 2.05V (typical). Fully functional operation is permitted down to 2.15 V input
voltage.
SHORT-CIRCUIT PROTECTION
The TPS62650-Q1 integrates a P-channel MOSFET current limit to protect the device against heavy load or
short circuits. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is
turned off and the N-channel MOSFET is turned on. The regulator continues to limit the current on a cycle-bycycle basis.
As soon as the output voltage falls below ca. 0.4V, the converter current limit is reduced to half of the nominal
value and the PWROK bit is reset. Because the short-circuit protection is enabled during start-up, the device
does not deliver more than half of its nominal current limit until the output voltage exceeds approximately 0.5V.
This needs to be considered when a load acting as a current sink is connected to the output of the converter.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds typically 140°C, the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction
temperature again falls below typically 130°C.
VOLTAGE AND MODE SELECTION
The TPS62650-Q1 features a pin-selectable output voltage. VSEL is primarily used to scale the output voltage
between active (VSEL = HIGH) and sleep mode (VSEL = LOW). For maximum flexibility, it is possible to
reprogram the operating mode of the converter (e.g. forced PWM, or auto transition PFM/PWM) associated with
VSEL signal via the I2C interface
VSEL output voltage and mode selection is defined as following:
VSEL = LOW: –– DC/DC output voltage determined by VSEL0 register value. DC/DC mode of operation is
determined by MODE0 bit in CONTROL1 register.
VSEL = HIGH: –– DC/DC output voltage determined by VSEL1 register value. DC/DC mode of operation is
determined by MODE1 bit in CONTROL1 register.
The application processor programs via I2C the output voltages associated with the two states of VSEL signal:
floor (VSEL0) and roof (VSEL1) values. The application processor also writes the DEFSLEW value in the
CONTROL2 register to control the output voltage ramp rate.
These two registers can be continuously updated via I2C to provide the appropriate output voltage according to
the VSEL input. The voltage changes with the selected ramp rate immediately after writing to the VSEL0 or
VSEL1 register.
Table 1 shows the output voltage states depending on VSEL0, VSEL1 registers, and VSEL signal.
Table 1. Dynamic Voltage Scaling Functional Overview
VSEL PIN
VSEL0 REGISTER
VSEL1 REGISTER
OUTPUT VOLTAGE
Low
No action
No action
Floor
Low
Write new value
No action
Change to new value
Low
No action
Write
No change stays at floor voltage
High
No action
No action
Roof
High
Write new value
No action
No change stays at roof voltage
High
No action
Write new value
Change to new value
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In PFM mode, when the output voltage is programmed to a lower value by toggling VSEL signal from high to low,
PWROK is defined as low, while the output capacitor is discharged by the load until the converter starts pulsing
to maintain the voltage within regulation. In multiple-step mode, PWROK is defined as low while the output
voltage is ramping up or down.
V (ROOF)
Output Voltage
Change Initiated
Output Voltage
Change Initiated
V (FLOOR)
V (ROOF)
V (FLOOR)
PWROK
PWROK
Figure 49. PWROK Functional Behavior
VOLTAGE RAMP CONTROL
The TPS62650-Q1 offers a voltage ramp rate control that can operate in two different modes:
• Multiple-Step Mode
• Single-Step Mode
The mode is selected via DEFSLEW control bits in the CONTROL2 register.
Single-Step Voltage Scaling Mode (default), DEFSLEW[2:0] = [111]
In single-step mode, the TPS62650-Q1 ramps the output voltage with maximum slew-rate when transitioning
between the floor and the roof voltages (switch to a higher voltage).
When switching between the roof and the floor voltages (transition to a lower voltage), the ramp rate control is
dependent on the mode selection (see CONTROL1 register) associated with the target register (Forced PWM or
auto transition PFM/PWM).
Table 2 shows the ramp rate control when transitioning to a lower voltage with DEFSLEW set to immediate
transition.
Table 2. Ramp Rate Control vs. Target Mode
Mode Associated with Target Voltage
Output Voltage Ramp Rate
Forced PWM
Immediate
PFM/PWM
DC/DC converter stops switching.
Time to ramp down depends on output capacitance and load current
For instance, when the output is programmed to transition to a lower voltage with PFM operation enabled, the
TPS62650-Q1 ramps down the output voltage without controlling the ramp rate or having intermediate microsteps. The required time to ramp down the voltage depends on the capacitance present at the output of the
TPS62650-Q1 and on the load current. From an overall system perspective, this is the most efficient way to
perform dynamic voltage scaling.
Multiple-Step Voltage Scaling Mode, DEFSLEW[2:0] = [000] to [110]
In multiple-step mode the TPS62650-Q1 controls the output voltage ramp rate regardless of the load current and
mode of operation (e.g. Forced PWM or PFM/PWM). The voltage ramp control is done by adjusting the time
between the voltage micro-steps.
24
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THEORY OF OPERATION
Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The TPS62650-Q1 device works as a slave and supports the following data transfer modes, as defined in the
I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), fast mode plus (1 Mbps) and high-speed
mode (up to 3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as supply voltage remains above 2.1 V (typical).
The data transfer protocol for standard, fast and fast plus modes is exactly the same, therefore, they are referred
to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is
referred to as HS-mode. The TPS62650-Q1 device supports 7-bit addressing; 10-bit addressing and general call
address are not supported.
The TPS62650-Q1 device has a 7-bit address with two bits factory programmable allowing up to four dc/dc
converters to be connected to the same bus. The 4 MSBs are 1001 and the LSB is 0.
Standard-, Fast- and Fast-Mode Plus Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, see Figure 50. All I2C-compatible devices should recognize a
start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse, see Figure 51. All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge, see Figure 52, by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that the communication link
with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high, see Figure 50. This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address
Attempting to read data from register addresses not listed in this section results in 00h being read out.
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H/S-Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions are used
to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
DATA
CLK
S
P
Start
Condition
Stop
Condition
Figure 50. START and STOP Conditions
DATA
CLK
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 51. Bit Transfer on the Serial Interface
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
S
9
Clock Pulse for
Acknowledgement
START
Condition
Figure 52. Acknowledge on the I2C Bus
26
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Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
MSB
Acknowledgement
Signal From Slave
Sr
Address
R/W
SCL
1
S
or
Sr
2
7
8
9
ACK
1
2
3−8
9
ACK
Sr
or
P
Clock Line Held Low While
Interrupts are Serviced
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Figure 53. Bus Protocol
TPS62650-Q1 I2C Update Sequence
The TPS62650-Q1 requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS62650-Q1 device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. A valid I2C address selects the TPS62650-Q1. TPS62650-Q1
performs an update on the falling edge of the LSB byte.
When the TPS62650-Q1 is in hardware shutdown (EN pin tied to ground) the device can not be updated via the
I2C interface. Conversely, the I2C interface is fully functional during software shutdown (EN_DCDC bit = 0).
1
7
1
1
8
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A
P
“0” Write
A = Acknowledge
S = START condition
P = STOP condition
From Master to TPS6265x
From TPS6265x to Master
Figure 54. "Write" Data Transfer Format in Standard, Fast- and Fast-Plus Modes
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
“0” Write
From Master to TPS6265x
From TPS6265x to Master
“1” Read
A
A
S
Sr
P
= Acknowledge
= Not Acknowledge
= START condition
= REPEATED START condition
= STOP condition
Figure 55. "Read" Data Transfer Format in Standard, Fast- and Fast-Plus Modes
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F/S Mode
S
HS Mode
A Sr SLAVE ADDRESS R/W A
HS-MASTER CODE
REGISTER ADDRESS
F/S Mode
A
DATA
Data Transferred
(n x Bytes + Acknowledge)
A/A
P
HS Mode Continues
Sr Slave Address
Figure 56. Data Transfer Format in H/S-Mode
Slave Address Byte
MSB
X
1
0
0
1
A2
A1
LSB
0
The slave address byte is the first byte received following the START condition from the master device. The first
four bits (MSBs) of the address are factory preset to 1001. The next two bits (A2, A1) of the address are device
option dependent. The LSB bit (A0) is also factory preset to 0. Up to 4 TPS62650-Q1 type of devices can be
connected to the same I2C-Bus. See the ordering information table for more details.
Register Address Byte
MSB
0
0
0
0
0
0
D1
LSB
D0
Following the successful acknowledgment of the slave address, the bus master sends a byte to the TPS62650Q1, which contains the address of the register to be accessed. The TPS62650-Q1 contains four 8-bit registers
accessible via a bidirectional I2C-bus interface. All internal registers have read and write access.
28
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REGISTER DESCRIPTION
VSEL0 REGISTER DESCRIPTION
Memory location: 0x00
Description
Bits
Memory type
Default value
EN_DCDC
D7
R/W
1
FREE
D6
R/W
0
D5
R/W
X
D4
R/W
X
VSM0[5:0]
D3
D2
R/W
R/W
X
X
Bit
Description
EN_DCDC
Enable/Disable DC/DC operation.
This bit gates the external EN pin control signal. This bit is mirrored in VSEL1 register.
0: Device in shutdown regardless of the EN signal.
1: Device enabled when EN is high, disabled when EN is low.
VSM0[5:0]
Output voltage selection bits (floor voltage). (1)
6-bit unsigned binary linear coding.
Output voltage = Minimum output voltage + (VSM0[5:0] x 12.5 mV)
(1)
D1
R/W
X
D0
R/W
X
D1
R/W
X
D0
R/W
X
Register value is set according to the default output voltage, see ordering information table.
VSEL1 REGISTER DESCRIPTION
Memory location: 0x01
Description
Bits
Memory type
Default value
EN_DCDC
D7
R/W
1
FREE
D6
R/W
0
D5
R/W
X
D4
R/W
X
VSM1[5:0]
D3
D2
R/W
R/W
X
X
Bit
Description
EN_DCDC
Enable/Disable DC/DC operation.
This bit gates the external EN pin control signal. This bit is mirrored in VSEL0 register.
0: Device in shutdown regardless of the EN signal.
1: Device enabled when EN is high, disabled when EN is low.
VSM1[5:0]
Output voltage selection bits (roof voltage). (1)
6-bit unsigned binary linear coding.
Output voltage = Minimum output voltage + (VSM1[5:0] x 12.5 mV)
(1)
Register value is set according to the default output voltage, see ordering information table.
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CONTROL1 REGISTER DESCRIPTION
Memory location: 0x02
Description
Bits
Memory type
Default value
RESERVED
D7
R
0
RESERVED
D6
R
0
FREE
D5
R/W
0
FREE
D4
R/W
0
Bit
Description
MODE_CTRL[1:0]
Mode control bits. (1)
00: Operation follows MODE0, MODE1.
01: PFM/PWM operation independent of VSEL signal.
10: Forced PWM operation independent of VSEL signal.
11: PFM/PWM operation independent of VSEL signal.
MODE1
VSEL high (roof voltage) operating mode selection bit.
0: Forced PWM.
1: PFM/PWM automatic transition.
MODE0
VSEL low (floor voltage) operating mode selection bit.
0,1: PFM/PWM automatic transition (no effect).
(1)
MODE_CTRL[1:0]
D3
D2
R/W
R/W
0
0
MODE1
D1
R/W
0
MODE0
D0
R/W
0
See the ordering information table to verify the validity of this option.
CONTROL2 REGISTER DESCRIPTION
Memory location: 0x03
Description
Bits
Memory type
Default value
FREE
D7
R/W
0
OUTPUT_DISCHARGE
D6
R/W
1
PWROK
D5
R/W
0
FREE
D4
R/W
0
FREE
D3
R/W
0
D2
R/W
1
DEFSLEW
D1
R/W
1
Bit
Description
OUTPUT_
DISCHARGE
Output capacitor auto-discharge control bit.
0: The output capacitor is not actively discharged when the converter is disabled.
1: The output capacitor is discharged through an internal resistor when the converter is disabled.
PWROK
Power good bit.
0: The output voltage is not within its regulation limits.
1: The output voltage is in regulation.
DEFSLEW
Output voltage slew-rate control bits.
000: 0.15mV/μs
001: 0.3mV/μs
010: 0.6mV/μs
011: 1.2mV/μs
100: 2.4mV/μs
101: 4.8mV/μs
110: 9.6mV/μs
111: Immediate
30
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R/W
1
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APPLICATION INFORMATION
INDUCTOR SELECTION
The TPS62650-Q1 series of step-down converters have been optimized to operate with an effective inductance
value in the range of 0.3μH to 1.3μH and with output capacitors in the range of 4.7μF to 10μF. The internal
compensation is optimized to operate with an output filter of L = 0.47μH and CO = 4.7μF. Larger or smaller
inductor values can be used to optimize the performance of the device for specific operation conditions. For more
details, refer to the section "checking loop stability".
The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage
ripple and the efficiency. The selected inductor has to be rated for its dc resistance and saturation current. The
inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO.
V
V - VO
DI
DIL = O x I
DIL(MAX) = IO(MAX) + L
VI
L x fsw
2
with: fSW = switching frequency (6 MHz typical)
L = inductor value
ΔIL = peak-to-peak inductor ripple current
IL(MAX) = maximum inductor current
(1)
In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e.
quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care
should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing
the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor
size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance (R(DC)) and the following frequencydependent components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
The following inductor series from different suppliers have been used with the TPS62650-Q1 converters.
Table 3. List of Inductors
MANUFACTURER
MURATA
SERIES
DIMENSIONS
LQM21PN1R0NGR
2.0 x 1.2 x 1.0 max. height
LQM21PNR54MG0
2.0 x 1.2 x 1.0 max. height
LQM21PNR47MG0
2.0 x 1.2 x 1.0 max. height
LQM2MPN1R0NG0
2.0 x 1.6 x 1.0 max. height
TOKO
MDT2012-CX1R0A
2.0 x 1.2 x 1.0 max. height
FDK
MIPS2012D1R0-X2
2.0 x 1.2 x 1.0 max. height
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OUTPUT CAPACITOR SELECTION
The advanced fast-response voltage mode control scheme of the TPS62650-Q1 allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. For best performance, the device should be operated with a minimum effective output
capacitance of 1.6μF. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor
impedance.
At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load
transitions. A 4.7μF capacitor typically provides sufficient bulk capacitance to stabilize the output during large
load transitions. The typical output voltage ripple is 1.5% of the nominal output voltage VO.
The output voltage ripple during PFM mode operation can be kept small. The PFM pulse is time controlled, which
allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM
output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor
value. The PFM frequency decreases with smaller inductor values and increases with larger once. Increasing the
output capacitor value and the effective inductance will minimize the output ripple voltage.
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. For most applications, a 2.2μF or 4.7μF capacitor is sufficient. If the application exhibits a
noisy or erratic switching frequency, the remedy will probably be found by experimenting with the value of the
input capacitor.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between CI and the power source lead to reduce ringing than can occur between the inductance of the power
source leads and CI.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR
is the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error
signal used by the regulator to return VO to its steady-state value. The results are most easily interpreted when
the device operates in PWM mode.
During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
load current range, and temperature range.
32
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LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the
TPS62650-Q1 devices demand careful attention to PCB layout. Care must be taken in board layout to get the
specified performance. If the layout is not carefully done, the regulator could show poor line and/or load
regulation, stability and switching frequency issues as well as EMI problems. It is critical to provide a low
inductance, impedance ground path. Therefore, use wide and short traces for the main current paths.
VOUT
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor. In order to get an optimum ESL step, the output voltage feedback point (FB) should be taken in the
output capacitor path, approximately 1mm away for it. The feed-back line should be routed away from noisy
components and traces (e.g. SW line).
GND
L1
C1
C2
A
B
C
VIN
A: EN
B: SCL
C: SDA
L
E
S
V
Figure 57. Suggested Layout (Top)
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Thermal Information
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
The maximum recommended junction temperature (TJ) of the TPS62650-Q1 device is 105°C. The thermal
resistance of the 9-pin CSP package (YFF) is RθJA = 105°C/W. The regulator operation is specified to a
maximum ambient temperature TA of 105°C. Therefore, the maximum power dissipation is about 200mW.
o
o
TJMAX - TA
105 C - 85 C
= 190 mW
=
PDMAX =
o
RqJA
105 C/W
(2)
PACKAGE SUMMARY
CHIP SCALE PACKAGE
(BOTTOM VIEW)
D
A3
A2
A1
B3
B2
B1
C3
C2
C1
CHIP SCALE PACKAGE
(TOP VIEW)
YMSCC
LLLL
A1
E
Code:
34
•
YM - Year Month date code
•
S - assembly site code
•
CC - Chip code
•
LLLL - Lot trace code
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PACKAGE OPTION ADDENDUM
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30-Jul-2012
PACKAGING INFORMATION
Orderable Device
TPS62650TYFFRQ1
Status
(1)
Package Type Package
Drawing
ACTIVE
DSBGA
YFF
Pins
Package Qty
9
3000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
SNAGCU
MSL Peak Temp
(3)
Samples
(Requires Login)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS62650-Q1 :
• Catalog: TPS62650
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS62650TYFFRQ1
Package Package Pins
Type Drawing
SPQ
DSBGA
3000
YFF
9
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
1.45
B0
(mm)
K0
(mm)
P1
(mm)
1.45
0.8
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS62650TYFFRQ1
DSBGA
YFF
9
3000
210.0
185.0
35.0
Pack Materials-Page 2
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