TI TPS7350QPE4

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
D
Available in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V
Fixed-Output and Adjustable Versions
Integrated Precision Supply-Voltage
Supervisor Monitoring Regulator Output
Voltage
Active-Low Reset Signal with 200-ms Pulse
Width
Very Low Dropout Voltage . . . Maximum of
35 mV at IO = 100 mA (TPS7350)
Low Quiescent Current – Independent of
Load . . . 340 µA Typ
Extremely Low Sleep-State Current,
0.5 µA Max
2% Tolerance Over Full Range of Load,
Line, and Temperature for Fixed-Output
Versions§
Output Current Range of 0 mA to 500 mA
TSSOP Package Option Offers Reduced
Component Height For Critical Applications
D
D
D
D
D
D
D
D
D OR P PACKAGE
(TOP VIEW)
GND
EN
IN
IN
1
8
2
7
3
6
4
5
RESET
SENSE†/FB‡
OUT
OUT
PW PACKAGE
(TOP VIEW)
GND
GND
GND
NC
NC
EN
NC
IN
IN
IN
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
RESET
NC
NC
FB‡
NC
SENSE†
OUT
OUT
NC
NC
NC – No internal connection
† SENSE – Fixed voltage options only
(TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350)
‡ FB – Adjustable version only (TPS7301)
description
The TPS73xx devices are members of a family of
micropower low-dropout (LDO) voltage regulators.
They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset
function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.¶
AVAILABLE OPTIONS
OUTPUT VOLTAGE
(V)
NEGATIVE-GOING RESET
THRESHOLD VOLTAGE (V)
PACKAGED DEVICES
TJ
MIN
– 40°C to
125°C
125
C
TYP
MAX
MIN
TYP
MAX
SMALL
OUTLINE
(D)
PLASTIC DIP
(P)
TSSOP
(PW)
CHIP FORM
(Y)
4.9
5
5.1
4.55
4.65
4.75
TPS7350QD
TPS7350QP
TPS7350QPW
TPS7350Y
4.75
4.85
4.95
4.5
4.6
4.7
TPS7348QD
TPS7348QP
TPS7348QPW
TPS7348Y
3.23
3.3
3.37
2.868
2.934
3
TPS7333QD
TPS7333QP
TPS7333QPW
TPS7333Y
2.94
3
3.06
2.58
2.64
2.7
TPS7330QD
TPS7330QP
TPS7330QPW
TPS7330Y
2.425
2.5
2.575
2.23
2.32
2.39
TPS7325QD
TPS7325QP
TPS7325QPW
TPS7325Y
TPS7301QD
TPS7301QP
TPS7301QPW
TPS7301Y
Adjustable
1.2 V to 9.75 V
1.101
1.123
1.145
The D and PW packages are available taped and reeled. Add an R suffix to device type (e.g., TPS7350QDR). The TPS7301Q is programmable
using an external resistor divider (see application information). The chip form is tested at 25°C.
§ The TPS7325 has a tolerance of ± 3% over the full temperature range.
¶ The TPS71xx and the TPS72xx are 500-mA and 250-mA output regulators respectively, offering performance similar to that of the TPS73xx but
without the delayed-reset function. The TPS72xx devices are further differentiated by availability in 8-pin thin-shrink small-outline packages
(TSSOP) for applications requiring minimum package size.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
description (continued)
The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event
of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator
to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low. RESET stays low
for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out
begins. At the completion of the 200-ms delay, RESET goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance
is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mV
at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1).
Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains
constant, independent of output loading (typically 340 µA over the full range of output current, 0 mA to 500 mA).
These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator,
reducing the quiescent current to 0.5 µA maximum at TJ = 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is
available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of
1.2 mm.
0.3
TPS73xxPW†
TA = 25°C
TPS7330
0.25
Dropout Voltage – V
TPS7333
0.2
8
VI
IN
RESET
IN
SENSE
9
TPS7325
IN
0.15
To System
Reset
15
10
0.1 µF
20
OUT
6
EN
OUT
TPS7348
250 kΩ
14
VO
13
+
GND
0.1
1
TPS7350
2
3
CO ‡
10 µF
CSR = 1 Ω
0.05
0
0
50 100 150 200 250 300 350 400 450 500
IO – Output Current – mA
Figure 1. Dropout Voltage Versus Output Current
2
POST OFFICE BOX 655303
† TPS7325, TPS7330, TPS7333, TPS7348, TPS7350 (fixed-voltage
options)
‡ Capacitor selection is nontrivial. See application information
section for details.
Figure 2. Typical Application Configuration
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS73xxY chip information
These chips, when properly assembled, display characteristics similar to those of the TPS73xxQ. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted
with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(5)
IN
(5)
(3)
(4)
(6)
EN
(2)
(6)
TPS73xx
(4)
(7)
SENSE†
FB‡
OUT
RESET
(1)
(7)
GND
CHIP THICKNESS: 15 TYPICAL
80
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
† SENSE – Fixed voltage options only (TPS7325, TPS7330,
TPS7333, TPS7348, and TPS7350)
‡ FB – Adjustable version only (TPS7301)
(3)
(1) (2)
NOTE A. For most applications, OUT and SENSE should
be tied together as close as possible to the device;
for other implementations, refer to SENSE-pin
connection discussion in the applications
information section of this data sheet.
92
functional block diagram
IN
RESISTOR DIVIDER OPTIONS
¶
EN
¶
¶
RESET
_
+
OUT
Vref
+
_
Delayed
Reset
DEVICE
R1
R2
UNIT
TPS7301
TPS7325
TPS7330
TPS7333
TPS7348
TPS7350
0
260
358
420
726
756
∞
233
233
233
233
233
Ω
kΩ
kΩ
kΩ
kΩ
kΩ
NOTE A. Resistors are nominal values only.
SENSE§/FB
R1
R2
COMPONENT COUNT
MOS transistors
Bilpolar transistors
Diodes
Capacitors
Resistors
464
41
4
17
76
GND
§ For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to
SENSE-pin connection discussion in applications information section.
¶ Switch positions are shown with EN low (active).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
timing diagram
VI
Vres†
Vres
t
VO
VIT +
VIT +
Threshold
Voltage
VIT –
VIT –
t
RESET
Output
Output
Undefined
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
200 ms
Delay
200 ms
Delay
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Output
Undefined
t
† Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Input voltage range§, VI, RESET, SENSE, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 11 V
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
§ All voltage values are with respect to network terminal ground.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (SEE FIGURE 3)
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 125°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
145 mW
P
1175 mW
9.4 mW/°C
752 mW
235 mW
PW†
700 mW
5.6 mW/°C
448 mW
140 mW
PACKAGE
DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (SEE FIGURE 4)
PACKAGE
TC ≤ 25°C
POWER RATING
D
P
DERATING FACTOR
ABOVE TC = 25°C
TC = 70°C
POWER RATING
TC = 125°C
POWER RATING
2188 mW
9.4 mW/°C
1765 mW
1248 mW
2738 mW
21.9 mW/°C
1752 mW
548 mW
PW†
4025 mW
32.2 mW/°C
2576 mW
805 mW
† Refer to Thermal Information section for detailed power dissipation considerations when using the
TSSOP package.
MAXIMUM CONTINUOUS DISSIPATION
vs
CASE TEMPERATURE
MAXIMUM CONTINUOUS DISSIPATION
vs
FREE-AIR TEMPERATURE
4800
1200
1000
P Package
RθJA = 106°C/W
800
D Package
RθJA = 172°C/W
600
400
PW Package
RθJA = 178°C/W
200
PD – Maximum Continuous Dissipation – mW
PD – Maximum Continuous Dissipation – mW
1400
4400
4000
PW Package
RθJC = 37°C/W
3600
3200
2800
P Package
RθJC = 46°C/W
2400
2000
1600
1200
D Package
RθJC = 57°C/W
800
400
0
0
25
50
75
100
125
150
25
50
75
100
125
150
TC – Case Temperature – °C
TA – Free-Air Temperature – °C
Figure 3
Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
recommended operating conditions
Input voltage,
voltage VI†
MIN
MAX
TPS7301Q
2.47
10
TPS7325Q
3.1
10
TPS7330Q
3.5
10
TPS7333Q
3.77
10
TPS7348Q
5.2
10
TPS7350Q
5.33
10
High-level input voltage at EN, VIH
2
Low-level input voltage at EN, VIL
Output current range, IO
0
UNIT
V
V
V
V
0.5
V
500
mA
Operating virtual junction temperature range, TJ
– 40
125
°C
† Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage, VDO,
at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads.
To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:
V
V
V
I(min)
O(max)
DO(max load)
Because the TPS7301 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for calculating
VDO from rDS(on) is given in Note 2 in the TPS7301 electrical characteristics table. The minimum value of 2.97 V is the absolute lower limit for
the recommended input voltage range for the TPS7301.
+
6
)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR‡ = 1 Ω), SENSE/FB shorted to
OUT (unless otherwise noted)
TEST CONDITIONS§
PARAMETER
Ground current (active mode)
EN ≤ 0.5 V,
0 mA ≤ IO ≤ 500 mA
Input current (standby mode)
EN = VI,
2 7 V ≤ VI ≤ 10 V
2.7
Output current limit
VO = 0 V
V,
VI = 10 V
Pass-element leakage
g current in standby
y
mode
EN = VI,
2 7 V ≤ VI ≤ 10 V
2.7
RESET leakage current
Normal operation,
operation V at RESET = 10 V
TJ
MIN
25°C
VI = VO + 1 V,
EN logic low (active mode)
25°C
0.01
0.5
2
25°C
1.2
– 40°C to 125°C
2
2
25°C
0.01
– 40°C to 125°C
0.5
1
0.02
– 40°C to 125°C
0.5
0.5
– 40°C to 125°C
61
75
2.5 V ≤ VI ≤ 6 V
6 V ≤ VI ≤ 10 V
2 7 V ≤ VI ≤ 10 V
2.7
– 40°C to 125°C
2
25°C
0.5
– 40°C to 125°C
0.5
0 V ≤ VI ≤ 10 V
50
25°C
– 0.5
– 40°C to 125°C
– 0.5
25°C
0.001
25°C
– 40°C to 125°C
µA
A
µA
µA
ppm/°C
2.05
2.5
2.5
1
V
mV
0.5
0.5
– 40°C to 125°C
IO(RESET) = – 300 µA
µA
V
2.7
25°C
UNIT
°C
165
Minimum VI for active pass element
Minimum VI for valid RESET
400
– 40°C to 125°C
EN hysteresis voltage
EN input current
340
550
Thermal shutdown junction temperature
EN logic high (standby mode)
MAX
– 40°C to 125°C
25°C
Output voltage temperature coefficient
TYP
1.5
1.9
µA
V
V
‡ CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to Co.
§ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7301Q electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), FB
shorted to OUT at device leads (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Reference voltage (measured at FB)
2.5 V ≤ VI ≤ 10 V,
See Note 1
5 mA ≤ IO ≤ 500 mA,
Reference voltage temperature
coefficient
Pass-element series resistance
(See Note 2)
Input regulation
Output regulation
Output noise voltage
TYP
1.147
– 40°C to 125°C
61
75
25°C
0.7
1
150 mA ≤ IO ≤ 500 mA
VI = 2
2.9
9V
V,
50 µA ≤ IO ≤ 500 mA
VI = 3.9 V,
VI = 5.9 V,
50 µA ≤ IO ≤ 500 mA
25°C
0.32
50 µA ≤ IO ≤ 500 mA
25°C
0.23
VI = 2.5 V to 10 V,,
See Note 1
50 µ
µA ≤ IO ≤ 500 mA,,
25°C
3
2.5 V ≤ VI ≤ 10 V,,
See Note 1
IO = 5 mA to 500 mA,,
2.5 V ≤ VI ≤ 10 V,,
See Note 1
IO = 50 µA
µ to 500 mA,,
– 40°C to 125°C
10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage§
VO(FB) decreasing
RESET hysteresis voltage§
Measured at VO(FB)
25°C
RESET output low voltage§
VI = 2
2.13
13 V,
V
0.83
0.52
– 40°C to 125°C
18
25
25°C
5
– 40°C to 125°C
14
25
25°C
7
– 40°C to 125°C
22
54
25°C
48
– 40°C to 125°C
44
Ω
25°C
45
– 40°C to 125°C
44
2
25°C
95
Co = 10 µF
25°C
89
Co = 100 µF
25°C
74
1.101
12
25°C
0.1
– 40°C to 125°C
µVrms
– 20
0.1
V
mV
0.4
0.4
– 10
mV
µV/√Hz
1.145
25°C
25°C
mV
dB
54
25°C
– 40°C to 125°C
mV
59
Co = 4.7 µF
FB input current
0.85
0.85
– 40°C to 125°C
IO(RESET) = 400 µA
ppm/°C
1.3
1.3
25°C
– 40°C to 125°C
V
1
– 40°C to 125°C
f = 120 Hz
UNIT
V
1.217
VI = 2
2.4
4V
V,
f = 120 Hz
MAX
1.182
50 µA ≤ IO ≤ 150 mA
IO = 500 mA,,
See Note 1
Output noise-spectral density
– 40°C to 125°C
MIN
VI = 2
2.4
4V
V,
IO = 50 µA
Ripple rejection
TJ
25°C
10
20
V
nA
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§ Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 33) to a point where the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on)
rDS(on) is a function of both output current and input voltage. This parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other
programmed values, refer to Figure 33.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7325Q electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 10 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
Dropout voltage§
3.5 V ≤ VI ≤ 10 V,
5 mA ≤ IO ≤ 500 mA
IO = 10 mA
mA,
97 V
VI = 2
2.97
IO = 100 mA,
mA
VI = 2
2.97
97 V
IO = 500 mA,
mA
VI = 2
2.97
97 V
Pass element series resistance§
Pass-element
(
(2.97
V – VO))/IO,
IO = 500 mA
VI = 2.97 V,,
Input regulation
VI = 3.5
3 5 V to 10 V,
V
50 µA ≤ IO ≤ 500 mA
mA
IO = 5 mA to 500 mA,
3 5 V ≤ VI ≤ 10 V
3.5
IO = 50 µA to 500 mA
mA,
3 5 V ≤ VI ≤ 10 V
3.5
IO = 50 µA
f = 120 Hz
IO = 500 mA
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
VO decreasing
RESET output low voltage
VI = 2
2.1
1V
V,
MIN
TYP
2.45
2.5
– 40°C to 125°C
2.425
25°C
50
– 40°C to 125°C
25°C
270
– 40°C to 125°C
0.5
400
0.7
1.4
25°C
6
– 40°C to 125°C
20
25
25°C
20
– 40°C to 125°C
32
50
25°C
28
– 40°C to 125°C
60
100
25°C
50
– 40°C to 125°C
49
25°C
49
– 40°C to 125°C
32
mV
mV
mV
dB
53
Co = 4.7 µF
25°C
274
Co = 10 µF
25°C
228
25°C
Ω
53
2
25°C
mV
600
25°C
– 40°C to 125°C
80
150
25°C
IO(RESET) = – 0.8
0 8 mA
V
14
25°C
– 40°C to 125°C
2.55
UNIT
5
– 40°C to 125°C
Co = 100 µF
MAX
2.575
– 40°C to 125°C
Output regulation
Ripple rejection
TJ
25°C
µV/√Hz
µVrms
159
2.23
2.32
2.39
0.14
0.4
0.4
V
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§ Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from
output voltage.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7330Q electrical characteristics at IO = 10 mA, VI = 4 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
4 V ≤ VI ≤ 10 V,
5 mA ≤ IO ≤ 500 mA
mA
IO = 10 mA,
94 V
VI = 2
2.94
IO = 100 mA,
mA
VI = 2
2.94
94 V
IO = 500 mA,
mA
VI = 2
2.94
94 V
Pass element series resistance
Pass-element
(
(2.94
V – VO)/I
) O,
IO = 500 mA
VI = 2.94 V,,
Input regulation
VI = 4 V to 10 V,
V
50 µA ≤ IO ≤ 500 mA
mA
IO = 5 mA to 500 mA,
4 V ≤ VI ≤ 10 V
IO = 50 µA to 500 mA,
mA
4 V ≤ VI ≤ 10 V
Dropout voltage
IO = 50 µA
f = 120 Hz
IO = 500 mA
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
VO decreasing
RESET output low voltage
VI = 2
2.6
6V
V,
MIN
– 40°C to 125°C
2.94
TYP
25°C
3.06
5.2
– 40°C to 125°C
52
– 40°C to 125°C
25°C
267
25°C
0.5
6
– 40°C to 125°C
0.7
23
29
25°C
20
– 40°C to 125°C
32
60
25°C
28
– 40°C to 125°C
60
120
25°C
43
– 40°C to 125°C
40
25°C
39
– 40°C to 125°C
36
mV
mV
mV
dB
53
Co = 4.7 µF
25°C
274
Co = 10 µF
25°C
228
25°C
Ω
53
2
25°C
mV
450
1
25°C
– 40°C to 125°C
75
500
25°C
IO(RESET) = – 0.8
0 8 mA
V
7
100
– 40°C to 125°C
– 40°C to 125°C
UNIT
10
25°C
Co = 100 µF
MAX
3
– 40°C to 125°C
Output regulation
Ripple rejection
TJ
25°C
µV/√Hz
µVrms
159
2.58
2.64
2.7
0.14
0.4
0.4
V
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7333Q electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
4.3 V ≤ VI ≤ 10 V,
5 mA ≤ IO ≤ 500 mA
IO = 10 mA
mA,
23 V
VI = 3
3.23
IO = 100 mA,
mA
VI = 3
3.23
23 V
IO = 500 mA,
mA
VI = 3
3.23
23 V
Pass element series resistance
Pass-element
(
(3.23
V – VO)/I
) O,
IO = 500 mA
VI = 3.23 V,,
Input regulation
VI = 4.3
4 3 V to 10 V,
V
50 µA ≤ IO ≤ 500 mA
Dropout voltage
Output regulation
IO = 50 µA to 500 mA
mA, 4
4.3
3 V ≤ VI ≤ 10 V
IO = 50 µA
f = 120 Hz
IO = 500 mA
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
VO decreasing
MIN
– 40°C to 125°C
3.23
4.5
7
44
60
– 40°C to 125°C
80
25°C
235
– 40°C to 125°C
25°C
0.44
mV
300
0.6
0.8
25°C
6
– 40°C to 125°C
23
29
25°C
21
– 40°C to 125°C
38
75
25°C
31
– 40°C to 125°C
60
120
25°C
43
– 40°C to 125°C
40
25°C
39
– 40°C to 125°C
36
mV
mV
mV
dB
49
Co = 4.7 µF
25°C
274
Co = 10 µF
25°C
228
25°C
Ω
51
2
µV/√Hz
µVrms
159
2.868
V
25°C
18
25°C
0.17
– 40°C to 125°C
V
400
25°C
IO(RESET) = – 1 mA
UNIT
8
25°C
RESET hysteresis voltage
VI = 2
2.8
8V
V,
3.37
– 40°C to 125°C
– 40°C to 125°C
MAX
3.3
25°C
Co = 100 µF
RESET output low voltage
TYP
– 40°C to 125°C
3 V ≤ VI ≤ 10 V
IO = 5 mA to 500 mA
mA, 4
4.3
Ripple rejection
TJ
25°C
mV
0.4
0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7348Q electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
5.85 V ≤ VI ≤ 10 V,
5 mA ≤ IO ≤ 500 mA
IO = 10 mA
mA,
75 V
VI = 4
4.75
IO = 100 mA,
mA
VI = 4
4.75
75 V
IO = 500 mA,
mA
VI = 4
4.75
75 V
Pass element series resistance
Pass-element
(
(4.75
V – VO)/I
) O,
IO = 500 mA
VI = 4.75 V,,
Input regulation
VI = 5
5.85
85 V to 10 V
V,
50 µA ≤ IO ≤ 500 mA
Dropout voltage
Output regulation
IO = 50 µA to 500 mA
mA, 5
5.85
85 V ≤ VI ≤ 10 V
IO = 50 µA
f = 120 Hz
IO = 500 mA
Output noise-spectral density
MIN
– 40°C to 125°C
4.75
10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
VO decreasing
2.9
6
28
37
– 40°C to 125°C
54
25°C
150
– 40°C to 125°C
0.28
25°C
9
– 40°C to 125°C
0.37
35
37
25°C
28
– 40°C to 125°C
42
80
25°C
42
– 40°C to 125°C
65
130
25°C
42
– 40°C to 125°C
39
25°C
39
– 40°C to 125°C
35
mV
mV
mV
dB
50
2
25°C
410
Co = 10 µF
25°C
328
25°C
Ω
53
Co = 4.7 µF
µV/√Hz
µVrms
212
4.5
4.7
25°C
26
25°C
0.2
– 40°C to 125°C
mV
180
0.52
25°C
IO(RESET) = – 1.2
1 2 mA,V
mA VI = 4.12
4 12 V
V
250
25°C
– 40°C to 125°C
UNIT
8
25°C
RESET hysteresis voltage
RESET output low voltage
4.95
– 40°C to 125°C
Co = 100 µF
MAX
4.85
25°C
f = 120 Hz
Output noise voltage
TYP
– 40°C to 125°C
85 V ≤ VI ≤ 10 V
IO = 5 mA to 500 mA
mA, 5
5.85
Ripple rejection
TJ
25°C
V
mV
0.4
0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7350Q electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
6 V ≤ VI ≤ 10 V,
5 mA ≤ IO ≤ 500 mA
IO = 10 mA
mA,
88 V
VI = 4
4.88
IO = 100 mA,
mA
VI = 4
4.88
88 V
IO = 500 mA,
mA
VI = 4
4.88
88 V
Pass element series resistance
Pass-element
(
(4.88
V – VO)/I
) O,
IO = 500 mA
VI = 4.88 V,,
Input regulation
VI = 6 V to 10 V,
V
50 µA ≤ IO ≤ 500 mA
mA
IO = 5 mA to 500 mA,
6 V ≤ VI ≤ 10 V
IO = 50 µA to 500 mA
mA,
6 V ≤ VI ≤ 10 V
Dropout voltage
IO = 50 µA
f = 120 Hz
IO = 500 mA
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
VO decreasing
MIN
– 40°C to 125°C
4.9
5.1
2.9
6
27
35
– 40°C to 125°C
– 40°C to 125°C
50
25°C
146
– 40°C to 125°C
0.27
25°C
4
– 40°C to 125°C
0.35
25
45
25°C
30
– 40°C to 125°C
45
86
25°C
45
– 40°C to 125°C
65
140
25°C
43
– 40°C to 125°C
38
25°C
41
– 40°C to 125°C
36
mV
mV
mV
dB
51
Co = 4.7 µF
25°C
430
Co = 10 µF
25°C
345
25°C
Ω
53
2
µV/√Hz
µVrms
220
4.55
4.75
25°C
28
25°C
0.15
– 40°C to 125°C
mV
170
0.5
25°C
IO(RESET) = – 1.2
1 2 mA,
mA VI = 4.25
4 25 V
V
230
25°C
RESET hysteresis voltage
UNIT
8
25°C
– 40°C to 125°C
MAX
5
25°C
Co = 100 µF
RESET output low voltage
TYP
– 40°C to 125°C
Output regulation
Ripple rejection
TJ
25°C
V
mV
0.4
0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
switching characteristics
PARAMETER
RESET time-out
time out delay
TJ
TEST CONDITIONS
See Figure 5
TPS7301Q, TPS7333Q
TPS7348Q, TPS7350Q
MIN
TYP
MAX
25°C
140
200
260
– 40°C to 125°C
100
300
UNIT
ms
electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE/FB
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
TPS7301Y, TPS7333Y
TPS7348Y, TPS7350Y
MIN
TYP
UNIT
MAX
Ground current (active mode)
EN ≤ 0.5 V,
0 mA ≤ IO ≤ 500 mA
VI = VO + 1 V,
340
µA
Input current (standby mode)
EN = VI,
2.7 V ≤ VI ≤ 10 V
0.01
µA
Output current limit
VO = 0 V,
VI = 10 V
1.2
A
Pass-element leakage current in standby mode
EN = VI,
2.7 V ≤ VI ≤ 10 V
0.01
µA
RESET leakage current
Normal operation,
V at RESET = 10 V
0.02
µA
Thermal shutdown junction temperature
EN logic low (active mode)
EN hysteresis voltage
EN input current
°C
165
2.7 V ≤ VI ≤ 10 V
0 V ≤ VI ≤ 10 V
Minimum VI for active pass element
0.5
V
50
mV
0.001
µA
2.05
V
IO(RESET) = – 300 µA
1
V
Minimum VI for valid RESET
† CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7301Y electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
TJ = 25°C, FB shorted to OUT at device leads (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Reference voltage (measured at FB)
MIN
TYP
1.182
MAX
UNIT
V
VI = 2.4 V,
VI = 2.4 V,
50 µA ≤ IO ≤ 150 mA
150 mA ≤ IO ≤ 500 mA
0.83
VI = 2.9 V,
VI = 3.9 V,
50 µA ≤ IO ≤ 500 mA
0.52
50 µA ≤ IO ≤ 500 mA
0.32
VI = 5.9 V,
VI = 2.5 V to 10 V,
See Note 1
50 µA ≤ IO ≤ 500 mA
0.23
50 µA ≤ IO ≤ 500 mA,
3
mV
2.5 V ≤ VI ≤ 10 V,
See Note 1
IO = 5 mA to 500 mA,
5
mV
2.5 V ≤ VI ≤ 10 V,
See Note 1
IO = 50 µA to 500 mA,
7
mV
Ripple rejection
f = 120 Hz
IO = 50 µA
IO = 500 mA,
See Note 1
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
RESET hysteresis voltage§
Measured at VO(FB)
RESET output low voltage§
VI = 2.13 V,
Pass-element series resistance (See Note 2)
Input regulation
Output regulation
0.7
59
54
2
Co = 4.7 µF
95
Co = 10 µF
89
Co = 100 µF
74
IO(RESET) = 400 µA
FB input current
Ω
dB
µV/√Hz
µVrms
12
mV
0.1
V
0.1
nA
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§ Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 33) to a point where the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on)
rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other
programmed values, refer to Figure 33.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7325Y electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 10 µF (CSR† = 1 Ω),
TJ = 25°C, SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
VI = 2.97 V
VI = 2.97 V
IO = 500 mA,
(2.97 V – VO)/IO,
IO = 500 mA
VI = 2.97 V
VI = 2.97 V,
VI = 3.5 V to 10 V,
IO = 5 mA to 500 mA,
50 µA ≤ IO ≤ 500 mA
IO = 50 µA to 500 mA,
Ripple rejection
f = 120 Hz
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
Pass-element series resistance§
Input regulation
Output regulation
TYP
2.5
IO = 10 mA,
IO = 100 mA,
Dropout voltage§
MIN
MAX
UNIT
V
5
50
mV
270
0.5
Ω
6
mV
3.5 V ≤ VI ≤ 10 V
20
mV
3.5 V ≤ VI ≤ 10 V
28
mV
IO = 50 µA
IO = 500 mA
53
53
2
Co = 4.7 µF
274
Co = 10 µF
228
Co = 100 µF
159
dB
µV/√Hz
µVrms
VI = 2.1 V,
IO(RESET) = – 0.8 mA
0.14
V
RESET output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§ Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from
output voltage.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7330Y electrical characteristics at IO = 10 mA, VI = 4 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
TJ = 25°C, SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
MIN
Output voltage
TYP
MAX
3
IO = 10 mA,
IO = 100 mA,
VI = 2.94 V
VI = 2.94 V
5.2
IO = 500 mA,
(2.94 V – VO)/IO,
IO = 500 mA
VI = 2.94 V
VI = 2.94 V,
267
VI = 4 V to 10 V,
IO = 5 mA to 500 mA,
50 µA ≤ IO ≤ 500 mA
IO = 50 µA to 500 mA,
Ripple rejection
f = 120 Hz
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
Dropout voltage
Pass-element series resistance
Input regulation
Output regulation
UNIT
V
mV
52
Ω
0.5
6
mV
4 V ≤ VI ≤ 10 V
20
mV
4 V ≤ VI ≤ 10 V
28
mV
IO = 50 µA
IO = 500 mA
53
dB
53
µV/√Hz
2
Co = 4.7 µF
274
Co = 10 µF
228
Co = 100 µF
159
µVrms
VI = 2.6 V,
IO(RESET) = – 0.8 mA
0.14
V
RESET output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7333Y electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
TJ = 25°C, SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
MIN
TYP
3.3
MAX
UNIT
V
IO = 10 mA,
IO = 100 mA,
VI = 3.23 V
VI = 3.23 V
4.5
IO = 500 mA,
(3.23 V – VO)/IO,
IO = 500 mA
VI = 3.23 V
VI = 3.23 V,
235
VI = 4.3 V to 10 V,
IO = 5 mA to 500 mA,
50 µA ≤ IO ≤ 500 mA
6
mV
4.3 V ≤ VI ≤ 10 V
21
mV
IO = 50 µA to 500 mA,
4.3 V ≤ VI ≤ 10 V
31
mV
Ripple rejection
f = 120 Hz
IO = 50 µA
IO = 500 mA
51
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
Dropout voltage
Pass-element series resistance
Input regulation
Output regulation
44
0.44
49
2
Co = 4.7 µF
274
Co = 10 µF
228
Co = 100 µF
159
18
RESET hysteresis voltage
mV
Ω
dB
µV/√Hz
µVrms
mV
VI = 2.8 V,
IO(RESET) = – 1 mA
0.17
V
RESET output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7348Y electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
TJ = 25°C, SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
MIN
TYP
4.85
IO = 10 mA,
IO = 100 mA,
VI = 4.75 V
VI = 4.75 V
2.9
IO = 500 mA,
(4.75 V – VO)/IO,
IO = 500 mA
VI = 4.75 V
VI = 4.75 V,
150
VI = 5.85 V to 10 V,
IO = 5 mA to 500 mA,
50 µA ≤ IO ≤ 500 mA
IO = 50 µA to 500 mA,
Ripple rejection
f = 120 Hz
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
Dropout voltage
Pass-element series resistance
Input regulation
Output regulation
28
0.28
MAX
UNIT
V
mV
Ω
9
mV
5.85 V ≤ VI ≤ 10 V
28
mV
5.85 V ≤ VI ≤ 10 V
42
mV
IO = 50 µA
IO = 500 mA
53
50
2
Co = 4.7 µF
410
Co = 10 µF
328
Co = 100 µF
212
26
RESET hysteresis voltage
dB
µV/√Hz
µVrms
mV
IO(RESET) = – 1.2 mA, VI = 4.12 V
0.2
V
RESET output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7350Y electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
TJ = 25°C, SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
MIN
TYP
MAX
5
UNIT
V
IO = 10 mA,
IO = 100 mA,
VI = 4.88 V
VI = 4.88 V
2.9
6
27
35
IO = 500 mA,
(4.88 V – VO)/IO,
IO = 500 mA
VI = 4.88 V
VI = 4.88 V,
146
170
0.27
0.35
VI = 6 V to 10 V,
IO = 5 mA to 500 mA,
50 µA ≤ IO ≤ 500 mA
4
25
mV
6 V ≤ VI ≤ 10 V
28
75
mV
IO = 50 µA to 500 mA,
6 V ≤ VI ≤ 10 V
41
Ripple rejection
f = 120 Hz
IO = 50 µA
IO = 500 mA
53
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
Dropout voltage
Pass-element series resistance
Input regulation
Output regulation
430
345
Co = 100 µF
220
µV/√Hz
µVrms
28
RESET hysteresis voltage
RESET output low voltage
dB
2
Co = 10 µF
IO(RESET) = – 1.2 mA, VI = 4.25 V
0.15
Ω
mV
51
Co = 4.7 µF
mV
mV
0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
VO
VIT+
t
VI
IN
RESET
EN
SENSE
OUT
0.1 µF
Reset
+
GND
VO
10 µF
RESET
RESET
Timeout Delay
CSR
t
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 5. Test Circuit and Voltage Waveforms
VI
To Load
IN
OUT
SENSE
EN
+
CO
GND
Ccer†
RL
CSR
† Ceramic capacitor
Figure 6. Test Circuit for Typical Regions of Stability (Refer to Figures 29 through 32)
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
Table of Graphs
IQ
Quiescent current
IQ
Quiescent current
TPS7348
vs Output current
7
vs Input voltage
8
vs Free-air temperature
10
vs Free-air temperature
11
IQ
Quiescent current
VDO
∆VDO
Dropout voltage
vs Output current
12
Change in dropout voltage
vs Free-air temperature
13
VDO
∆VO
Dropout voltage
vs Output current
14
Change in output voltage
vs Free-air temperature
15
VO
VO
Output voltage
vs Input voltage
16
TPS7325
vs Input voltage
17
TPS7301
vs Output current
19
TPS7325
vs Output current
20
TPS7330
vs Output current
21
TPS7333
vs Output current
22
TPS7348
vs Output current
23
TPS7350
vs Output current
24
Output voltage
TPS7325
9
vs Input voltage
TPS7301
Line regulation
VO
Output voltage
18
Output voltage response from enable (EN)
Load transient response
25
TPS7301 or TPS7333
26
TPS7325
27
TPS7348 or TPS7350
28
TPS7301
29
TPS7333
30
TPS7348 or TPS7350
31
Ripple rejection
vs Frequency
32
Output spectral noise density
vs Frequency
33
vs Output current
34
vs Added ceramic capacitance
35
vs Output current
36
vs Added ceramic capacitance
37
Compensation series resistance
(CSR)
Co = 4
4.7
7 µF
Co = 10 µF
rDS(on)
Pass-element resistance
vs Input voltage
38
VI
VIT–
Minimum input voltage for valid RESET
vs Free-air temperature
39
Negative-going reset threshold
vs Free-air temperature
40
IOL(RESET)
td
RESET output current
vs Input voltage
41
Reset time delay
vs Free-air temperature
42
td
Distribution for reset delay
43
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
INPUT VOLTAGE
QUIESCENT CURRENT
vs
OUTPUT CURRENT
500
450
450
425
TPS73xx, VI = 10 V
I Q – Quiescent Current – µ A
I Q – Quiescent Current – µ A
TA = 25°C
IO = 500 mA
TA = 25°C
400
375
TPS7350, VI = 6 V
350
325
TPS7348, VI = 5.85 V
TPS7333, VI = 4.3 V
300
TPS7333
350
TPS7348
TPS7350
300
250
TPS7301 With VO
Programmed to 2.5 V
200
150
100
TPS7330, VI = 4 V
275
400
TPS7325, VI = 3.5 V
50
0
0
50
100
150
200
250
0
1
Figure 7
4
5
7
6
8
9
Figure 8
TPS7348
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
TPS7325
QUIESCENT CURRENT
vs
INPUT VOLTAGE
500
500
VI = 5.85 V
IO = 500 mA
450
I Q– Quiescent Current – µ A
I Q– Quiescent Current – µ A
3
VI – Input Voltage – V
IO – Output Current – mA
450
2
400
350
300
TA = 125°C
400
TA = 85°C
350
TA = 25°C
300
250
250
200
– 50
200
TA = 0°C
TA = –40°C
– 25
0
25
50
75
100
125
3
4
TA – Free-Air Temperature – °C
Figure 9
22
5
6
7
8
VI – Input Voltage – V
Figure 10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
10
10
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TPS7325
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
500
0.3
IL = 750 mA
TA = 25°C
TPS7330
0.25
TPS7333
400
Dropout Voltage – V
I Q– Quiescent Current – µ A
450
VI = 10 V
350
300
VI = 3.5 V
0.2
TPS7325
0.15
TPS7348
0.1
TPS7350
250
0.05
200
– 50
– 25
0
25
50
75
100
0
125
0
50 100 150 200 250 300 350 400 450 500
TA – Free-Air Temperature – °C
IO – Output Current – mA
Figure 11
Figure 12
TPS7301
CHANGE IN DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
8
1.6
IO = 100 mA
TA = 25°C
VI = 2.4 V
1.4
6
VDO – Dropout Voltage – V
∆ VDO– Change In Dropout Voltage – mV
10
4
2
0
–2
–4
–6
VI = 2.9 V
1
VI = 2.6 V
VI = 3.2 V
VI = 3.9 V
0.8
VI = 5.9 V
0.6
VI = 9.65 V
0.4
0.2
–8
– 10
– 50
1.2
– 25
0
25
50
75
100
125
0
0
TA – Free-Air Temperature – °C
50
100
150
200
IO – Output Current – mA
250
Figure 14
Figure 13
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
CHANGE IN OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
6
15
TA = 25°C
IO = 500 mA
VI = VO(nom) + 1 V
IO = 100 mA
TPS7350
5
10
VO – Output Voltage – V
∆ VO – Change in Output Voltage – mV
20
5
0
–5
– 10
TPS7348
4
3
TPS7333
TPS7301 With VO
Programmed to 2.5 V
and TPS7325
2
1
– 15
0
– 20
– 50
– 25
0
25
50
75
100
125
0
1
2
3
4
5
6
7
8
9
10
VI – Input Voltage – V
TA – Free-Air Temperature – °C
Figure 16
Figure 15
TPS7325
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
LINE REGULATION
3
20
TA = 25°C
∆VO– Change In Output Voltage – mV
100 mA
VO – Output Voltage – V
2.5
500 mA
2
1.5
1
0.5
0
0
1
2
3
4
5
6
7
8
9
10
TA = 25°C
IO = 250 mA
15
10
TPS7350
5
TPS7348
0
–5
TPS7333
TPS7325
– 10
– 15
– 20
4
VI – Input Voltage – V
8
6
7
VI – Input Voltage – V
Figure 18
Figure 17
24
5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
10
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TPS7301
TPS7325
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
2.52
2.515
2.515
2.51
VO – Output Voltage – V
VO – Output Voltage – V
2.52
TA = 25°C
VO Programmed to 2.5 V
2.505
2.5
VI = 3.5 V
2.495
VI = 10 V
2.49
2.51
VI = 10 V
2.505
2.5
2.495
VI = 3.5 V
2.49
2.485
2.485
2.48
2.48
0
100
200
400
300
500
0
100
IO – Output Current – mA
500
Figure 20
Figure 19
TPS7333
TPS7330
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.34
3.15
TA = 25°C
TA = 25°C
3.12
3.33
VO – Output Voltage – V
3.09
VO – Output Voltage – V
200
300
400
IO – Output Current – mA
3.06
3.03
3
2.97
2.94
3.32
3.31
VI = 10 V
3.3
VI = 4.3 V
3.29
3.28
2.91
3.27
2.88
2.85
3.26
0
100
200
300
400
500
0
IO – Output Current – mA
100
200
300
400
500
IO – Output Current – mA
Figure 21
Figure 22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TPS7348
TPS7350
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.06
4.92
4.9
5.04
4.89
5.03
VO – Output Voltage – V
VO – Output Voltage – V
5.05
TA = 25°C
4.91
4.88
4.87
VI = 5.85 V
4.86
4.85
VI = 10 V
4.84
5.02
5.01
4.99
4.82
4.96
4.81
4.95
4.94
100
200
400
300
500
VI = 10 V
4.98
4.97
0
VI = 6 V
5
4.83
4.8
TA = 25°C
0
100
IO – Output Current – mA
200
300
400
IO – Output Current – mA
Figure 23
Figure 24
6
VO(nom)
4
2
0
TA = 25°C
RL = 500 Ω
Co = 4.7 µF (CSR = 1Ω)
No Input Capacitance
6
4
2
0
–2
0
20
40
60
80 100 120 140
Time – µs
Figure 25
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
EN Voltage – V
VO – Output Voltage – V
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
500
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
LOAD TRANSIENT RESPONSE
200
100
0
TA = 25°C
VI = 6 V
CI = 0
Co = 4.7 µF (CSR = 1 Ω)
– 100
– 200
105
55
5
0
100
200
300
400
– 45
500
I O – Output Current – mA
∆VO – Change in Output Voltage – mV
TPS7301 (WITH VO PROGRAMMED TO 2.5 V) OR TPS7333
t – Time – µs
Figure 26
TPS7325
LOAD TRANSIENT RESPONSE
∆VO – Change in Output Voltage – mV
150
100
50
0
–50
– 100
∆IO = 100 mA
VI = 6 V
CI = 0
Co = 10 µF
TA = 25°C
–150
–200
– 250
–300 –200 –100
0
100 200
300 400
500
600
t – Time – µs
Figure 27
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
200
100
0
VI = 6 V
CI = 0
Co = 4.7 µF
CSR = 1 Ω
TA = 25°C
– 100
– 200
105
55
5
0
100
200
300
400
– 45
500
I O – Output Current – mA
∆VO – Change in Output Voltage – mV
TPS7348 OR TPS7350
LOAD TRANSIENT RESPONSE
t – Time – µs
TPS7301 WITH VO PROGRAMMED TO 2.5 V
LINE TRANSIENT RESPONSE
100
50
0
– 50
– 100
TA = 25°C
CI = 0
Co = 4.7 µF (CSR = 1 Ω)
6.5
6.25
6
0
100
200
300
t – Time – µs
Figure 29
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5.75
400
VI – Input Voltage – V
∆VO – Change in Output Voltage – mV
Figure 28
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
200
100
0
– 50
TA = 25°C
CI = 0
Co = 4.7 µF (CSR = 1 Ω)
– 100
6.5
6.25
6
0
100
200
300
400
5.75
500
V I – Input Voltage – V
∆VO – Change in Output Voltage – mV
TPS7333
LINE TRANSIENT RESPONSE
t – Time – µs
Figure 30
100
50
0
– 50
TA = 25°C
CI = 0
Co = 4.7 µF (CSR = 1 Ω)
– 100
6.5
6.25
6
0
100
200
300
400
5.75
500
V I – Input Voltage – V
∆VO – Change in Output Voltage – mV
TPS7348 OR TPS7350
LINE TRANSIENT RESPONSE
t – Time – µs
Figure 31
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
RIPPLE REJECTION
vs
FREQUENCY
OUTPUT SPECTRAL-NOISE DENSITY
vs
FREQUENCY
60
TPS7333
TPS7348/
TPS7350
Output Spectral-Noise Density – µV/ Hz
Ripple Rejection – dB
50
40
10
TA = 25°C
No Input
Capacitance Added
VI = VO + 1 V
IO = 100 mA
Co = 4.7 µF (CSR = 1)
TPS7301 With
VO Programmed
to 2.5 V
30
20
10
0
10
100
1K
10 K
100 K
1M
TA = 25°C
No Input Capacitance Added
VI = VO + 1 V
Co = 4.7 µF (CSR = 1 Ω)
1
Co = 10 µF (CSR = 1 Ω)
0.1
Co = 100 µF (CSR = 1 Ω)
0.01
10
10 M
100
f – Frequency – Hz
Figure 32
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)†
vs
OUTPUT CURRENT
COMPENSATION SERIES RESISTANCE (CSR)†
vs
ADDED CERAMIC CAPACITANCE
100
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
100 k
Figure 33
100
Region of Instability
10
1
TA = 25°C
VI = VO + 1 V
Co = 4.7 µF
No Added Ceramic Capacitance
No Input Capacitance Added
0.1
Region of Instability
0.01
0
50
100
Region of
Instability
10
TA = 25°C
VI = VO + 1 V
IO = 500 mA
Co = 4.7 µF
No Input Capacitor Added
1
0.1
Region of Instability
0.01
150
200
250
0
0.1
0.2 0.3 0.4 0.5
0.6 0.7 0.8
Added Ceramic Capacitance – µF
IO – Output Current – mA
Figure 34
30
1k
10 k
f – Frequency – Hz
Figure 35
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.9
1
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)†
vs
OUTPUT CURRENT
COMPENSATION SERIES RESISTANCE (CSR)†
vs
ADDED CERAMIC CAPACITANCE
100
Region of Instability
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
100
10
TA = 25°C
VI = VO + 1 V
Co = 10 µF
No Added Ceramic Capacitance
No Input Capacitor Added
1
0.1
Region of Instability
0.01
Region of
Instability
10
1
0.1
Region of Instability
0.01
0
50
100
150
200
250
0
0.1
0.2 0.3 0.4 0.5
Figure 36
VI – Minimum Input Voltage For Valid RESET – V
TA = 25°C
VI(FB) = 1.12 V
0.9
0.8
IO = 500 mA
0.6
0.5
IO = 100 mA
0.4
0.3
0.2
0.1
2
3
4
1
MINIMUM INPUT VOLTAGE FOR VALID RESET
vs
FREE-AIR TEMPERATURE
1.1
0.7
0.9
Figure 37
PASS-ELEMENT RESISTANCE
vs
INPUT VOLTAGE
1
0.6 0.7 0.8
Added Ceramic Capacitance – µF
IO – Output Current – mA
rDS(on) – Pass-Element Resistance – Ω
TA = 25°C
VI = VO + 1 V
IO = 500 mA
Co = 10 µF
No Input Capacitor Added
6
8
5
7
VI – Input Voltage – V
9
10
1.1
1.09
1.08
1.07
1.06
ÁÁ
ÁÁ
1.05
– 50
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
125
Figure 39
Figure 38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
NEGATIVE-GOING RESET THRESHOLD
vs
FREE-AIR TEMPERATURE
RESET OUTPUT CURRENT
vs
INPUT VOLTAGE
4
IL = 10 mA
VOL ≤ 0.4 V
TA = 25°C
3.5
I OL – RESET Output Current – mA
VIT– – Negative-Going Reset Threshold – mV
15
10
5
0
–5
ÁÁ
ÁÁ
– 10
– 15
– 50
3
2.5
2
TPS7350
1.5
TPS7348
1
TPS7333
0.5
– 25
0
25
50
75
100
0
125
0
1
2
TA – Free-Air Temperature – °C
3
4
5
6
7
8
9
10
VI – Input Voltage – V
Figure 40
Figure 41
RESET DELAY TIME
vs
FREE-AIR TEMPERATURE
DISTRIBUTION FOR RESET DELAY
50
197
TA = 25°C
197 Devices
45
196
Percentage of Units – %
td – Reset Delay Time – ms
40
195
194
193
192
35
30
25
20
15
10
191
190
– 50
5
– 25
0
25
50
75
100
TA – Free-Air Temperature –°C
125
0
180
Figure 42
32
185
200
205
190
195
td – Reset Delay Time – ms
Figure 43
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
210
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
THERMAL INFORMATION
In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch
surface-mount packages. Implementation of many of today’s high-performance devices in these packages requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat
sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation
limits of a given component.
Three basic approaches for enhancing thermal performance are illustrated in this discussion:
D Improving the power-dissipation capability of the PWB design
D Improving the thermal coupling of the component to the PWB
D Introducing airflow in the system
Figure 44 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout involves
adding copper on the PWB to conduct heat away from the device. The RθJA (thermal resistance, junction-to-ambient)
for this component / board system is illustrated in Figure 45. The family of curves illustrates the effect of increasing
the size of the copper-heat-sink surface area. The PWB is a standard FR4 board (L × W × H = 3.2 inch × 3.2 inch
× 0.062 inch); the board traces and heat sink area are 1-oz (per square foot) copper.
Figure 46 shows the thermal resistance for the same system with the addition of a thermally-conductive compound
between the body of the TSSOP package and the PWB copper routed directly beneath the device. The thermal
conductivity for the compound used in this analysis is 0.815 W/m × °C.
Using these figures to determine the system RθJA allows the maximum power-dissipation limit to be calculated with
the equation:
+ RJ(max)
D(max)
T
P
* TA
qJA(system)
Where
TJ(max) is the maximum allowable junction temperature; 150°C absolute maximum and 125°C
maximum recommended operating temperature for specified operation.
This limit should then be applied to the internal power dissipated by the TPS73xx regulator. The equation for
calculating total internal power dissipation of the TPS73xx is:
P
D(total)
ǒ
Ǔ
+ VI * VO
I
O
) VI
I
Q
Because the quiescent current of the TPS73xx family is very low, the second term is negligible, further simplifying
the equation to:
P
D(total)
ǒ
Ǔ
+ VI * VO
I
O
For a 20-lead TSSOP / FR4 board system with thermally conductive compound between the board and the device
body, where TA = 55°C, airflow = 100 ft /min, and copper heat sink area = 1 cm2, the maximum power-dissipation limit
can be calculated. As indicated in Figure 46, the system RθJA is 94°C/W; therefore, the maximum power-dissipation
limit is:
+ RJ(max)
D(max)
T
P
* TA
qJA(system)
ǒ
Ǔ
+ 12594° C° C*ń W55° C + 745 mW
If the system implements a TPS7348 regulator where VI = 6 V and IO = 150 mA, the internal power dissipation is:
P
D(total)
+ VI * VO
I
O
+ (6 * 4.85)
0.150
POST OFFICE BOX 655303
+ 173 mW
• DALLAS, TEXAS 75265
33
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
THERMAL INFORMATION
Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the maximum
limit. When it does, one of two corrective actions can be taken. The power-dissipation limit can be raised by increasing
either the airflow or the heat-sink area. Alternatively, the internal power dissipation of the regulator can be lowered
by reducing either the input voltage or the load current. In either case, the above calculations should be repeated with
the new system parameters.
Copper Heat Sink
1 oz Cu
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
AIR FLOW
190
Component /Board System
20-Lead TSSOP
0 cm2
170
1 cm2
150
2 cm2
130
110
90
4 cm2
8 cm2
70
50
0
50
100
150
200
250
300
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
AIR FLOW
RθJA – Thermal Resistance, Junction-to-Ambient – °C/W
RθJA – Thermal Resistance, Junction-to-Ambient – °C/W
Figure 44. Thermally Enhanced PWB Layout (not to scale) for the 20-Pin TSSOP
190
Component /Board System
20-Lead TSSOP
Includes Thermally Conductive
Compound Between Body and Board
170
150
0 cm2
130
8 cm2
110
2 cm2
90
50
0
50
100
150
200
Air Flow – ft /min
Figure 45
Figure 46
POST OFFICE BOX 655303
1 cm2
70
Air Flow – ft /min
34
4 cm2
• DALLAS, TEXAS 75265
250
300
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
APPLICATION INFORMATION
The TPS73xx series of low-dropout (LDO) regulators overcome many of the shortcomings of earlier generation
LDOs, while adding features such as a power-saving shutdown mode and a supply-voltage supervisor. The
TPS73xx family includes five fixed-output voltage regulators: the TPS7325 (2.5 V), TPS7330 (3 V), TPS7333
(3.3 V), the TPS7348 (4.85 V), and the TPS7350 (5 V). The family also offers an adjustable device, the TPS7301
(adjustable from 1.2 V to 9.75 V).
device operation
The TPS73xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even
with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly
proportional to the load current through the regulator (IB = IC/β). Close examination of the data sheets reveals
that such devices are typically specified under near no-load conditions; actual operating currents are much
higher as evidenced by typical quiescent current versus load current curves (see Figure 7). The TPS73xx uses
a PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents
are low and invariable over the full load range. The TPS73xx specifications reflect actual performance under
load.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in IB to maintain the load. During power-up, this translates
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS73xx quiescent current remains low even when the regulator drops out, thus eliminating both problems.
Included in the TPS73xx family is a 4.85-V regulator, the TPS7348. Designed specifically for 5-V cellular
systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems
specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack
before the device drops out, adding crucial talk minutes between charges.
The TPS73xx family also features a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent current to under 0.5 µA. When the
shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated
output voltage is reestablished in typically 120 µs.
minimum load requirements
The TPS73xx family is stable even at zero load; no minimum load is required for operation.
SENSE connection
The SENSE terminal of fixed-output devices must be connected to the regulator output for proper functioning
of the regulator. Normally, this connection should be as short as possible; however, the connection can be made
near a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a
high-impedance wide-bandwidth amplifier through a resistor-divider network, and noise pickup feeds through
to the regulator output. It is essential to route the SENSE connection in such a way as to minimize/avoid noise
pickup. Adding an RC network between SENSE and OUT to filter noise is not recommended because it can
cause the regulator to oscillate.
external capacitor requirements
An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load
transient response and noise rejection when the TPS73xx is located more than a few inches from the power
supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
APPLICATION INFORMATION
external capacitor requirements (continued)
As with most LDO regulators, the TPS73xx family requires an output capacitor for stability. A low-ESR 10-µF
solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the
full load range (see Figure 42). Adding high-frequency ceramic or film capacitors (such as power-supply bypass
capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum
capacitor is less than 1.2 Ω over temperature. Capacitors with published ESR specifications such as the
AVX TPSD106M035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at
25°C is 300 mΩ (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the
temperature drops from 25°C to – 40°C). Where component height and/or mounting area is a problem,
physically smaller, 10-µF devices can be screened for ESR. Figures 29 through 32 show the stable regions of
operation using different values of output capacitance with various values of ceramic load capacitance.
In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be
reduced to 4.7 µF, provided ESR is maintained between 0.7 and 2.5 Ω. Because capacitor minimum ESR is
seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limit
ESR to 1.5 Ω maximum. As shown in the CSR graphs (Figures 29 through 32), minimum ESR is not a problem
when using 10-µF or larger output capacitors.
Below is a partial listing of surface-mount capacitors usable with the TPS73xx family. This information, along
with the CSR graphs, is included to assist in selection of suitable capacitance for the user’s application. When
necessary to achieve low height requirements along with high output current and/or high ceramic load
capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
All load and temperature conditions with up to 1 µF of added ceramic load capacitance:
PART NO.
MFR.
VALUE
MAX ESR†
SIZE (H × L × W)†
T421C226M010AS
Kemet
22 µF, 10 V
0.5
2.8 × 6 × 3.2
593D156X0025D2W
Sprague
15 µF, 25 V
0.3
2.8 × 7.3 × 4.3
593D106X0035D2W
Sprague
10 µF, 35 V
0.3
2.8 × 7.3 × 4.3
10 µF, 35 V
0.3
2.8 × 7.3 × 4.3
TPSD106M035R0300 AVX
Load < 200 mA, ceramic load capacitance < 0.2 µF, full temperature range:
MFR.
VALUE
MAX ESR†
SIZE (H × L × W)†
592D156X0020R2T
Sprague
15 µF, 20 V
1.1
1.2 × 7.2 × 6
595D156X0025C2T
Sprague
15 µF, 25 V
1
PART NO.
2.5 × 7.1 × 3.2
595D106X0025C2T
Sprague
10 µF, 25 V
1.2
2.5 × 7.1 × 3.2
293D226X0016D2W
Sprague
22 µF, 16 V
1.1
2.8 × 7.3 × 4.3
Load < 100 mA, ceramic load capacitance < 0.2 µF, full temperature range:
MFR.
VALUE
MAX ESR†
SIZE (H × L × W)†
195D106X06R3V2T
Sprague
10 µF, 6.3 V
1.5
1.3 × 3.5 × 2.7
195D106X0016X2T
Sprague
10 µF, 16 V
1.5
1.3 × 7 × 2.7
595D156X0016B2T
Sprague
15 µF, 16 V
1.8
1.6 × 3.8 × 2.6
695D226X0015F2T
Sprague
22 µF, 15 V
1.4
1.8 × 6.5 × 3.4
695D156X0020F2T
Sprague
15 µF, 20 V
1.5
1.8 × 6.5 × 3.4
695D106X0035G2T
Sprague
10 µF, 35 V
1.3
2.5 × 7.6 × 2.5
PART NO.
† Size is in mm. ESR is maximum resistance at 100 kHz and TA = 25°C. Listings are sorted by height.
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
APPLICATION INFORMATION
external capacitor requirements (continued)
TPS73xxPW†
8
VI
IN
RESET
IN
SENSE
9
To System
Reset
15
10
IN
0.1 µF
20
OUT
6
EN
OUT
250 kΩ
14
VO
13
+
GND
1
2
3
10 µF
CSR = 1 Ω
† TPS7333, TPS7348, TPS7350 (fixed-voltage options)
Figure 47. Typical Application Circuit
programming the TPS7301 adjustable LDO regulator
Programming the adjustable regulators is accomplished using an external resistor divider as shown in
Figure 43. The equation governing the output voltage is:
V
O
+ Vref
ǒ) Ǔ
1
R1
R2
Where
Vref = reference voltage, 1.182 V typ
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
APPLICATION INFORMATION
Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2
is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent
advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at
FB will introduce an error. Solving for R1 yields a more useful equation for choosing the appropriate resistance:
R1
+
ǒ Ǔ
V
V
O
ref
*1
R2
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS7301
>2.7 V
VI
0.1 µF
IN
EN
RESET
To System
Reset
250 kΩ
OUT
VO
<0.5 V
R1
FB
GND
+
10 µF
CSR = 1 Ω
R2
OUTPUT
VOLTAGE
R1
R2
UNIT
2.5 V
191
169
kΩ
3.3 V
309
169
kΩ
3.6 V
348
169
kΩ
4V
402
169
kΩ
5V
549
169
kΩ
6.4 V
750
169
kΩ
Figure 48. TPS7301 Adjustable LDO Regulator Programming
undervoltage supervisor function
The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event
of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator
to detect the undervoltage condition. When that occurs, the RESET output transistor turns on taking the RESET
signal low.
On power up, the output voltage tracks the input voltage. The RESET output becomes active (low) as VI
approaches the minimum required for a valid RESET signal (specified at 1.5 V for 25°C and 1.9 V over full
recommended operating temperature range). When the output voltage reaches the appropriate positive-going
input threshold (VIT+), a 200-ms (typical) timeout period begins during which the RESET output remains low.
Once the timeout has expired, the RESET output becomes inactive. Since the RESET output is an open-drain
NMOS, a pullup resistor should be used to ensure that a logic-high signal is indicated.
The supply-voltage-supervisor function is also activated during power-down. As the input voltage decays and
after the dropout voltage is reached, the output voltage tracks linearly with the decaying input voltage. When
the output voltage drops below the specified negative-going input threshold (VIT– — see electrical
characteristics tables), the RESET output becomes active (low). It is important to note that if the input voltage
decays below the minimum required for a valid RESET, the RESET is undefined.
Since the circuit is monitoring the regulator output voltage, the RESET output can also be triggered by disabling
the regulator or by any fault condition that causes the output to drop below VIT–. Examples of fault conditions
include a short circuit on the output and a low input voltage. Once the output voltage is reestablished, either by
reenabling the regulator or removing the fault condition, then the internal timer is initiated, which holds the
RESET signal active during the 200-ms (typical) timeout period.
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
APPLICATION INFORMATION
undervoltage supervisor function (continued)
Transient loads or line pulses can also cause a reset to occur if proper care is not taken in selecting the input
and output capacitors. Load transients that are faster than 5 µs can cause a reset if high-ESR output capacitors
(greater than approximately 7 Ω) are used. A 1-µs transient causes a reset when using an output capacitor with
greater than 3.5 Ω of ESR. Note that the output-voltage spike during the transient can drop well below the reset
threshold and still not trip if the transient duration is short. A 1-µs transient must drop at least 500 mV below the
threshold before tripping the reset circuit. A 2-µs transient trips RESET at just 400 mV below the threshold.
Lower-ESR output capacitors help by reducing the drop in output voltage during a transient and should be used
when fast transients are expected.
NOTE:
VIT+ = VIT – +Hysteresis
output noise
The TPS73xx has very low output noise, with a spectral noise density < 2 µV/ √Hz. This is important when
noise-susceptible systems, such as audio amplifiers, are powered by the regulator.
regulator protection
The TPS73xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the
input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be
appropriate.
The TPS73xx also features internal current limiting and thermal protection. During normal operation, the
TPS73xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator
operation resumes.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS7301QD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7301QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7301QDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7301QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7301QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7301QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7301QPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7301QPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7301QPWLE
OBSOLETE
TSSOP
PW
20
TPS7301QPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7301QPWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7325QD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7325QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7325QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7325QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7325QPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7325QPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7325QPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7325QPWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7330QD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7330QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7330QDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7330QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7330QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7330QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TBD
Addendum-Page 1
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2008
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS7330QPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7330QPWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7333QD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7333QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7333QDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7333QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7333QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7333QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7333QPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7333QPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7333QPWLE
OBSOLETE
TSSOP
PW
20
TPS7333QPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7333QPWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7348QD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7348QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7348QDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7348QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7348QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7348QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7348QPWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
TPS7350QD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7350QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7350QDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7350QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7350QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7350QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7350QPWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
TBD
Addendum-Page 2
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
Call TI
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2008
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS7350QPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7350QPWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS7301QDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPS7301QPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TPS7325QPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TPS7330QDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPS7330QPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TPS7333QDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPS7333QPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TPS7348QDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPS7350QDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPS7350QPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7301QDR
SOIC
D
8
2500
367.0
367.0
35.0
TPS7301QPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
TPS7325QPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
TPS7330QDR
SOIC
D
8
2500
367.0
367.0
35.0
TPS7330QPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
TPS7333QDR
SOIC
D
8
2500
367.0
367.0
35.0
TPS7333QPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
TPS7348QDR
SOIC
D
8
2500
367.0
367.0
35.0
TPS7350QDR
SOIC
D
8
2500
367.0
367.0
35.0
TPS7350QPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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