TOTALLY RE-CONFIGURABLE ANALOG CIRCUIT - TRAC® TRAC020LH Issue 2 - MARCH 1999 • • • • DEVICE DESCRIPTION The TRAC020LH is a Micro-Power version of the existing TRAC products. It also offers significant improvements in bandwidth and function accuracy. The TRAC020LH is the latest addition to the TRAC family of Field Programmable Analog Devices (FPAD) which offers an integrated path from signal processing problems to working silicon solutions - in minutes! The Totally Reconfigurable Analog Circuit is a highly flexible single chip solution to the signal processing problems found in many markets. Instrumentation Transducer Characteristic Correction Vector Analysis FEATURES AND BENEFITS • • • • Introducing a Top-Down, Structured design discipline, TRAC enables rapid implementation, prototyping and product release. Rather than working at the component level, TRAC champions the Computational Approach, providing designers with benefits formerly associated with programmable digital devices. TRAC brings a truly integrated Signal Processing problem solving process and offers a path to Custom Silicon for high volume applications. • • • • • • • • • APPLICATIONS Many analog signal processing applications including:- • • • • • • • Log, Linear and Modern Filter Design Analog Computation Analog Signal Processing (ASP) Faster design and verification of signal processing solutions Instant working silicon Flexibility to react to changing requirements Stay thinking about analog problems mathematically - minimal circuit design Just as versatile as FPGA - and just as easy Complete more projects on time High level of integration and design secrecy Integration with other CAE systems Transparent design migration to semi-custom and future devices Less than 8 bytes to program Full industrial temperature range Standby mode for improved battery life Devices easily cascaded for more complex designs Classical & Modern Control Systems • Audio Applications ORDERING INFORMATION Sonar and Ultrasonic Systems Combines silicon, software and support PART NUMBER PACKAGE PART MARK TRAC020LHQ36 QSOP36 TRAC020LH Analog Correlation Echo Cancellation For more information on Fast Analog Solutions and all our products see www.fas.co.uk 1 TRAC020LH ABSOLUTE MAXIMUM RATINGS Voltage on any pin = 7.0V (relative to VSS) Operating Temperature = -40 to 85°C Storage Temperature = -55 to 125°C GENERAL ELECTRICAL CHARACTERISTICS Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = -2.0V±0.10V PARAMETER CONDITIONS MIN TYPICAL MAX General Characteristics Dynamic Range 80dB 15nV/√ Hz Noise Voltage 10Hz-100kHz Total Harmonic Distortion 100mV peak-peak 1.0V peak-peak 0.02% 0.08% Intermodulation Distortion < 0.1% Supply Rejection 60dB Cell to cell crosstalk -60dB Input Range (all IO pins) VDD -2.0V, VSS +1.0V Slew Rate 4V/µS Supply Current Operating Current IDD Cells to NIP function PD=VDD Operating Current ISS Shutdown Current IDD 2.5mA 5.0mA 6.0mA -2.5mA -5.0mA -6.0mA PD=VSS 10µA Cell Output Capability Sink Current 150µA Source Current 150µA 2 TRAC020LH ELECTRICAL CHARACTERISTICS OF THE CELL Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V FUNCTION Non Inverting Pass PARAMETER Gain CONDITIONS Vin = ±800mV MIN 0.996 Input Resistance Offset Vin=0mV -1.2mV 100nA 260nA 12MHz Bandwidth (large signal) 500mV peak-peak 3MHz Gain Vin = ±800mV -1.010 -1.000 -0.990 30kΩ 40kΩ 50kΩ -2.4mV 0mV 2.4mV Offset Vin=0mV Bandwidth(small signal) 20mV peak-peak 7MHz Bandwidth(large signal) 500mV peak-peak 3MHz Gain VA=VB =±400mV -1.012 -1.000 -0.988 30kΩ 40kΩ 50kΩ 0mV 3.4mV Offset Vin=0mV Bandwidth (small signal) 20mV peak-peak -3.4mV 6MHz Bandwidth (large signal) 500mV peak-peak 3MHz Output Voltage Vin =±1.000V ±625 mV Input Resistance ±685 mV 30kΩ 40kΩ Gain RF = RS =20kΩ, -0.993 Input Current RF = RS =20kΩ, Vin = 0 mV 100nA RF = RS =20kΩ, Vin = 0mV 2.0mV Offset Output Saturation Voltage Vin =±50mV <VSS+0.2V Open Loop 300 3 ±745 mV ±60mV Transfer Characteristic Vin =±10mV, (Change in output for a 10x ±100mV,±1000mV change in input voltage) Auxiliary 1.2mV 20mV peak-peak Input Resistance Log 1.004 0mV Bandwidth (small signal) Input Resistance Add 1.000 MAX 60MΩ Input Current Negate TYPICAL 50kΩ >VDD-1.7V 700 TRAC020LH ELECTRICAL CHARACTERISTICS OF THE CELL (Continued) Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V FUNCTION PARAMETER CONDITIONS MIN Output Voltage Vin = ±685mV Transfer Characteristic (Multiplication of the output voltage for fixed steps in input voltage) Vin =±565mV, ±625mV, ±685mV steps Output Voltage Vin = −685mV Vin = 685mV Transfer Characteristic (Multiplication of the output voltage for fixed steps in input voltage) Vin =−565mV, −625mV, −685mV steps Off Attenuation Vin =±1.0V LOG/ALOG Gain Vin= ±1.0V 1.00 Bandwidth (small signal) 20mV peak-peak 6MHz Bandwidth (large signal) 500mV peak-peak 2MHz Gain Vin= ±1.0V 1.00 Bandwidth (small signal) 20mV peak-peak 6MHz Bandwidth (large signal) 500mV peak-peak 2MHz Alog Rectify LOG/REC ± 0.80V TYPICAL ±1.00V MAX ±1.2V ±10 +0.80V -5.0mV +1.00V +1.2V 5.0mV +10 -60dB -80dB ELECTRICAL CHARACTERISTICS OF THE LOGIC FUNCTIONS(VDD-VSS=5.0V±0.25V) FUNCTION CONDITIONS MIN TYPICAL MAX (VOH (for output pins DOUT, CLCR ) IOH=-4mA 4.0V (WRT VSS) 5.0V (WRT VSS) VOL (for outputs DOUT, CLCR IOH=4mA 0.0V (WRT VSS) 0.4V (WRT VSS) IIH (for inputs DATA CLOCK, RESET,PD ) VIH=5V (WRT VSS) IIL (for inputs DATA CLOCK, RESET,PD ) VIL=0V (WRT VSS) 1.0µA -1.0µA Max. CLOCK frequency 10MHz 4 TRAC020LH DESCRIPTION OF PIN FUNCTIONS DATA Serial programming data is input to the TRAC via this pin. Each TRAC cell contains a 3-bit shift register that allows each cell to be programmed to the required analog function. RESET Active low - The pin resets all on-chip shift registers to the logic zero state, which sets all TRAC cells to the OFF function. The pin should be held high while the device is being programmed and when the analog functions are in use. PD Active low - The pin switches off the bias generators to the analog cells, which turns off the supply current to all the TRAC cells. This does not influence the programming of the cells so this feature can be used to reduce power consumption for applications that have a standby mode. The pin should be held high while the device is being programmed and when the analog functions are in use. This pin is permanently held high (VDD) on the TRAC development board. CLOCK Used to clock in the serial data to program the TRAC device. The on-chip shift registers are positive edge triggered. DOUT This pin is the serial data output from cell 20 on the TRAC device. This is used for validation of programming of the TRAC device. This pin also allows two or more TRAC devices to be connected in a serial architecture. This is done by connecting the DOUT pin of the first TRAC device to the DATA pin of the second TRAC device, and connecting the CLOCK pins. CLCR Clock Clear. When the TRAC device is used in stand alone applications CLCR is used as a control pin. It allows the downloading circuitry to be switched off when the programming serial data from the EEPROM is complete. IO3..IO22 These are the analog inputs / outputs for cells 1 to 20. IO1,IO2 These are the analog inputs for cells 1 and 2. VDD TRAC positive supply rail (+3V) AGND Analog Ground VSS TRAC negative supply rail (-2V) - this will also be the system ground 5 TRAC020LH CELL FUNCTION DETAILS ADD (code 011) Can be represented as an operational amplifier with three resistors of equal value R. The virtual earth at the inverting input gives:Eo = -R(Ea/R + Eb/R) = - (Ea + Eb) The output is the inverted sum of the input voltages. NEGATE (code 010) The negate function is provided by an adder, but with only one input, therefore Eo=-Eb NON INVERTING PASS (code 100) Used for topological reasons. It provides a route through the cell with no modification. i.e. a unity gain amplifier LOG (code 110) Can be represented as an operational amplifier with a pair of back to back diodes in the negative feedback loop and an input resistor R. The virtual earth at the inverting input gives:Eo = -kT/q log (Ea/RIo + 1) where k = Boltzmann’s constant T = absolute temperature q = electron charge Io=saturation current ANTI - LOG (code 101) Similar to the log circuit except that the diodes and resistors are reversed. The output voltage is therfore given as :Eo = -RIo (exp qEa/KT - 1) When the signal is processed through both log and anti-log the magnitude of the saturation current and absolute temperature cancel. 6 TRAC020LH CELL FUNCTION DETAILS (Continued) RECTIFIER (code 111) Similar to the anti-log function except that one of the diodes is removed so that a positive input gives zero output. AUX (code 001) As for an operational amplifier external components are used to provide the following functions - external components are shown dotted Amplification Attenuation Differentiation Integration OFF (code 000) In the off condition there is no signal path through the cell. 7 TRAC020LH TRAC020LH SCHEMATIC DIAGRAM TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Cell Frequency Responses, Small Signal Amplitude 20mV Pk-Pk 3 12 0 6 -3 0 Gain (dB) Gain (dB) Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V -6 -9 -12 -6 -12 -18 -15 -24 10 100 1000 10000 100000 10 Frequency (kHz) 10000 100000 NEG Small Signal Bandwidth 12 12 6 Gain (dB) 6 Gain (dB) 1000 Frequency (kHz) NIP Small Signal Bandwidth 0 -6 -12 0 -6 -12 -18 -18 -24 10 100 1000 10000 100000 10 Frequency (kHz) 100 1000 10000 100000 Frequency (kHz) ADD Small Signal Bandwidth AUX Small Signal Bandwidth (RS=RF=20K, RS Shunts preceeding OFF cell) (for both A and B inputs) 12 12 6 6 Gain (dB) Gain (dB) 100 0 -6 -12 0 -6 -12 -18 -18 10 100 1000 10000 10 100000 Frequency (kHz) 100 1000 10000 100000 Frequency (kHz) LOG/ALOG Small Signal Bandwidth LOG/REC Small Signal Bandwidth (26mV DC Biased) (26mV DC Biased) 10 TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Cell Phase Delay, Small Signal Amplitude 20mV Pk-Pk 45 225 0 180 Phase (Degrees) Phase (Degrees) Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V -45 -90 -135 -180 135 90 45 0 10 100 1000 10000 100000 10 Frequency (kHz) 10000 100000 NEG Phase Shift V Frequency 225 225 180 180 Phase (Degrees) Phase (Degrees) 1000 Frequency (kHz) NIP Phase Shift V Frequency 135 90 45 0 135 90 45 0 10 100 1000 10000 100000 10 Frequency (kHz) 100 1000 10000 100000 Frequency (kHz) AUX Phase Shift V Frequency ADD Phase Shift V Frequency (RS=RF=20K, RS Shunts preceeding OFF Cell) (For both A and B inputs) 45 45 0 0 Phase (Degrees) Phase (Degrees) 100 -45 -90 -135 -180 -225 -45 -90 -135 -180 -225 -270 -270 10 100 1000 10 10000 Frequency (kHz) 100 1000 10000 Frequency (kHz) LOG/REC Phase Shift V Frequency LOG/ALOG Phase Shift V Frequency (26mV DC Biased) (26mV DC Biased) 11 TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Cell Offset Voltage against Temperature CharacteristicsTest Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V 0.4 Offset Voltage (mV) Offset Voltage (mV) 0.2 0 -0.2 -0.4 -40 -20 0 20 40 60 80 0.2 0 -0.2 -0.4 -0.6 -0.8 -40 100 -20 Temperature (°C) NIP Offset Voltage V Temp. Offset Voltage (mV) Offset Voltage (mV) 60 80 100 -0.2 -0.4 -20 0 20 40 60 80 80 100 80 100 0 -0.1 -0.2 -0.3 -40 100 -20 Temperature (°C) 0 20 40 60 Temperature (°C) ADD Offset Voltage Vs Temp. AUX Offset Voltage V Temp. 0.4 Offset Voltage (mV) 0.2 Offset Voltage (mV) 40 0.1 0 0.1 0 -0.1 -0.2 -40 20 NEG Offset Voltage V Temp. 0.2 -0.6 -40 0 Temperature (°C) -20 0 20 40 60 80 0.2 0 -0.2 -0.4 -40 100 Temperature (°C) -20 0 20 40 60 Temperature (°C) LOG/ALOG Offset Voltage V Temp. LOG/REC Offset Voltage V Temp. 12 TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Cell Voltage Gain against Temperature Characteristics Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V 0.1 -0.1 Gain Error (%) Gain Error (%) 0.09 0.08 0.07 0.06 0.05 -40 -20 0 20 40 60 80 0 20 40 60 80 NIP Gain Error V Temp. NEG Gain Error V Temp. 100 1000 Differential Gain Gain Error (%) -20 Temperature (° C) 0 -0.05 -0.1 -20 0 20 40 60 80 900 800 700 600 -40 100 -20 0 20 40 60 80 Temperature (°C) Temperature (°C) ADD Gain Error V Temp. AUX Open Loop Gain V Temp. 3 100 2 2.5 1.6 Gain Error (%) Gain Error (%) -0.25 Temperature (°C) 0.05 2 1.5 1 1.2 0.8 0.4 0.5 0 -40 -0.2 -0.3 -40 100 0.1 -0.15 -40 -0.15 -20 0 20 40 60 80 0 -40 100 -20 0 20 40 60 80 Temperature (°C) Temperature (°C) LOG/ALOG Gain Error V Temp. LOG/REC Gain Error V Temp. 13 100 TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Cell DC Transfer Characteristics 1000 1000 750 750 500 500 Vout (mV) Vout (mV) Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V 250 0 -250 -500 250 0 -250 -500 -750 -750 -1000 -1000 0 -500 500 -1000 -1000 1000 0 -500 Vin (mV) 800 800 600 600 400 400 200 0 -200 -400 200 0 -200 -400 -600 -600 -800 -400 -800 -1000 0 -200 200 400 -100 500 Vout (mV) 750 250 0 -250 250 0 -250 -500 -500 -750 -750 500 560 620 -1000 -680 680 Vin (mV) ≈ ≈ -500 1000 ≈ ≈ 1000 500 -560 100 LOG DC Transfer Characteristics 750 -620 10 Log Vin (mV) ADD DC Transfer Characteristics 1000 0 -10 Va = Vb (mV) Vout (mV) 1000 NEG DC Transfer Characteristics Vout (mV) Vout (mV) NIP DC Transfer Characteristics -1000 -680 500 Vin (mV) -620 -560 -500 500 560 620 Vin (mV) ALOG DC Transfer Characteristics REC DC Transfer Characteristics 14 680 TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Settling Performance for Power Down and Data Clocking Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V 1.4 0.4 0.2 Input = +800mV Output Voltage (v) Output Voltage (v) 1.2 1.0 0.8 0.6 0.4 PD = VDD 0.2 PD = VDD PD = VSS 0.0 -0.2 Input = -800mV -0.4 -0.6 -0.8 PD = VSS -1.0 0.0 0 200 100 300 400 500 600 0 50 100 NIP Power Down Response Output Voltage (v) Output Voltage (v) 0.4 Vin = 800mV Switched to NIP @ t = 0uS 0.0 -0.4 -0.8 0 0.5 1.0 0 -0.4 -0.8 -1.2 -1.6 -0.5 1.5 Vin = -800mV Switched to NIP @ t = 0 µS 0 0.5 1.0 1.2 1.2 Output Voltage (v) OFF Cell to NIP Cell Response 0.8 Input = 800mV Switched to NEG @ t = 0uS 0.4 0.0 -0.4 -0.8 0 0.5 1.5 Time (µS) OFF Cell to NIP Cell Response -1.2 -0.5 250 0.4 0.8 Time (µS) Output Voltage (v) 200 NIP Power Down Response 1.2 -1.2 -0.5 150 Time (µS) Time (µS) 1.0 0.8 0.4 -0.4 -0.8 -1.2 -0.5 1.5 Time (µS) Input = -800mV Switched to NEG @ t = 0uS 0.0 0 0.5 1.0 Time (µS) NIP Cell to NEG Cell Response NIP Cell to NEG Cell Response 15 1.5 TRAC020LH CONNECTION DIAGRAM QSOP 36 Lead Note: For clarity the IO pin definition has been changed from previous issue TOP VIEW (NOT TO SCALE) PACKAGING INFORMATION A C E B D H P IN N o. 1 0 J .1 3(.005) F I K Fast Analog Solutions Ltd. Fields New Road, Chadderton, Oldham, OL9 8NP, United Kingdom. Tel: (+44) (0) 161 622 4567 Fax: (+44) (0) 161 622 4568 e-mail: [email protected] Internet: http://www.fas.co.uk TRAC products are supported by agents and distributors in many countries of the world. Details can be found on our web site. A ZETEX GROUP COMPANY This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of any product or service. 16