TI UCC28251PWT

UCC28251
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SLUSBD8D – FEBRUARY 2013 – REVISED APRIL 2013
Advanced PWM Controller With Pre-Bias Operation
Check for Samples: UCC28251
FEATURES
DESCRIPTION
•
•
The UCC28251 PWM controller is designed for high
power density applications that may have stringent
pre-biased startup requirements. The UCC28251’s
integrated synchronous rectifier control outputs target
high efficiency and high performance topologies such
as half-bridge, full-bridge, interleaved forward, and
push-pull. The UCC27210 half bridge drivers and
UCC2752x MOSFET drivers used in conjunction with
the UCC28251 provide a complete power converter
solution.
1
•
•
•
•
•
•
•
Pre-biased Startup
Synchronous Rectifier Control Outputs with
Programmable Delays (Including Zero Delay
Support)
Voltage Mode Control with Input Voltage FeedForward or Current Mode Control
Primary or Secondary-Side Control
3.3-V, 1.5% Accurate Reference Output
Lower Minimum Operating Frequency
1% Accurate Cycle-by-Cycle Over Current
Protection with Matched Duty Cycle Outputs
Programmable Soft-Start and Hiccup Restart
Timer
Thermally Enhanced 4-mm x 4-mm QFN-20
Package and 20-pin TSSOP Package
The UCC28251 is a functional variant of the
UCC28250 PWM Controller. While the same basic
functionality of the UCC28250 is largely maintained,
the UCC28251 is designed to enhance performance
in both offline, 400-V input DC-to-DC applications and
48-V input full-bridge or half-bridge applications.
Externally
programmable
soft-start,
used
in
conjunction with an internal pre-biased startup circuit,
allows the controller to gradually reach a steady-state
operating point under all output conditions. The
UCC28251 can be configured for primary or
secondary-side control and either voltage or current
mode control can be implemented.
APPLICATIONS
•
•
•
•
•
Half-Bridge, Full-Bridge, Interleaved Forward,
and Push-Pull Isolated Converters
Telecom and Data-com Power
Wireless Base Station Power
Server Power
Industrial Power Systems
The oscillator operates at frequencies up to 1.8 MHz,
and can be synchronized to an external clock. Input
voltage feedforward, cycle-by-cycle current limit, and
a programmable hiccup timer allow the system to
stay within a safe operation range. Input voltage,
output voltage and temperature protection can be
implemented. Dead time between primary-side switch
and secondary-side synchronous rectifiers can be
independently programmed.
Simple Application Diagram (400-VIN DC-to-DC Converter)
Secondary
Primary
Secondary
400 V
700-V Driver
UCC28251
OUTA
VREF
HI
HO
LI
LO
VOUT
Isolation
OUTB
RAMP
Secondary
RT
SRA
SS
SRB
UCC2752x
VSENSE
FB
GND
Not Shown : PS, SP, HICC, VDD , EA+, EN AND ILIM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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UCC28251
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Simple Application Diagram (48-VIN DC-to-DC Converter)
VIN (36 V ~ 48 V)
VIN (36 V ~ 48 V)
UCC27210A
UCC28251
OVP
OUTA
HI
HI
RAMP
OUTB
LO
LO
RT
SRA
SS
SRB
VOUT
Isolation
UCC272x
Feedback and Isolation
COMP
GND
Not Shown : PS, SP, HICC, VDD, EA+, EA-, VREF , EN, ILIM, AND VSENSE
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TEMPERATURE RANGE
TA = TJ
PACKAGE
Plastic 20-pin QFN (RGP)
-40°C to 125°C
Plastic 20-pin TSSOP (PW)
2
TAPE AND REEL QTY
PART NUMBER
250
UCC28251RGPT
3000
UCC28251RGPR
250
UCC28251PWT
3000
UCC28251PWR
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (1) (2) (unless otherwise noted)
PARAMETER
VDD
(3)
HBM
CDM
VALUE
Input supply voltage
-0.3 to 20.0
OUTA, OUTB, SRA and SRB
-0.3 to VDD + 0.3
COMP
-0.3 to VREF + 0.3
Input voltages on SS and EN
-0.3 to 5.5
Input voltages on RT, PS, SP, ILIM, OVP, HICC, VSENSE, EA+ and EA-
-0.3 to 3.6
Input voltage on RAMP/CS
-0.3 to 4.3
Output voltage on VREF
-0.3 to 3.6
(2)
(3)
V
3k
ESD rating
2k
Lead temperature (soldering 10 sec) PW package
(1)
UNIT
300
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
THERMAL INFORMATION
UCC28251
UCC28251
RGP
PW (1)
20 PINS
20 PINS
126 with hot spot,
104 without hot spot
60.3 with hot spot,
39.3 without hot spot
THERMAL METRIC
θJA
Junction-to-ambient thermal resistance (2)
θJC(top)
Junction-to-case(top) thermal resistance
θJB
Junction-to-board thermal resistance
θJC(bottom)
Junction-to-case(bottom) thermal resistance
(1)
(2)
(3)
(4)
(5)
(3)
31.5
(4)
UNITS
°C/W
55.8
(5)
0.8
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage range, VDD
TYP
4.7
Supply bypass capacitor, CVDD
MAX
12
UNIT
17
V
1
VREF bypass capacitor
0.47
2.20
Error amplifier input common mode range (REF/EA+, FB/EA-)
0
3.0
VSENSE input voltage range
0
3.3
12.5
200
5
250
RT resistor range
PS, SP resistor range
RAMP/CS voltage range
Operating junction temperature range
µF
V
kΩ
0
2.3
V
-40
150
°C
ELECTRICAL CHARACTERISTICS (1)
VDD = 12 V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = -40°C to 125°C, RT = 75 kΩ connected to ground to set
FSW = 200 kHz (unless otherwise noted).
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Supply Currents
IDD(off)
Startup current
VDD = 3.6 V
150
275
µA
IDD
Operating supply current
100-pF capacitor on OUTA, OUTB, SRA and SRB
1.2
2.0
2.5
mA
IDD(dis)
Standby current
EN = 0 V
250
425
600
µA
4.00
4.30
4.65
3.8
4.1
4.4
0.15
0.20
0.25
Under Voltage Lockout
VUVLOR
Start threshold
VUVLOF
Minimum operating voltage
after start
Hysteresis
V
Soft Start
ISS
Soft-start charge current
26
28
30
µA
VSS(max)
Clamp voltage
VSS = 0 V
3.3
3.6
4.0
V
Trigger threshold
1.5
2.0
2.25
V
Minimum pulse width for
pulse enable
3.2
Enable (2)
µs
Error Amplifier
High-level COMP voltage
2.8
Low-level COMP voltage
3
0.3
Input offset
-16.2
0.4
18.0
Open loop gain
70
100
ICOMP(snk)
COMP sink current
3.0
6.5
9.0
ICOMP(src)
COMP source current
2.0
4.5
8.0
(1)
(2)
4
V
mV
dB
mA
Typical values for TA = 25°C.
Refer to EN pin description.
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ELECTRICAL CHARACTERISTICS(1) (continued)
VDD = 12 V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = -40°C to 125°C, RT = 75 kΩ connected to ground to set
FSW = 200 kHz (unless otherwise noted).
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Oscillator
FSW(nom)
Nominal switching frequency
at OUTA or OUTB set by RT
resistor
FSW(min_sync)
Minimum switching frequency
at OUTA or OUTB set by
fRT/SYNC = 50 kHz
external sync frequency
FSW(max_sync)
Maximum switching
frequency at OUTA or OUTB
set by external sync
frequency
RT/SYNC = 75 kΩ, RSP = 20 kΩ
90
106
42
fRT/SYNC = 2.5 MHz
External synchronization
signal high
98
kHz
945
1
V
External synchronization
signal low
0.2
Voltage Reference
VVREF
Output voltage
Short circuit current
VDD = from 7 V to 17 V, IVREF = 2 mA
3.17
3.25
3.33
0 < IREF < 10 mA
3.17
3.25
3.33
12
25
40
0.497
0.505
0.513
15
25
36
12.3
25.0
38.7
35
60
90
VREF = 3 V, TJ = 25°C
V
mA
Current Sense, Cycle-by-Cycle Current Limit With Hiccup
VILIM
ILIM cycle-by-cycle threshold
TPDILIM
Propagation delay from ILIM
to OUTA and OUTB outputs
TBLANK
leading edge blanking
Exclude leading edge blanking (UCC28251RGP)
Exclude leading edge blanking (UCC28251PW)
Current limit shutdown delay
timing program current
Measured at HICC pin
55
75
95
Hiccup timing program
current
Measured at HICC pin
2.0
2.7
3.5
V
ns
µA
VHICC_SD
Current limit shutdown delay
timer threshold at HICC
0.55
0.60
0.65
VHICC_PU
HICC pull-up threshold
2.25
2.40
2.50
VHICC_RST
Hiccup restart threshold
0.25
0.30
0.35
VCS(max)
RAMP/CS clamp voltage
3.5
4.0
4.5
10-V ramp charging voltage source with 40-kΩ
current limiting resistor
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5
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ELECTRICAL CHARACTERISTICS(1) (continued)
VDD = 12 V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = -40°C to 125°C, RT = 75 kΩ connected to ground to set
FSW = 200 kHz (unless otherwise noted).
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
OVP/OTP Comparator
VOVP
Internal reference
IOVP
Internal current
0.66
0.70
0.74
V
6.0
8.5
11.0
µA
Primary Outputs
Rise/fall time
CLOAD = 100 pF
8
ns
RSRC
Output source resistance
IOUT = 20 mA
12
20
35
RSNK
Output sink resistance
IOUT = 20 mA
4
12
30
IOUT = 20 mA, VDD = 12 V
12
20
35
IOUT = 20 mA, VDD = 5 V
15
25
45
Ω
Synchronous Rectifier Outputs
Rise/fall time
RSRC
Output source resistance
RSNK
Output sink resistance
TDPS
TDSP
6
Primary off to secondary on
dead time
Secondary off to primary on
dead time
CLOAD = 100 pF
IOUT = 20 mA, VDD = 12 V
8
ns
4
12
30
PS = VREF
-5.0
0
7.5
PS = 27 kΩ
25
38
48
PS = 27 kΩ, 25°C
32
38
43
SP = VREF
-5.0
0
7.5
SP = 20 kΩ
33
43
55
SP = 20 kΩ, 25°C
39
43
48
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Ω
ns
ns
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DEVICE INFORMATION
Over
temperature
OUTA
OUTB
SRA
SRB
Functional Block Diagram
9
8
7
6
OTP
+
4.1V/4.3V
UVLO
VDD 5
Vref OK
COMP
2
FB/EA-
1
REF/EA+
EN_INT
Switching Logic
LDO
OP
+
+
OCP
VREF 20
3
Vref ready
+
Enable detection
Level&pulse
EN 18
+
Cycle by cycle
current limit
& duty cycle match
+
0.5V
OCP delay
timer
420 mV
HICC 10
8.5 mA
SS
16
RAMP/CS
14
VSENSE
BLANK
SR_RAMP
ILIM 17
Enable
13
SR_RAMP
generator
gm
+
+
Hiccup
timer
4
OVP/OTP 19
+
0.7V
OVP
RT 15
CLK
Oscillator
SP 12
PS 11
GND
70ns
leading edge blanking
BLANK
Deadtime
NOTE
Pin numbers are used for RGP package. PW package has different pin numbers.
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+
Typical Application Diagram
Figure 1. Primary-Side Half-Bridge Controller with Synchronous Rectification
8
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Figure 2. Secondary-Side Half-Bridge Controller with Synchronous Rectification
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DEVICE INFORMATION
Pinout Drawings
TSSOP-20
TOP VIEW
QFN-20
TOP VIEW
RT VSENSE SS
SP
PS
15
12
11
14
13
RAMP/CS 16
10 HICC
ILIM 17
9
OUTA
EN 18
8
OUTB
OVP/OTP 19
7
SRA
VREF 20
6
SRB
1
2
3
4
REF/EA+ FB/EA- COMP GND
10
5
VDD
VSENSE
1
20 SS
RT
2
19 SP
RAMP/CS
3
18 PS
ILIM
4
17 HICC
EN
5
16 OUTA
OVP/OTP
6
15 OUTB
VREF
7
14 SRA
REF/EA+
8
13 SRB
FB/EA-
9
12 VDD
COMP 10
11 GND
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TERMINAL FUNCTIONS
QFN-20
PW-20
NAME
I/O
FUNCTION
5
12
VDD
I
Bias supply input.
20
7
VREF
O
3.3-V reference output.
18
5
EN
I
Device enable and disable.
15
2
RT
I
Oscillator frequency set or synchronous clock input.
12
19
SP
I
Synchronous rectifier off to primary on dead-time set .
11
18
PS
I
Primary off to synchronous rectifier on dead-time set .
16
3
RAMP/CS
I
PWM ramp input (for voltage mode control) or current sense input (for current
mode control).
1
8
REF/EA+
I
Error amplifier non-inverting input.
2
9
FB/EA-
I
Error amplifier inverting input.
3
10
COMP
I/O
14
1
VSENSE
I
Error amplifier output.
13
20
SS
I/O
17
4
ILIM
I
Current sense for cycle-by-cycle over-current protection.
10
17
HICC
I
Cycle-by-cycle current limit time delay and Hiccup time setting.
19
6
OVP/OTP
I
Over voltage and over temperature protection pin.
9
16
OUTA
O
0.2-A sink/source primary switching output.
8
15
OUTB
O
0.2-A sink/source primary switching output.
7
14
SRA
O
0.2-A sink/source synchronous rectifier output.
6
13
SRB
O
0.2-A sink/source synchronous rectifier output.
4
11
GND
I
Ground.
Output voltage sensing for pre-bias control.
Soft-start programming.
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DETAILED PIN DESCRIPTIONS
VDD (5/12)
The UCC28251 can be powered up by a wide supply range from 4.3 V (UVLO rising typical) to 20 V (absolute
maximum), making it suitable for primary-side control or secondary-side control. When the voltage at the VDD
pin is lower than 4.1 V (typical), the controller is in stand-by mode and consumes 150 µA (typical) at 3.6 V VDD.
In stand-by mode, VREF continues to be regulated to 3.3 V or follows VDD if VDD is lower than 3.3 V. Please
refer to the VREF description for more detailed information. A minimum 1-µF bypass capacitor is required from
VDD to ground. Keep the bypass capacitor as close to the device as possible.
VREF (Reference Generator) (20/7)
The VREF pin is regulated at 3.3 V. An external ceramic capacitor must be placed as close as possible to the
VREF and GND pins for noise filtering and to provide compensation to the regulator. The capacitance range
must be limited between 0.47 µF to 2.2 µF for stability. This reference is used to power the controller’s internal
circuits, and can also be used to bias an opto-coupler transistor, an external house-keeping microcontroller, or
other peripheral circuits. This reference can also be used to generate the reference for an external error
amplifier. This regulator output is internally current limited to 25 mA (typical).
EN (Enable Pin) (18/5)
The following conditions must be met before the controller allows start up:
1. VDD voltage has been sustained above the rising UVLO threshold 4.3 V (typical);
2. The 3.3-V reference voltage output at the VREF pin is 2.4 V (typical) for at least 20 us;
3. Junction temperature is below the thermal shutdown threshold 130°C (minimum);
4. The voltage at OVP is below 0.7 V (typical).
If all these conditions are met, the signal driving the EN pin is able to initiate the soft start process. Once the
device is enabled, the 27-µA internal charging current at the SS pin is turned on and begins to charge the softstart capacitor. The EN pin can accept both level-enable and pulse-enable signals.
For level-enable, the voltage level on the EN pin needs to be continuously higher than 2.25 V to allow continuous
operation. Once the EN pin falls below threshold, the device is disabled after 2 µs (see Figure 3).
UVLO
EN
SS
0.3V
CLK
Figure 3. Level Enable at EN pin
12
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A pulse signal may also be applied to the EN pin. Pulse-enable operation is shown on Figure 4. If the EN falling
edge happens before the SS voltage reaches 0.3 V, the enable signal at EN pin is considered as a pulse. In this
case, the next rising edge at EN pin disables the controller. If the falling edge of the first pulse at EN pin happens
after SS rises to 0.3 V, the UCC28251 interprets the pulse enable as a level enable, and an external solution as
shown on Figure 5 (a) can be used to reduce the pulse width. In this circuit, R2 is used to limit the current
(especially the negative current) through the internal ESD cell. Figure 5 (b) illustrates the waveforms based on
this solution. To prevent false trigger by noises, the pulse at the EN pin must be at least 2.25 V (minimum) high
and 3 µs wide to be considered valid.
Choose the R1, R2, and C values based on the following equations:
Choose R2 based on the current limit requirement of under 0.1 mA .
R2 > 10kW
(1)
Choose R1 arbitrarily but much smaller than R2 and choose C1 according to the time constant requirement to
generate longer than 3-µs pulse.
C1 =
6 ms
R1
(2)
If enable function is not used, pull EN pin to VREF.
UVLO
EN
0.3V
SS
CLK
Figure 4. Pulse Enable at EN Pin
(a)
(b)
UCC28251
Enable
Signal
C1
R2
EN
Enable
Signal
R1
EN
Figure 5. An External Solution to Generate Enable Pulses for Pulse Enable
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RT (Oscillator Frequency Set and Synchronization) (15/2)
The UCC28251 oscillator frequency is set by an external resistor connected between the RT pin and ground. The
oscillator frequency can be set to any value between 50 kHz to 1.4 MHz, which is equivalent to an 25-kHz to
700-kHz switching frequency. Switching frequency selection is a trade-off between efficiency and component
size. Based on the selected switching frequency, the programming resistor value can be calculated as:
1
- tD(SP)
2 ´ fSW
RT =
66.4pF
(3)
In this equation, fSW is the switching frequency and TD(sp) is the dead time between synchronous rectifier turn-off
to primary switch turn-on. TD(sp) is set by an external resistor between the SP pin and ground (refer to the SP pin
description).
FOSC (kHz)
Each output (OUTA, OUTB, SRA, SRB) switches at half the oscillator frequency (fSW = ½ x fOSC). Figure 6 shows
the relationship between RT and fOSC at certain TD(sp) and can be used to program oscillator frequency
accordingly.
1350
1250
1150
1050
950
850
750
650
550
450
350
250
150
50
TDps=40ns
TDps=100ns
0
50
100
150
RT (k
200
C00
Figure 6. Oscillator Frequency FOSC vs External Resistance of RT at TD(ps) = 40 ns and 100 ns
The UCC28251 can be synchronized to an external clock by applying an external clock source to the RT pin.
Synchronization helps with parallel operation and/or preventing beat frequency noise. The UCC28251
synchronizes its internal oscillator to an external frequency source ranging from 84 kHz to 1.89 MHz, which is
equivalent to an 42-kHz to 0.945-MHz switching frequency. The internal oscillator frequency is clamped to 84
kHz during synchronization if the external source frequency drops below 84 kHz.
14
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The UCC28251 aligns the turn-on of primary outputs OUTA and OUTB to the falling edge of the synchronizing
signal, as shown in Figure 7. If the frequency source is from the gate outputs of another half bridge controller,
interleaving can be achieved. The interleaving angle is determined by the frequency source’s duty cycle. When a
50% duty cycle is applied, optimal interleaving is achieved, and EMI filters can be minimized.
Frequency
Source
OUTA
OUTB
Figure 7. Timing Diagram for Synchronization
CLK
OUTA
SRA
Td(SP)
Td(PS)
OUTB
SRB
Td(SP)
Td(PS)
Figure 8. UCC28251 Outputs Timing Waveforms
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SP (Synchronous Rectifier Turn-Off to Primary Output Turn-On Dead Time Programming) (13/19)
The dead time TD(sp) between synchronous rectifier turn-off to primary output turn-on is programmed by an
external resistor, RSP, connected between the SP pin and ground. The value of RSP can be determined by
Figure 9. Zero dead time can be achieved by tying the SP pin to VREF. The falling edge of synchronous rectifier
SRA/SRB is aligned with the rising edge of the primary output OUTA/OUTB.
NOTE
The minimum value for RPS and RSP is 5 kΩ and the maximum value is 250 kΩ.
SP DEAD TIME
vs
SP RESISTOR
400
350
TD(sp) - SP Dead Time - ns
300
250
200
150
100
50
0
0
20 40 60 80 100 120 140 160 180 200 220 240
RSP - SP Resistor - kW
Figure 9. Dead Time TD(sp) vs. External Resistor RSP at SP Pin
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PS (Primary Output Turn-Off to Synchronous Rectifier Turn-On Dead Time Programming) (11/18)
The dead time TD(ps) between primary output turn-off to synchronous rectifier turn-on is set by external resistor,
RPS, connected between PS pin and ground. The value of is RPS is defined by Figure 10. Zero dead time can be
achieved by tying the SP pin to VREF.
NOTE
The minimum value for RPS and RSP is 5 kΩ and the maximum value is 250 kΩ.
PS DEAD TIME
vs
PS RESISTOR
400
350
TD(ps) - PS Dead Time - ns
300
250
200
150
100
50
0
0
20 40 60 80 100 120 140 160 180 200 220 240
RPS - PS Resistor - kW
Figure 10. Dead Time TD(ps) vs. External Resistor RPS at PS Pin
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RAMP/CS (PWM Ramp Input or Current Sense Input) (16/3)
The UCC28251 can be controlled using either voltage mode or current mode. RAMP/CS is a multi-function pin
used either to generate the ramp signal for voltage mode control or to sense current for current mode control.The
following sections describe the RAMP/CS functionality for voltage mode and current mode control.
RAMP: Voltage Mode Control with Feed-Forward Operation
For voltage mode control, a resistor RCS and a capacitor CCS must be connected to the RAMP/CS pin as shown
in Figure 11. The internal pull-down switch has approximately 40-Ω on-resistance. The RAMP/CS pin is clamped
internally to not exceed 4 V for internal device protection. The CCS value must be small enough to discharge the
RAMP/CS pin from its peak voltage to ground within the pulse width of the BLANK signal (TD(sp) + 70 ns). The
following formula derives a CCS value.
æ 4 V / 2 ö TD(SP) + 70ns
CCS < ç
÷´
4V
è 40 W ø
(4)
A CCS value less than 650 pF works for most applications. In order to minimize the impacts of parasitic
capacitance caused by the PCB layout and routing, a minimum of 100 pF is recommended for CCS. Once CCS is
determined, RCS can be calculated according to the desired ramp peak amplitude.
RCS =
1
æ VCHARGE
2 ´ ln ç
è VCHARGE - VPK
ö
÷ ´ CCS ´ fSW
ø
(5)
In this equation, the VCHARGE is the voltage used to generate the ramp, VPK is the desired ramp amplitude and
the fSW is the switching frequency.
UCC28251
UCC28251
VIN 36 V to 75 V
VREF
R CS
R CS
RAMP /CS
C CS
GND
RAMP /CS
BLANK
C CS
GND
BLANK
Figure 11. Fixed Ramp Generation/Ramp Generation With Input Voltage Feedforward
Voltage feed-forward can be achieved by driving RCS from line input VIN. The peak of RAMP/CS is proportional
to VIN and output will have much faster line transient response. When the UCC28251 is used for the primaryside control, RAMP parameters are critical for the optimal pre-biased start up performance. Refer to the ‘Voltage
Mode Control and Input Voltage Feed-Forward’ section of the Functional Description section for a detailed design
procedure of choosing RCS.
If the line input cannot be easily accessed due to limited board area or other limitation, a RAMP signal with fixed
peak voltage can be implemented by simply driving RCS from 3.3 V VREF (Figure 11).
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CS: Current Mode Control
For current mode control, the RAMP/CS pin is driven by a signal representative of the transformer primary-side
current. The current signal has to have compatible input range of the COMP pin. As shown in Figure 12, the
COMP pin voltage is used as the reference for peak current. The primary-side signals OUTA and OUTB are
turned on by the internal clock signal and turned off when sensed peak current reaches the COMP pin voltage.
Choose the current sense transformer turns ratio (1:n) and the burden resistor value (RB) based on the peak
current at maximum load IMAX. Refer to the Functional Description section for more details on the current mode
control.
RB =
3V
IMAX / n
(6)
COMP
CS
OUTA
OUTB
Figure 12. Peak Current Mode Control and PWM Generation
REF/EA+ (1/8)
REF/EA+ is the non-inverting input of the UCC28251’s internal error amplifier.
When the UCC28251 is configured for secondary-side control, the internal error amplifier is used as the control
loop error amplifier. Connect REF/EA+ directly to the VREF pin to provide the reference voltage for the feedback
loop.
When the UCC28251 is configured for primary-side control, the error amplifier is connected as a voltage follower.
Connect REF/EA+ to the opto-coupler output.
The voltage range on REF/EA+ pin is 0 V to 3.7 V.
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FB/EA- (2/9)
FB/EA- is the inverting input of the UCC28251’s internal error amplifier.
When the UCC28251 is configured for secondary-side control, connect the output voltage sensing divider to this
pin. The voltage divider can be selected according to the voltage on REF/EA+ pin. Referring to Figure 14, pick
the lower resistor RO1 value arbitrarily, and choose the upper resistor RO2 value as:
æ VO
ö
RO2 = ç
- 1÷ ´ RO1
è VREF / EA +
ø
(7)
Because the control loop gain is affected by voltage divider resistor values, choose an appropriate RO1 value so
that the voltage loop DC gain is larger than 40 dB to prevent interference between the primary-side control loop
and the SR control loop during start up.
When the UCC28251 is sitting on the primary side, the error amplifier is connected as a voltage follower.
Connect FB/EA- directly with COMP pin.
The maximum voltage allowed on FB/EA- pin is 3.7 V.
COMP (3/10)
The COMP pin is the internal error amplifier’s output and also the input signal for PWM comparator. The
maximum input common voltage of the PWM comparator is 2.8 V. It is suggested to program the peak value of
RAMP to be lower than 2.3 V. Otherwise, the voltage of COMP pin should be clamp to be lower than 2.8 V by
external circuit in order to make the internal PWM comparator work properly. An external circuit detailed as below
is recommended for voltage clamp function. Both the primary-side switches’ duty cycle and secondary-side SRs’
duty cycle is controlled by the COMP pin voltage. At steady state, a higher COMP pin voltage results in a larger
duty cycle for the primary-side switches and a smaller duty cycle on the SRs.
When the UCC28251 controller is set up for secondary-side control, connect the compensation network from the
FB/EA- pin to the COMP pin.
For primary-side control, the error amplifier is connected as a voltage follower. Directly connect the COMP pin to
the FB/EA- pin.
UCC28251
REF
R CS
COMP
C CS
GND
Figure 13. COMP Clamp Circuit
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VSENSE (14/1)
The VSENSE pin is used to directly sense the output voltage and to feed it into a transconductance error
amplifier. The measured voltage allows the UCC28251 to achieve optimal pre-biased start up performance.
When configured as a secondary-side controller, the output voltage is sensed and fed into the FB/EA- pin. The
UCC28251 uses a conventional error amplifier approach to allow type III compensation. Therefore, the FB/EApin voltage always follows the REF/EA+ voltage. The FB/EA- pin does not reflect the true output voltage and
therefore this dedicated VSENSE pin is required. The voltage divider connected to VSENSE is discussed in the
Pre-Biased Start-Up Section.
When UCC28251 is set up as primary-side control, connect VSENSE pin to VREF.
SS (Soft Start Programming Pin) (13/20)
The soft-start circuit gradually increases the converter’s output voltage until steady state operation is reached.
This reduces start-up stresses and current surge.
When the UCC28251 reaches its valid operating threshold, the SS pin capacitor is charged with a 27-µA current
source. The UCC28251’s internal error amplifier non-inverting terminal follows the SS pin voltage on REF/EA+
pin voltage depending on which one is lower. Hence, during soft start, the SS pin voltage is lower than REF/EA+.
The internal error amplifier then uses the SS pin as its reference voltage, until the SS pin voltage rises above the
REF/EA+ level. Once the SS pin voltage is above REF/EA+ voltage, soft-start time is considered finished.
The soft-start implementation scheme and timing is different, depending on the location of the UCC28251 with
respect to the isolation barrier.
For secondary-side control, the internal error amplifier is used to achieve the voltage regulation. The REF/EA+ is
connected to an external reference voltage, FB/EA- is connected to the voltage sensing divider, and the error
amplifier’s output pin (COMP) is connected through a compensation filter back to the FB/EA- pin (Figure 14). In
this case, the primary output’s start-up is a closed loop soft start (soft-start input reference of error amplifier). The
output soft-start time is determined by the external capacitor connected at SS pin based on the internal 27-µA
charging current and the voltage set at REF/EA+ pin.
Based on the soft-start time TSS, choose soft start capacitor CSS value as:
CSS =
27 mA ´ TSS
VREF / EA +
(8)
VOUT
UCC28251
VSENSE
C P1
R O2
VREF
RZ3
RS2
R Z2
C Z2
COMP
C Z3
FB/EA-
REF/EA+
+
+
RS1
R O1
SS
C SS
Figure 14. Error Amplifier EAMP Connections for secondary-side Control
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For primary-side control, the internal error amplifier is connected as a buffer stage. In other words, the COMP pin
is shorted to the FB/EA- pin, and the output of an external error amplifier is connected to the REF/EA+ pin
through an optical coupler (Figure 15). In this case, the output start-up is an open loop soft start because the
COMP follows the soft-start voltage instead of the voltage loop output. The soft-start time is still determined by
external capacitor CSS and the 27-µA internal charge current. The voltage depends on the value of final COMP
voltage which corresponds to the regulated primary output duty cycle. According to the desired soft start time and
COMP pin voltage level at steady state, the SS pin capacitor can be calculated as:
CSS =
27 mA ´ TSS
VCOMP _ final
(9)
After soft start, the voltage at SS pin is eventually clamped at around 4 V. Under fault conditions (UVLO, internal
thermal shut down, OVP/OTP, hiccup mode), or when externally disabled, SS pin is pulled down to ground
quickly by an internal switch with 2 kΩ on resistance to prepare for re-start. Pulling SS pin to ground externally
shuts down the controller as well.
VOUT
UCC28251
R O2
C P1
VSENSE
RZ3
R Z2
C Z2
VREF
COMP
C Z3
+
FB/EA-
REF/EA+
R O1
+
+
SS
External
Reference
C SS
Figure 15. Error Amplifier EAMP Connections for primary-side Control
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ILIM (Current Limit for Cycle-By-Cycle Over-Current Protection) (17/4)
Cycle-by-cycle current limit is accomplished using the ILIM pin for current mode control or for voltage mode
control. The input to the ILIM pin represents the primary current information. If the voltage sensed at ILIM pin
exceeds 0.5 V, the current sense comparator terminates the pulse of output OUTA or OUTB. If the high current
condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the
current sense comparator instead of the PWM comparator. ILIM pin is pulled down by an internal switch when
OUTA or OUTB goes low. This internal switch remains on for an additional 70 ns after OUTA or OUTB goes high
to blank leading edge transient noise in the current sensing loop. This reduces the filtering requirements at the
ILIM pin and improves the current sense response time.
Transformer Primary Side
Current
UCC28251
ILIM
CT
RS
HICC
CS
1:n
CHICC
Figure 16. Current Limit Circuit
Once the over current protection level IPK is selected, the current transformer turns ratio and the burden resistor
value can be decided as:
RS =
0.5 V ´ n
IPK
(10)
In this equation, current transformer turns ratio is 1:n and RS is the burden resistor value.
Some filtering capacitance is required to reduce the sensing noise. Choose the RC constant at about 100 ns,
and calculate the capacitor value as:
CS =
100ns
RS
(11)
The cycle-by-cycle current limit operation time before all four outputs shut down can be programmed by external
capacitor CHICC at HICC pin. (See HICC pin description)
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HICC (10/17)
The cycle-by-cycle current limit operation time before all four outputs shut down can be programmed by an
external capacitor CHICC from HICC pin to ground, as shown in Figure 16. Once all four outputs are shutdown,
controller goes into hiccup cycle which is about 100 times the cycle-by-cycle current limit shut-down delay time. A
1-mA internal current source charges HICC pin up to 2.4 V, then the HICC pin is discharged by a 2.7-µA internal
current source to generate long hiccup restart time until HICC reaches 0.3 V. Based on the system requirement,
once the cycle-by-cycle current limit delay time TOC(delay) is selected, the HICC pin capacitor CHICC can be
selected based on the equation
TOC(delay ) ´ 75 mA
CHICC =
0.6 V
(12)
TOCdealy
THICC
HICC
2.4V
0.6V
0.3V
t
SS
4V
t
OUTA
OUTB
Normal
OC
Normal
OC
Hiccup
Soft Start
Figure 17. Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer
As shown in Figure 17, cycle-by-cycle current limiting shut-down delay time is:
TOC(delay ) = CHICC ´
0.6 V
75 mA
(13)
And hiccup-restart-time THICC is equal to:
THICC = CHICC ´
2.4 V - 0.3 V
2.7 mA
(14)
As soon as the outputs are shut-down, the SS pin is pulled to ground internally until the hiccup restart timer is
reset after time duration THICC.
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OVP/OTP (19/6)
The OVP/OTP pin provides multiple fault protection functions. If the voltage on the OVP/OTP pin exceeds 0.7 V,
a fault shutdown occurs. All outputs stop switching and stay off (low) during the shutdown, and the SS pin is
pulled to ground internally. Once the fault condition is cleared (i.e. OVP/OTP voltage drops below 0.7 V), the
UCC28251 enters hiccup mode. A soft-start cycle begins after the hiccup cycle is finished. An internal 8.5-µA
switched current source is used to create hysteresis.
If the external resistor divider runs from line voltage VIN, a line over voltage protection is implemented.
If the external resistor divider runs from the output voltage, output over voltage fault protection is achieved.
Figure 18 shows the over-voltage protection external configuration at the OVP/OTP pin.
According to the protection threshold VR and recovery threshold VF, choose an arbitrary R2 value. To ensure a
realistic solution, R2 needs to meet the following:
R2 <
0.7 V ´ (VR - VF )
8.5 mA ´ (VR - 0.7 V )
(15)
The other two resistors, R1 and R3 can be calculated.
R1 =
R3 <
VR - 0.7 V
´ R2
0.7 V
(16)
0.7 V ´ (VR - VF ) - 11mA ´ R2 ´ (VR - 0.7 V )
8.5 mA ´ VR
(17)
If the external resistor divider runs from 3.3-V VREF, and replaces R2 with a positive temperature coefficient
(PTC) thermistor, an over temperature fault protection with programmable hysteresis is accomplished
(Figure 19). Choose an arbitrary PTC value, which has a resistance as RPTC1 at protection temperature and
resistance as RPTC2 at recovery temperature. Because of its positive temperature coefficient, RPTC1 is larger than
RPTC2. To ensure an available solution, RPTC1 and RPTC2 need to meet the criteria.
0.7 V ´ (RPTC1 - RPTC2 ) - 8.5 mA ´ RPTC1 ´ RPTC2 ³ 0
(18)
And resistors R1 and R3 can be calculated as:
R1 = 3.7 ´ RPTC1
R3 <
(19)
2.6 V ´ ëé0.7 V ´ (RPTC1 - RPTC2 ) - 8.5 mA ´ RPTC1 ´ RPTC2 ûù
8.5 mA ´ (2.6 ´ RPTC1 + 0.7 V ´ RPTC2 )
(20)
UCC28251
VREF
VIN or VOUT
8.5 ?A
R1
R3
OVP
+
R2
0.7 V
Figure 18. Over Voltage Protection
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UCC28251
VREF
R1
8.5 ?A
R3
OVP
+
0.7 V
PTC
Figure 19. Over Temperature Protection
Figure 20 shows an external configuration using the OVP/OTP pin to achieve both over-voltage and over
temperature protection. Follow the same design procedure for the OVP setting to choose R1, R2, and R3. Choose
an NTC value at protection temperature much smaller than R1 and with the resistance at protection temperature
as RNTC1, and recover temperature as RNTC2. The R4 value can be calculated as:
R4 =
0.7 V
´ RNTC1
3.3 V - 0.7 V
(21)
Because of the interaction between the two voltage dividers, over temperature protection thresholds move
slightly with the different input voltages.
UCC28251
VREF
VIN or VOUT
NTC
R1
8.5 ?A
R3
OVP
+
R4
R2
0.7 V
Figure 20. Over Voltage and Over Temperature Protection With Single OVP Pin
OUTA (9/16) and OUTB (8/15)
OUTA and OUTB are the primary-side switch control signals. With the 0.2-A peak current capability, an external
gate driver is required.
SRA (7/14) and SRB (6/13)
SRA and SRB are the synchronous rectifier control signals. With the 0.2A peak current capability, an external
gate driver is required.
GND (4/11)
GND pin is the ground reference for the whole device. Tie all the signal returns to this pin.
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TYPICAL CHARACTERISTICS
START-UP CURRENT
vs
TEMPERATURE
STAND-BY CURRENT
vs
TEMPERATURE
240
465
VDD = 12V
IDD(dis) − Stand−by Current (uA)
IDD(off) − Start−up Current (uA)
VDD = 3.6V
220
200
180
160
140
120
100
−45
−15
15
45
75
TJ − Temperature (°C)
105
435
420
405
390
375
−45
135
−15
G000
15
45
75
TJ − Temperature (°C)
105
135
G000
Figure 21.
Figure 22.
UVLO THRESHOLDS
vs
TEMPERATURE
UVLO VOLTAGE LOCKOUT HYSTERESIS
vs
TEMPERATURE
4.41
UVLO - Under Voltage Lockout Hysteresis - V
0.225
4.33
Turn On
UVLO Thresholds - V
450
4.25
4.17
Turn Off
4.09
4.01
3.93
0.220
0.215
0.210
0.205
0.200
0.195
0.190
-45
-15
15
45
75
105
135
-45
TJ - Temperature - °C
Figure 23.
-15
15
45
75
105
135
TJ - Temperature - °C
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
OPERATING SUPPLY CURRENT
vs
TEMPERATURE
SOFT-START CURRENT
vs
TEMPERATURE
2.85
27.4
27.3
2.80
ISS - Soft-Start Current - mA
IDD - Operating Supply Current - mA
FSW = 200 kHz
2.75
2.70
2.65
27.2
27.1
27.0
26.9
2.60
26.8
-45
-15
15
45
75
105
135
-45
-15
504.8
504.6
504.4
504.2
504
503.8
105
135
G000
VHICC_PU / VCS(max) - RAMP/CS Clamp Voltage and Hiccup
Pull-Up Threshold - V
ILIMCycle−by−Cycle current limit threshold (mV)
505
15
45
75
TJ − Temperature (°C)
105
135
RAMP/CS CLAMP VOLTAGE AND HICCUP PULL-UP
THRESHOLD
vs
TEMPERATURE
5.0
505.2
−15
75
TJ - Temperature - °C
Figure 26.
CYCLE-BY-CYCLE CURRENT LIMIT
vs
TEMPERATURE
503.6
−45
45
15
TJ - Temperature - °C
Figure 25.
4.5
4.0
VCS(max)
3.5
3.0
2.5
VHICC_PU
2.0
1.5
-45
-15
15
45
75
105
135
TJ - Temperature - °C
Figure 27.
28
Figure 28.
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PROPAGATION DELAY/LEADING EDGE BLANKING
vs
TEMPERATURE
90
TPD_ILIM
TBLANK
70
50
30
10
−45
−15
15
45
75
TJ − Temperature (°C)
105
135
G000
VHICC_SD / VHICC_RST - Current Limit Shutdown Delay Timer
and Hiccup Restart - V
& Leading Edge Blanking
TPD_ILIM TBLANK − Prop delay ILIM to Output (ns)
TYPICAL CHARACTERISTICS (continued)
CURRENT LIMIT SHUTDOWN DELAY TIMER AND HICCUP
RESTART
vs
TEMPERATURE
0.7
0.6
VHICC_SD
0.5
0.4
VHICC_RST
0.3
0.2
-45
-15
15
45
75
105
135
TJ - Temperature - °C
Figure 29.
Figure 30.
REFERENCE VOLTAGE
vs
TEMPERATURE
REFERENCE VOLTAGE
vs
TEMPERATURE
3.253
3.258
VREF − Reference Voltage (V)
VREF − Reference Voltage (V)
ILOAD = 2mA
3.2525
3.252
3.2515
VDD = 7V
VDD = 12V
VDD = 17V
3.251
3.2505
−45
−15
15
45
75
TJ − Temperature (°C)
105
135
3.256
3.254
VDD = 12V
3.252
3.25
ILOAD = 10uA
ILOAD = 1mA
ILOAD = 10mA
3.248
3.246
3.244
3.242
−45
G000
Figure 31.
−15
15
45
75
TJ − Temperature (°C)
105
135
G000
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
OVP INTERNAL REFERENCE
vs
TEMPERATURE
OVP INTERNAL CURRENT
vs
TEMPERATURE
IOVP − OVP Internal Current (uA)
8.7
693.3
693.2
693.1
693
692.9
FSW(nom) − Nominal Switching Frequency (kHz)
−15
15
45
75
TJ − Temperature (°C)
105
8.68
8.66
8.64
8.62
8.6
8.58
8.56
8.54
8.52
−45
135
15
45
75
TJ − Temperature (°C)
105
Figure 34.
MINIMUM SYNCHRONIZATION FREQUENCY
vs
TEMPERATURE
MAXIMUM SYNCHRONIZATION FREQUENCY
vs
TEMPERATURE
55
53
51
49
47
45
43
41
−45
−15
15
45
75
TJ − Temperature (°C)
105
135
0.96
0.95
0.94
0.93
0.92
0.91
0.9
−45
−15
G000
15
45
75
TJ − Temperature (°C)
Figure 35.
Figure 36.
NOMINAL SWITCHING FREQUENCY
vs
TEMPERATURE
DEAD TIME
vs
TEMPERATURE
97.8
47
46
97.7
97.6
97.5
135
G000
Figure 33.
105
135
G000
TDPS at RPS= 27k Ω
TDSP at RSP= 20k Ω
45
44
43
42
41
40
39
38
97.4
−45
−15
15
45
75
TJ − Temperature (°C)
105
135
37
−45
G000
Figure 37.
30
−15
G000
FSYN(max) − Maximum Synchronization (MHz)
FSYN(min) − Minimum Synchronization (kHz)
692.8
−45
TSP/TPS − Dead Time (ns)
VOVP − OVP Internal Reference (mV)
693.4
−15
15
45
75
TJ − Temperature (°C)
105
135
G000
Figure 38.
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TYPICAL CHARACTERISTICS (continued)
12
VDD = 12 V
TR / TF - Output Rise/Fall Time - ns
11
TR
10
9
TF
8
7
6
-45
-15
15
45
75
105
135
RSRC / RSNK - Output Source Resistance/Sink Resistance - W
OUTPUT RISE/FALL TIME
vs
TEMPERATURE
OUTPUT SOURCE RESISTANCE/SINK RESISTANCE
vs
TEMPERATURE
35
30
RSRC
25
RSNK
20
15
10
-45
TJ - Temperature - °C
Figure 39.
-15
15
45
75
105
135
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31
TJ - Temperature - °C
Figure 40.
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APPLICATION INFORMATION
The UCC28251 is a high performance PWM controller with advanced synchronous rectifier outputs and is ideally
suited for regulated half-bridge, full-bridge and push-pull converters. A dedicated internal pre-biased start up
control loop working in conjunction with a primary-side voltage loop achieves monotonic pre-biased start up for
either primary-side or secondary-side control applications. The UCC28251 architecture allows either voltage
mode or current mode control.
Input voltage feedforward can be implemented, allowing PWM ramp generator to improve the converter line
transient response. Advanced cycle-by-cycle current limit achieves volt-second balancing even during fault
conditions. The hiccup timer helps the system to stay within a safe operation range under over load conditions.
With a multifunction OVP/OTP pin, combinations of input voltage protection, output voltage protection and over
temperature protection can be implemented. The UCC28251 allows individual programming of dead time
between primary-side switch and secondary-side SRs, in order to allow optimal power stage design. Dead time
can also be reduced to zero, and this allows optimal system configuration considering the delays on the gate
driver stage. The UCC28251 also provides complete system level protection functions, including UVLO, thermal
shut down and over voltage, over current protection.
UCC28251 Enhancements Over the UCC28250
The UCC28251 is a functional variant of the UCC28250 PWM Controller. While the same basic functionality of
the UCC28250 is largely maintained, the UCC28251 is designed to enhance performance in both offline, 400-V
input DC-to-DC applications and 48-V input full-bridge or half-bridge applications. The overall improvements that
are made in UCC28251 can be summarized in the table below:
Table 1. UCC28251 Improvements
NEW IN UCC28251
UCC28250
ENHANCEMENT
When synchronized to an external frequency
source, the minimum switching frequency can be
as low as 42 kHz. When programmed by RT
resistor, the minimum switching frequency can be
as low a 27 kHz.
UCC28250 does not allow support frequencies
lower than 85 kHz.
UCC28251 enables better power
efficiency in offline (400 VIN) DCto-DC converters.
PS and SP delay times are fully independent and
maintain their programmed values under all
conditions.
Whenever OUTA/B turn on time + ps delay is
greater than ½ switching cycle time, the PS delay
would be clamped (identical) to SP delay.
UCC28251 prevents shootthrough between primary and
secondary side MOSFETs
EN shut down delay time shortened to ~1.5 µs
(typical).
UCC28250 EN shutdown time was ~6 µs.
UCC28251 enables quicker shut
down in offline DC-to-DC
applications.
The synchronous rectifier outputs, SRA and SRB,
are ensured to follow after the primary outputs and
have a minimum 50% duty cycle during startup.
SRA and SRB continue to be active and will only
be disabled when UCC28251 is disabled.
The synchronous rectifier duty cycle will be equal
to 0 when primary duty cycle is very narrow. This
duty cycle loss can increased MOSFET VDS and
cause poor reverse recovery.
UCC28251 reduces MOSFET
stress and enables better
reverse recovery.
UCC28251 startup is delayed by 20 µs typical after
reaching VDD UVLO. This 20 µs delay provides
enough time for SS pin to fully discharge.
No delay, immediate startup after UVLO is
reached. After startup, if the applied VDD happens
to drop below UVLO then rises back up above
ULVO very quickly, the UCC28250’s SS pin does
not have enough time to discharge.
UCC28251 SS pin will fully
discharge under VDD brownout
conditions.
When OVP is detected, the internal current source
now turn on for a minimum of 5 µs typical. This
allows the capacitor connected to the OVP pin to
be charged up sufficiently. (The internal current
source has been changed to 8 µA).
In UCC28250, if the OVP comparator is triggered,
the internal current source does not turn on for any
minimum amount of time. In some cases this may
result in the external OVP capacitor not being
charged properly. This could result poor voltage
hysteresis for OVP protection. (The internal current
source is 11 µA).
UCC28251 allows over voltage
protection to have enough
voltage hysteresis.
32
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Error Amplifier and PWM Generation
The UCC28251 includes a high performance internal error amplifier with low input offset, high source/sink current
capability and high gain bandwidth (typical 3.5 MHz). The reference of the error amplifier (REF/EA+ pin) is set
externally to support flexible trimming of the voltage loop, and to make the controller flexible for both primary
side, as well as secondary-side control. The extra positive input for the error amplifier is the SS pin which is used
to externally program the soft-start time of the converter’s output.
During steady state operation, the primary switch duty cycle, D, is generated based on the external ramp on
RAMP/CS pin and the COMP pin voltage. A higher COMP pin voltage results in a larger duty cycle. The
secondary-side SR duty cycle is SR_D = (1-D), complementary to the primary-side duty cycle, without
considering the dead time between primary-side switch and secondary-side SR. The primary outputs begin to
switch when COMP pin voltage is above the 420 mV internal offset. The synchronous rectifier outputs, SRA and
SRB, follow after the primary outputs and have a minimum 50% duty cycle during startup. SRA and SRB
continue to be active and will only be disabled when UCC28251 is disabled (either through UVLO, EN shut
down, OVP and etc). According to the internal logic, the minimum pulse width for the primary-side OUTA and
OUTB is typically 100 ns.
During soft start, the primary-side switch duty cycle is generated based on the external ramp on RAMP/CS pin
and the COMP pin voltage. However, the duty cycle of secondary-side SR is generated based on an internal
ramp and the COMP pin voltage. When the converter is controlled on the primary side, an internal ramp is a
fixed ramp with 3-V peak voltage. When the converter is controlled on secondary side, an internal ramp is
generated based on the internal pre-biased start-up loop. An internal pre-biased start-up loop modifies the SR
duty cycle during soft start to achieve the optimal pre-biased start-up performance.
After the SS pin reaches 2.9 V, the pre-biased start-up control loop is disabled. The secondary-side SR
instantaneously changes into its steady state value as complementary to the primary-side duty cycle.
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Pre-Biased Start Up
With the internal error amplifier, UCC28251 supports both primary-side control and secondary-side control. For
different control methods, the controller is configured accordingly and so is the pre-biased start-up control. During
soft start, both the primary-side switches’ duty cycle and secondary-side SRs’ duty cycle are increased. This
gradually increases the output voltage until steady state operation is reached, thereby reducing surge current.
Secondary-Side Control
For secondary-side control, the UCC28251 implements close-loop control of both the primary-side switches and
secondary-side synchronous rectifiers’ duty cycles. This makes it easy to achieve optimal start up performance.
The internal error amplifier is set up as the control loop error amplifier. Connect REF/EA+, FB/EA-, COMP and
VSENSE as shown in Figure 41. To achieve optimal pre-biased start up performance, the output voltage needs
to be directly measured. The UCC28251 uses the VSENSE pin to directly sense this output voltage. Choose the
voltage dividers on VSENSE slightly different to the FB/EA- voltage divider so that the voltage on VSENSE pin is
roughly 10% to 15% more than FB/EA- pin voltages. Select RO1 equal to RS1, and RS2 about 10% to 15% smaller
than RO2.
VOUT
UCC28251
VSENSE
C P1
R O2
VREF
RZ3
RS2
R Z2
C Z2
COMP
C Z3
FB/EA-
REF/EA+
+
+
RS1
R O1
SS
C SS
Figure 41. Error Amplifier Set Up for Secondary-Side Control
The error amplifier uses the lower voltage between the SS pin and the REF/EA+ pin to be the reference voltage
for the feedback loop. In this method, the control loop is said to be ‘closed’ during the entire start up process, as
it is always based on the true output voltage.
During soft start, the primary-side switch duty cycle is controlled by the COMP pin voltage and ramp voltage
generated on the RAMP/CS pin. A higher COMP pin voltage results in larger duty cycle. However, to improve
start up performance, the secondary-side synchronous rectifier duty cycle is controlled by a separate, internal
ramp signal (generated by a dedicated pre-biased start up loop) and by the COMP pin voltage. This dedicated
pre-biased loop is much faster than the regular voltage loop in order to avoid interaction between the two loops.
The start up loop reads the output voltage via a transconductance error amplifier connected to the VSENSE pin.
When the output voltage is higher than the reference, the pre-biased start up loop increases the SR duty cycle to
reduce the output voltage. Conversely, when the output voltage is lower than the reference, the SR duty cycle is
decreased to help maintain higher output voltage. To speed up the start up time, the minimum duty cycle of the
synchronous rectifier is 50%.
Once the soft start is finished, the pre-biased loop is disabled and the duty cycle of the synchronous rectifiers
becomes the complimentary of primary switches’ duty cycle, with some dead time inserted in between.
34
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Primary-Side Control
When the UCC28251 is sitting on the primary side, the internal error amplifier is connected as a voltage follower
and an extra error amplifier is needed on the secondary side for closed loop control. The error amplifier
implementation is shown in Figure 42.
VOUT
UCC28251
R O2
C P1
VSENSE
RZ3
R Z2
C Z2
VREF
COMP
C Z3
+
FB/EA-
REF/EA+
R O1
+
+
SS
External
Reference
C SS
Figure 42. Error Amplifier Setup for Primary-Side Control
In the above configuration, the UCC28251 can only see the control loop feedback voltage, and cannot directly
access the output voltage. The design of the soft-start time is critical to achieve optimal pre-biased start up
performance. Some trial and error approaches are needed to achieve optimal performance. It is also important to
choose the appropriate ramp amplitude. Refer to the ramp section discussion on the detailed design procedure
for choosing ramp generation components.
During soft start, regardless of the pre-biased condition, the output voltage is always lower than the regulation
voltage, so that the feedback loop is always saturated. When the internal error amplifier is connected as a
voltage follower, the COMP voltage follows the lower of the voltage on the RER/EA+ pin and the SS pin. Since
the feedback loop is saturated, the COMP pin always follows the SS pin voltage, until the output voltage
becomes regulated and the feedback voltage takes over. In this control method, the output voltage control loop is
always saturated, and the controller soft starts the COMP pin voltage. Therefore, it is called open loop soft start.
The primary-side switch duty cycle is controlled by the COMP pin voltage and by the RAMP/CS pin voltage.
During soft start, the COMP pin voltage follows the SS pin as it is rising, so the primary-side switch duty cycle
keeps increasing. When the output voltage becomes regulated, the feedback voltage becomes less than the SS
pin voltage and the primary-side switch comes controlled by the control loop.
For the primary-side control setup, because output voltage is not directly accessible, the internal pre-biased start
up loop is disabled by connecting VSENSE to VREF. Instead, the internal ramp used to generate the
synchronous rectifier duty cycle is fixed, with the peak voltage of 3 V. The duty cycle of the synchronous rectifier
increases as the SS pin voltage increases. When the SS pin voltage reaches 2.9 V, the soft start is considered
finished and the synchronous rectifier duty cycle becomes the complementary of the primary-side switch duty
cycle, minus the programmed dead time. Because of different COMP pin voltages at different line voltages, the
SR duty cycle generated by the internal ramp might be different than the complementary of the primary-side
switch duty cycle (1-D). If the duty cycle is too large, the internal logic is able to limit the duty cycle to (1-D).
However, if the duty cycle is too small, when the soft start is finished, the SR duty cycle has a sudden change,
which will cause output voltage disturbance. To optimize the pre-biased start up performance, it is recommended
that the duty cycle change at the end of soft start be as small as possible.
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Voltage Mode Control and Input Voltage Feed-Forward
For voltage mode control, a resistor RCS and a capacitor CCS are connected externally at RAMP/CS pin as
shown in Figure 43. A ramp signal is generated on the RAMP/CS pin, at a rate of two times that of the switching
frequency. The generated ramp signal is used to control the duty cycle for both the primary-side switches and
secondary-side synchronous rectifiers. The ramp amplitude can be fixed or variable with the input voltage (input
voltage feedforward).
To realize a fixed amplitude ramp, connect RCS to the constant voltage source, so that the ramp capacitor
charging voltage is fixed regardless of line and load condition. The RAMP/CS pin is clamped internally to 4 V for
internal device protection. Because the internal pull-down switch has about 40-Ω on-resistance, the CCS value
must be small enough to discharge RAMP/CS from the peak to ground within TD(sp) + 70 ns (i.e. the pulse width
of BLANK signal).
To achieve the input voltage feedforward, the slope of the ramp needs to be proportional to the input voltage. Tie
RCS to the input line voltage. Because the ramp voltage is much lower than the input voltage, the ramp capacitor
charging current is considered to be proportional to the input voltage. With input voltage feedforward, the COMP
pin voltage should only move slightly even with large input voltage variation. This will provide much better line
transient response for the converter.
UCC28251
VCHARGE
UCC28251
VIN 36 V to 75 V
RCS
RCS
RAMP/CS
CCS
GND
RAMP/CS
BLANK
CCS
GND
BLANK
Figure 43. External Configuration of RAMP/CS Pin With/Without Feed-Forward Operation
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The input voltage feedforward also helps on pre-biased start up. When doing primary-side control to pre-biased
start up, three conditions need to be considered:
Condition 1
At initial start up the primary side needs to provide enough energy to prevent output voltage dip;
Condition 2
At the end of soft start, it is required to keep the SR duty cycle change to be as small as possible. With input
voltage feedforward, the COMP pin voltage is virtually fixed for different input voltages. Therefore, before the end
of soft start, the duty cycle is the same for different input voltages. Choose the RCS and CCS following the
procedure below.
Considering initial start up, the RAMP peak voltage should be:
VRAMP
VIN
- VPRE -BIAS
= 2´n
´ VSR(ramp)
2 ´ VPRE -BIAS
(22)
In this equation, VIN is the input voltage because of the feedforward any input voltage should be fine; VPRE-BIAS is
the highest pre-bias start-up voltage required by the system; n is the tranformer primary to secondary turns ratio
and VSR(ramp) is the internal SR ramp peak voltage 3 V.
Another consideration is at the end of soft start, the SR duty cycle changes from controlled by the soft start, to
complimentary to the primary-side duty cycle. The design should keep the transition as smooth as possible.
Considering this, based on the output voltage and input voltage range, as well as the transformer turns ratio,
calculate the SR duty cycle at different line voltages.
Next, based on the maximum duty cycle on the SR_DMAX, and the internal fixed ramp amplitude 3 V, the COMP
voltage at regulation can be chosen as:
VCOMP( final) = (SR _ DMAX - 0.5 )´ 3 V ´ 2
(23)
Condition 3
Use the calculated COMP pin voltage to derive the external ramp amplitude
VRAMP =
VCOMP( final)
(1 - SR _ DMAX )´ 2
(24)
According to the calculated ramp voltage from Equation 22 and Equation 24 some trade off is required to pick up
the appropriate ramp voltage. Based on the selected ramp capacitor CCS value, choose the ramp resistor RCS
value:
RCS =
VIN(max) ´ 2
VRAMP ´ CCS ´ fsw
(25)
In this equation, VIN(max) is the maximum input voltage, fSW is the switching frequency.
Because these calculations ignore the dead time and the non-linearity of the ramp, slight modification is expected
to achieve the optimal design. When the input voltage feed forward is not used, refer to the RAMP pin discussion
for RC calculation.
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Peak Current Mode Control
For peak current mode control, RAMP/CS pin is connected directly with the current signal generated from a
current transformer. The current signal must be compatible with the input range of the COMP pin. External slope
compensation is required to prevent sub-harmonic oscillation and to maintain flux-balance. The slope
compensation can be implemented by using OUTA and OUTB to charge external capacitors and use the voltage
follower to add into the sensed the current signal, as shown in Figure 44. Follow the peak current mode control
theory to select compensation slope or refer to “Modeling, Analysis and Compensation of the Current-Mode
Converter”, (TI Literature Number SLUA101).
OUTA
OUTB
UCC28251
VREF
Transformer Primary Side
Current
RAMP/CS
CT
BLANK
RS
CS
1:n
Figure 44. UCC28251 Set Up for Peak Current Mode Control
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Cycle-by-Cycle Current Limit and Hiccup Mode Protection
Cycle-by-cycle current limit is accomplished using the ILIM pin for both current mode control and voltage mode
control. The input to the ILIM pin represents the primary current information. If the voltage sensed at ILIM pin
exceeds 0.5 V, the current sense comparator terminates the pulse of output OUTA or OUTB. If the high current
condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the
current sense comparator instead of the PWM comparator. ILIM pin is pulled down by an internal switch at the
rising edge of each clock cycle. This internal switch remains on for an additional 70 ns after OUTA or OUTB
goes high to blank leading edge transient noise in the current sensing loop. This reduces the filtering
requirements at the ILIM pin and improves the current sense response time.
UCC28251 makes it possible to maintain flux balance during cycle-by-cycle current limit operation. The duty
cycles of primary switches are always matched. If one switch duty cycle is terminated earlier because of current
limiting, a matched duty cycle is applied to the other switch for the next half switching cycle, regardless of the
current condition, as shown in Figure 45. This matched duty cycle helps to maintain volt-second balancing on the
transformer and prevents the transformer saturation.
CLK
70ns
0.5V
ILIM
OUTA
OUTB
Figure 45. Cycle-by-Cycle Current Limit Duty Cycle Matching
Once the current limit is triggered, the 75-µA internal current source begins to charge the capacitor on HICC pin.
If the current limit condition went away before HICC pin reaches 0.6 V, the device stops charge HICC capacitor
and begins to discharge it with 2.7-µA current source. If the cycle-by-cycle current limit condition continues, HICC
pin reachs 0.6 V, and all four outputs are shut down. The UCC28251 then enters hiccup mode. During hiccup
mode, all four outputs keep low; SS pin is pulled to ground internally; a 2.7-µA current source continuously
discharge HICC pin capacitor; until HICC pin voltage reaches 0.3 V. After that, HICC pin is discharged internally
to get ready for the next HICC event. The whole converter starts with soft start after hiccup mode.
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The cycle-by-cycle current limit operation time before all four outputs shut down is programmed by external
capacitor CHICC at HICC pin. The delay time can be calculated as:
TOC(delay ) = CHICC ´
0.6 V
75 mA
(26)
The hiccup timer keeps all outputs being zero until the timer expires. The hiccup time THICC is calculated as:
THICC = CHICC ´
2.4 V - 0.3 V
2.7 mA
(27)
As soon as the outputs are shut-down, SS pin is pulled down internally until the hiccup restart timer is reset after
time duration THICC. The detailed illustration of HICCUP mode is shown in Figure 46.
TOCdealy
THICC
HICC
2.4V
0.6V
0.3V
t
SS
4V
t
OUTA
OUTB
Normal
OC
Normal
OC
Hiccup
Soft Start
Figure 46. Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer
Thermal Protection
Internal thermal shutdown circuitry protects the UCC28251 in the event the maximum rated junction temperature
is exceeded. When activated, typically at 160°C, with the maximum threshold at 170°C and minimum threshold at
150°C the controller is forced into a low power standby mode. The outputs (OUTA, OUTB, SRA, SRB) are
disabled. This helps to prevent accidental device overheating. A 20°C hysteresis is added to prevent comparator
oscillation. During thermal shutdown, the UCC28251 follows a normal start up sequence after the junction
temperature falls below 140°C (typical value, with 130°C minimum threshold and 150°C maximum threshold).
40
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Design Example
The example provided here is to show how to design a symmetrical half bridge converter of voltage mode control
with UCC28251 on primary side.
+
Figure 47 is the circuit diagram to be used in this design example. This design example is to show how to
determine the values in the circuit associated to UCC28251 programming.
Figure 47. Circuit Diagram in Design Example.
Table 2 shows the specifications for the design example.
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Design Steps
Step 1, Power Stage Design
The power stage design in this example is standard and the same as that for symmetrical half bridge converter of
voltage mode control. From the standard design, these components are determined. This includes Q1 through
Q4, C1, C2, CT1, D1 and D2, D3, T1, T2 and T3, and U6. Their design is standard. Also, design associated to
current sensing and protection is also standard. This includes CT1, D1, D2, R5 and C5.
Step 2, Feedback Loop Design
D3 (TLV431) with U6, R6, R9, R10, R12, R13, C11 and C12 are composed of standard type 3 feedback loop
compensation network and output voltage set point. Their design is also standard.
Table 2. Specifications for the Design Example
PARAMETER
MIN
TYP
36
MAX
Input voltage
VOUT
Output voltage
POUT
Outpu power
75
W
IOUT
Output load current
23
A
COUT
Load capacitance
fSW
Switching frequency
PLIMIT
Over-power limit
η
Efficiancy at full load
72
3.3
5000
150
VDC
µF
kHz
150%
90%
Isolation
42
48
UNITS
VIN
1500
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Step 3, Programming the Device
Step 3-1
Equation 3 is used to determine RT based on switching frequency, 300 kHz and assumes the dead time of 150
ns.
1
- 150ns
3.18 ms
´
2
150kHz
=
= 47.9 kW
RT =
66.4pF
66.4pF
R4 = 47.9 kW
(28)
Step 3-2, Determine RAMP Resistance and Capacitance
There are two-fold considerations to determine RAMP resistance and capacitance. Equation 22 provides RAMP
consideration for SR initial start up with prebias. The corresponding RAMP peak voltage is determined with input
voltage low line and maximum prebias output voltage. In the below T1 turns ratio n = 4.
VRAMP
VIN
36 V
- Vpre -bias
- 3.0 V
= 2´n
´ VSR _ RAMP = 2 ´ 4
´ 3.0 V = 0.750 V
2 ´ Vpre -bias
2 ´ 3.0 V
(29)
Equation 23 and Equation 24 provides RAMP consideration for soft start completion to make duty cycle match
(1-D) = SR_D.
1. Calculate OUTA or OUTB duty cycle at 75-V input voltage, 3.3-V output.
D=
n ´ VO 1 4 ´ 3.3 V 1
´ =
´ = 0.176
VIN
2 75 V / 2 2
2
(30)
2. Calculate SRA or SRB duty cycle.
SR _ D = 1 - D = 1 - 0.176 = 0.82
(31)
3. Calculate the COMP voltage value in steady state (Equation 23).
VCOMP = (SR _ D - 0.5) ´ 3.0 V ´ 2 = (0.824 - 0.5) ´ 3.0 V ´ 2 = 1.944 V
(32)
4. Calculate the RAMP peak value (Equation 24).
VRAMP =
VCOMP
1.944 V
=
= 5.523 V
(D ´ 2) (0.176 ´ 2)
(33)
5. Arbitrary select CRAMP 470 pF, then C3 = 470 pF.
6. Calculate RRAMP.
RRAMP _ 1 =
1
æ
ö
VCHARGE
2 ´ ln ç
÷ ´ CRAMP ´ fsw
è VCHARGE - VRAMP ø
=
1
= 336.9kW
36 V
2 ´ ln(
) ´ 470pF ´ 150kHz
36 V - 0.750 V
(34)
RRAMP _ 2 =
1
æ
ö
VCHARGE
2 ´ ln ç
÷ ´ CRAMP ´ fsw
è VCHARGE - VRAMP ø
=
1
= 92.7kW
75 V
2 ´ ln(
) ´ 470pF ´ 150kHz
75 V - 5.523 V
(35)
As different RAMP resistor values are obtained, at this stage, we may take their average value for initial design.
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Step 3-3, Determine Soft-Start Capacitance
Determine soft-start capacitance with soft-start time 15 ms.
CSS =
27 mA ´ TSS 27 mA ´ 15ms
=
= 0.101mF Þ C8 = 0.1mF
VCOMP( final)
4.0 V
(36)
Step 3-4, Determine Dead-Time Resistance
Assuming the dead time is 150 ns, Select R7 = R8 = 121 kΩ based on Figure 9 and Figure 10.
Step 3-5, Determine OCP Hiccup Off-Time Capacitance
Assuming off time is 0.8 s (Equation 14).
CHICC = THICC ´
2.7 mA
2.7 mA
= 0.8 s ´
= 1.03 mF Þ C7 = 1.0 mF
2.4 V - 0.3 V
2.4 V - 0.3 V
(37)
Step 3-6, Determine Primary-Side OVP Resistance
Assuming OV_OFF = 73 V, OV_ON = 72 V (Equation 15 to Equation 17).
R2 £
0.7 V ´ (Vr - Vf )
11mA ´ (Vr - 0.7 V )
=
0.7 V ´ (73 V - 72 V )
11mA ´ (73 V - 0.7 V )
= 880 W Þ R2 = 866 W
(38)
VR - 0.7 V
73 V - 0.7 V
´ R2 =
´ 866 W = 89.4kW Þ R1 = 88.7kW
0.7 V
0.7 V
0.7 V ´ (VR - VF ) - 11mA ´ R2 ´ (VR - 0.7 V )
R3 =
=
11mA ´ Vr
R1 =
=
0.7 V ´ (73 V - 72 V ) - 11mA ´ 866 W ´ (73 V - 0.7 V )
11mA ´ 73 V
(39)
= 14 W Þ R14 = 14 W
(40)
Step 3-7, Select Capacitance for VDD and VREF
As recommended by the datasheet, select C6 = C4 = 1.0 µF. The final design is shown in Figure 48.
44
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UCC28251
SLUSBD8D – FEBRUARY 2013 – REVISED APRIL 2013
+
+
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Figure 48. Schematics of Primary-Side Control Design Example
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45
UCC28251
SLUSBD8D – FEBRUARY 2013 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Original (February 2013) to Revision A
•
Page
Added Figure 6, Oscillator Frequency FOSC vs External Resistance of RT at TD(ps) = 40 ns and 100 ns .......................... 14
Changes from Revision A (February 2013) to Revision B
Page
•
Added Start threshold electical characteristics. .................................................................................................................... 4
•
Added Input offset electrical characteristics. ........................................................................................................................ 4
•
Added Primary off to secondary on dead time electrical characteristics. ............................................................................. 6
•
Added Secondary off to primary on dead time electrical characteristics. ............................................................................. 6
•
Added note, "The minimum value for RPS/RSP is 5 kΩ and the maximum value is 250 kΩ." in two places. ...................... 16
Changes from Revision B (March 2013) to Revision C
Page
•
Changed Operating junction temperature range from (-40 to 125) to (125 to 150). ............................................................. 4
•
Added UCC28251PW Current Sense data. .......................................................................................................................... 5
•
Changed Functional Block Diagram ..................................................................................................................................... 7
Changes from Revision C (April, 2013) to Revision D
Page
•
Added VREF value for EN (Enable Pin) pin description. .................................................................................................... 12
•
Changed Equation 3. .......................................................................................................................................................... 14
•
Changed Figure 9. .............................................................................................................................................................. 16
•
Changed Figure 10. ............................................................................................................................................................ 17
•
Changed Equation 4. .......................................................................................................................................................... 18
•
Changed Current Limit Circuit diagram. ............................................................................................................................. 23
•
Changed UCC28251 Set Up for Peak Current Mode Control diagram. ............................................................................. 38
•
Changed Equation 28. ........................................................................................................................................................ 43
46
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
UCC28251PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28251
UCC28251PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28251
UCC28251RGPR
ACTIVE
QFN
RGP
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
28251
UCC28251RGPT
ACTIVE
QFN
RGP
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
28251
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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Addendum-Page 2
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