TI LM5122

LM5122/LM5122-Q1
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SNVS954C – APRIL 2013 – REVISED MAY 2013
Wide Input Synchronous Boost Controller with Multiple Phase Capability
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FEATURES
APPLICATIONS
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Available in AEC-Q100 (LM5122-Q1)
Maximum Input Voltage : 65 V
Min Input Voltage : 3.0 V (4.5 V for startup)
Output Voltage up to 100 V
Bypass (VOUT = VIN) Operation
1.2 V Reference with ±1.0% Accuracy
Free-Run/Synchronizable Switching to 1 MHz
Peak Current Mode Control
Robust 3 A Integrated Gate Drivers
Adaptive Dead-Time Control
Optional Diode Emulation Mode
Programmable Cycle-by-Cycle Current Limit
Hiccup Mode Overload Protection
Programmable Line UVLO
Programmable Soft-Start
Thermal Shutdown Protection
Low Shutdown Quiescent Current: 9 μA
Programmable Slope Compensation
Programmable Skip Cycle Mode Reduces
Standby Power
Allows External VCC Supply
Inductor DCR Current Sensing Capability
Multiphase Capability
Thermally Enhanced 20-Pin HTSSOP
12 V, 24 V, and 48 V Power Systems
Automotive Start-Stop
Audio Power Supply
High Current Boost Power Supply
DESCRIPTION
The LM5122 is a multiphase capable synchronous
boost
controller
intended
for
high-efficiency
synchronous boost regulator applications. The control
method is based upon peak current mode control.
Current mode control provides inherent line feedforward, cycle-by-cycle current limiting and ease of
loop compensation.
The switching frequency is programmable up to 1
MHz. Higher efficiency is achieved by two robust Nchannel MOSFET gate drivers with adaptive deadtime control. A user-selectable diode emulation mode
also enables discontinuous mode operation for
improved efficiency at light load conditions.
An internal charge pump allows 100% duty cycle for
high-side synchronous switch (Bypass operation). A
180º phase shifted clock output enables easy multiphase interleaved configuration. Additional features
include thermal shutdown, frequency synchronization,
hiccup mode current limit and adjustable line
undervoltage lockout.
SIMPLIFIED APPLICATION DIAGRAM
VIN
VOUT
+
VCC
BST
SW
LO
CSN
HO
CSP
COMP
VIN
UVLO
SLOPE
FB
RES
SS
SYNCIN/RT
MODE
SYNCOUT
PGND
AGND
OPT
LM5122
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
LM5122/LM5122-Q1
SNVS954C – APRIL 2013 – REVISED MAY 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
2
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SNVS954C – APRIL 2013 – REVISED MAY 2013
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted)
VALUE
Input
Output (3)
ESD Rating
Thermal
(1)
(2)
(3)
UNIT
MIN
MAX
VIN, CSP, CSN
–0.3
75
V
BST to SW, FB, MODE, UVLO, OPT, VCC (2)
–0.3
15
V
SW
–5.0
105
V
BST
–0.3
115
V
SS, SLOPE, SYNCIN/RT
–0.3
7
V
CSP to CSN, PGND
–0.3
0.3
V
HO to SW
–0.3
BST to SW+0.3
V
LO
–0.3
VCC+0.3
V
COMP, RES, SYNCOUT
–0.3
7
V
Human-Body Model (HBM) JESD22-A114
2
kV
Charged-Device Model (CDM) JESD22-C101
1
kV
Storage Temperature
–55
150
ºC
Junction Temperature
–40
150
ºC
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless
otherwise specified, all voltages are referenced to AGND pin.
See Application Information when input supply voltage is less than the VCC voltage.
All output pins are not specified to have an external voltage applied.
THERMAL CHARACTERISTICS
THERMAL METRIC
UNIT
θJA Junction-to-ambient thermal resistance (Typ.)
40
ºC/W
θJC Junction-to-case thermal resistance (Typ.)
4
ºC/W
RECOMMENDED OPERATING CONDITIONS (1)
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
4.5
65
V
14
V
14
V
65
V
Input supply voltage (2)
VIN
Low-side driver bias voltage
VCC
High-side driver bias voltage
BST to SW
3.8
CSP, CSN
3.0
Current sense common mode range
(2)
Switch node voltage
SW
Junction temperature
TJ
(1)
(2)
–40
UNIT
100
V
125
ºC
Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but does not
guarantee specific performance limits.
Minimum VIN operating voltage is always 4.5 V. The minimum input power supply voltage can be 3.0 V after start-up, assuming VIN
voltage is supplied from an available external source.
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ELECTRICAL CHARACTERISTICS
Unless otherwise specified, these specifications apply for -40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VUVLO = 0 V
9
17
µA
VUVLO = 2 V, non-switching
4
5
mA
7.6
8.3
V
0.25
V
VIN SUPPLY
ISHUTDOWN VIN shutdown current
IBIAS
VIN operating current (exclude
the current into RT resistor)
VCC REGULATOR
VCC(REG)
VCC regulation
VCC dropout (VIN to VCC)
IVCC
No load
6.9
VVIN = 4.5 V, no external load
VVIN = 4.5 V, IVCC = 25 mA
0.28
VVCC = 0 V
VCC operating current (exclude
the current into RT resistor)
VVCC = 8.3 V
3.5
5
mA
VVCC = 12 V
4.5
8
mA
4.0
4.1
V
3.7
V
VCC undervoltage threshold
3.9
62
V
VCC sourcing current limit
VCC rising, VVIN = 4.5 V
50
0.5
VCC falling, VVIN = 4.5 V
VCC undervoltage hysteresis
mA
0.385
V
UNDERVOLTAGE LOCKOUT
UVLO threshold
UVLO rising
UVLO hysteresis current
VUVLO = 1.4 V
UVLO standby enable threshold
UVLO rising
1.17
1.20
1.23
V
7
10
13
µA
0.3
0.4
0.5
V
0.1
0.125
V
1.24
1.28
V
UVLO standby enable hysteresis
MODE
Diode emulation mode threshold
MODE rising
1.20
Diode emulation mode hysteresis
0.1
Default MODE voltage
Default skip cycle threshold
Skip cycle hysteresis
145
155
COMP rising, measured at COMP
1.290
COMP falling, measured at COMP
1.245
Measured at COMP
V
170
mV
V
V
40
mV
ERROR AMPLIFIER
VREF
FB reference voltage
Measured at FB, VFB= VCOMP
FB input bias current
VFB= VREF
VOH
COMP output high voltage
VOL
COMP output low voltage
AOL
DC gain
fBW
Unity gain bandwidth
Slave mode threshold
1.188
1.200
1.212
5
ISOURCE = 2 mA, VVCC = 4.5 V
2.75
ISOURCE = 2 mA, VVCC = 12 V
3.40
V
V
ISINK = 2 mA
0.25
FB rising
V
nA
V
80
dB
3
MHz
2.7
3.4
V
OSCILLATOR
fSW1
Switching frequency 1
RT = 20 kΩ
400
450
500
kHz
fSW2
Switching frequency 2
RT = 10 kΩ
775
875
975
kHz
RT output voltage
1.2
RT sync rising threshold
RT rising
RT sync falling threshold
RT falling
Minimum sync pulse width
2.5
1.6
V
2.9
2.0
V
V
100
ns
SYNCOUT
4
SYNCOUT high-state voltage
ISYNCOUT = –1 mA
SYNCOUT low-state voltage
ISYNCOUT = 1 mA
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3.3
4.3
0.15
V
0.25
V
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SNVS954C – APRIL 2013 – REVISED MAY 2013
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, these specifications apply for -40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.0
3.0
4.0
V
OPT
Synchronization selection
threshold
OPT rising
SLOPE COMPENSATION
SLOPE output voltage
VSLOPE
Slope compensation amplitude
1.17
1.20
1.23
V
RSLOPE = 20 kΩ, fSW = 100 kHz, 50%
duty cycle, TJ = –40ºC to +125ºC
1.375
1.650
1.925
V
RSLOPE= 20 kΩ, fSW= 100 kHz, 50% duty
cycle, TJ = 25ºC
1.400
1.650
1.900
V
7.5
10
12
µA
SOFT-START
ISS-SOURCE SS current source
VSS = 0 V
SS discharge switch RDS-ON
Ω
13
PWM COMPARATOR
tLO-OFF
tON-MIN
Forced LO off-time
Minimum LO on-time
COMP to PWM voltage drop
VVCC = 5.5 V
330
400
ns
VVCC = 4.5 V
560
750
ns
RSLOPE = 5 kΩ
150
RSLOPE = 200 kΩ
ns
300
ns
TJ = –40ºC to +125ºC
0.95
1.10
1.25
V
TJ = 25ºC
1.00
1.10
1.20
V
CSP to CSN, TJ = –40ºC to +125ºC
65.5
75.0
87.5
mV
CSP to CSN, TJ = 25ºC
67.0
75.0
86.0
mV
CURRENT SENSE / CYCLE-BY-CYCLE CURRENT LIMIT
VCS-TH1
VCS-ZCD
Cycle-by-cycle current limit
threshold
Zero cross detection threshold
CSP to CSN, rising
CSP to CSN, falling
7
0.5
6
mV
12
mV
Current sense amplifier gain
10
V/V
ICSP
CSP input bias current
12
µA
ICSN
CSN input bias current
11
Bias current matching
ICSP - ICSN
CS to LO delay
Current sense / current limit delay
–1.75
1
µA
3.75
150
µA
ns
HICCUP MODE RESTART
VRES
VHCP-
Restart threshold
Hiccup counter upper threshold
UPPER
RES rising
1.15
1.20
1.25
V
RES rising
4.2
V
RES rising,
VVIN = VVCC = 4.5 V
3.6
V
RES falling
2.15
V
Hiccup counter lower threshold
RES falling,
VVIN = VVCC = 4.5 V
1.85
V
IRESSOURCE1
RES current source1
Fault-state charging current
IRES-SINK1
RES current sink1
Normal-state discharging current
IRESSOURCE2
RES current source2
Hiccup mode off-time charging current
IRES-SINK2
RES current sink2
Hiccup mode off-time discharging current
VHCPLOWER
Hiccup cycle
RES discharge switch RDS-ON
Ratio of hiccup mode off-time to
restart delay time
20
30
40
µA
5
µA
10
µA
5
µA
8
Cycles
40
Ω
122
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, these specifications apply for -40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.15
0.24
V
0.18
HO GATE DRIVER
VOHH
HO high-state voltage drop
IHO = –100 mA, VOHH = VBST –VHO
VOLH
HO low-state voltage drop
IHO = 100 mA, VOLH = VHO –VSW
0.1
HO rise time (10% to 90%)
CLOAD = 4700 pF, VBST = 12 V
25
ns
HO fall time (90% to 10%)
CLOAD = 4700 pF, VBST = 12 V
20
ns
VHO = 0 V, VSW = 0 V, VBST = 4.5 V
0.8
A
VHO = 0 V, VSW = 0 V, VBST = 7.6 V
1.9
A
VHO = VBST = 4.5 V
1.9
A
VHO = VBST= 7.6 V
3.2
A
µA
IOHH
Peak HO source current
IOLH
Peak HO sink current
IBST
BST charge pump sourcing
current
BST charge pump regulation
VVIN = VSW = 9.0 V , VBST - VSW = 5.0 V
100
200
BST to SW, IBST= –70 μA,
VVIN = VSW = 9.0 V
5.3
6.2
6.75
V
BST to SW, IBST = –70 μA,
VVIN = VSW = 12 V
7
8.5
9
V
2.0
3.0
3.5
V
30
45
µA
0.15
0.25
V
0.17
BST to SW undervoltage
BST DC bias current
V
VBST - VSW = 12 V, VSW = 0 V
LO GATE DRIVER
VOHL
LO high-state voltage drop
ILO = –100 mA, VOHL = VVCC –VLO
VOLL
LO low-state voltage drop
ILO = 100 mA, VOLL = VLO
0.1
LO rise time (10% to 90%)
CLOAD = 4700 pF
25
ns
LO fall time (90% to 10%)
CLOAD = 4700 pF
20
ns
VLO = 0 V, VVCC = 4.5 V
0.8
A
VLO = 0 V
2.0
A
VLO = VVCC = 4.5 V
1.8
A
VLO = VVCC
3.2
A
IOHL
Peak LO source current
IOLL
Peak LO sink current
V
SWITCHING CHARACTERISTICS
tDLH
LO fall to HO rise delay
No load, 50% to 50%
50
80
115
ns
tDHL
HO fall to LO rise delay
No load, 50% to 50%
60
80
105
ns
Thermal shutdown
Temperature rising
THERMAL
TSD
Thermal shutdown hysteresis
6
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165
ºC
25
ºC
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TYPICAL CHARACTERISTICS
6.00
5.00
4.00
3.00
LO PEAK CURRENT [A]
HO PEAK CURRENT [A]
5.00
SINK
2.00
SOURCE
1.00
4.00
SINK
3.00
SOURCE
2.00
1.00
VVIN = 12V
VSW = 0V
VVIN = 12V
0.00
0.00
4
5
6
7
8
9
10
11
12
13
VBST - VSW [V]
4
14
7
8
95
80.00
90
70.00
85
Dead-time [ns]
100
90.00
60.00
tDHL
50.00
40.00
tDLH
VVIN = 12V
VSW = 12V
CLOAD=2600pF
1V to 1V
20.00
10.00
9
10
11
12
13
14
C001
Figure 2. LO Peak Current vs VVCC
100.00
Dead-time [ns]
6
VVCC [V]
Figure 1. HO Peak Current vs VBST - VSW
30.00
5
C001
tDHL
80
75
70
tDLH
65
60
55
0.00
50
4
5
6
7
8
9
10
11
VVCC [V]
12
-50
-25
0
25
50
75
100
125
Temperature [ƒC]
C001
Figure 3. Dead Time vs VVCC
150
C001
Figure 4. Dead Time vs Temperature
100.0
20
90.0
15
70.0
tDHL
ISHUTDOWN [PA]
Dead-time [ns]
80.0
60.0
50.0
tDLH
40.0
30.0
VVIN = 12V
VVCC = 7.6V
CLOAD=2600pF
1V to 1V
20.0
10.0
10
5
0.0
0
0
10
20
30
40
VSW [V]
50
60
-50
-25
Figure 5. Dead Time vs VSW
0
25
50
75
100
125
Temperature [ƒC]
C001
150
C001
Figure 6. ISHUTDOWN vs Temperature
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TYPICAL CHARACTERISTICS (continued)
8
8
No load
6
VVCC [V]
VVCC [V]
6
4
4
2
2
0
0
No load
0
10
20
30
40
50
60
70
0
80
IVCC [mA]
1
2
3
4
5
6
Figure 7. VVCC vs IVCC
8
9
10
11
12
13
14
C001
Figure 8. VVCC vs VVIN
40
15
180
ACL=101, COMP unload
ICSP
30
PHASE
20
90
10
45
0
10000
100000
FREQUENCY [Hz]
10
ICSN
5
0
GAIN
-10
1000
ICSP, ICSN [PA]
135
PHASE [°]
GAIN [dB]
7
VVIN [V]
C001
0
-45
10000000
1000000
-50
-25
0
25
50
75
100
125
Temperature [ƒC]
C002
Figure 9. Error Amp Gain and Phase vs Frequency
150
C001
Figure 10. ICSP, ICSN vs Temperature
15.0
300
280
BST Charging Current [PA]
IBST = -70uA
VBST-SW [V]
10.0
5.0
VVIN=VSW=9V
260
240
220
200
180
160
140
120
100
0.0
4
9
14
-50
19
VSW [V]
-25
0
25
50
75
100
125
Temperature [ƒC]
C001
Figure 11. VBST-SW vs VSW
150
C001
Figure 12. IBST vs Temperature
80
90
VVIN=VCSP
VCS-TH1 [mV]
VCS-TH1 [mV]
85
75
80
75
70
65
60
70
4
5
6
7
8
9
10
VVIN [V]
12
-50
-25
0
25
50
75
100
Temperature [ƒC]
C001
Figure 13. VCS-TH1 vs VVIN
8
11
125
150
C001
Figure 14. VCS-TH1 vs Temperature
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TYPICAL CHARACTERISTICS (continued)
12.00
11.00
10.00
VSW = 12V
9.00
VBST-SW [V]
8.00
7.00
6.00
5.00
VSW = 9V
4.00
3.00
VVIN = VSW
IBST = -70uA
2.00
1.00
0.00
-50
-25
0
25
50
75
100
Temperature [ƒC]
125
150
C001
Figure 15. VBST-SW vs Temperature
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DEVICE INFORMATION
HTSSOP-20
(TOP VIEW)
SYNCOUT
1
20
BST
OPT
2
19
HO
CSN
3
18
SW
CSP
4
17
VCC
VIN
5
16
LO
EP
UVLO
6
15
PGND
SS
7
14
RES
SYNCIN/RT
8
13
MODE
AGND
9
12
SLOPE
FB
10
11
COMP
PIN FUNCTIONS
PIN
(1)
10
I/O (1)
DESCRIPTION
NAME
NO.
AGND
9
G
Analog ground connection. Return for the internal voltage reference and analog circuits.
BST
20
P/I
High-side driver supply for bootstrap gate drive. Connect to the cathode of the external bootstrap
diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the highside N-channel MOSFET gate and should be placed as close to controller as possible. An internal
BST charge pump will supply 200 µA current into bootstrap capacitor for bypass operation.
COMP
11
O
Output of the internal error amplifier. The loop compensation network should be connected between
this pin and the FB pin.
CSN
3
I
Inverting input of current sense amplifier. Connect to the negative-side of the current sense resistor.
CSP
4
I
Non-inverting input of current sense amplifier. Connect to the positive-side of the current sense
resistor.
EP
EP
N/A
Exposed pad of the package. No internal electrical connections. Should be soldered to the large
ground plane to reduce thermal resistance.
FB
10
I
Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin
sets the output voltage level. The regulation threshold at the FB pin is 1.2 V. The controller is
configured as slave mode if the FB pin voltage is above 2.7 V at initial power-on.
HO
19
O
High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side synchronous
N-channel MOSFET switch through a short, low inductance path.
LO
16
O
Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side N-channel
MOSFET switch through a short, low inductance path.
MODE
13
I
Switching mode selection pin. 700 kΩ pull-up and 100 kΩ pull-down resistor internal hold MODE pin
to 0.15 V as a default. By adding external pull-up or pull-down resistor, MODE pin voltage can be
programmed. When MODE pin voltage is greater than 1.2 V diode emulation mode threshold,
forced PWM mode is enabled, allowing current to flow in either direction through the high-side Nchannel MOSFET switch. When MODE pin voltage is less than 1.2 V, the controller works in diode
emulation mode. Skip cycle comparator is activated as a default. If MODE pin is grounded, the
controller still operates in diode emulation mode, but the skip cycle comparator will not be triggered
in normal operation, this enables pulse skipping operation at light load.
OPT
2
I
Clock synchronization selection pin. This pin also enables/disables SYNCOUT related with
master/slave configuration. The OPT pin should not be left floating.
PGND
15
G
Power ground connection pin for low-side N-channel MOSFET gate driver. Connect directly to the
source terminal of the low-side N-channel MOSFET switch.
G = Ground, I = Input, O = Output, P = Power
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PIN
I/O (1)
DESCRIPTION
14
O
The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay
during over load conditions. Connect directly to the AGND when hiccup mode operation is not
required.
SLOPE
12
I
Slope compensation is programmed by a single resistor between SLOPE and the AGND.
SS
7
I
Soft-start programming pin. An external capacitor and an internal 10 μA current source set the ramp
rate of the internal error amplifier reference during soft-start.
SW
18
I/O
Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the
high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET
switch through short, low inductance paths.
SYNCIN/RT
8
I
The internal oscillator frequency is programmed by a single resistor between RT and the AGND.
The internal oscillator can be synchronized to an external clock by applying a positive pulse signal
into this SYNCIN pin. The recommended maximum internal oscillator frequency in master
configuration is 2 MHz which leads to 1 MHz maximum switching frequency.
SYNCOUT
1
O
Clock output pin. SYNCOUT provides 180º shifted clock output for an interleaved operation.
SYNCOUT pin can be left floating when it is not used. See Slave Mode and SYNCOUT section.
NAME
NO.
RES
UVLO
6
I
Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the
shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below
1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the
HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the startup sequence begins. A 10 μA
current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external
UVLO resistors to provide hysteresis. The UVLO pin should not be left floating.
VCC
17
P/O/I
VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to
controller as possible.
VIN
5
P/I
Supply voltage input source for the VCC regulator. Connect to input capacitor and source power
supply connection with short, low impedance paths.
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FUNCTIONAL BLOCK DIAGRAM
VIN
RS
LIN
CIN
CSP
VIN
10uA
CSN
1.2V
RUV2
+
RUV1
STANDBY
+
UVLO
A=10
0.4V/0.3V
+
LM5122
SHUTDOWN
SLOPE
RSLOPE
SLOPE
Generator
9
VSLOPE =
COMP
+
QH
-
1.2V
HO
+
- ZCD threshold
LEVEL SHIFT
DIODE EMULATION
ERR
AMP
SS
SW
C/L
Comparator
+
COUT
VCC
PWM
Comparator
10uA
S
Q
PWM
QL
R Q
1.2V
RFB2
Skip Cycle
Comparator
700k
20mV
+
MODE
100k
CLK
LO
ADAPTIVE
TIMER
+
-
CSS
VOUT
CBST
+
-
FB
+
CVCC
DBST
+
750mV
CCOMP RCOMP
BST Charge Pump
BST
VSENSE2
1.2 V
VCC
VCC
Regulator
VSENSE1
6 u 10
RSLOPE u fSW
CHF
VIN
CS
AMP
1.2V
-
+
+
-
Diode
Emulation
Comparator
Diode
Emulation
OPT
30uA
40mV
Hysteresis
10uA
RESTART
TIMER
CLK
Clock Generator
/SYNC Detector
SYNCIN/RT
SYNCOUT
RFB1
RES
fCLK / 2
or
fCLK
5uA
CRES
AGND PGND
RT
Functional Description
The LM5122 wide input range synchronous boost controller features all of the functions necessary to implement
a highly efficient synchronous boost regulator. The regulator control method is based upon peak current mode
control. Peak current mode control provides inherent line feed-forward and ease of loop compensation. This
highly integrated controller provides strong high-side and low-side N-channel MOSFET drivers with adaptive
dead-time control. The switching frequency is user programmable up to 1 MHz set by a single resistor or
synchronized to an external clock. The LM5122’s 180º shifted clock output enables easy multi-phase
configuration.
The control mode of high-side synchronous switch can be configured as either forced PWM (FPWM) or diode
emulation mode. Fault protection features include cycle-by-cycle current limiting, hiccup mode over load
protection, thermal shutdown and remote shutdown capability by pulling down the UVLO pin. The UVLO input
enables the controller when the input voltage reaches a user selected threshold, and provides a tiny 9 μA
shutdown quiescent current when pulled low. The device is available in 20-pin HTSSOP package featuring an
exposed pad to aid in thermal dissipation.
12
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Undervoltage Lockout (UVLO)
The LM5122 features a dual level UVLO circuit. When the UVLO pin voltage is less than the 0.4 V UVLO
standby enable threshold, the LM5122 is in the shutdown mode with all functions disabled. The shutdown
comparator provides 0.1 V of hysteresis to avoid chatter during transition. If the UVLO pin voltage is greater than
0.4 V and below 1.2 V during power up, the controller is in standby mode with the VCC regulator operational and
no switching at the HO and LO outputs. This feature allows the UVLO pin to be used as a remote shutdown
function by pulling the UVLO pin down below the UVLO standby enable threshold with an external open collector
or open drain device.
VIN
UVLO Hysteresis
Current
RUV2
RUV1
STANDBY
UVLO
UVLO
Threshold
UVLO Standby
Enable Threshold
SHUTDOWN
+
+
STANDBY
SHUTDOWN
Figure 16. UVLO Remote Standby and Shutdown Control
If the UVLO pin voltage is above the 1.2 V UVLO threshold and VCC voltage exceeds the VCC UV threshold, a
startup sequence begins. UVLO hysteresis is accomplished with an internal 10 μA current source that is switched
on or off into the impedance of the UVLO setpoint divider. When the UVLO pin voltage exceeds 1.2 V, the
current source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below
the 1.2 V UVLO threshold, the current source is disabled causing the voltage at the UVLO pin to quickly fall. In
addition to the UVLO hysteresis current source, a 5 μs deglitch filter on both rising and falling edge of UVLO
toggling helps preventing chatter upon power up or down.
An external UVLO setpoint voltage divider from the supply voltage to AGND is used to set the minimum input
operating voltage of the regulator. The divider must be designed such that the voltage at the UVLO pin is greater
than 1.2 V when the input voltage is in the desired operating range. The maximum voltage rating of the UVLO
pin is 15 V. If necessary, the UVLO pin can be clamped with an external zener diode. The UVLO pin should not
be left floating. The values of RUV1 and RUV2 can be determined from Equation 1 and Equation 2.
VHYS
RUV2
ª: º
10 $ ¬ ¼
(1)
1.2V u RUV2
RUV1
ª: º
VIN(STARTUP) 1.2V ¬ ¼
(2)
where
•
•
VHYS is the desired UVLO hysteresis
VIN(STARTUP) is the desired startup voltage of the regulator during turn-on.
Typical shutdown voltage during turn-off can be calculated as follows:
VIN(SHUTDOWN) VIN(STARTUP) VHYS [V]
(3)
High Voltage VCC Regulator
The LM5122 contains an internal high voltage regulator that provides typical 7.6 V VCC bias supply for the
controller and N-channel MOSFET drivers. The input of VCC regulator, VIN, can be connected to an input
voltage source as high as 65 V. The VCC regulator turns on when the UVLO pin voltage is greater than 0.4 V.
When the input voltage is below the VCC setpoint level, the VCC output tracks VIN with a small dropout voltage.
The output of the VCC regulator is current limited at 50 mA minimum.
Upon power-up, the VCC regulator sources current into the capacitor connected to the VCC pin. The
recommended capacitance range for the VCC capacitor is 1.0 μF to 47 μF and is recommended to be at least 10
times greater than CBST value. When operating with a VIN voltage less than 6 V, the value of VCC capacitor
should be 4.7 µF or greater.
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The internal power dissipation of the LM5122 device can be reduced by supplying VCC from an external supply.
If an external VCC bias supply exists and the voltage is greater than 9 V and below 14.5 V. The external VCC
bias supply can be applied to the VCC pin directly through a diode, as shown in Figure 17.
External
VCC
VCC Supply
LM5122
CVCC
Figure 17. External Bias Supply when 9 V<VEXT<14.5 V
Shown in Figure 18 is a method to derive the VCC bias voltage with an additional winding on the boost inductor.
This circuit must be designed to raise the VCC voltage above VCC regulation voltage to shut off the internal VCC
regulator.
VCC
+
nuVOUT
nuVIN
+
+
nu(VOUT -VIN)
1:n
VIN
VOUT
+
+
Figure 18. External Bias Supply using Transformer
The VCC regulator series pass transistor includes a diode between VCC and VIN that should not be fully forward
biased in normal operation, as shown in Figure 19. If the voltage of the external VCC bias supply is greater than
the VIN pin voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent
the external bias supply from passing current to the input supply through VCC. The need for the blocking diode
should be evaluated for all applications when the VCC is supplied by the external bias supply. Especially, when
the input power supply voltage is less than 4.5 V, the external VCC supply should be provided and the external
blocking diode is required.
VIN
VIN
LM5122
External
VCC Supply
VCC
Figure 19. VIN Configuration when VVIN<VVCC
14
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Oscillator
The LM5122 switching frequency is programmable by a single external resistor connected between the RT pin
and the AGND pin. The resistor should be located very close to the device and connected directly to the RT pin
and AGND pin. To set a desired switching frequency (fSW), the resistor value can be calculated from Equation 4.
9 u 109
ª: º
fSW ¬ ¼
RT
(4)
Slope Compensation
For duty cycles greater than 50%, peak current mode regulators are subject to sub-harmonic oscillation. Subharmonic oscillation is normally characterized by observing alternating wide and narrow duty cycles. This subharmonic oscillation can be eliminated by a technique, which adds an artificial ramp, known as slope
compensation, to the sensed inductor current.
Additional slope
tON
Sensed Inductor Current
= ILIN u RS u10
Figure 20. Slope Compensation
The amount of slope compensation is programmable by a single resistor connected between the SLOPE pin and
the AGND pin. The amount of slope compensation can be calculated as follows:
6 x109
xD
fSW x RSLOPE
VSLOPE
[V]
where
D
•
1
VIN
VOUT
(5)
RSLOPE value can be determined from the following equation at minimum input voltage:
LIN u 6 u 109
ª¬: º¼
ªK u VOUT VIN(MIN) º u RS u 10
¬
¼
RSLOPE
where
•
K=0.82~1 as a default
(6)
From the above equation, K can be calculated over the input range as follows:
K
§
LIN u 6 u 109
¨1
¨
VIN u RS u 10 u RSLOPE
©
·
¸ u D'
¸
¹
where
D'
•
VIN
VOUT
(7)
In any case, K should be greater than at least 0.5. At higher switching frequency over 500 kHz, K factor is
recommended to be greater than or equal to 1 because the minimum on-time affects the amount of slope
compensation due to internal delays.
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The sum of sensed inductor current and slope compensation should be less than COMP output high voltage
(VOH) for proper startup with load and proper current limit operation. This limits the minimum value of RSLOPE to
be:
RSLOPE !
•
VIN MIN ·
¸ ª: º
VOUT ¸ ¬ ¼
¹
This equation can be used in most cases
RSLOPE !
•
5.7 u 109 §
u ¨ 1.2
¨
fSW
©
8 u 109
ª: º
fSW ¬ ¼
This conservative selection should be considered when VIN(MIN) < 5.5 V
The SLOPE pin cannot be left floating.
Error Amplifier
The internal high-gain error amplifier generates an error signal proportional to the difference between the FB pin
voltage and the internal precision 1.2 V reference. The output of the error amplifier is connected to the COMP pin
allowing the user to provide a Type 2 loop compensation network.
RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to achieve a stable voltage
loop. This network creates a pole at DC, a mid-band zero (fZ_EA) for phase boost, and a high frequency pole
(fP_EA). The minimum recommended value of RCOMP is 2 kΩ. See Feedback Compensation section.
1
fZ _ EA
ªHz º
2S u RCOMP u CCOMP ¬ ¼
(9)
fP _ EA
1
§ CCOMP u CHF
2S u RCOMP u ¨
© CCOMP CHF
·
¸
¹
ª¬Hz º¼
(10)
PWM Comparator
The PWM comparator compares the sum of sensed inductor current and slope compensation ramp to the
voltage at the COMP pin through a 1.2 V internal COMP to PWM voltage drop, and terminates the present cycle
when the sum of sensed inductor current and slope compensation ramp is greater than VCOMP –1.2 V.
ILIN
RS
CSP
CSN
+
CS A=10
AMP
RSLOPE
SLOPE
Generator
VOUT
REF
+
+
-
+
PWM
Comparator
RFB2
1.2 V
FB
Error
Amplifier
COMP
RCOMP
CCOMP
RFB1
CHF (optional)
Type 2 Compensation Components
Figure 21. Feedback Configuration and PWM Comparator
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Soft-start
The soft-start feature helps the regulator to gradually reach the steady state operating point, thus reducing
startup stresses and surges. The LM5122 regulates the FB pin to the SS pin voltage or the internal 1.2 V
reference, whichever is lower. The internal 10 μA soft-start current source gradually increases the voltage on an
external soft-start capacitor connected to the SS pin. This results in a gradual rise of the output voltage starting
from the input voltage level to the target output voltage. Soft-start time (tSS) varies by the input supply voltage, is
calculated from Equation 11.
CSS u 1.2V §
VIN ·
u ¨1
tSS
¸ ªsec º¼
10 $
9OUT ¹ ¬
©
(11)
When the UVLO pin voltage is greater than the 1.2 V UVLO threshold and VCC voltage exceeds the VCC UV
threshold, an internal 10 μA soft-start current source turns on. At the beginning of this soft-start sequence, VSS
should be allowed to fall down below 25 mV by the internal SS pull-down switch. The SS pin can be pulled down
by external switch to stop switching, but pulling up to enable switching is not allowed. The startup delay (see
Figure 22) should be long enough for high-side boot capacitor to be fully charged up by internal BST charge
pump.
The value of CSS should be large enough to charge the output capacitor during soft-start time.
10 $ u 9OUT &OUT
CSS !
u
ªF º
1.2V
IOUT ¬ ¼
(12)
Standby
Shut down
1.2V
UVLO
0.4V
VCC UV threshold
VCC
Startup delay
1.2V
10µA
current
source
SS
LO
HO-SW
VIN
VOUT
tSS
Figure 22. Startup Sequence
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HO and LO Drivers
The LM5122 contains strong N-channel MOSFET gate drivers and an associated high-side level shifter to drive
the external N-channel MOSFET switches. The high-side gate driver works in conjunction with an external boot
diode DBST, and bootstrap capacitor CBST. During the on-time of the low-side N-channel MOSFET driver, the SW
pin voltage is approximately 0 V and the CBST is charged from VCC through the DBST. A 0.1 μF or larger ceramic
capacitor, connected with short traces between the BST and SW pin, is recommended.
The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs
are never enabled at the same time. When the controller commands LO to be enabled, the adaptive dead-time
logic first disables HO and waits for HO-SW voltage to drop. LO is then enabled after a small delay (HO Fall to
LO Rise Delay). Similarly, the HO turn-on is delayed until the LO voltage has discharged. HO is then enabled
after a small delay (LO Fall to HO Rise Delay). This technique insures adequate dead-time for any size Nchannel MOSFET device, especially when VCC is supplied by a higher external voltage source. Be careful when
adding series gate resistors, as this may decrease the effective dead-time.
Care should be exercised in selecting the N-channel MOSFET devices threshold voltage, especially if the VIN
voltage range is below the VCC regulation level or a bypass operation is required. If the bypass operation is
required, especially when output voltage is less than 12 V, a logic level device should be selected for the highside N-channel MOSFET. During startup at low input voltages, the low-side N-channel MOSFET switch’s gate
plateau voltage should be sufficient to completely enhance the N-channel MOSFET device. If the low-side Nchannel MOSFET drive voltage is lower than the low-side N-channel MOSFET device gate plateau voltage
during startup, the regulator may not start up properly and it may stick at the maximum duty cycle in a high
power dissipation state. This condition can be avoided by selecting a lower threshold N-channel MOSFET switch
or by increasing VIN(STARTUP) with the UVLO pin voltage programming.
MODE Control (Forced PWM Mode and Diode Emulation Mode)
A fully synchronous boost regulator implemented with a high-side switch rather than a diode has the capability to
sink current from the output in certain conditions such as light load, overvoltage or load transient. The LM5122
can be configured to operate in either forced PWM mode or diode emulation mode.
In forced PWM mode (FPWM), reverse current flow in high-side N-channel MOSFET switch is allowed and the
inductor current conducts continuously at light or no load conditions. The benefit of the forced PWM mode is fast
light load to heavy load transient response and constant frequency operation at light or no load conditions. To
enable forced PWM mode, connect the MODE pin to VCC or tie to a voltage greater than 1.2 V. In FPWM mode,
reverse current flow is not limited.
In diode emulation mode, current flow in the high-side switch is only permitted in one direction (source to drain).
Turn-on of the high-side switch is allowed if CSP to CSN voltage is greater than 7 mV rising threshold of zero
current detection during low-side switch on-time. If CSP to CSN voltage is less than 6 mV falling threshold of
zero current detection during high-side switch on-time, reverse current flow from output to input through the highside N-channel MOSFET switch is prevented and discontinuous conduction mode of operation is enabled by
latching off the high-side N-channel MOSFET switch for the remainder of the PWM cycle. A benefit of the diode
emulation is lower power loss at light load conditions.
1.2 V
COMP
+
-
40mV
Hysteresis
1.2V
MODE
SkipCycle
+
700k
Default
150mV
20mV
+
Skip Cycle
Comparator
1.2V
100k
+
-
Diode
Emulation
Figure 23. MODE Selection
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During startup the LM5122 forces diode emulation, for startup into a pre-biased load, while the SS pin voltage is
less than 1.2 V. Forced diode emulation is terminated by a pulse from PWM comparator when SS is greater than
1.2 V. If there are no LO pulses during the soft-start period, a 350 ns one-shot LO pulse is forced at the end of
soft-start to help charge the boot strap capacitor. Due to the internal current sense delay, configuring the LM5122
for diode emulation mode should be carefully evaluated if the inductor current ripple ratio is high and when
operating at very high switching frequency. The transient performance during full load to no load in FPWM mode
should also be verified.
MODE Control (Skip Cycle Mode and Pulse Skipping Mode)
Light load efficiency of the regulator typically drops as the losses associated with switching and bias currents of
the converter become a significant percentage of the total power delivered to the load. In order to increase the
light load efficiency the LM5122 provides two types of light load operation in diode emulation mode.
The skip cycle mode integrated into the LM5122 controller reduces switching losses and improves efficiency at
light load condition by reducing the average switching frequency. Skip cycle operation is achieved by the skip
cycle comparator. When a light load condition occurs, the COMP pin voltage naturally decreases, reducing the
peak current delivered by the regulator. During COMP voltage falling, the skip cycle threshold is defined as
VMODE –20 mV and during COMP voltage rising, it is defined as VMODE +20 mV. There is 40mV of internal
hysteresis in the skip cycle comparator.
When the voltage at PWM comparator input falls below VMODE –20 mV, both HO and LO outputs are disabled.
The controller continues to skip switching cycles until the voltage at PWM comparator input increases to VMODE
+20 mV, demanding more inductor current. The number of cycles skipped depends upon the load and the
response time of the frequency compensation network. The internal hysteresis of skip cycle comparator helps to
produce a long skip cycle interval followed by a short burst of pulses. An internal 700 kΩ pull-up and 100 kΩ pulldown resistor sets the MODE pin to 0.15 V as a default. Since the peak current limit threshold is set to 750 mV,
the default skip threshold corresponds to approximately 17% of the peak level. In practice the skip level will be
lower due to the added slope compensation. By adding an external pull-up resistor to SLOPE or VCC pin or
adding an external pull-down resistor to the ground, the skip cycle threshold can be programmed. Because the
skip cycle comparator monitors the PWM comparator input which is proportional to the COMP voltage, skip cycle
operation is not recommended when the bypass operation is required.
Conventional pulse skipping operation can be achieved by connecting the MODE pin to ground. The negative 20
mV offset at the positive input of skip cycle comparator ensures the skip cycle comparator will not trigger in
normal operation. At light or no load conditions, the LM5122 skips LO pulses if the pulse width required by the
regulator is less than the minimum LO on-time of the device. Pulse skipping appears as a random behavior as
the error amplifier struggles to find an average pulse width for LO in order to maintain regulation at light or no
load conditions.
Bypass Operation (VOUT = VIN)
The LM5122 allows 100% duty cycle operation for the high-side synchronous switch when the input supply
voltage is equal to or greater than the target output voltage. An internal 200 μA BST charge pump maintains
sufficient high-side driver supply voltage to keep the high-side N-channel MOSFET switch on without the power
stage switching. The internal BST charge pump is enabled when the UVLO pin voltage is greater than 1.2 V and
the VCC voltage exceeds the VCC UV threshold. The BST charge pump generates 5.3 V minimum BST to SW
voltage when SW voltage is greater than 9 V. This requires minimum 9 V boost output voltage for proper bypass
operation. The leakage current of the boot diode should be always less than the BST charge pump sourcing
current to maintain a sufficient driver supply voltage at both low and high temperatures. Forced PWM mode is
the recommended PWM configuration when bypass operation is required.
Cycle-by-Cycle Current Limit
The LM5122 features a peak cycle-by-cycle current limit function. If the CSP to CSN voltage exceeds the 75 mV
cycle-by-cycle current limit threshold, the current limit comparator immediately terminates the LO output.
For the case where the inductor current may overshoot, such as inductor saturation, the current limit comparator
skips pulses until the current has decayed below the current limit threshold. Peak inductor current in current limit
can be calculated as follows:
75mV
IPEAK(CL)
ªA º
RS ¬ ¼
(13)
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Hiccup Mode Over-Load Protection
If cycle-by-cycle current limit is reached during any cycle, a 30 μA current is sourced into the RES capacitor for
the remainder of the clock cycle. If the RES capacitor voltage exceeds the 1.2 V restart threshold, a hiccup mode
over load protection sequence is initiated; The SS capacitor is discharged to GND, both LO and HO outputs are
disabled, the voltage on the RES capacitor is ramped up and down between 2 V hiccup counter lower threshold
and 4 V hiccup counter upper threshold eight times by 10 μA charge and 5 μA discharge currents. After the
eighth cycles, the SS capacitor is released and charged by the 10 μA soft-start current again. If a 3 V zener
diode is connected in parallel with the RES capacitor, the regulator enters into the hiccup mode off mode and
then never restarts until UVLO shutdown is cycled. Connect RES pin directly to the AGND when the hiccup
mode operation is not used.
IRES = 10µA
IRES = -5µA
4V
2.0V
1.2V
Count to Eight
RES
IRES = 30µA
Restart Delay tRD
SS
Hiccup Mode Off-time tRES
HO
LO
Figure 24. Hiccup Mode Over-Load Protection
Slave Mode and SYNCOUT
The LM5122 is designed to easily implement dual (or higher) phase boost converters by configuring one
controller as a master and all others as slaves. Slave mode is activated by connecting the FB pin to the VCC pin.
The FB pin is sampled during initial power-on and if a slave configuration is detected, the state is latched. In the
slave mode, the error amplifier is disabled and has a high impedance output, 10 μA hiccup mode off-time
charging current and 5 μA hiccup mode off-time discharging current are disabled, 5 μA normal-state RES
discharging current and 10 μA soft-start charging current are disabled, 30 μA fault-state RES charging current is
changed to 35 μA. 10 μA UVLO hysteresis current source works the same as master mode. Also, in slave mode,
the internal oscillator is disabled, and an external synchronization clock is required.
The SYNCOUT function provides a 180º phase shifted clock output, enabling easy dual-phase interleaved
configuration. By directly connecting master1 SYNCOUT to slave1 SYNCIN, the switching frequency of slave
controller is synchronized to the master controller with 180º phase shift. In master mode, if OPT pin is tied to
GND, an internal oscillator clock divided by two with 50% duty cycle is provided to achieve an 180º phase-shifted
operation in two phase interleaved configuration. Switching frequency of master controller is half of the external
clock frequency with this configuration. If the OPT pin voltage is higher than 2.7 V OPT threshold or the pin is
tied to VCC, SYNCOUT is disabled and the switching frequency of master controller becomes the same as the
external clock frequency. An external synchronization clock should be always provided and directly connected to
SYNCIN for master2, slave1 and slave2 configurations. See Interleaved Boost Configuration section for detailed
information.
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Table 1. LM5122 Multiphase Configuration
MULTIPHASE
CONFIGURATION
FB
OPT
ERROR
AMPLIFIER
SWITCHING FREQUENCY
Master1
Feedback
GND
Enable
fSYNC/2, Free running with RT resistor
SYNCOUT
fSYNC/2, fSW –180º
Slave1
VCC
GND
Disable
fSYNC, No free running
Disable
Master2
Feedback
VCC
Enable
fSYNC, No free running
Disable
Slave2
VCC
VCC
Disable
fSYNC/2, No free running
fSYNC/2, fSW –180º
Clock Synchronization
The SYNCIN/RT pin can be used to synchronize the internal oscillator to an external clock. A positive going
synchronization clock at the RT pin must exceed the RT sync rising threshold and negative going
synchronization clock at RT pin must exceed the RT sync falling threshold to trip the internal synchronization
pulse detector.
In Master1 mode, two types of configurations are allowed for clock synchronization. With the configuration in
Figure 25, the frequency of the external synchronization pulse is recommended to be within +40% and –20% of
the internal oscillator frequency programmed by the RT resistor. For example, 900 kHz external synchronization
clock and 20 kΩ RT resistor are required for 450 kHz switching in master1 mode. The internal oscillator can be
synchronized by AC coupling a positive edge into the RT pin. A 5 V amplitude pulse signal coupled through 100
pF capacitor is a good starting point. The RT resistor is always required with AC coupling capacitor with the
Figure 25 configuration, whether the oscillator is free running or externally synchronized.
Care should be taken to guarantee that the RT pin voltage does not go below –0.3 V at the falling edge of the
external pulse. This may limit the duty cycle of external synchronization pulse. There is approximately 400 ns
delay from the rising edge of the external pulse to the rising edge of LO.
fSYNC
SYNCIN/RT
CSYNC
RT
LM5122
Figure 25. Oscillator Synchronization Through AC Coupling in Master1 Mode
With the configuration in Figure 26, the internal oscillator can be synchronized by connecting the external
synchronization clock into the RT pin through RT resistor with free of the duty cycle limit. The output stage of the
external clock source should be a low impedance totem-pole structure. Default logic state of fSYNC should be low.
fSYNC
SYNCIN/RT
RT
LM5122
Figure 26. Oscillator Synchronization Through a Resistor in Master1 Mode
In master2 and slave modes, this external synchronization clock should be directly connected to the RT pin and
always provided continuously. The internal oscillator frequency can be either of two times faster than switching
frequency or the same as the switching frequency by configuring the combination of FB and OPT pins (see
Table 1).
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Maximum Duty Cycle
When operating with a high PWM duty cycle, the low-side N-channel MOSFET device is forced off each cycle.
This forced LO off-time limits the maximum duty cycle of the controller. When designing a boost regulator with
high switching frequency and high duty cycle requirements, a check should be made of the required maximum
duty cycle. The minimum input supply voltage which can achieve the target output voltage is estimated from
Equation 14 .
VIN(MIN) fSW u VOUT u (750ns margin) [V]
(14)
In normal operation, about 100 ns of margin is recommended.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low-power shutdown
mode, disabling the output drivers, disconnection switch and the VCC regulator. This feature is designed to
prevent overheating and destroying the device.
22
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APPLICATION INFORMATION
Feedback Compensation
The open loop response of a boost regulator is defined as the product of modulator transfer function and
feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator
gain and feedback gain. The modulator transfer function of a current mode boost regulator including a power
stage transfer function with an embedded current loop can be simplified as one pole, one zero and one Right
Half Plane (RHP) zero system.
Modulator transfer function is defined as follows:
§
· §
s
s
¨1
¸ u ¨1
¨
¸
¨
Ö
&
&
VOUT (s)
Z _ ESR ¹ ©
Z _ RHP
AM u ©
Ö
§
VCOMP (s)
s ·
¨1
¸
¨ &P _ LF ¸
©
¹
·
¸
¸
¹
where
RLOAD
D'
u
RS _ EQ u A S 2
AM (Modulator DC gain)
•
•
&P _ LF /RDG SROH
2
RLOAD u COUT
&Z _ ESR (65 ]HUR
1
RESR u COUT
&Z _ RHP 5+3 ]HUR
RLOAD u (D' )2
LIN _ EQ
•
•
•
•
LIN _ EQ
LIN
, RS _ EQ
n
RS
n
n is the number of the phase.
(15)
If the ESR of COUT (RESR) is small enough and the RHP zero frequency is far away from the target crossover
frequency, the modulator transfer function can be further simplified to one pole system and the voltage loop can
be closed with only two loop compensation components, RCOMP and CCOMP, leaving a single pole response at the
crossover frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees
of phase margin.
The feedback transfer function includes the feedback resistor divider and loop compensation of the error
amplifier. RCOMP, CCOMP and optional CHF configure the error amplifier gain and phase characteristics, create a
pole at origin, a low frequency zero and a high frequency pole.
Feedback transfer function is defined
s
1
&Z _ EA
VÖ COMP
AFB u
§
VÖ OUT
s
s u ¨1
¨
&
P _ EA
©
as follows:
·
¸
¸
¹
where
AFB (Feedback DC gain)
•
•
1
RFB2 u CCOMP
&Z _ EA /RZ IUHTXHQF\ ]HUR
&P _ EA +LJK IUHTXHQF\ SROH
•
CHF
1
RCOMP u CCOMP
1
RCOMP u CHF
(16)
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The pole at the origin minimizes the output steady state error. The low frequency zero should be placed to cancel
the load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output
capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an
order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at
the crossover frequency. The high frequency pole should be placed beyond the crossover frequency since the
addition of CHF adds a pole in the feedback transfer function.
The crossover frequency (open loop bandwidth) is usually selected between one twentieth and one fifth of the
fSW. In a simplified formula, the estimated crossover frequency can be defined as:
RCOMP
fCROSS
u D' [Hz]
S u RS _ EQ u RFB2 u A S u COUT
where
D'
•
VIN
VOUT
(17)
For higher crossover frequency, RCOMP can be increased, while proportionally decreasing CCOMP. Conversely,
decreasing RCOMP while proportionally increasing CCOMP, results in lower bandwidth while keeping the same zero
frequency in the feedback transfer function.
The modulator transfer function can be measured by a network analyzer and the feedback transfer function can
be configured for the desired open loop transfer function. If the network analyzer is not available, step load
transient tests can be performed to verify acceptable performance. The step load goal is minimum
overshoot/undershoot with a damped response.
Sub-Harmonic Oscillation
Peak current mode regulator can exhibit unstable behavior when operating above 50% duty cycle. This behavior
is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin.
Sub-harmonic oscillation can be prevented by adding an additional slope voltage ramp (slope compensation) on
top of the sensed inductor current. By choosing K≥0.82~1.0, the sub-harmonic oscillation will be eliminated even
with wide varying input voltage.
In time-domain analysis, the steady-state inductor current starting from an initial point returns to the same point.
When the amplitude of an end cycle current error (dI1) caused by an initial perturbation (dI0) is less than the
amplitude of dI0 or dI1/dI0 > –1, the perturbation naturally disappears after a few cycles. When dl1/dl0<-1, the
initial perturbation no longer disappear, it results in sub-harmonic oscillation in steady-state.
Steady-State
Inductor Current
dI0
tON
dI1
Inductor Current with
Initial Perturbation
Figure 27. Effect of Initial Perturbation when dl1/dl0 < -1
dI1/dI0 can be calculated as:
dI1
1
1
dI0
K
(18)
The relationship between dI1/dI0 and K factor is illustrated graphically below.
24
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Figure 28. dl1/dl0 vs K Factor
The absolute minimum value of K is 0.5. When K<0.5, the amplitude of dl1 is greater than the amplitude of dl0
and any initial perturbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in
one switching cycle. This is known as one-cycle damping. When -1<dl1/dl0<0, any initial perturbation will be
under-damped. Any perturbation will be over-damped when 0<dl1/dl0<1.
In the frequency-domain, Q, the quality factor of sampling gain term in modulator transfer function, is used to
predict the tendency for sub-harmonic oscillation, which is defined as:
1
Q
S K 0.5
(19)
The relationship between Q and K factor is illustrated in Figure 29
Figure 29. Sampling Gain Q vs K Factor
The recommended absolute minimum value of K is 0.5. High gain peaking when K is less than 0.5 results subharmonic oscillation at fSW/2. A higher value of K factor may introduce additional phase shift near the crossover
frequency, but has the benefit of reducing noise susceptibility in current loop. The maximum allowable value of K
factor can be calculated by the maximum crossover frequency equation in frequency analysis formulas in
Table 2.
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Table 2. BOOST REGULATOR FREQUENCY ANALYSIS
SIMPLIFIED FORMULA
MODULATOR TRANSER
FUNCTION
Modulator DC gain
(2)
§
s
¨1
¨
ZZ _ ESR
©
AM u
§
¨1
¨
©
VÖ OUT (s)
Ö
V
(s)
COMP
RLOAD u (D')2
LIN _ EQ
ESR zero
&Z _ ESR
1
RESR u COUT
ESR pole
Not considered
Dominant load pole
&P _ LF
(2)
·
¸
¸
¹
VÖ OUT s
Ö
VCOMP s
1
RESR1 u COUT1
&P _ ESR
1
RESR1 u COUT1 / /COUT2
Sub-harmonic double pole
K factor
FEEDBACK TRANSFER
FUNCTION
s2 ·
¸
&n2 ¸¹
2
RLOAD u COUT
Not considered
Not considered
Not considered
Q
1
S K 0.5
&n
&SW
2
S u ISW
AFB u
§
s
s u ¨1
¨
&
P
_ EA
©
1
RFB2 u (CCOMP
fn
fSW
2
K
§
LIN u 6 u 109
¨1
¨
V
u
IN RS u 10 u RSLOPE
©
·
¸ u D'
¸
¹
s
&Z _ EA
1
OUT
4 u &n
or
K=1
VÖ COMP (s)
VÖ
(s)
fSW
K 0.5
or
&P _ HF
Quality factor
§
s
¨1
¨
&P_LF
©
§
s · §
s ·
¨1
¸ u ¨1
¸
¨
&ZESR ¸ ¨© &ZRHP ¸¹
©
¹
· §
· §
s
s
¸ u ¨1
¸ u ¨1
¸ ¨
¸
¨
&
&P_HF
p _ ESR ¹ ©
¹ ©
&Z _ ESR
&P _ HF
Sampled gain inductor pole
AM u
(1)
RLOAD
D'
u
RS _ EQ u A S 2
AM
&Z _ RHP
RHP zero
· §
s
¸ u ¨1
¸ ¨
ZZ _ RHP
¹ ©
s ·
¸
ZP _ LF ¸¹
COMPREHENSIVE FORMULA
Feedback DC gain
AFB
Mid-band Gain
AFB _ MID
Low frequency zero
&Z _ EA
1
RCOMP u CCOMP
High frequency pole
&P _ EA
1
RCOMP u CHF
·
¸
¸
¹
CHF )
RCOMP
RFB2
&P _ EA
1
RCOMP u CCHF / /CCOMP
(1)
Comprehensive equation includes an inductor pole and a gain peaking at fSW/2, which is caused by sampling effect of the current mode
control. Also, it assumes that a ceramic capacitor COUT2 (No ESR) is connected in parallel with COUT1. RESR1 represents ESR of COUT1.
(2)
With multiphase configuration,
number of phases.
26
LIN _ EQ
LIN
RS _ EQ
n ,
RS R
LOAD
n ,
VOUT
IOUT of each phase u n ,
and COUT = COUT of each phase x n, where n =
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Table 2. BOOST REGULATOR FREQUENCY ANALYSIS (continued)
SIMPLIFIED FORMULA
§
s
¨1
¨ &Z _ ESR
©
AM u AFB u
§
¨1
¨
©
OPEN LOOP RESPONSE
T s
Crossover frequency (3)
(Open loop band width)
fCROSS
· §
s
¸ u ¨1
¸ ¨ &Z _ RHP
¹ ©
s ·
¸
&P _ LF ¸¹
·
¸
¸
¹u
COMPREHENSIVE FORMULA
1
s
&Z _ EA
§
s
s u ¨1
¨ &P _ EA
©
RCOMP
u D'
S u RS _ EQ u RFB2 u A S u COUT
·
¸
¸
¹
§
· §
·
s
s
¨1
¸ u ¨1
¸
¨
&Z _ ESR ¸¹ ¨© &Z _ RHP ¸¹
©
AM u AFB u
§
· §
s · §
s
s
¨1
¸ u ¨1
¸ u ¨1
¨
&P _ LF ¸¹ ¨©
&p _ ESR ¸¹ ¨©
&PHF
©
T s
fSW &Z _RHP
or
whichever is smaller
5
2u Su 4
fCROSS _MAX
1
s2 ·
¸
&n2 ¸¹
u
s
&Z _ EA
§
s
s u ¨1
¨
&P _ EA
©
·
¸
¸
¹
Use graphic tool
fCROSS _MAX
Maximum cross over
frequency (4)
(1)
fSW §
u ¨ 1 4 u Q2
4uQ ©
1 ·¸
¹
or
&Z _ RHP
2u Su 4
, whichever is smaller
(3)
(4)
f
&Z _ RHP
CCOMP
RLOAD u COUT
D'
4 u RCOMP , and
Assuming &Z _ EA &P _ LF, &P _ EA &Z _ ESR, CROSS 2 u S u 10 ,
The frequency at which 45º phase shift occurs in modulator phase characteristics.
VIN
VOUT .
Interleaved Boost Configuration
Interleaved operation offers many advantages in single output, high current applications such as higher
efficiency, lower component stresses and reduced input and output ripple. For dual phase interleaved operation,
the output power path is split reducing the input current in each phase by one-half. Ripple currents in the input
and output capacitors are reduced significantly since each channel operates 180 degrees out of phase from the
other. Shown in Figure 30 is a normalized (IRMS/IOUT) output capacitor ripple current vs duty cycle for both a
single phase and dual phase boost converter, where IRMS is the output current ripple RMS.
Figure 30. Normalized Output Capacitor RMS Ripple Current
To configure for dual phase interleaved operation, one device should be configured as a master and the other
device should be configured in slave mode by connecting FB to VCC. Also COMP, UVLO, RES, SS and
SYNCOUT on the master side should be connected to COMP, UVLO, RES, SS and SYNCIN on slave side
respectively. The compensation network is connected between master FB and the common COMP connection.
The output capacitors of the two power stages are connected together at the common output.
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VSUPPLY
VOUT
+
CSN VCC BST
SW
CSP
VIN
LO
HO
UVLO
SLOPE
RES
OPT
SS
SYNCOUT
SYNCIN/RT
FB
COMP
MASTER
VSUPPLY
CSN VCC
CSP
BST
SW
LO
VIN
HO
COMP
SYNCIN/RT
SLOPE
OPT
SS
VCC
RES
FB
UVLO
SLAVE
Figure 31. Dual Phase Interleaved Boost Configuration
Shown in Figure 32 is a dual phase timing diagram. The 180° phase shift is realized by connecting SYNCOUT on
the master side to the SYNCIN on the slave side.
fSYNC
Free running when no
SYNCIN(MASTER)
external synchronization.
Optional fSYNC
GND
Master
CSYNC
SYNCIN/RT
(5VPP)
SYNCOUT
RT
Duty cycle of fSYNC
Should be controlled
for RT not to go below GND
Internal
CLK(MASTER)
OPT=GND
SW(MASTER)
Slave
SYNCIN/RT
OPT=GND
SYNCOUT(MASTER)
SYNCIN(SLAVE)
(50%Duty-cycle)
Internal
CLK(SLAVE)
SW(SLAVE)
Figure 32. Dual Phase Configuration and Timing Diagram
Shown in Figure 33 are two possible 4-phase configurations and the timing diagrams. Each channel is
synchronized by an individual external clock in the diagram (a). The SYNCOUT pin is used in the diagram (b)
requiring only one external clock source. A 50% duty cycle of external synchronization pulse should be always
provided with this daisy chain configuration.
28
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Current sharing between phases is achieved by sharing one error amplifier output of the master controller with
the 3 slave controllers. Resistor sensing is a preferred method of current sensing to accurately balance the
phase currents.
fSYNC should be always provided
Master
(5VPP)
SYNCIN/RT
OPT=VCC
fSYNC1
fSYNC1
SYNCIN_MASTER
Slave1
SYNCIN/RT
fSYNC2
OPT=GND
fSYNC2
SYNCIN_SLAVE1
Slave2
fSYNC3
SYNCIN_SLAVE2
SYNCIN/RT
OPT=GND
fSYNC3
fSYNC4
SYNCIN_SLAVE3
Slave3
SYNCIN/RT
fSYNC4
OPT=GND
Master
fSYNC should be always provided
(5VPP)
fSYNC
SYNCIN
RT
D QZ
SYNCOUT
OPT=GND
fSYNC
Slave1
SYNCIN_MASTER
SYNCIN
Q
OPT=GND
SYNCIN_SLAVE1
Slave2
SYNCIN
RT
SYNCOUT
OPT=VCC
Slave3
SYNCIN_SLAVE2
SYNCIN_SLAVE3
SYNCIN
OPT=GND
Figure 33. 4-Phase Timing Diagram (a) Individual Clock (b) Daisy Chain
DCR Sensing
For the applications requiring lowest cost with minimum conduction loss, Inductor DC resistance (DCR) is used
to sense the inductor current rather than using a sense resistor. Shown in Figure 34 is a DCR sensing
configuration using two DCR sensing resistors and one capacitor.
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VOUT
LIN
RDCR
VIN
+
RCSP
+
CDCR
RCSN
SW
HO
LO
CSN
CSP
LM5122
Figure 34. DCR Sensing
RCSN and CDCR selection should meet Equation 20 since this indirect current sensing method requires a time
constant matching. CDCR is usually selected to be in the range of 0.1 µF to 2.2 µF.
LIN
CDCR u RCSN
RDCR
(20)
Smaller value of RCSN minimizes the voltage drop caused by CSN bias current, but increases the dynamic power
dissipation of RCSN. The DC voltage drop of RCSN can be compensated by selecting the same value of RCSP, but
the gain of current amplifier, which is typically 10, is affected by adding RCSP. The gain of current amplifier with
the DCR sensing network can be determined as:
A CS _ DCR 12.5 k: / (1.25 k: RCSP )
(21)
Due to the reduced accuracy of DCR sensing, FPWM mode operation is recommended when DCR sensing is
used.
Output Overvoltage Protection
Output overvoltage protection can be achieved by adding a simple external circuit. The output overvoltage
protection circuit shown in Figure 35 shuts down the LM5122 when the output voltage exceeds the overvoltage
threshold set by the zener diode.
VOUT
LM5122
UVLO
Figure 35. Output Overvoltage Protection
30
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PC Board Layout Recommendation
In a boost regulator, the primary switching loop consists of the output capacitor and N-channel MOSFET power
switches. Minimizing the area of this loop reduces the stray inductance and minimizes noise. Especially, placing
high quality ceramic output capacitors as close to this loop earlier than bulk aluminum output capacitors
minimizes output voltage ripple and ripple current of the aluminum capacitors.
In order to prevent a dv/dt induced turn-on of high-side switch, HO and SW should be connected to the gate and
source of the high-side synchronous N-channel MOSFET switch through short and low inductance paths. In
FPWM mode, the dv/dt induced turn-on can occur on the low-side switch. LO and PGND should be connected to
the gate and source of the low-side N-channel MOSFET, through short and low inductance paths. All of the
power ground connections should be connected to a single point. Also, all of the noise sensitive low power
ground connections should be connected together near the AGND pin and a single connection should be made
to the single point PGND. CSP and CSN are high impedance pins and noise sensitive. CSP and CSN traces
should be routed together with kelvin connections to the current sense resistor as short as possible. If needed,
place 100 pF ceramic filter capacitor as close to the device. MODE pin is also high impedance and noise
sensitive. If an external pull-up or pull-down resistor is used at MODE pin, the resistor should be placed as close
the device. VCC, VIN and BST capacitor must be as physically close as possible to the device.
The LM5122 has an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad
helps conduct heat away from the device. The junction to ambient thermal resistance varies with application. The
most significant variables are the area of copper in the PC board, the number of vias under the exposed pad and
the amount of forced air cooling. The integrity of the solder connection from the device exposed pad to the PC
board is critical. Excessive voids greatly decrease the thermal dissipation capacity. The highest power dissipating
components are the two power switches. Selecting N-channel MOSFET switches with exposed pads aids the
power dissipation of these devices.
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Design Example and Component Selection
OPERATING CONDITIONS
● Output Voltage (VOUT)
:
24 V
● Full Load Current (IOUT)
:
4.5 A
● Output Power
:
108 W
● Minimum Input Voltage (VIN(MIN))
:
9V
● Typical Input Voltage (VIN(TYP))
:
12 V
● Maximum Input Voltage (VIN(MAX))
:
20 V
● Switching Frequency (fSW)
:
250 kHz
TIMING RESISTOR RT
Generally, higher frequency applications are smaller but have higher losses. Operation at 250 kHz is selected for
this example as a reasonable compromise between small size and high-efficiency. The value of RT for 250 kHz
switching frequency is calculated as follows:
RT
9 u 109
fSW
9 u 109
250 kHz
36.0 k:
(22)
A standard value of 36.5 kΩ is chosen for RT.
UVLO DIVIDER RUV2, RUV1
The desired startup voltage and the hysteresis are set by the voltage divider RUV2, RUV1. The UVLO shutdown
voltage should be high enough to enhance the low-side N-channel MOSFET switch fully. For this design, the
startup voltage is set to 8.7 V which is 0.3 V below VIN(MIN). VHYS is set to 0.5 V. This results 8.2 V of
VIN(SHUTDOWN). The values of RUV2, RUV1 are calculated as follows:
VHYS
0.5 V
RUV2
50 k:
IHYS
10 PA
(23)
RUV1
1.2V u RUV2
VIN(STARTUP) 1.2V
1.2V u 50 k:
8.7V 1.2V
8 k:
(24)
A standard value of 49.9 kΩ is selected for RUV2. RUV1 is selected to be a standard value of 8.06 kΩ.
INPUT INDUCTOR LIN
The inductor ripple current is typically set between 20% and 40% of the full load current, known as a good
compromise between core loss and copper loss of the inductor. Higher ripple current allows for a smaller inductor
size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. For this
example, a ripple ratio (RR) of 0.25, 25% of the input current was chosen. Knowing the switching frequency and
the typical output voltage, the inductor value can be calculated as follows:
LIN
VIN
VIN ·
1 §
u
u ¨1
¸
IIN u RR fSW ©
VOUT ¹
12V
1
§ 12V ·
u
u ¨1
108W
250 kHz © 24V ¸¹
u 0.25
12V
10.7 +
(25)
The closest standard value of 10 μH was chosen for LIN.
The saturation current rating of inductor should be greater than the peak inductor current, which is calculated at
the minimum input voltage and full load. 8.7 V startup voltage is used conservatively.
IPEAK
32
IIN
§
VIN
VIN ·
1
u
u ¨1
¸
2 LIN u fSW © VOUT ¹
24V u 4.5A
8.7V
1
8.7V
§ 8.7V ·
13.5 A
u
u 1
2 10 + u
N+] ©¨
9 ¹¸
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CURRENT SENSE RESISTOR RS
The maximum peak input current capability should be 20~50% higher than the required peak current at low input
voltage and full load, accounting for tolerances. For this example, 40% is margin is chosen.
VCS TH1
75 mV
RS
3.97 m
IPEAK(CL) 13.5A u 1.4
(27)
A closest standard value of 4 mΩ is selected for RS. The maximum power loss of RS is calculated as follows.
PLOSS(RS)
I2R
(13.5A u 1.4)2 u 4mQ 1.43W
(28)
CURRENT SENSE FILTER RCSFP, RCSFN, CCS
The current sense filter is optional. 100 pF of CCS and 100 Ω of RCSFP, RCSFN are normal recommendations.
Because CSP and CSN pins are high impedance, CCS should be placed physically as close to the device.
VIN
RCSFN
+
RCSFP
RS
CSN
LM5122
CCS
CSP
Figure 36. Current Sense Filter
SLOPE COMPENSATION RESISTOR RSLOPE
The K value is selected to be 1 at the minimum input voltage. RSLOPE should be carefully selected so that the
sum of sensed inductor current and slope compensation is less than COMP output high voltage.
RSLOPE !
8 u 109
fSW
8 u 109
250 kHz
32 k:
(29)
9
RSLOPE
LIN u 6 u 10
ªK u VOUT VIN(MIN) º u RS u 10
¬
¼
9
10 + u u
1u 24V 9V u 4m: u 10
100 k:
(30)
A closest standard value of 100 kΩ is selected for RSLOPE.
OUTPUT CAPACITOR COUT
The output capacitors smooth the output voltage ripple and provide a source of charge during transient loading
conditions. Also the output capacitors reduce the output voltage overshoot when the load is disconnected
suddenly.
Ripple current rating of output capacitor should be carefully selected. In boost regulator, the output is supplied by
discontinuous current and the ripple current requirement is usually high. In practice, the ripple current
requirement can be dramatically reduced by placing high quality ceramic capacitors earlier than the bulk
aluminum capacitors as close to the power switches.
The output voltage ripple is dominated by ESR of the output capacitors. Paralleling output capacitor is a good
choice to minimize effective ESR and split the output ripple current into capacitors.
In this example, three 330 µF aluminum capacitors are used to share the output ripple current and source the
required charge. The maximum output ripple current can be simply calculated at the minimum input voltage as
follows:
IOUT
4.5A
IRIPPLE _ MAX(COUT)
6A
VIN(MIN)
9V
u
2
2u
24V
VOUT
(31)
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Assuming 60 mΩ of ESR per an output capacitor, the output voltage ripple at the minimum input voltage is
calculated as follows:
§
· 4.5A § 60m:
IOUT
·
1
1
VRIPPLE _ MAX(COUT)
u ¨R
u
¸
¸ 0.252V
VIN(MIN) © ESR 4 u COUT u fSW ¹
9V ¨© 3
4 u 3 u 330 ) u
N+] ¹
24V
VOUT
(32)
In practice, four 10 µF ceramic capacitors are additionally placed earlier than the bulk aluminum capacitors to
reduce the output voltage ripple and split the output ripple current.
Due to the inherent path from input to output, unlimited inrush current can flow when the input voltage rises
quickly and charges the output capacitor. The slew rate of input voltage rising should be controlled by a hot-swap
or by starting the input power supply softly for the inrush current not to damage the inductor, sense resistor or
high-side N-channel MOSFET switch.
INPUT CAPACITOR CIN
The input capacitors smooth the input voltage ripple. Assuming high quality ceramic capacitors are used for the
input capacitors, the maximum input voltage ripple which happens when the input voltage is half of the output
voltage can be calculated as follows:
VOUT
24V
VRIPPLE _ MAX(CIN)
0.09V
32 u LIN u CIN u fSW 2 32 u 10 + u u
)u
N+]2
(33)
The value of input capacitor is also a function of source impedance, the impedance of source power supply. The
more input capacitor will be required to prevent a chatter condition upon power up if the impedance of source
power supply is not enough low.
VIN FILTER RVIN, CVIN
An R-C filter (RVIN, CVIN) on VIN pin is optional. It is not required if CIN capacitors are high quality ceramic
capacitors and placed physically close to the device. The filter helps to prevent faults caused by high frequency
switching noise injection into the VIN pin. A 0.47 μF ceramic capacitor is used this example. 3 Ω of RVIN and 0.47
µF of CVIN are normal recommendations. A larger filter with 2.2 µ~4.7 µF CVIN is recommended when the input
voltage is lower than 8 V or the required duty cycle is close to the maximum duty cycle limit.
VIN
VIN
RVIN
CVIN
LM5122
Figure 37. VIN Filter
BOOTSTRAP CAPACITOR CBST AND BOOST DIODE DBST
The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side Nchannel MOSFET device gate during each cycle’s turn-on and also supplies recovery charge for the bootstrap
diode. These current peaks can be several amperes. The recommended value of the bootstrap capacitor is 0.1
μF. CBST should be a good quality, low ESR, ceramic capacitor located at the pins of the device to minimize
potentially damaging voltage transients caused by trace inductance. The minimum value for the bootstrap
capacitor is calculated as follows:
QG
CBST
ªF º
û9BST ¬ ¼
(34)
Where QG is the high-side N-channel MOSFET gate charge and ΔVBST is the tolerable voltage droop on CBST,
which is typically less than 5% of VCC or 0.15 V, conservatively. In this example, the value of the BST capacitor
(CBST) is 0.1 µF.
34
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The voltage rating of DBST should be greater than the peak SW node voltage plus 16 V. A low leakage diode is
mandatory for the bypass operation. The leakage current of DBST should be low enough for the BST charge
pump to maintain a sufficient high-side driver supply voltage at high temperature. A low leakage diode also
prevents the possibility of excessive VCC voltage during shutdown, in high output voltage applications. If the
leakage is excessive, a zener VCC clamp or bleed resistor may be required. High-side driver supply voltage
should be greater than the high-side N-channel MOSFET switch’s gate plateau at the minimum input voltage.
VCC CAPACITOR CVCC
The primary purpose of the VCC capacitor is to supply the peak transient currents of the LO driver and bootstrap
diode as well as provide stability for the VCC regulator. These peak currents can be several amperes. The value
of CVCC should be at least 10 times greater than the value of CBST, and should be a good quality, low ESR,
ceramic capacitor. CVCC should be placed close to the pins of the IC to minimize potentially damaging voltage
transients caused by trace inductance. A value of 4.7 µF was selected for this design example.
OUTPUT VOLTAGE DIVIDER RFB1, RFB2
RFB1 and RFB2 set the output voltage level. The ratio of these resistors is calculated as follows:
VOUT
RFB2
1
RFB1
1.2V
(35)
The ratio between RCOMP and RFB2 determines the mid-band gain, AFB_MID. A larger value for RFB2 may require a
corresponding larger value for RCOMP. RFB2 should be large enough to keep the total divider power dissipation
small. 49.9 kΩ in series with 825 Ω was chosen for high-side feedback resistors in this example, which results in
a RFB1 value of 2.67 kΩ for 24 V output.
SOFT-START CAPACITOR CSS
The soft-start time (tSS) is the time for the output voltage to reach the target voltage from the input voltage. The
soft-start time is not only proportional with the soft-start capacitor, but also depends on the input voltage. With
0.1 µF of CSS, the soft-start time is calculated as follows:
CSS u 1.2V § VIN(MAX) · 0.1 ) u 9 §
9·
tSS(MIN)
2 msec
u ¨¨1
u ¨1
¸¸
ISS
VOUT ¹
10 $
9 ¸¹
©
©
(36)
t SS(MAX)
VIN(MIN)
CSS u 1.2V §
u ¨¨ 1
ISS
VOUT
©
·
¸¸
¹
0.1 ) u
9 §
u ¨1
10 $
©
9 ·
9 ¸¹
7.5 msec
(37)
RESTART CAPACITOR CRES
The restart capacitor determines restart delay time tRD and hiccup mode off time tRES (see Figure 24). tRD should
be greater than tSS(MAX). The minimum required value of CRES can be calculated at the low input voltage as
follows:
IRES u tSS(MAX) 30 $ u
PVHF
CRES(MIN)
0.19 PF
VRES
1.2V
(38)
A standard value of 0.47 µF is selected for CRES.
LOW-SIDE POWER SWITCH QL
Selection of the power N-channel MOSFET devices by breaking down the losses is one way to compare the
relative efficiencies of different devices. Losses in the low-side N-channel MOSFET device can be separated into
conduction loss and switching loss.
Low-side conduction loss is approximately calculated as follows:
2
PCOND(LS)
D u IIN2 u RDS _ ON(LS) u 1.3
§
VIN · § IOUT u VOUT ·
¨1
¸u¨
¸ u RDS _ ON(LS) u 1.3 [W]
VOUT ¹ ©
VIN
¹
©
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Where, D is the duty cycle and the factor of 1.3 accounts for the increase in the N-channel MOSFET device onresistance due to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature onresistance of the N-channel MOSFET device can be estimated using the RDS(ON) vs temperature curves in the Nchannel MOSFET datasheet.
Switching loss occurs during the brief transition period as the low-side N-channel MOSFET device turns on and
off. During the transition period both current and voltage are present in the channel of the N-channel MOSFET
device. The low-side switching loss is approximately calculated as follows:
PSW(LS) 0.5 u VOUT u IIN u (tR tF ) u fSW [W]
(40)
tR and tF are the rise and fall times of the low-side N-channel MOSFET device. The rise and fall times are usually
mentioned in the N-channel MOSFET datasheet or can be empirically observed with an oscilloscope.
An additional Schottky diode can be placed in parallel with the low-side N-channel MOSFET switch, with short
connections to the source and drain in order to minimize negative voltage spikes at the SW node.
HIGH-SIDE POWER SWITCH QH AND ADDITIONAL PARALLEL SCHOTTKY DIODE
Losses in the high-side N-channel MOSFET device can be separated into conduction loss, dead-time loss and
reverse recovery loss. Switching loss is calculated for the low-side N-channel MOSFET device only. Switching
loss in the high-side N-channel MOSFET device is negligible because the body diode of the high-side N-channel
MOSFET device turns on before and after the high-side N-channel MOSFET device switches.
High-side conduction loss is approximately calculated as follows:
2
PCOND(HS)
(1 D) u IIN2 u RDS _ ON(HS) u 1.3
§ VIN · § IOUT u VOUT ·
¨
¸u¨
¸ u RDS _ ON(HS) u 1.3 [W]
VIN
¹
© VOUT ¹ ©
(41)
Dead-time loss is approximately calculated as follows:
PDT(HS) VD x IIN x (tDLH tDHL ) x fSW [W]
where
•
VD is the forward voltage drop of the high-side NMOS body diode.
(42)
Reverse recovery characteristics of the high-side N-channel MOSFET switch strongly affect efficiency, especially
when the output voltage is high. Small reverse recovery charge helps to increase the efficiency while also
minimizes switching noise.
Reverse recovery loss is approximately calculated as follows:
PRR(HS) VOUT u QRR u fSW [W]
(43)
where
•
QRR is the reverse recovery charge of the high-side N-channel MOSFET body diode.
(44)
An additional Schottky diode can be placed in parallel with the high-side switch to improve efficiency. Usually, the
power rating of this parallel Schottky diode can be less than the high-side switch’s because the diode conducts
only during dead-times. The power rating of the parallel diode should be equivalent or higher than high-side
switch’s if bypass operation is required, hiccup mode operation is required or any load exists before switching.
SNUBBER COMPONENTS
A resistor-capacitor snubber network across the high-side N-channel MOSFET device reduces ringing and
spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to
the output voltage. Selecting the values for the snubber is best accomplished through empirical methods. First,
make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and
50 Ω. Increasing the value of the snubber capacitor results more damping, but this also results higher snubber
losses. Select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the
switch waveform at heavy load. A snubber may not be necessary with an optimized layout.
LOOP COMPENSATION COMPONENTS CCOMP, RCOMP, CHF
RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to produce a stable voltage
loop. For a quick start, follow the 4 steps listed below:
36
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STEP1: Select fCROSS
Select the cross over frequency (fCROSS) at one fourth of the RHP zero or one tenth of the switching frequency
whichever is lower.
fSW
25 kHz
10
(45)
VOUT
VIN 2
)
u(
fZ _ RHP
RLOAD u (D')2
IOUT
VOUT
5.3 kHz
4
4 u 2S u LIN _ EQ
4 u 2S u LIN _ EQ
(46)
5.3 kHz of the crossover frequency is selected between two. RHP zero at minimum input voltage should be
considered if the input voltage range is wide.
STEP2: Determine required RCOMP
Knowing fCROSS, RCOMP is calculated as follows:
RCOMP
fCROSS u S u RS u RFB2 u 10 u COUT u
VOUT
VIN
68.5 k:
(47)
A standard value of 68.1 kΩ is selected for RCOMP
STEP3: Determine CCOMP to cancel load pole. Place error amplifier zero at the twice of load pole frequency.
Knowing RCOMP, CCOMP is calculated as follows:
RLOAD x COUT
CCOMP
20.2nF
4 x RCOMP
(48)
A standard value of 22 nF is selected for CCOMP
STEP4: Determine CHF to cancel ESR zero.
Knowing RCOMP, RESR and CCOMP, CHF is calculated as follows:
RESR u COUT u CCOMP
CHF
307 pF
RCOMP u CCOMP RESR u COUT
(49)
A standard value of 330 pF is selected for CCOMP
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Figure 38. Single Phase Example Schematic
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ALTERNATE APPLICATION IDEAS
VSUPPLY
VOUT
+
LO
HO
LM5122
CSN
FB
CSP
COMP
VIN
RES
SYNCOUT
SS
OPT
PGND
AGND
UVLO
SLOPE
SYNCIN/RT
MODE VCC BST SW
Figure 39. Sepic Converter Simplified Schematic
VSUPPLY 9V ~ 36V
VOUT 12V
744851101
COUPLED
INDUCTOR
LO
LM5122
HO
CSN
FB
CSP
COMP
VIN
SYNCOUT
UVLO
SLOPE
SYNCIN/RT
+
RES
SS
OPT
PGND
AGND
MODE VCC BST SW
Figure 40. Non-Isolated Synchronous Flyback Converter Simplified Schematic
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LM5122MH/NOPB
ACTIVE
HTSSOP
PWP
20
73
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM5122
MH
LM5122MHX/NOPB
ACTIVE
HTSSOP
PWP
20
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM5122
MH
LM5122QMH/NOPB
ACTIVE
HTSSOP
PWP
20
73
TBD
Call TI
Call TI
-40 to 125
LM5122QMHX/NOPB
ACTIVE
HTSSOP
PWP
20
2500
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5122, LM5122-Q1 :
• Catalog: LM5122
• Automotive: LM5122-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
MECHANICAL DATA
PWP0020A
MXA20A (Rev C)
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