1 1 0 SLUS477 – FEBRUARY 2000 – REVISED DECEMBER 2000 Thermal Packaging for Low Junction LVD-Only Active Termination 2.7-V to 5.25-V Operation Differential Failsafe Bias Integrated SPI-3 Mode Change/Filter Delay Temperature and Better MTBF 2.85-V Regulator With Load Share Meets Ultra2 (SPI-2 LVD), Ultra3/Ultra160 (SPI-3) and Ultra320 (SPI-4) Standards description The UCC5642 is an LVD-only small computer system interface (SCSI) terminator that integrates the mode change delay function required by the SPI-3 specification. The device senses what types of SCSI drivers are present on the bus via the voltage on the DIFFSENS SCSI control line. Single-ended (SE) and high-voltage differential (HVD) (EIA485) SCSI drivers are not supported. If the chip detects the presence of an SE or HVD SCSI driver, it disconnects itself by switching all terminating resistors off the bus and enters a high-impedance state. The terminator can also be commanded to disconnect the terminating resistors with the DISCNCT input. Impedance is trimmed for accuracy and maximum effectiveness. Bus lines are biased to a failsafe state to ensure signal integrity. A 2.85-V, 300-mA sourcing regulator on chip can share with two other UCC5642 devices in a parallel configuration for a 900 mA total. The UCC5642 is offered in a 36-pin QSOP (MWP) package for a temperature range of 0°C to 70°C. block diagram VCC 24 VOUTM 29 VCC TO 2.85 V REGULATOR VOLTAGE AMPLIFIER 3.6 kΩ 4 kΩ CURRENT AMPLIFIER 1.5 V HPD 2.1 V DIFFB LVD FILTER/ DELAY 5 0.6 V TRMPWR 12 TTL DRIVERS 25 VREG 30 SHARE 31 LVD 6 DIFSENS 21 L1– 22 L1+ 34 L9– 33 L9+ SE DIFFSENS REF 1.3 V ENABLE SOURCE/SINK REGULATOR SW1 10 µA DISCNCT 7 HS/GND 8 HS/GND 10 HS/GND 26 28 GND 32 SW1 SE DOWN LVD DOWN HPD DOWN DISCNCT OPEN 56 mV − + 56 mV + ENABLE MODE HS/GND 124 LVD REF 1.25 V 124 OTHER SWITCHES OPEN DOWN OPEN OPEN 52 52 – 56 mV 52 – + 56 mV 52 + – 11 REG UDG-00158 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated #& ')%+#'& #* ,))&+ * ' (,$#+#'& + )',+* '& ')% +' *(# #+#'&* () +" +)%* ' .* &*+),%&+* *+&) -))&+/ )',+#'& ()'**#&! '* &'+ &**)#$/ #&$, +*+#&! ' $$ ()%+)* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLUS477 – FEBRUARY 2000 – REVISED DECEMBER 2000 package information MWP PACKAGE (TOP VIEW) AVAILABLE OPTIONS PACKAGED DEVICES TJ 0°C to 70°C † QSOP (MWP) UCC5642MWP Available tape and reeled. Add R suffix to device type to order quantities of 1000 devices per reel. 1 LINE7+ LINE8– 36 2 LINE7– LINE8+ 35 3 LINE6+ LINE9– 34 4 LINE6– LINE9+ 33 5 DIFFB SGND 32 6 DIFSENS LVD 31 7 DISCNCT SHARE 30 8 GND VOUTM 29 9 GND GND 28 10 GND GND 27 11 REG GND 26 12 TRMPWR 13 LINE5– VREG 25 VCC 24 14 LINE5+ N/C 23 15 LINE4– LINE1+ 22 16 LINE4+ LINE1– 21 17 LINE3– LINE2+ 20 18 LINE3+ LINE2– 19 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† TRMPWR voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Signal line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 5 V Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Interface Products Data Book (TI Literature Number SLUD002) for thermal limitations and considerations of packages. recommended operating conditions TRMPWR voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 5.25 V 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS477 – FEBRUARY 2000 – REVISED DECEMBER 2000 electrical characteristics, these specifications apply for TA = TJ = 0°C to 70°C, TRMPWR = 2.7 V to 5.25 V, VCC = 4.75 V to 5.25 V,(unless otherwise stated) TRMPWR supply current section PARAMETER TRMPWR supply current TEST CONDITIONS MIN TYP MAX UNITS LVD SCSI mode 25 40 mA DISCNCT mode 0.5 1 mA 5 10 mA VCC supply current regulator section PARAMETER TEST CONDITIONS 1.25 V regulator output voltage 0.5 ≤ VCM ≤ 2, 1.25 V regulator source current VREG = 0 V VREG = 3.0 V 1.25 V regulator sink current See Note 1 MIN 1.15 TYP MAX UNITS 1.25 1.35 V –100 –80 mA 80 100 2.85 V regulator output voltage 2.79 2.85 2.91 V 2.85 V regulator source current –800 –600 –400 mA 3 5 8 mA 2.85 V regulator sink current Share output gain Share input gain VOUTM input resistance mA 4.8 6.2 7.2 V/A 0.130 0.160 0.192 A/V 4 7.6 12 kΩ diff sense driver (DIFFSENS) section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 1.3 V DIFFSENS output voltage 0.5 mA ≤ IDIFSENS ≤ 50 µA 1.2 1.4 V 1.3 V DIFFSENS source current VDIFFSENS = 0 V VDIFFSENS = 2.75 V –15 –5 mA 50 200 µA 1.3 V DIFFSENS sink current 1.3 differential termination section PARAMETER TEST CONDITIONS Differential impedance Common mode impedance L+ and L– shorted together, See Note 2 Differential bias voltage Common mode bias MIN TYP UNITS Ω 105 110 110 140 165 Ω 125 mV 1.35 V 100 L+ and L– shorted together MAX 100 1.15 1.25 NOTES: 1. VCM is applied to all L+ and L– lines simultaneously. (2.0 V 0.5 V) 2. Z @ VCM(max) = 2.0, VCM(min) = 0.5 V. CM I I I VCM(max) VCM(min) 3. Ensured by design. Not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLUS477 – FEBRUARY 2000 – REVISED DECEMBER 2000 electrical characteristics, these specifications apply for TA = TJ = 0°C to 70°C, TRMPWR = 2.7 V to 5.25 V, VCC = 4.75 V to 5.25 V, (unless otherwise stated) disconnected termination section (applies to each line pair, 1–9, in DISCNCT, SE or HVD mode) Output leakage Output capacitance Single ended measurement to ground, See Note 3 400 nA 3 pF disconnect (DISCNCT) and diff buffer (DIFFB) input section PARAMETER TEST CONDITIONS MIN TYP MAX 2.0 UNITS DISCNCT threshold 0.8 DISCNCT input current –30 V DIFFB SE to LVD SCSI threshold 0.5 0.7 DIFFB LVD SCSI to HPD threshold 1.9 2.4 V DIFFB input current –1 1 µA µA –10 V low voltage differential (LVD) status bit section PARAMETER ISOURCE ISINK TEST CONDITIONS MIN VLOAD = 2.4 V VLOAD = 0.4 V TYP –6 2 MAX –4 5 UNITS mA mA time delay/filter section PARAMETER TEST CONDITIONS MIN A new mode change can start any time after a previous mode change has been detected. Mode change delay 100 TYP 190 MAX 300 UNITS ms thermal shutdown section PARAMETER Thermal shutdown threshold TEST CONDITIONS For increasing temperature, MIN See Note 3 Thermal shutdown hysteresis 3. Ensured by design. Not production tested. 4 TYP 155 10 NOTES: 1. VCM is applied to all L+ and L– lines simultaneously. (2.0 V 0.5 V) 2. Z @ VCM(max) = 2.0, VCM(min) = 0.5 V. CM I I I VCM(max) VCM(min) 140 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 170 UNITS °C °C SLUS477 – FEBRUARY 2000 – REVISED DECEMBER 2000 pin descriptions DIFFB: Input pin for the comparators that select SE, LVD or HIPD modes of operation. This pin should be decoupled with a 0.1-µF capacitor to ground and then coupled to the DIFSENS pin through a 20-kΩ resistor. DIFSENS: SCSI bus DIFFSENS line driver. DISCNCT: Input pin used to shut down the terminator if the terminator is not connected at the end of the bus. Connect this pin to ground to activate the terminator or open to disable the terminator. HS/GND: Heat sink ground pins. Connected to large ground area PC board traces to increase the power dissipation capability. GND: Power supply return. L1– thru L9–: Line termination pins. Negative lines in differential pair. In HIPD and SE mode, these lines are high impedance. L1+ thru L9+: Line termination pins. Positive lines in differential pair. In HIPD and SE mode, these lines are high impedance. REG: Regulator bypass pin, must be connected to a 4.7-µF capacitor to ground and a high frequency, low ESR 0.01-µF capacitor to ground. SHARE: Load share pin for the 2.85-V regulator. Connect to the SHARE pins of the other devices in a parallel configuration. TRMPWR: 2.7-V to 5.25-V power input pin. Bypass near the terminators with a 4.7-µF capacitor and a high frequency, low ESR 0.01-µF capacitor to ground. VCC: 4.75-V to 5.25-V power-input pin. Connect to a 4.7-µF capacitor and a low ESR 0.01-µF capacitor to ground. VOUTM: VREG voltage feedback input pin for the 2.85-V regulator. VREG: 2.85-V regulator output pin, must be connected to a 10-µF low ESR capacitor. APPLICATION INFORMATION All SCSI buses require a termination network at each end to function properly. Specific termination requirements differ, depending on which types of SCSI driver devices are present on the bus. The UCC5642 is a low-voltage differential (LVD) only device. It senses which types of drivers are present on the bus. If it detects the presence of a single-ended (SE) or high-voltage differential (HVD) driver, the UCC5642 will place itself in a high-impedance input state, effectively disconnecting the chip from the bus. The UCC5642 senses what kinds of drivers are present on the bus by the voltage on SCSI bus control line DIFFSENS, which is monitored by the DIFFB input pin. The DIFSENS output pin on the UCC5642 attempts to drive a DIFFSENS control line to 1.3 V. If only LVD devices are present, the DIFFSENS line will be successfully driven to that voltage. If HVD drivers are present, they will pull the DIFFSENS line high. If any single-ended drivers are present, they pull the DIFSENS line to ground (even if HVD drivers are also present on the bus). If the voltage on the DIFFB is below 0.5 V or above 2.4 V, the UCC5642 enters the high-impedance SE/HVD state. If it is between 0.7 V and 1.9 V, the UCC5642 enters the LVD mode. These thresholds accommodate differences in ground potential that can occur between the ends of long bus lines. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLUS477 – FEBRUARY 2000 – REVISED DECEMBER 2000 APPLICATION INFORMATION Three UCC5642 ICs are required at each end of the SCSI bus to terminate 27 lines (18 data, 9 control). Every UCC5642 contains a DIFSENS driver, but only one should be used to drive the line at each end. The DIFSENS pin on the other devices should be left unconnected. On power up (the voltage on the TRMPWR pin rising above 2.7 V), the UCC5642 assumes the SE/HVD mode. If the voltage on the DIFFB input indicates LVD mode, the chip waits 100 ms to 300 ms before changing the mode of the bus. If the voltage at the DIFFB input later crosses one of the thresholds, the UCC5642 again waits 100 ms to 300 ms before changing the mode of the bus. The magnitude of the delay is the same when changing in or out of either bus mode. A new mode change can start anytime after a previous mode change has been detected. The DIFFB inputs on all three chips at each end of the bus should be connected together. Properly filtered, noise on DIFFB will not cause a false mode change. There should be a shared 50-Hz noise filter implemented on DIFFB at each end of the bus as close as possible to the DIFFB pins. This is implemented with a 20-kΩ resistor between the DIFFB and DIFSENS pins, and a 0.1-µF capacitor from DIFFB to ground. See the Typical Application diagram at the end of this data sheet. The 5-V to 2.85-V regulator in the UCC5642 can run as a stand-alone regulator by connecting the output (VREG) to the voltage-feedback input (VOUTM). Also connect to VREG a low ESR 10-µF capacitor. The other side of the low ESR capacitor is connected to GND. When the load sinks current from VREG the voltage will start to drop, this drop will be detected by the feedback at VOUTM, and more current will be driven by VREG. Because the feedback loop has a slight delay the 10-µF low ESR capacitor is very important to supply current for fast transient and to stabilize the loop. In this configuration VREG can supply about 300-mA. To supply more current, all three VREG output can be connected together. To keep one regulator from supplying all the current the SHARE pins need to be connected together. Because this is an unusual feature a short description follows. In the stand alone configuration, the SHARE pin voltage is proprotional to the output current. By design, the SHARE pin drive is a strong pullup and a weak pulldown. When the share pin is pulled up from outside the UCC5642 the current out of VREG is proportional to the voltage on the SHARE pin. In the parallel configuration, the VREG pins are connected together to provided the load current. The SHARE pins are connected together so the regulators will share the load current. When the load is appllied, one regulator will start to supply more current than the other two and will drive the common SHARE connection higher. This higher voltage on the common SHARE connection will cause each of the other two regulators to supply the same current, thus sharing the load current. In this configuration one regulator sets the voltage and supplies one-third of the load current. Each of the other regulators supply an additional one-third of the current. Because the 10 µF stabilizes the voltage feedback loop, there must be one 10-µF low ESR capacitor near each VREG output for each UCC5642. If better transient response is required there can be as much as 100 µF for each UCC5642. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS477 – FEBRUARY 2000 – REVISED DECEMBER 2000 APPLICATION INFORMATION UCC5642 12 TRMPWR L1+ 22 Termpower 0.01µF 4.7µF 24 VCC 4.7µF 22 L1+ L1– 21 21 L1– 25 VREG 29 VOUTM 10µF L9+ 33 33 L9+ L9– 34 34 L9– DIFF SENSE 30 SHARE 6 REG DISCNCTDIFFB 11 7 5 0.01µF 4.7µF 20 kΩ 6 20 kΩ 24 VCC 22 L1+ 21 L1– L9+ 33 33 L9+ 29 VOUTM L9– 34 10µF 30 SHARE REG DISCNCTDIFFB 11 7 5 34 L9– 24 VCC 4.7µF 29 VOUTM 10µF VREG 2.85 V Load 4.7µF VCC 24 4.7µF 0.01µF VREG 25 VOUTM 29 4.7µF 22 L1+ L1– 21 21 L1– L9+ 33 33 L9+ L9– 34 34 L9– 30 SHARE REG DISCNCTDIFFB 11 7 5 0.01µF 0.01µF UCC5642 TRMPWR 12 10 µF 0.01µF UCC5642 TRMPWR 12 VCC 24 DATA HIGH BYTE LINES (9) 25 VREG 10µF DIFFB DISCNCT REG 5 7 11 UCC5642 12 TRMPWR L1+ 22 VCC 0.01µF SHARE 30 4.7µF 0.01µF 0.01µF VOUTM 29 DATA LOW BYTE LINES (9) 25 VREG 4.7µF VREG 25 0.1µF L1– 21 Termpower 4.7µF 0.01µF SHARE30 DIFFB DISCNCT REG 5 7 11 0.1µF UCC5642 12 TRMPWR L1+ 22 4.7µF VCC 24 CONTROL LINES (9) 0.01µF 0.01µF UCC5642 TRMPWR 12 VCC 4.7µF 0.01µF VREG 25 VOUTM 29 10µF SHARE30 DIFFB DISCNCT REG 5 7 11 4.7µF 4.7µF 0.01µF VREG 2.85 V Load Figure 1. Application Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2001, Texas Instruments Incorporated