DATA SHEET MOS INTEGRATED CIRCUIT µPD16435, 16435A DOT MATRIX LCD CONTROLLER/DRIVER DESCRIPTION The µPD16435 and 16435A are controllers/drivers for a 119 × 73-dot LCD, and perform LCD full-dot and character composite display by means of control by a microprocessor that has a 4 or 8-bit data bus. A charge pump type DC/DC converter is also incorporated, enabling 3 or 5 V single power supply drive. The µPD16435 uses an external reference clock. The µPD16435A has the on-chip oscillation circuit (external crystal resonator). FEATURES • Can interface to 4 or 8-bit CPU. • Incorporates 119 segment outputs and 73 common outputs. (Display duty selectable from 1/35, 1/37, 1/71, 1/73) • 5 × 7 character font 208 character data configuration character generation ROM and 16 character data configuration character generation RAM, allowing composite full-dot and character display • Incorporates extended display functions such as magnification, lateral scrolling, blink, reverse, etc. • Operating voltage: 2.7 V to 5.5 V • On-chip DC/DC converter: Selectable between ×4 set-up circuit and ×2 step-up circuit • On-chip temperature correction circuit • Master/slave operation capability • On-chip power-on reset circuit • On-chip oscillation circuit (µPD16435A) • 232-pin TCP (Tape Carried Package) ORDERING INFORMATION Part Number Package µPD16435N-001-××× TCP (TAB), Standard ROM code µPD16435N-001-001 Standard quad TCP (Conforms to EIAJ), Standard ROM code µPD16435N-001-002 Standard dual TCP (Output OLB: 0.25 mm pitch), Standard ROM code µPD16435AN-001-××× TCP (TAB), Standard ROM code µPD16435AN-001-001 Standard quad TCP (Conforms to EIAJ), Standard ROM code µPD16435AN-001-052 Standard dual TCP (Output OLB: 0.25 mm pitch), Standard ROM code Explanation of Part Number µPD16435 (A) N-xxx-xxx TCP code ROM code The TCP model is a custom model. For details, consult NEC sales representative. Document No. S10298EJ3V0DS00 (3rd edition) Date Published April 1997 N Printed in Japan © 1995 µPD16435, 16435A SEG1 SEG119 COM1 OSC OSC1 OSC2 COM73 BLOCK DIAGRAM Common Driver 119-Bit Latch 73-Bit Shift Register Cursor Blinking Control Register Scroll RAM 13 × 73 Bits CGROM 5 × 7 × 208 Bits Display RAM 119 × 73 Bits 5 Selector OSC3 119 Scaler Timing Generator 73 119 Segment Driver V1 V2 V3 V4 V5 5 7 Address Counter CGRAM 5 × 7 × 16 Bits – VIN 8 8 VIN+ Busy Flag Data Register Instruction Register OP-Amp 8 8 8 Instruction Decoder ×2/×4 Step-Up Circuit GND2 VDD GND1 VCC 3/5 C3+ C3– C2+ C2– C1+ C1– SCR SYNC RESET BUSY D0~7 WR RD RS CS WS TEST1 2 TEST2 8 Parallel I/F 79 80 SEG83 SEG84 Dummy15 Dummy1 Dummy2 COM38 COM39 Dummy14 SEG31 SEG32 Dummy26 VDD GND1 CS RS RD WR WS D0 D1 D2 D3 D4 D5 D6 D7 RESET SCR BUSY SYNC TEST1 TEST2 3/5 OSC1 OSC2 OSC3 VCC Dummy25 C1– C1+ C2– C2+ C3– C3+ VIN(–) VIN(+) GND2 V1 V2 V3 V4 V5 Dummy24 Dummy23 µPD16435, 16435A PIN CONFIGURATION (CHIP) 258 214 215 1 COM73 Dummy3 Dummy4 SEG1 Dummy13 135 136 Dummy22 Dummy21 COM1 COM2 COM37 Dummy20 Dummy17 SEG119 SEG30 Dummy5 SEG85 Dummy16 3 µPD16435, 16435A PIN DESCRIPTIONS 4 Pin Name Pin No. Input/Output Output Type Description CS 255 Input ––– Chip select signal RS 254 Input ––– Register selection signal (specifies address register when “0”, control register when “1”). RD 253 Input (Schmitt) ––– Read enable signal. Reads write address when scrolling. Active edge is falling edge. WR 252 Input (Schmitt) ––– Write enable signal. Active edge is falling edge. WS 251 Input ––– Word length selection signal (4-bit input when “1”, 8-bit input when “0”). D0 to D7 250 to 243 Input/output CMOS 3-state Transmit/receive data (3-state bidirectional) Upper → D4 to D7 Lower → D0 to D3 (These pins should be set as unused in case of 4-bit data). In test mode, these pins are output pins. In a 4-bit transfer, storage is performed in the upper (MSB) in order from the data transferred first. BUSY 240 Output Nch open-drain “0” indicates busy state. RESET 242 Input ––– SCR 241 Output CMOS SYNC 239 Input/output Nch open-drain “0” → Initialization of all internal registers and commands is performed. Output is fixed at V1. Signal is output to CPU on completion of one-character scroll. Synchronization signal input/output pins for master/slave operation. OSC1 OSC2 235 234 ––– ––– µPD16435: Input the 4.19 MHz reference clock to the OSC1 pin externally. Leave the OSC2 pin open. (Always outputs high level.) µPD16435A: This is the pin to which the 4.19 MHz crystal resonator is connected. Input the external clock to OSC1 first. OSC3 233 Input (Schmitt) ––– 2 Hz external clock input pin. Scaled by 2 internally to generate 1 Hz, used as blink synchronization signal. COM1 to COM73 212 to 176 3 to 38 Output Analog switch Common output signals SEG1 to SEG119 41 to 70 81 to 134 137 to 171 Output Analog switch Segment output signals TEST1 TEST2 238 237 Output ––– “1” → Test mode “0” or open → Normal operating mode µPD16435, 16435A Pin Name Pin No. Input/Output Output Type Description V1 221 Output ––– LCD drive power supply pin Internal OP-amp output V2 to V5 220 to 217 Input ––– LCD drive power supply pins Can be adjusted by addition of external resistor. VIN(–) VIN(+) 224 223 Input ––– Liquid crystal drive power supply OP-amp input pins VCC, GND1 232, 256 ––– ––– Logic power supply, GND VDD, GND2 257, 222 ––– ––– Liquid crystal drive (step-up) power supply, GND 3/5 236 Input ––– Drive voltage selection pin “1” → VDD = 3 V (×4 step-up circuit selected) “0” → VDD = 5 V (×2 step-up circuit selected) C1±, C2±, C3± 230 to 225 ––– ––– A 1 µF tantalum or ceramic capacitor should be connected externally. REFERENCE CLOCK Product Name µPD16435 µPD16435A Reference Clock External input On-chip oscillation circuit (External crystal resonator) OSC CIRCUIT (µPD16435A) OSC1 OSC2 4.19 MHz 5 µPD16435, 16435A REGISTER FUNCTIONS (1) Address Register Sets the address of each register, and also sets display control, standby mode, and scaler resetting. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 × : Don’t Care Register address (0H to CH) See table below Display control 00: Display control off (SEGn, COMn = V1) 01: Display control off (SEGn, COMn = unselected waveform) 10: Normal operation 11: Normal operation Standby mode setting 0: Normal operation 1: Standby mode Note Blink internal scaler reset and 1/2 scaler reset 0: Normal operation 1: Reset (Blinking starts when it lights.) (Used to synchronize time variations and time mark blinking.) Note Standby mode = DC/DC converter stopped OSC1 input invalid ( µ PD16435) OSC stopped ( µ PD16435A) SEGn, COMn = V1 Data write/read prohibited After powering on 0 0 0 0 0 0 0 0 Register address list Address 6 Register Name b3 b2 b1 b0 0 0 0 0 Full-dot X address register 0 0 0 1 Full-dot Y address register 0 0 1 0 Full-dot data register 0 0 1 1 Character X address register 0 1 0 0 Character Y address register 0 0 1 1 0 1 1 0 Character data register CGRAM address register 0 1 1 1 CGRAM data register 1 0 0 0 Extension register 1 0 0 1 Extension register X address register 1 0 1 0 Extension register Y address register 1 1 0 1 1 0 1 0 Scroll register Control register µPD16435, 16435A (2) Full-Dot X Address Register (Register Address = 0000B) Performs full-dot display, display screen X (segment) direction address setting. As scrolling is not possible with a fulldot display, addresses are not allocated to the scroll RAM area. MSB LSB × : Don’t Care b3 b2 b1 b0 Full-dot X address (00H to 0EH) After powering on: Undefined (3) Full-Dot Y Address Register (Register Address = 0001B) Performs full-dot display, display screen Y (common) direction address setting. MSB LSB × : Don’t Care b6 b5 b4 b3 b2 b1 b0 Full-dot Y address (00H to 48H) After powering on: Undefined (4) Full-Dot Data Register (Register Address = 0010B) Inputs full-dot display data. Display data is stored in the display memory with the MSB on the left, and display data “1” corresponds to illumination. Full-dot X address = 00H to 0DH MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Full-dot display data Full-dot X address = 0EH MSB b7 b6 b5 b4 b3 b2 b1 LSB × : Don’t Care Full-dot display data After powering on: Undefined 7 µPD16435, 16435A Full-Dot X Address and Y Address Allocation X Address Y Address 0EH(15) 01H(2) 00H(1) 00H(1) 01H(2) 48H(73) b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 8 Bits b5 b4 b3 b2 b1 7 Bits (5) Character X Address Register (Register Address = 0011B) Performs character display display, screen X (segment) direction address setting. X addresses include the scroll RAM area. MSB LSB b4 b3 b2 b1 b0 × : Don’t Care Character X address (00H to 15H) After powering on: Undefined (6) Character Y Address Register (Register Address = 0100B) Performs character display display, screen Y (common) direction address setting. MSB LSB b2 b1 b0 × : Don’t Care Character Y address (00H to 07H) After powering on: Undefined 8 µPD16435, 16435A (7) Character Data Register (Register Address = 0101B) The character indicated in the character code table is displayed at the position indicated by the character X and Y address registers. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 × : Don’t Care Character code After powering on: Undefined Character X Address and Y Address Allocation Y Address X Address Scroll RAM Area Display RAM Area 00H(1) 01H(2) 13H(20) 14H (21) 15H (22) 00H(1) 01H(2) 1 Bit 8 Bits 07H(8) 1 Bit 5 Bits 9 µPD16435, 16435A (8) CGRAM Address Register (Register Address = 0110B) Performs address setting when display data is written to CGRAM. Bits b6 to b3 of the CGRAM address indicate the character code, and bits b2 to b0 indicate the character line. MSB LSB b6 b5 b4 b3 b2 b1 b0 × : Don’t Care Line address (00H to 06H) Note Character code (00H to 0FH) Note If auto increment is set with the control register, 06H is followed by 07H. Dummy data should be sent when the address is 07H. Example: (CGRAM address with auto increment) --- → 15H → 16H → 17H → 18H → --- After powering on: Underfined (9) CGRAM Data Register (Register Address = 0111B) CGRAM display data. The lower 5 bits of the write data are valid. MSB LSB b4 b3 b2 b1 b0 × : Don’t Care CGRAM data After powering on: Undefined 10 µPD16435, 16435A (10) Extension Register (Register Address = 1000B) Performs magnification, reverse, cursor, and time mark setting. MSB LSB b3 b2 b1 b0 × : Don’t Care In case of magnification setting 00: Standard 01: ×2 horizontal 10: ×2 vertical 11: ×4 magnification (×2 horizontal & vertical) Magnification display is performed at any line position; characters of different sizes cannot be displayed on the same line. Line specification magnification display is possible by setting an extension Y address after this command, and multiple-line magnification display is possible by setting consecutive extension Y address. In case of reverse setting 00: Reverse cancellation (line specification) 01: Reverse (line specification) 10: Reverse cancellation (full screen) 11: Reverse (full screen) Line specification reverse display is possible by setting an extension Y address after this command, and multiple-line reverse display is possible by setting consecutive extension Y addresses. Regarding the reverse display Y address direction, a total of 9 dots (7 character part dots + 1 cursor part dot + 1 top space dot) are reversed. In the case of ×2 vertical magnification or ×4 magnification, a total of 18 dots (14 character part dots + 2 cursor part dots + 2 top space dots) are reversed. In case of cursor setting 00: Cursor non-display 01: Cursor display (blinking stopped) 10: Cursor display (blink operation) 11: Don’t Care Blinking display can be performed at any address by specifying an extension X and Y address after this command. The specification is for one address only. The address specification should be performed in the order: X address → Y address. In case of character blink setting X0: Blinking stopped X1: Blink operation Blinking can be performed at any address by specifying an extension X and Y address after this command. The specification is for one address only. The address specification should be performed in the order: X address → Y address. Extension function setting 00: Magnification setting 01: Reverse setting 10: Cursor setting 11: Character blink setting After powering on 0 0 0 0 11 µPD16435, 16435A Display and RAM Allocation in Case of Magnification Setting (1) Example of ×2 horizontal magnification (line 07H specified) Display 00H(1) 01H(2) 13H(20) 00H(1) 01H(2) 1 Bit 07H(8) (X=00H) (X=09H) 10 Bits 2 Bits 8 Bits 1 Bit RAM 00H(1) 13H(20) 01H(2) 14H(21) 15H(22) 00H(1) 01H(2) Non-Display Area Display Area 07H(8) 00H 01H 09H 0AH 15H Note Lines 0AH to 15H for which ×2 horizontal magnification is specified can be used as scroll RAM. 12 µPD16435, 16435A (2) Example of ×2 vertical magnification (line 00H specified) Display 00H(1) 01H(2) 13H(20) 16 Bits 00H(1) 2 Bits 01H(2) 1 Bit 06H(7) 5 Bits RAM 00H(1) 13H(20) 01H(2) 14H(21) 15H(22) 00H(1) 01H(2) Display Area Non-Display Area 06H(7) 07H(8) Note If ×2 vertical magnification is specified for line 07H, the lower half will be outside the display area. Also, if ×2 vertical magnification is specified for line 06H, the bottom dot will be a space. 13 µPD16435, 16435A (3) Example of ×4 magnification (line 00H specified) 1 Bit 2 Bits Display 09H(10) 00H(1) 10 Bits 16 Bits 00H(1) 2 Bits 01H(2) 1 Bit 06H(7) 00H 01H 00H(1) 01H(2) 13H RAM 09H(10) 0AH(11) 14H(21) 15H(22) 00H(1) 01H(2) Non-Display Area Display Area 06H(7) 07H(8) 00H 01H 13H 14H 15H Note Lines 0AH to 15H for which ×4 magnification is specified can be used as scroll RAM. If ×4 magnification is specified for line 07H, the lower half will be outside the display area, and if ×4 magnification is specified for line 06H, the bottom dot will be a space. 14 µPD16435, 16435A (11) Extension X Address Register (Register Address = 1001B) Performs extension display, display screen X (segment) direction address setting. X addresses include the scroll RAM area. This register must be executed before the extension Y address register. MSB LSB b4 b3 b2 b1 b0 × : Don’t Care Character X address (00H to 15H) After powering on: Undefined (12) Extension Y Address Register (Register Address = 1010B) Performs extension display, display screen Y (common) direction address setting. This register must be executed after the X address. MSB LSB b2 b1 b0 × : Don’t Care Character Y address (00H to 07H) After powering on: Undefined (13) Scroll Register (Register Address = 1011B) Performs scroll setting. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 × : Don’t Care Scroll direction setting 00: Scroll reset Note 1 01: Right scroll 10: Left scroll 11: Scrolling stopped Note 2 Scrolling by specification of any line is possible by setting a character Y address after this command. Scrolling can only be performed for one character-unit line. Scroll speed setting (00H to 3FH) This value specifies the number of frames for a one-bit move. If 00H is set, scrolling is stopped. Notes 1. When scroll reset is executed, the screen leftmost character X address returns to 00H, and scrolling is stopped. 2. After scrolling has been stopped, character Y address setting is necessary when scrolling is restarted. It is not possible to set a different address from the character Y address before scrolling was stopped. After powering on 0 0 0 0 0 0 0 0 15 µPD16435, 16435A (14) Control Register (Register Address = 1100B) Performs address increment direction, common output, frame frequency, blinking, and master/slave setting. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 × : Don’t Care Address increment direction setting 00: Auto increment in X direction (up-count) 01: Auto increment in Y direction (up-count) 1×: Address retention When auto increment is used, the address is automatically Note up-counted after a full-dot, character, or CGRAM data write. The character X address is reset to 13H. When address retention is specified, the address is retained after a data write. Common output setting 00: 35 outputs (1/35 duty, COM2 to COM36 selected) 01: 37 outputs (1/37 duty, COM1 to COM37 selected) 10: 71 outputs (1/71 duty, COM2 to COM72 selected) 11: 73 outputs (1/73 duty, COM1 to COM73 selected) Frame frequency setting 00: 100 Hz 01: 75 Hz 10: 50 Hz 11: Don’t Care LCD drive is performed by frame inversion. Blink source setting 0: External clock (OSC3) 1: Internal scaled block Master/slave setting 0: Master 1: Slave Note CGRAM is incremented in the Y direction even if 00H is set. After powering on 0 16 0 0 0 0 0 0 0 µPD16435, 16435A Standard ROM Code (001) Higher Bit Lower 4 Bits Bit 4 Bits xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0001 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 CC RAM (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) 17 µPD16435, 16435A ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C, GND1 = GND2 = 0 V) Rating Unit Supply voltage 1 (3/5 = L) Parameter VCC1 Symbol –0.3 to +7.0 V Supply voltage 2 (3/5 = H) Logic input voltage VCC2 VIN –0.3 to +4.0 –0.3 to VCC+0.3 V V Logic output voltage VOUT1 –0.3 to VCC+0.3 V LCD drive power supply voltage VDD VCC–0.3 to +16.0 V LCD drive power supply input voltage V2 to V5 –0.3 to VDD+0.3 V LCD drive power supply output voltage V1 –0.3 to VDD+0.3 V Amplifier input voltage Driver output voltage (Segment, common) VIN (+), VIN (–) VOUT2 –0.3 to VDD+0.3 –0.3 to VDD+0.3 V V Storage temperature range Tstg. –55 to +150 ˚C RECOMMENDED OPERATING RANGES Parameter Supply voltage 1 (3/5 = L) Symbol VCC1 MIN. 4.5 TYP. 5.0 Supply voltage 2 (3/5 = H) LCD drive supply voltage VCC2 2.7 VDD VCC Logic input voltage VIN LCD drive power supply input voltage LCD drive power supply output voltage External capacitance Operating temperature range TA 18 MAX. 5.5 Unit V 3.0 3.6 V 8.0 14.5 V 0 VCC V V2 to V5 0 VDD V V1 C0 to C3 0 1 VDD 4.7 –40 +85 V µF ˚C µPD16435, 16435A ELECTRICAL SPECIFICATIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1 µF, Vcc = 5 V ±10% : 3/5 = L or Vcc = 2.7 V to 3.6 V : 3/5 = H) Parameter Symbol Test Conditions Input voltage high VIH1 Except Schmitt inputs Input voltage low VIL1 Except Schmitt inputs Input voltage high VIH2 Schmitt inputs Input voltage low VIL2 Schmitt inputs Hysteresis voltage VH Schmitt inputs Input current high IIH1 MIN. TYP. MAX. 0.7VCC V 0.3VCC 0.8VCC 0.05VCC 0.2VCC V 0.2VCC V 1 µA –1 µA OSC3, VIN(+), VIN(–), VIN = VCC CS, RS, RD, WR, WS, RESET, 3/5, IIH1 V V CS, RS, RD, WR, WS, RESET, 3/5, Input current low Unit OSC3, VIN(+), VIN(–), VIN = 0 V Input current high IIH2 TEST1, TEST2, VIN = VCC 6 mA Input current low IIL2 TEST1, TEST2, VIN = 0 V –100 µA Output voltage high VOH1 Dn, SCR, 3/5 = L 0.9VCC V IOH = –1 mA Dn, BUSY, SCR, SYNC, 3/5 = L Output voltage low VOL1 0.1VCC V IOL = 4 mA Dn, SCK, 3/5 = H Output voltage high 0.9VCC VOH2 V IOH = –0.6 mA Dn, BUSY, SCR, SYNC, 3/5 = H Output voltage low VOL2 0.1VCC V IOL = 2.4 mA V1 pin Output voltage high VOH3 IOH = –1 mA 0.9VCC V VIN(+) = VDD, VIN(–) = 0 V V1 pin Output voltage low VOL3 IOL = –10 µA 0.1VDD V 10 µA –10 µA 5 kΩ 10 kΩ 1.9VCC 2.0VCC V 3.6VCC 4.0VCC V VIN(+) = 0 V, VIN(–) = VDD Dn, SYNC, BUSY Leak current high ILOH VIN/OUT = VCC Dn, SYNC, BUSY Leak current low ILOL VIN/OUT = 0 V COM1 to COM73 Common output RCOM on-resistance |IO| = 100 µA SEG1 to SEG119 Segment output RSEG on-resistance |IO| = 100 µA RB = 10 kΩ Driver unit supply voltage VDD1 3/5 = L (step-up voltage) RB = 10 kΩ Driver unit supply voltage VDD2 (step-up voltage) 3/5 = H 19 µPD16435, 16435A ELECTRICAL SPECIFICATIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1 µF, Vcc = 5 V ±10% : 3/5 = L or Vcc = 2.7 V to 3.6 V : 3/5 = H) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 0.35 1 mA 0.35 1 mA 1.3 2.5 mA 0.75 1.5 mA 0.6 1.5 mA 0.65 1.5 mA 1.5 3 mA 1.05 2 mA VCC = 3.0 V, no load, 3/5=H ICC1 fOSC = 4.19 MHz VCC = 5.0 V, no load, 3/5=L ICC2 fOSC = 4.19 MHz Logic consumption current (µPD16435) VCC = 3.0 V, 3/5=H ICC3 RB = 10 kΩNote fOSC = 4.19 MHz VCC = 5.0 V, 3/5=L ICC4 RB = 10 kΩNote fOSC = 4.19 MHz VCC = 3.0 V, no load, 3/5=H ICC1 fOSC = 4.19 MHz VCC = 5.0 V, no load, 3/5=L ICC2 fOSC = 4.19 MHz Logic consumption current (µPD16435A) VCC = 3.0 V, 3/5=H ICC3 RB = 10 kΩNote fOSC = 4.19 MHz VCC = 5.0 V, 3/5=L ICC4 RB = 10 kΩNote fOSC = 4.19 MHz Note TYP. values are reference values for TA = 25 ˚C. 20 µPD16435, 16435A NOTE MEASUREMENT CIRCUIT + – VIN+ VIN- V1 V2 RB RB V3 V4 RB RB V5 RB VCC SWITCHING SPECIFICATIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1 µF, Vcc = 5 V ±10%, RL = 5 kΩ, CL = 150 pF) Parameter Test Conditions Symbol MIN. TYP. MAX. Unit 150 ns RD data delay time tRDD RD↓ → Dn RD data hold time tRDH RD↑ → Dn 10 BUSY low-level time tBL When full-dot data is written 3 9 CLKNote BUSY low-level time tBL When charactor data is written 48 54 CLKNote SCR high-level time tSCR 100 550 µs ns Note CLK = 4/fOSC 21 µPD16435, 16435A REQUIRED TIMING CONDITIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1 µF, VCC = 5 V ±10%, RL = 5 kΩ, CL = 150 pF) Parameter Test Conditions Symbol MIN. TYP. MAX. Unit 4.19 4.61 MHz Clock frequency fOSC µPD16435 only 3.77 High-level clock pulse width tWHC µPD16435 only 100 ns Low-level clock pulse width tWLC µPD16435 only 100 ns RD high-level width tRDH 200 ns RD low-level width tRDL 200 ns WR high-level width tWRH 200 ns WR low-level width tWRL 200 ns WR – RD time tWRRD WR↑ → RD↓ 200 ns RD – WR time tRDWR RD↑ → WR↓ 200 ns CS, RS setup time tCRS CS↓, RS → WR↓, RD↓ 0 ns CS, RS hold time tCRH WR↑, RD↑ → CS↑, RS 300 ns Input data setup time tDS Dn → WR↑ 0 ns Input data hold time tDH WR↑ → Dn 200 ns SWITCHING SPECIFICATIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1 µF, Vcc = 2.7 to 3.6 V, RL = 5 kΩ, CL = 150 pF) Parameter Test Conditions Symbol MIN. TYP. MAX. Unit 500 ns RD data delay time tRDD RD↓ → Dn RD data hold time tRDH RD↑ → Dn 15 BUSY low-level time tBL When full-dot data is written 3 9 CLKNote BUSY low-level time tBL When charactor data is written 48 54 CLKNote SCR high-level time tSCR 100 550 µs Note CLK = 4/fOSC 22 ns µPD16435, 16435A REQUIRED TIMING CONDITIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1 µF, VCC = 2.7 to 3.6 V, RL = 5 kΩ, CL = 150 pF) Parameter Test Conditions Symbol MIN. TYP. MAX. Unit 4.19 4.61 MHz Clock frequency fOSC µPD16435 only 3.77 High-level clock pulse width tWHC µPD16435 only 100 ns Low-level clock pulse width tWLC µPD16435 only 100 ns RD high-level width tRDH 400 ns RD low-level width tRDL 400 ns WR high-level width tWRH 400 ns WR low-level width tWRL 400 ns WR – RD time tWRRD WR↑ → RD↓ 400 ns RD – WR time tRDWR RD↑ → WR↓ 400 ns CS, RS setup time tCRS CS↓, RS → WR↓, RD↓ 0 ns CS, RS hold time tCRH WR↑, RD↑ → CS↑, RS 600 ns Input data setup time tDS Dn → WR↑ 0 ns Input data hold time tDH WR↑ → Dn 400 ns 23 µPD16435, 16435A AC TIMING TEST VOLTAGE VIH Input VIL VOH Output VOL AC CHARACTERISTICS WAVEFORM OSC OSC1 tWHC tWLC I/fOSC READ TIMING CS, RS tCRS RD tRDL tRDH tRDWR tCRH tWRRD tCRH WR tRDD tRDH Dn WRITE TIMING CS, RS tCRS WR tWRL tWRH RD tDS Dn 24 tDH µPD16435, 16435A BUSY BUSY tBL SCR SCR tSCR 25 µPD16435, 16435A EXAMPLE TEMPERATURE CORRECTION CIRCUIT CONNECTION + - VIN+ VIN- V1 Rt V2 RB V3 RB V4 RB V5 RB RB VCC Rp R1 Rt : Thermistor 26 13.475 13.475 12.70 12.70 P0.40 ± 0.01X60 = 24.00 ± 0.04 11.50 P0.28 ± 0.01X57 = 15.96 ± 0.025 W0.12 ± 0.02 4.75 ± 0.03 12.70 P0.40 11.50 0.50 0.142 ± 0.03 11.50 13.475 0.65 From Pattern Center 16.30 90° 0.15 3 257 232 13.475 9.50 212 217 ° 2.25 30 18.00 2.25 2.25 13.475 3.50 13.475 14.50 +0 12.1 -4.6 COATING AREA 27 µPD16435, 16435A 4.00 1.00 11.50 13.475 12.70 +0.04 31.82 -0.07 12.70 8.33 18.00 41 13.475 7.50 171 P0.40 ± 0.01X60 = 24.00 ± 0.04 81 70 11.50 137 134 P0.28 ± 0.01X57 = 15.96 ± 0.025 6.00 COATING AREA +0 12.93 -4.6 W0.12 ± 0.02 1.00 1.42 ± 0.03 12.70 P0.40 From Pattern Center 0.3 ± 0.3 11.00 13.475 2.25 (0.30) 0.60±0.015 11.50 0.40±0.015 φ1.00 Cu 13.475 MAX. 0.9 STANDARD TCP PACKAGE DRAWINGS (µPD16435N-001-001, µPD16435AN-001-001) Detail of Test Pad and Alignment Mark 28 DUMMY COM11 COM13 DUMMY SEG93 SEG91 DUMMY COM10 COM12 COM14 SEG94 SEG92 SEG90 D U M M Y D U M M Y C O M 0 9 S E G 8 9 S E G 8 8 C O M 0 1 S E G 8 7 V 0 5 S E G 8 6 V 0 4 S E G 8 5 V 0 3 S E G 8 4 D U M M Y D U M M Y C S G N D 0 1 S E G 3 6 V D D S E G 3 5 C O M 3 8 S E G 3 4 S E G 3 3 C O M 4 6 S E G 3 2 D U M M Y D U M M Y COM47 COM49 COM51 SEG27 SEG29 SEG31 DUMMY COM48 COM50 DUMMY SEG28 SEG30 DUMMY µPD16435, 16435A ■1.42 (50.25) 24.8 ± 0.3 1.175 ± 0.01 24.8 ± 0.3 1.175 ± 0.01 P0.25 ± 0.01X195 = 48.75 ± 0.075 W0.125 ± 0.015 P0.10X71 4.60 4.60 P0.10X65 P0.0964 (9.25) 10.90 11.10 3 257 +0.04 31.82 -0.07 (1.50) 0.3 ± 0.3 P0.1060 13.00 232 P0.1044 (12.50) 212 217 P0.10 9.00 1.00 f1.00 P0.1 41 6.00 171 8.33 0.70 2.50 7.50 P0.10 5.05 ± 0.3 4.65 P0.1003 0.95 81 70 2.00 (0.70) 4.75 (3.80) 137 134 P0.1005 10.00 7.00 6.00 +0 COATING AREA +0 4.465 -2.3 10.90 (4.20) P0.1013 8.465 -2.3 MAX 0.9 ± 0.03 ± 0.03 25.55 4.00 3.00 (0.70) Cu 10.00 3.50 10.00 P0.70 ± 0.01X41 = 28.70 ± 0.045 W0.35 ± 0.02 14.7 ± 0.3 (30.00) 31.00 WINDING WAY OUTPUT LEADS UNWINDING DIRECTION 17.50 19.00 +0 12.1 -4.6 Detail of Alignment Mark 2-φ1.30 Base Hole 29 2-R1.15 ± 0.3 SR 2-φ1.10 Cu 2-φ1.90 Cu FACE(COPPER) COATING AREA MATERIAL t=75 mm BASE FILM : UPILEX-S t=12 mm ADHESIVE : EPOXY t=18 mm COPPER FOIL : ELECTROLYSIS Cu : Sn t=MIN 0.25 mm PLATING t=25 mm SOLDER RESIST : EPOXY This Figure is shown by Copper side over Polyimide All tolerances unless otherwise specified 0.05 mm. Coner radius is 0.3 mm Max. II Sprocket holes (52.25 mm) for 1 Pattern µPD16435, 16435A 14.7 ± 0.3 STANDARD TCP PACKAGE DRAWINGS (µPD16435N-001-002) ■4.75 25.55 µPD16435, 16435A Detail of Test Pad and Alignment Mark from P.C. 25.55 1.175 ± 0.01 P0.25 0.40 30 0.10 from P.C. 10.90 0.50 0.50 (1.40) 1.40 (1.20) from P.C. 11.10 0.10 0.40 ± 0.015 0.125 1.50 0.20 0.30 0.10 0.60 ± 0.015 NC NC COM38 COM39 COM40 COM41 COM42 • • • • COM73 SEG1 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SEG119 COM37 • • • • COM5 COM4 COM3 COM2 COM1 NC NC DUMMY VDD GND1 CS RS RD WR WS D0 D1 D2 D3 D4 D5 D6 D7 RESET SCR BUSY SYNC TEST1 TEST2 3/5 OSC1 OSC2 OSC3 VCC C1C1+ C2C2+ C3C3+ VIN(-) VIN(+) GND2 V1 V2 V3 V4 V5 DUMMY ■1.42 (50.25) 24.8 ± 0.3 1.175 ± 0.01 24.8 ± 0.3 1.175 ± 0.01 P0.25 ± 0.01X195 = 48.75 ± 0.075 W0.125 ± 0.015 P0.10X71 4.60 4.60 P0.10X65 P0.0964 (9.25) 10.90 11.10 3 257 +0.04 31.82 -0.07 (1.50) 0.3 ± 0.3 P0.1060 13.00 232 P0.1044 (12.50) 212 217 P0.10 9.00 1.00 f1.00 P0.1 41 6.00 171 8.33 0.70 2.50 7.50 P0.10 5.05 ± 0.3 4.65 P0.1003 0.95 81 70 2.00 (0.70) 4.75 (3.80) 137 134 P0.1005 10.00 7.00 6.00 +0 COATING AREA +0 4.465 -2.3 10.90 (4.20) P0.1013 8.465 -2.3 MAX 0.9 ± 0.03 ± 0.03 25.55 4.00 3.00 (0.70) Cu 10.00 3.50 10.00 P0.70 ± 0.01X41 = 28.70 ± 0.045 W0.35 ± 0.02 14.7 ± 0.3 (30.00) 31.00 WINDING WAY OUTPUT LEADS UNWINDING DIRECTION 17.50 19.00 +0 12.1 -4.6 Detail of Alignment Mark 2-φ1.30 Base Hole 31 2-R1.15 ± 0.3 SR 2-φ1.10 Cu 2-φ1.90 Cu FACE(COPPER) COATING AREA MATERIAL t=75 mm BASE FILM : UPILEX-S t=12 mm ADHESIVE : EPOXY t=18 mm COPPER FOIL : ELECTROLYSIS Cu : Sn t=MIN 0.25 mm PLATING t=25 mm SOLDER RESIST : EPOXY This Figure is shown by Copper side over Polyimide All tolerances unless otherwise specified 0.05 mm. Coner radius is 0.3 mm Max. II Sprocket holes (52.25 mm) for 1 Pattern µPD16435, 16435A 14.7 ± 0.3 STANDARD TCP PACKAGE DRAWINGS (µPD16435AN-001-052) ■4.75 25.55 µPD16435, 16435A Detail of Test Pad and Alignment Mark from P.C. 25.55 1.175 ± 0.01 P0.25 0.40 32 0.10 from P.C. 10.90 0.50 0.50 (1.40) 1.40 (1.20) from P.C. 11.10 0.10 0.40 ± 0.015 0.125 1.50 0.20 0.30 0.10 0.60 ± 0.015 NC NC COM38 COM39 COM40 COM41 COM42 • • • • COM73 SEG1 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SEG119 COM37 • • • • COM5 COM4 COM3 COM2 COM1 NC NC DUMMY VDD GND1 CS RS RD WR WS D0 D1 D2 D3 D4 D5 D6 D7 RESET SCR BUSY SYNC TEST1 TEST2 3/5 OSC1 OSC2 OSC3 VCC C1C1+ C2C2+ C3C3+ VIN(-) VIN(+) GND2 V1 V2 V3 V4 V5 DUMMY µPD16435, 16435A REFERENCE DOCUMENTS NEC Semiconductor Device Reliability/Quality Control System (IEI-1212) Semiconductor Device Mounting Technology Manual (C10535E) 33 µPD16435, 16435A [MEMO] 34 µPD16435, 16435A [MEMO] 35 µPD16435, 16435A No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 32