DATA SHEET MOS INTEGRATED CIRCUIT µPD17P236 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROLLER The µPD17P236 is a model of the µPD17236 with a one-time PROM instead of an internal mask ROM. Since the user can write programs to the µPD17P236, it is ideal for experimental production or small-scale production of the µPD17230, 17231, 17232, 17233, 17234, 17235, or 17236 systems. When reading this document, also read the documents related to the µPD17230, 17231, 17232, 17233, 17234, 17235, and 17236. Detailed functions are described in the following user's manual. Read this manual when designing your system. µPD172×× Series User's Manual: U12795E FEATURES • Pin compatible with µPD17230, 17231, 17232, 17233, 17234, 17235, and 17236 (except PROM programming function) • Carrier generator circuit for infrared remote controller (REM output) • 17K architecture: General-purpose register method • Program memory (one-time PROM): 32 Kbytes (16,384 × 16) • Data memory (RAM): 223 × 4 bits • Low-voltage detection circuit • Input/output of P1A0 pin, clock selection for carrier generation µPD17P236M1 µPD17P236M2 Input/output of P1A0 pin Output Input Clock (RfX) selection for carrier generation RfX = fX/2 µPD17P236M3 Output µPD17P236M4 Input RfX = fX • Supply voltage: VDD = 2.2 to 3.6 V (fX = 4 MHz: high-speed mode, 4 µs) VDD = 3.0 to 3.6 V (fX = 8 MHz: high-speed mode, 2 µs) APPLICATIONS Preset remote controllers, toys, and portable systems The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14776EJ1V0DS00 (1st edition) Date Published June 2000 J CP(K) Printed in Japan © 2000 µPD17P236 ORDERING INFORMATION Part Number Package µPD17P236M1GT 28-pin plastic SOP (9.53 mm (375)) µPD17P236M1MC-5A4 30-pin plastic SSOP (7.62 mm (300)) µPD17P236M2GT 28-pin plastic SOP (9.53 mm (375)) µPD17P236M2MC-5A4 30-pin plastic SSOP (7.62 mm (300)) µPD17P236M3GT 28-pin plastic SOP (9.53 mm (375)) µPD17P236M3MC-5A4 30-pin plastic SSOP (7.62 mm (300)) µPD17P236M4GT 28-pin plastic SOP (9.53 mm (375)) µPD17P236M4MC-5A4 30-pin plastic SSOP (7.62 mm (300)) PIN CONFIGURATION (TOP VIEW) (1) Normal operation mode • 28-pin plastic SOP (9.53 mm (375)) µ PD17P236M1GT, 17P236M2GT, 17P236M3GT, 17P236M4GT 2 P0D 2 1 28 P0D 1 P0D 3 2 27 P0D 0 INT 3 26 P0C 3 P0E 0 4 25 P0C 2 P0E 1 5 24 P0C 1 P0E 2 6 23 P0C 0 P0E 3 7 22 P0B 3 REM 8 21 P0B 2 V DD 9 20 P0B 1 X OUT 10 19 P0B 0 X IN 11 18 P0A 3 GND 12 17 P0A 2 RESET 13 16 P0A 1 P1A0 14 15 P0A 0 Data Sheet U14776EJ1V0DS00 µPD17P236 • 30-pin plastic SSOP (7.62 mm (300)) µ PD17P236M1MC-5A4, 17P236M2MC-5A4, 17P236M3MC-5A4, 17P236M4MC-5A4 P0D2 1 30 IC2 P0D3 2 29 P0D1 INT 3 28 P0D0 P0E0 4 27 P0C3 P0E1 5 26 P0C2 P0E2 6 25 P0C1 P0E3 7 24 P0C0 REM 8 23 P0B3 VDD 9 22 P0B2 XOUT 10 21 P0B1 XIN 11 20 P0B0 GND 12 19 P0A3 RESET 13 18 P0A2 P1A0 14 17 P0A1 IC1 15 16 P0A0 GND : Ground IC1, IC2 : Internally connectedNote 1 INT : External interrupt request signal input P0A0-P0A3 : Input port (CMOS input) P0B0-P0B3 : Input/output port (CMOS input/N-ch open-drain output) P0C0-P0C3 : Input/output port (CMOS input/N-ch open-drain output) P0D0-P0D3 : Input/output port (CMOS input/N-ch open-drain output) P0E0-P0E3 : Input/output port (CMOS push-pull output) P1A0 : Input port (CMOS input) or output port (N-ch open-drain output) REM : Remote controller output (CMOS push-pull output) RESET : Reset input VDD : Power supply XIN, XOUT : Resonator connection Note 2 Notes 1. This pin cannot be used. Leave open. 2. Input port or output port is selected depending on the product (see 2. PIN FUNCTIONS). Data Sheet U14776EJ1V0DS00 3 µPD17P236 (2) PROM programming mode • 28-pin plastic SOP (9.53 mm (375)) µ PD17P236M1GT, 17P236M2GT, 17P236M3GT, 17P236M4GT D2 1 28 D1 D3 2 27 D0 VPP 3 26 D7 4 25 D6 5 24 D5 6 23 D4 7 22 MD3 (Open) 8 21 MD2 VDD 9 20 MD1 (Open) 10 19 MD0 CLK 11 18 GND 12 17 (L) 13 16 (Open) 14 15 (L) (L) 4 Data Sheet U14776EJ1V0DS00 µPD17P236 • 30-pin plastic SSOP (7.62 mm (300)) µ PD17P236M1MC-5A4, 17P236M2MC-5A4, 17P236M3MC-5A4, 17P236M4MC-5A4 D2 1 30 (Open) D3 2 29 D1 VPP 3 28 D0 4 27 D7 5 26 D6 6 25 D5 7 24 D4 (Open) 8 23 MD3 VDD 9 22 MD2 (Open) 10 21 MD1 CLK 11 20 MD0 GND 12 19 (L) 13 18 (Open) 14 17 (Open) 15 16 (L) (L) Caution Contents in parentheses indicate how to handle unused pins in PROM programming mode. L : Connect to GND via a resistor (470 Ω) separately. Open : Leave unconnected. CLK : Clock input for PROM D0-D7 : Data input/output for PROM GND : Ground MD0-MD3 : Mode select input for PROM VDD : Power supply VPP : Power supply for PROM writing Data Sheet U14776EJ1V0DS00 5 µPD17P236 BLOCK DIAGRAM P0A0 P0A1 P0A2 P0A3 P0A Remote Control Divider RF RAM 223 × 4 bits P0B0 (MD0) P0B1 (MD1) P0B2 (MD2) P0B3 (MD3) REM 8-bit timer SYSTEM REG. P0B Interrupt Controller INT (VPP) Reset Controller RESET ALU P0C0 (D4) P0C1 (D5) P0C2 (D6) P0C3 (D7) P0C One Time PROM 16,384 × 16 bits P0D0 (D0) P0D1 (D1) P0D2 (D2) P0D3 (D3) Instruction Decoder P0D Program Counter P0E0 P0E1 P0E2 P0E3 Power Supply Circuit P0E Stack (5 levels) Basic Interval/ Watchdog Timer Note P1A0 Remark XIN (CLK) OSC 6 Input port or output port is selected depending on the product (see 2. PIN FUNCTIONS). ( ): During PROM programming mode Data Sheet U14776EJ1V0DS00 GND CPU Clock P1A Note VDD XOUT µPD17P236 CONTENTS 1. DIFFERENCES BETWEEN µPD17236 AND µPD17P236 ........................................................... 8 2. PIN FUNCTIONS ........................................................................................................................... 9 2.1 Normal Operation Mode .................................................................................................................... 9 2.2 PROM Programming Mode ............................................................................................................... 10 2.3 Input/Output Circuits ......................................................................................................................... 11 2.4 Processing of Unused Pins .............................................................................................................. 12 2.5 Notes on Using the RESET and INT Pins ........................................................................................ 12 WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) .................................... 13 3.1 Operating Mode When Writing/Verifying Program Memory .......................................................... 13 3.2 Program Memory Writing Procedure ............................................................................................... 14 3.3 Program Memory Reading Procedure ............................................................................................. 15 4. ELECTRICAL SPECIFICATIONS ................................................................................................. 16 5. PACKAGE DRAWING .................................................................................................................. 23 6. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 25 APPENDIX. DEVELOPMENT TOOLS ................................................................................................ 27 3. Data Sheet U14776EJ1V0DS00 7 µPD17P236 1. DIFFERENCES BETWEEN µPD17236 AND µPD17P236 µPD17P236 is equipped with PROM to which data can be written by the user instead of the internal mask ROM (program memory) of the µPD17236. Table 1-1 shows the differences between the µPD17236 and µPD17P236. The CPU functions and internal hardware of the µPD17P236, 17230, 17231, 17232, 17233, 17234, 17235, and 17236 are identical. Therefore, the µPD17P236 can be used to evaluate the program developed for the µPD17230, 17231, 17232, 17233, 17234, 17235, and 17236 system. Note, however, that some of the electrical specifications such as supply current and low-voltage detection voltage of the µPD17P236 are different from those of the µPD17230, 17231, 17232, 17233, 17234, 17235, and 17236. Table 1-1. Differences among µPD17236 and µPD17P236 Product Name Item Program memory µPD17P236 µPD17P236M1, 17P236M2, 17P236M3, 17P236M4 One-time PROM µPD17236 Mask ROM 32 Kbytes (16,384 × 16) (0000H-3FFFH) Data memory 223 × 4 bits Input/output of P1A0 pin • Input (µPD17P236M2, 17P236M4) • Output (µPD17P236M1, 17P236M3) Any (mask option) Clock (RfX ) selection for carrier generation • RfX = fX/2 (µPD17P236M1, 17P236M2) • RfX = fX (µPD17P236M3, 17P236M4) Any (mask option) Low-voltage detection circuitNote Provided Any (mask option) Instruction execution time • 2 µs (VDD = 3.0 to 3.6 V) • 4 µs (VDD = 2.2 to 3.6 V) • 2 µs (VDD = 2.2 to 3.6 V) • 4 µs (VDD = 2.0 to 3.6 V) Supply voltage VDD = 2.2 to 3.6 V VDD = 2.0 to 3.6 V Package • 28-pin plastic SOP (9.53 mm (375)) • 30-pin plastic SSOP (7.62 mm (300)) Note 8 Although the circuit configuration is identical, its electrical characteristics differ depending on the product. Data Sheet U14776EJ1V0DS00 µPD17P236 2. PIN FUNCTIONS 2.1 Normal Operation Mode (1/2) Pin No. Symbol Function Output Format At Reset P0D0 P0D1 P0D2 P0D3 These pins constitute a 4-bit I/O port which can be set in the input or output mode in 4-bit units (group I/O). In the input mode, these pins serve as CMOS input pins with a pull-up resistor, and can be used as key return input lines of a key matrix. The standby status must be released when at least one of the input lines goes low. In the output mode, these pins are used as N-ch open-drain output pins and can be used as the output lines of a key matrix. N-ch open-drain Low-level output INT External interrupt request signal. This signal releases the standby status if an external interrupt request signal is input to it when the INT pin interrupt enable flag (IP) is set. – Input (4) (5) (6) (7) P0E0 P0E1 P0E2 P0E3 These pins constitute a 4-bit I/O port that can be set in the input or output mode in 1-bit units. In the output mode, this port functions as a high current CMOS output port. In the input mode, function as CMOS input and can be specified to connect pull-up resistor by program. CMOS push-pull Input 8 (8) REM 27 28 1 2 (28) (29) (1) (2) 3 (3) 4 5 6 7 Outputs transfer signal for infrared remote controller. Active-high output. CMOS Low-level push-pull output 9 (9) VDD Power supply – – 10 (10) 11 (11) XOUT XIN Connects ceramic resonator for system clock oscillation – (Oscillation stops) 12 (12) GND Ground – – 13 (13) RESET Turns ON pull down resistor if POC or watchdog timer overflows and if the stack pointer overflows or underflows, and resets the system. Usually, the pull-down resistor is ON. – Input 14 (14) P1A0 N-ch open-drain Highimpedance output – Input – Input N-ch open-drain Input µPD17P136M1, µPD17P136M3 This pin is 1-bit output port (N-ch open-drain output) and can be used as the output lines of a key matrix. µPD17P136M2, µPD17P136M4 This pin is 1-bit input port (CMOS input). However, it cannot release the STOP mode. 15 16 17 18 (16) (17) (18) (19) P0A0 P0A1 P0A2 P0A3 These pins are CMOS input pins with a 4-bit pull-up resistor. They can be used as the key return input lines of a key matrix. If any one of these pins goes low, the standby status is released. 19 20 21 22 (20) (21) (22) (23) P0B0 P0B1 P0B2 P0B3 These pins constitute a 4-bit I/O port that can be set in the input or output mode in 1-bit units. In the input mode, these pins are CMOS input pins with a pull-up resistor, and can be used as the key return input lines of a key matrix. The standby status is released when at least one of these pins goes low. In the output mode, they serve as N-ch open-drain output pins and can be used as the output lines of a key matrix. Remark The number in parenthesis in the Pin No. column indicates the pin numbers of the 30-pin plastic SSOP. Data Sheet U14776EJ1V0DS00 9 µPD17P236 2.1 Normal Operation Mode (2/2) Pin No. 23 24 25 26 (24) (25) (26) (27) (15) (30) Symbol P0C0 P0C1 P0C2 P0C3 IC1 IC2 Function These pins constitute a 4-bit I/O port that can be set in the input or output mode in 4-bit units (group I/O). In the input mode, these pins are CMOS input pins with a pull-up resistor, and can be used as the key return input lines of a key matrix. The standby status is released when at least one of these pins goes low. In the output mode, they serve as N-ch open-drain output pins and can be used as the output lines of a key matrix. These pins cannot be used. Leave open. Output Format At Reset N-ch open-drain Low-level output – – Remark The number in parenthesis in the Pin No. column indicates the pin numbers of the 30-pin plastic SSOP. 2.2 PROM Programming Mode Pin No. Symbol 3 VPP Function Power supply for PROM programming. Output Format At Reset – – – – Apply +12.5 V to this pin as the program voltage when writing/ verifying program memory. 9 VDD Power supply. Apply +6 V to this pin when writing/verifying program memory. 11 CLK Inputs clock for PROM programming. – – 12 GND Ground. – – 19 (20) MD0 Input pins used to select operation mode when PROM is – Input 22 (23) MD3 programmed. 23 (24) 26 (27) 27 (28) 28 (29) 1 2 D4 D7 D0 D1 D2 D3 CMOS push-pull Input Input/output 8-bit data for PROM programming Remarks 1. The other pins are not used in the PROM programming mode. How to handle the other opins are described in PIN CONFIGURATION (2) PROM programming mode. 2. The number in parenthesis in the Pin No. column indicates the pin numbers of the 30-pin plastic SSOP. 10 Data Sheet U14776EJ1V0DS00 µPD17P236 2.3 Input/Output Circuits The equivalent input/output circuit for each µPD17P236 pin is shown below. (4) P1A (1) P0A • Input mode (µPD17P236M2, 17P236M4) V DD Input buffer Input buffer • Output mode (µPD17P236M1, 17P236M3) (2) P0B, P0C, P0D VDD Output latch data N-ch P-ch (5) RESET Data Output latch VDD N-ch Output disable Reset input P-ch Selector Input buffer Input buffer Schmitt trigger input with hysteresis characteristics (3) P0E N-ch V DD (6) INT Data Pull-up register Data Output latch P-ch V DD P-ch Input buffer N-ch Output disable Schmitt trigger input with hysteresis characteristics (7) REM Selector Input buffer V DD Data Output disable Data Sheet U14776EJ1V0DS00 P-ch N-ch 11 µPD17P236 2.4 Processing of Unused Pins Process the unused pins as follows: Table 2-1. Processing of Unused Pins Pin P0A0-P0A3 Recommended Connection Leave open. P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P0E0-P0E3 Input : Individually connect to VDD or GND via resistor. Output : Leave open. P1A0 Connect to GND. REM Leave open. INT Connect to GND. IC1, IC2 These pins cannot be used. Leave open. 2.5 Notes on Using the RESET and INT Pins In addition to the functions shown in 2. PIN FUNCTIONS, the RESET pin also has the function of setting a test mode (for IC testing) in which the internal operations of the µPD17P236 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during normal operation, the µPD17P236 may be set in the test mode if noise exceeding VDD is applied. For example, if the wiring length of the RESET or INT pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. • Connect capacitor between VDD • Connect diode with low VF between VDD and RESET/INT pin and RESET/INT pin VDD Diode with low VF VDD RESET, INT 12 VDD VDD RESET, INT Data Sheet U14776EJ1V0DS00 µPD17P236 3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) The program memory of the µPD17P236 is a one-time PROM of 16,384 × 16 bits. To write or verify this one-time PROM, the pins shown in Table 3-1 are used. Note that no address input pin is used. Instead, the address is updated by using the clock input from the CLK pin. Table 3-1. Pins Used to Write/Verify Program Memory Pin Name Function VPP Supplies voltage when writing/verifying program memory. Apply +12.5 V to this pin. VDD Power supply. Supply +6 V to this pin when writing/verifying program memory. CLK Inputs clock to update address when writing/verifying program memory. By inputting pulse four times to CLK pin, address of program memory is updated. MD0-MD 3 Input to select operation mode when writing/verifying program memory. D0-D7 Inputs/outputs 8-bit data when writing/verifying program memory. 3.1 Operating Mode When Writing/Verifying Program Memory The µPD17P236 is set in the program memory write/verify mode when +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin after the µPD17P236 has been in the reset status (VDD = 5 V, RESET = 0 V) for a specific time. In this mode, the operating modes shown in Table 3-2 can be set by setting the MD0 through MD 3 pins. Leave all the pins other than those shown in Table 3-1 unconnected or connect them to GND via pull-down resistor (470 Ω). (See PIN CONFIGURATION (2) PROM programming mode.) Table 3-2. Setting Operation Mode Setting of Operating Mode VPP +12.5 V VDD +6 V Operating Mode MD0 MD1 MD2 MD3 H L H L Program memory address 0 clear mode L H H H Write mode L L H H Verify mode H × H H Program inhibit mode ×: don’t care (L or H) Data Sheet U14776EJ1V0DS00 13 µPD17P236 3.2 Program Memory Writing Procedure The program memory is written at high speed in the following procedure. (1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the V DD pin. Keep the V PP pin low. (3) Supply 5 V to the V PP pin after waiting for 10 µ s. (4) Set the program memory address 0 clear mode by using the mode setting pins. (5) Supply +6 V to V DD and +12.5 V to V PP. (6) Set the program inhibit mode. (7) Write data to the program memory in the 1-ms write mode. (8) Set the program inhibit mode. (9) Set the verify mode. If the data have been written to the program memory, proceed to (10). If not, repeat steps (7) through (9). (10) Additional writing of (number of times of writing in (7) through (9): X) × 1 ms. (11) Set the program inhibit mode. (12) Input a pulse to the CLK pin four times to update the program memory address (+1). (13) Repeat steps (7) through (12) up to the last address. (14) Set the 0 clear mode of the program memory address. (15) Change the voltages on the V DD and V PP pins to 5 V. (16) Turn off power. The following figure illustrates steps (2) through (12) above. Repeated X time Reset Verify Write Additional write Address increment VPP VPP VDD GND VDD VDD+1 VDD GND CLK D0-D7 Hi-Z Data input Hi-Z Data output Hi-Z MD0 MD1 MD2 MD3 14 Data Sheet U14776EJ1V0DS00 Data input Hi-Z µPD17P236 3.3 Program Memory Reading Procedure (1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the V DD pin. Keep the V PP pin low. (3) Supply 5 V to the V PP pin after waiting for 10 µ s. (4) Set the program memory address 0 clear mode by using the mode setting pins. (5) Supply +6 V to V DD and +12.5 V to V PP. (6) Set the program inhibit mode. (7) Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to (8) Set the program inhibit mode. (9) Set the program memory address 0 clear mode. the CLK pin four times. (10) Change the voltage on the V DD and V PP pins to 5 V. (11) Turn off power. The following figure illustrates steps (2) through (9) above. Reset VPP VPP VDD GND VDD VDD+1 VDD One cycle GND CLK D0-D7 Hi-Z Data output Data output Hi-Z MD0 MD1 "L" MD2 MD3 Data Sheet U14776EJ1V0DS00 15 µPD17P236 4. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Item Symbol Conditions Ratings Unit Supply voltage VDD –0.3 to +7.0 V PROM power supply VPP –0.3 to +13.5 V VI –0.3 to VDD + 0.3 V VO –0.3 to VDD + 0.3 V Peak value –36.0 mA rms value –24.0 mA Peak value –7.5 mA rms value –5.0 mA Peak value –22.5 mA rms value –15.0 mA Input voltage Output voltage High-level output current Note IOH REM pin 1 pin (P0E pin) Total of P0E pins Low-level output current Note IOL 1 pin (P0B, P0C, P0D, Peak value 7.5 mA P0E, P1A0, or REM pin) rms value 5.0 mA Total of P0B, P0C, P0D, Peak value 22.5 mA P1A0, REM pins rms value 15.0 mA Total of P0E pins Peak value 30.0 mA rms value 20.0 mA Operating temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Power dissipation Pd 180 mW Note TA = 85°C The rms value should be calculated as follows: [rms value] = [Peak value] × √ Duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 16 Data Sheet U14776EJ1V0DS00 µPD17P236 Recommended Operating Ranges (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Item Symbol Supply voltage Conditions VDD1 fX = 1 MHz High-speed mode (Instruction execution time: 16 µs) VDD2 fX = 4 MHz High-speed mode (Instruction execution time: 4 µs) VDD3 fX = 8 MHz Ordinary mode (Instruction execution time: 4 µs) VDD4 Oscillation frequency Low-voltage detector circuit Note High-speed mode (Instruction execution time: 2 µs) TYP. MAX. Unit 2.2 3.6 V 3.0 3.6 V fX 1.0 4.0 8.0 MHz TA –40 +25 +85 °C tCY 4 32 µs Operating temperature Note MIN. Reset if the status of VDD = 2.05 V (TYP.) lasts for 1 ms or longer. Program hang-up does not occur even if the voltage drops, until the reset function is effected. Some oscillators stop oscillating before the reset function is effected. fX vs VDD (MHZ) 10 9 8 7 6 System clock: fX (MHZ) (Normal mode) 5 4 3 Operation guaranteed area 2 1 0.4 0 2 2.2 3 3.6 4 Supply voltage: VDD (V) Remark The region indicated by the broken line in the above figure is the guaranteed operating range in the highspeed mode. Data Sheet U14776EJ1V0DS00 17 µPD17P236 System Clock Oscillator Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Resonator Recommended Constants Ceramic resonator X IN X OUT Item Conditions Oscillation frequency Note 1 (fX) Oscillation stabilization timeNote 2 MIN. TYP. MAX. Unit 1.0 4.0 8.0 MHz 4 ms After VDD reached MIN. in oscillation voltage range Notes 1. The oscillation frequency only indicates the oscillator characteristics. 2. The oscillation stabilization time is necessary for oscillation to be stabilized, after VDD application or STOP mode release. Caution To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: • Keep wiring length as short as possible. • Do not cross a signal line with some other signal lines. Do not route the wiring in the vicinity of lines through which a large current flows. • Always keep the oscillator capacitor ground at the same potential as GND. Do not ground the capacitor to a ground pattern, through which a large current flows. • Do not extract signals from the oscillator. External circuit example XIN XOUT R1 C1 Remark C2 For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 18 Data Sheet U14776EJ1V0DS00 µPD17P236 DC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Item High-level input voltage Symbol Conditions MIN. TYP. MAX. Unit VIHI1 P1A0 (input), RESET, INT 0.8VDD VDD V VIH2 P0A, P0B, P0C, P0D 0.7VDD VDD V VIH3 P0E 0.8VDD VDD V VIL1 P1A0 (input), RESET, INT 0 0.2VDD V VIL2 P0A, P0B, P0C, P0D 0 0.3VDD V VIL3 P0E 0 0.35VDD V High-level input leakage current ILIH P0A, P0B, P0C, P0D, P0E, P1A0, RESET, INT VIH = VDD 3 µA Low-level input leakage ILIL1 INT, P1A0 VIL = 0 V –3 µA current ILIL2 P0E VIL = 0 V w/o pull-up resistor –3 µA Internal pull-up resistor R1 P0E, RESET (pulled up) 25 50 100 kΩ R2 P0A, P0B, P0C, P0D 100 200 400 kΩ Internal pull-down resistor R3 RESET (pulled down) 2.5 5 10 kΩ High-level output current IOH1 REM VOH = 1.0 V, VDD = 3 V –6 –13 –24 mA High-level output voltage VOH P0E, REM IOH = –0.5 mA VDD–0.3 VDD V Low-level output voltage V OL1 P0B, P0C, P0D, P1A0 (output), REM IOL = 0.5 mA 0 0.3 V V OL2 P0E IOL = 1.5 mA 0 0.3 V Low-voltage detection voltage V DT RESET pin pulled down, VDT = V DD 2.2 V Data retention voltage VDDDR RESET = low level or STOP mode 3.6 V Low-level input voltage Supply current IDD1 Operating mode VDD = 3 V ±10% (high-speed) IDD2 Operating mode VDD = 3 V ±10% (low-speed) IDD3 IDD4 HALT mode STOP mode VDD = 3 V ±10% 2.05 1.3 fX = 1 MHz 0.55 1.1 mA fX = 4 MHz 1.0 2.0 mA fX = 8 MHz 1.3 2.6 mA fX = 1 MHz 0.5 1.0 mA fX = 4 MHz 0.75 1.5 mA fX = 8 MHz 0.9 1.8 mA fX = 1 MHz 0.4 0.8 mA fX = 4 MHz 0.5 1.0 mA fX = 8 MHz 0.6 1.2 mA 2.0 20.0 µA 2.0 5.0 µA VDD = 3 V ±10% built-in POC Data Sheet U14776EJ1V0DS00 TA = 25°C 19 µPD17P236 AC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Item Symbol Note CPU clock cycle time (instruction execution time) Conditions MIN. tCY1 tCY2 VDD = 3.0 to 3.6 V TYP. MAX. Unit 3.8 33 µs 1.9 33 µs INT high/low level width tINTH, tINTL 20 µs RESET low level lwidth tRSL 10 µs Note tCY vs VDD The CPU clock cycle time (instruction execution time) is determined by the oscillation frequency of the resonator 40 connected and SYSCK (RF: address 02H) of the register 33 file. The figure on the right shows the CPU clock cycle time 10 9 8 7 CPU clock cycle time tCY (µ s) tCY vs. supply voltage VDD characteristics. 6 Operation guaranteed area 5 4 3.8 3 2 1.9 2.2 1 0 1 2 3.6 3 4 Supply voltage VDD (V) 20 Data Sheet U14776EJ1V0DS00 µPD17P236 DC Programming Characteristics (TA = 25°C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter Symbol High-level input voltage Low-level input voltage Conditions VIH1 Other than CLK VIH2 CLK V IL1 Other than CLK V IL2 CLK Input leakage current ILI MIN. TYP. MAX. Unit VDD V V DD – 0.5 VDD V 0 0.3V DD V 0 0.4 V 10 µA 0.4 V 30 mA 30 mA 0.7V DD VIN = V IL or V IH High-level output voltage VOH IOH = –1 mA Low-level output voltage VOL IOL = 1.6 mA VDD supply current IDD VPP supply current IPP V DD – 1.0 V MD0 = V IL, MD1 = VIH Cautions 1. Keep VPP to within +13.5 V including overshoot. 2. Apply VDD before VPP and turns it off after VPP. AC Programming Characteristics (TA = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Address setup timeNote (vs. MD0↓) tAS 2 µs MD1 setup time (vs. MD 0↓) tM1S 2 µs Data setup time (vs. MD0↓) tDS 2 µs tAH 2 µs tDH 2 µs MD0↑→ data output float delay time tDF 0 VPP setup time (vs. MD 3↑) tVPS 2 VDD setup time (vs. MD 3↑) tVDS 2 Initial program pulse width tPW 0.95 Additional program pulse width tOPW 0.95 MD0 setup time (vs. MD 1↑) tMOS 2 Address hold timeNote (vs. MD 0↑) Data hold time (vs. MD0↑) MD0↓→ data output delay time tDV MD0 = MD1 = V IL MD1 hold time (vs. MD0↑) tM1H tM1H+tM1R ≥ 50 µs MD1 recovery time (vs. MD0↓) Program counter reset time CLK input high-, low-level width CLK input frequency Initial mode set time MD3 setup time (vs. MD1↑) µs 1.0 1.05 ms 21.0 ms µs 1 µs µs tM1R 2 µs tPCR 10 µs tXH, tXL 0.125 fX µs 4.19 MHz tI 2 µs tM3S 2 µs 2 µs 2 µs tM3H MD3 setup time (vs. MD0↓) tM3SR When program memory is read → data output delay time tDAD When program memory is read AddressNote → data output hold time tHAD When program memory is read 0 MD3 hold time (vs. MD0↑) tM3HR When program memory is read 2 MD3↓→ data output float delay time tDFR When program memory is read Reset setup time tRES Note ns µs 2 MD3 hold time (vs. MD1↓) AddressNote 130 2 µs 130 ns µs 2 10 µs µs The internal address increment (+1) is performed on the fall of the 3rd clock, where 4 clocks compreise one cycle. The internal clock is not connected to a pin. Data Sheet U14776EJ1V0DS00 21 µPD17P236 Program Memory Write Timing tRES tVPS VPP VPP VDD GND VDD VDD+1 VDD GND tVDS tXH CLK D0-D7 tXL Hi-Z Data input tI tDS Data output tDH tDV tDF Data input Data input tDH tAH tDS tAS MD0 tPW tM1R tMOS tOPW MD1 tPCR tM1S tM1H MD2 tM3H tM3S MD3 Program Memory Read Timing tRES tVPS VPP VPP VDD GND VDD tVDS VDD+1 VDD tXH GND CLK tXL tDAD tHAD Data output D0-D7 Data output tDV tI MD0 MD1 "L" tPCR MD2 tM3SR MD3 22 Data Sheet U14776EJ1V0DS00 tM3HR tDFR µPD17P236 5. PACKAGE DRAWING 28-PIN PLASTIC SOP (9.53 mm (375)) 28 15 detail of lead end P 1 14 A H F I G J S C D M B L N M S K E NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 17.9±0.17 B 0.78 MAX. C 1.27 (T.P.) D 0.42+0.08 −0.07 E 0.1±0.1 F 2.6±0.2 G 2.50 H 10.3±0.3 I 7.2±0.2 J 1.6±0.2 K 0.17+0.08 −0.07 L 0.8±0.2 M 0.12 N 0.15 P 3°+7° −3° P28GM-50-375B-5 Data Sheet U14776EJ1V0DS00 23 µPD17P236 30-PIN PLASTIC SSOP (7.62 mm (300)) 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B K M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 9.85±0.15 B 0.45 MAX. C 0.65 (T.P.) D 0.24+0.08 −0.07 E 0.1±0.05 F 1.3±0.1 G 1.2 H 8.1±0.2 I 6.1±0.2 J 1.0±0.2 K 0.17±0.03 L 0.5 M 0.13 N 0.10 P 3° +5° −3° T 0.25 U 0.6±0.15 S30MC-65-5A4-2 24 Data Sheet U14776EJ1V0DS00 µPD17P236 6. RECOMMENDED SOLDERING CONDITIONS For the µPD17P236 soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document "Semiconductor Device Mounting Technology Manual" (C10535E). For other soldering methods, please consult with NEC personnel. Table 6-1. Soldering Conditions of Surface Mount Type (1) µ PD17P236M1GT: 28-pin plastic SOP (9.35 mm (375)) µ PD17P236M2GT: 28-pin plastic SOP (9.35 mm (375)) µ PD17P236M3GT: 28-pin plastic SOP (9.35 mm (375)) µ PD17P236M4GT: 28-pin plastic SOP (9.35 mm (375)) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (210°C min.), Number of times: 2 max. Number of days: 7Note (after that, prebaking is necessary at 125°C for 10 hours) <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. IR35-107-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (200°C min.), Number of days: 7Note (after that, prebaking is necessary at 125°C for 10 hours) <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. VP15-107-2 Wave soldering Solder bath temperature: 260°C max, Time: 10 seconds max., Number of times: once, preheating temperature: 120°C max. (package surface temperature) Note Number of days: 7 (after that, prebaking is necessary at 125°C for 10 hours) WS60-107-1 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per side of device) Note — After opening the dry pack, store it at 25 °C or less and 6.5 % RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U14776EJ1V0DS00 25 µPD17P236 (2) µ PD17P236M1MC-5A4: 30-pin plastic SSOP (7.62 mm (300)) µ PD17P236M2MC-5A4: 30-pin plastic SSOP (7.62 mm (300)) µ PD17P236M3MC-5A4: 30-pin plastic SSOP (7.62 mm (300)) µ PD17P236M4MC-5A4: 30-pin plastic SSOP (7.62 mm (300)) Soldering Method Soldering Conditions Symbol Intrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (210°C min.), Note Number of times: 2 max. Number of days: 3 (after that, prebaking is necessary at 125°C for 10 hours) <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. IR35-103-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (200°C min.), Note Number of times: 2 max. Number of days: 3 (after that, prebaking is necessary at 125°C for 10 hours) <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. VP15-103-2 Wave soldering Solder bath temperature: 260°C max, Time: 10 seconds max., Number of times: once, preheating temperature: 120°C max. (package surface temperature) Note Number of days: 3 (after that, prebaking is necessary at 125°C for 10 hours) WS60-103-1 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per side of device) Note After opening the dry pack, store it at 25 °C or less and 6.5 % RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 26 — Data Sheet U14776EJ1V0DS00 µPD17P236 APPENDIX. DEVELOPMENT TOOLS To develop the programs for the µPD17P236 subseries, the following development tools are available: Hardware Name Remarks IE-17K and IE-17K-ET are the in-circuit emulators used in common with the 17K series microcontroller. IE-17K and IE-17K-ET are connected to a PC-9800 series or IBM PC/ATTM compatible machines as the host machine with RS-232C. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging environment can be provided by using man-machine interface SIMPLEHOST TM. In-circuit emulator IE-17K, IE-17K-ETNote 1 SE board (SE-17235) This is an SE board for µPD17236 subseries. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. Emulation probe (EP-17K28GT) EP-17K28GT is an emulation probe for 17K series 28-pin SOP (GM-375B). When used with Note 2 EV9500GT-28 , it connects an SE board to the target system. Emulation probe (EP-17K30GS) EP-17K30GS is an emulation probe for 17K series 30-pin SSOP (MC-5A4). When used with EV-9500GT-30Note 3, it connects an SE board to the target system. Conversion adapter (EV-9500GT-28Note 2) The EV-9500GT-28 is a conversion adapter for the 28-pin SOP (GM-375B). It is used to connect the EP-17K28GT and target system. Conversion adapter (EV-9500GT-30 Note 3 The EV-9500GT-30 is a conversion adapter for the 30-pin SSOP (MC-5A4). It is used to ) connect the EP-17K30GS and target system. PROM programmer Note 4 Note 4 (AF-9706 , AF-9708 , Note 4 AF-9709 ) AF-9706, AF-9708, and AF-9709 are PROM programmers corresponding to µPD17P236. By connecting program adapter PA-17P236 to this PROM programmer, µPD17P236 can be programmed. Program adapter (PA-17P236) PA-17P236 are adapters that is used to program µPD17P236, and is used in combination with AF-9706, AF-9708, or AF-9709. Notes 1. Low-cost model: External power supply type 2. Two EV-9500GT-28 are supplied with the EP-17K28GT. Five EV-9500GT-28 are optionally available as a set. 3. Two EV-9500GT-30 are supplied with the EP-17K30GS. Five EV-9500GT-30 are optionally available as a set. 4. These are products from Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd. (Tel: 033733-1166). Data Sheet U14776EJ1V0DS00 27 µPD17P236 Software Name 17K assembler (RA17K) Device file (AS17235) Support software (SIMPLEHOST) 28 Outline Host Machine OS Supply Order Code The RA17K is an assembler common to the 17K series products. When developing the program of devices, RA17K is used in combination with a device file (AS17235). PC-9800 series Japanese Windows 3.5" 2HD µSAA13RA17K IBM PC/AT compatible machine Japanese Windows 3.5" 2HC µSAB13RA17K The AS17235 is a device file for µPD17230, 17231, 17232, 17233, 17234, 17235, and 17236 and is used in combination with an assembler for the 17K series (RA17K). PC-9800 series Japanese Windows 3.5" 2HD µSAA13AS17235 IBM PC/AT compatible machine Japanese Windows 3.5" 2HC µSAB13AS17235 SIMPLEHOST is a software package that enables man-machine interface on the Windows when a program is developed by using an in-circuit emulator and a personal computer. PC-9800 series Japanese Windows 3.5" 2HD µSAA13ID17K IBM PC/AT compatible machine Japanese Windows 3.5" 2HC µSAB13ID17K TM µSBB13RA17K English Windows µSBB13AS17235 English Windows English Windows Data Sheet U14776EJ1V0DS00 µSBB13ID17K µPD17P236 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet U14776EJ1V0DS00 29 µPD17P236 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 30 Data Sheet U14776EJ1V0DS00 µPD17P236 SIMPLEHOST is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. Data Sheet U14776EJ1V0DS00 31 µPD17P236 • The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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