DATA SHEET MOS INTEGRATED CIRCUIT µ PD17P068 4-BIT SINGLE-CHIP MICROCONTROLLER WITH ON-CHIP HARDWARE FOR TV SYSTEMS The µPD17P068 is a one-time PROM version of the µ PD17068 that has on-chip mask ROM. The µ PD17P068, which can be programmed only once, is suited for testing during development of µ PD17068 systems and limited production runs. Use this data sheet together with µ PD17068 documents. The µPD17P068 does not provide a level of reliability intended for mass production of the customer's products. Use it only for functional evaluation when experimenting or doing product trial tests. FEATURES • Compatible with the µPD17068 • One-time PROM : 12160 × 16 bits • Operating voltage : VDD = 5 V ± 10 % ORDERING INFORMATION Part Number Package µ PD17P068GF-3BA 100-pin plastic QFP (14 × 20mm) The information in this document is subject to change without notice. Document No. U10336EJ1V0DS00 Date Published November 1995 P Printed in Japan © 1995 µPD17P068 FUNCTIONAL OUTLINE Part Number Item µPD17068 µPD17P068 Mask ROM One-time PROM Program memory (ROM) • 12160 × 16 bits Table reference area: 12160 × 16 bits Character ROM (CROM) • 6144 × 16 bits Data memory (RAM) • 1007 × 4 bits (including area serving also as VRAM) Data buffer: 4 × 4 bits, general register: 16 × 4 bits Video RAM (VRAM) • 672 × 4 bits (also used as data memory (RAM)) System register • 12 × 4 bits Register file • 12 × 4 bits General port register • 12 × 4 bits Instruction execution time • 2 µs (when using 8-MHz crystal resonator) Stack levels • 12 levels (stack manipulation possible) General ports • I/O ports • Input ports • Output ports : 19 : 4 : 21 • Number of displayable characters • Display format IDC (Image Display Controller) • Character types • Character format • Color • Character size Serial interface • 2 systems Serial interface 0 (compatible with 2-wire system, 3-wire system and I2C Bus) Serial interface 1 (3-wire system) D/A converter • 8 bits × 9 channels (PWM output, 12.5 V max.) A/D converter • 6 bits × 8 channels (successive approximation by software) Interrupt 2 : 192 characters max. per screen (up to 350 characters with program) : 16 × 16-dot mode 15 lines × 24 columns : 14 × 16-dot mode 17 lines × 24 columns : 255 types (user programmable) : 16 × 16 dots and 14 × 16 dots selectable (2 dots can be placed between characters) : 15 colors : Vertical : 16 sizes (specifiable for each line) Horizontal : 24 sizes (specifiable for each character) • 10 channels (maskable interrupt) External interrupt : 3 channels (INT0, INTNC, VSYNC, HSYNC) Internal interrupt : 7 channels (timer 0, 1, serial interface 0, 1, basic timer 2, VRAM pointer, timer 0 overflow) µPD17P068 Part Number µPD17068 Item Timer Reset Timer 0 Timer 1 Basic timer 0 Basic timer 1 Basic timer 2 Watch timer : : : : : : µPD17P068 10 µs to 204.75 ms (interrupt) 1 µs to 256 ms (interrupt) 1, 5, 100 ms (carry) 125 µs, 1 ms, 5 ms, 100 ms, external (carry) 125 µs, 1 ms, 5 ms, 100 ms, external (interrupt) Date, Hour, Minute, Second (counter) • Power-on reset • Reset with CE pin (CE pin: Low level → High level) • Power interruption detection Supply voltage VDD = 5 V ± 10 % Package 100-pin plastic QFP (14 × 20 mm) 3 µPD17P068 BLOCK DIAGRAM VCO PLL PSC EO RAM 1007 × 4 bits OSCIN (P0D 0/MD 0/XTOUT) (P0D 1/MD 1/XTIN) (P0D 2/MD 2) (P0D 3/MD 3) (P1C0/D 0) ADC7 (P1C2/D 2) OSC Circuit OSCOUT A/D Converter ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 VRAM (672 × 4 bits) HSYNC SYSTEM REG. VSYNC RF RED PWM 0 (P2C0) PWM 3 (P2C3) D/A Converter PWM 4 (P2B 0) PWM 7 (P2B 3) GREEN IDC PWM 8 (P2A 0) BLUE XTIN (P0D1/ADC2) BLANK ALU I (P0B 2) OSC XTOUT (P0D0/ADC1) CKOUT (P1B1) Watch Timer Hsync Counter HSCNT (P0B 3) Instruction Decoder Timer0 4 One-time PROM 12160 × 16 bits Timer1 P0D 0-P0D 3 4 CROM 6144 × 16 bits P1A 0-P1A 3 4 P1B 0-P1B 3 (D4-D7) 4 P1C0-P1C3 4 P1D 0-P1D 3 4 P0A 0-P0A 3 4 P0B 0-P0B 3 4 P0C0-P0C3 Basic Timer0 Program Counter Basic Timer1 Port Stack 12 × 14 bits TMIN (P1B 3) Basic Timer2 P2A 0 SDA (P0A 0) P2B 0-P2B 3 4 P2C0-P2C 3 4 P2D 0-P2D 2 3 SCL (P0A1) Serial I/O0 SCK 0 (P0A 2) SO 0 (P0A 3) X IN/CLK XOUT VDD CE RLSSTP/P1B 2 GND0, GND1 4 SI 0 (P0B 0) Main Oscillator Reset CPU Peripheral Serial I/O1 SCK1 (P2D0) SO 1 (P2D1) SI 1 (P2D2) Interrupt INT NC (VPP) INT 0 µPD17P068 PIN CONFIGURATION (Top View) P1D3 CE PSC EO VCO GND2 GND1 NC NC NC NC NC NC VDD1 VDD0 XIN XOUT INT NC XT OUT /ADC 1 /P0D 0 XT IN /ADC 2 /P0D 1 (1) Normal operation mode 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P0D 2 /ADC 3 P0D 3 /ADC 4 P1C0 /ADC 5 P1C1 /ADC 6 NC P1C2 /ADC 7 P1C3 NC ADC 0 NC P0C0 NC P0C1 NC P0C2 NC P0C3 NC P2C0 /PWM 0 NC P2C1 /PWM 1 NC P2C2 /PWM 2 NC P2C3 /PWM 3 NC P2B 0 /PWM 4 P2B 1 /PWM 5 P2B 2 /PWM 6 P2B 3 /PWM 7 RED GREEN NC BLUE BLANK HSYNC NC VSYNC P0B 3 /HSCNT NC NC P0B 2 /I P0B 1 NC P0B0 /SI 0 P0A3 /SO 0 P0A2 /SCK0 NC P0A 1 /SCL P0A 0 /SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 µ PD17P068GF-3BA P1D 2 P1D 1 P1D 0 INT 0 NC P1B 3 /TMIN P1B 2 /RLSSTP NC P1B 1 /CKOUT P1B 0 NC NC P1A 3 P1A 2 NC NC NC P1A 1 P1A 0 NC P2A 0 /PWM 8 NC NC P2D 2 /SI 1 P2D 1 /SO 1 P2D 0 /SCK1 NC GND 0 OSCOUT OSC IN 5 µPD17P068 VDD1 VDD0 CLK (OPEN) VPP MD 0 MD 1 (OPEN) (L) GND 2 GND 1 (OPEN) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 µ PD17P068GF-3BA MD 2 MD 3 D0 D1 (OPEN) D2 D3 (OPEN) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (L) (L) (OPEN) (OPEN) (L) (OPEN) (L) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (OPEN) (L) (OPEN) (L) (OPEN) GND 0 (OPEN) (L) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (OPEN) (L) (OPEN) D7 D6 (OPEN) D5 D4 (OPEN) (OPEN) (L) (2) PROM programming mode Caution Contents in parentheses indicate how to handle unused pins in PROM programming mode. L: Connect to GND via a resistor (470 Ω) separately. OPEN: Leave unconnected. 6 µPD17P068 PIN IDENTIFICATIONS ADC 0-ADC 7 : A/D converter input P1C 0-P1C 3 : Port 1C BLANK : Blanking signal output P1D 0-P1D 3 : Port 1D BLUE : Character signal output P2A 0 : Port 2A CE : Chip enable P2B 0-P2B 3 : Port 2B CKOUT : Watch timer adjustment P2C 0-P2C 3 : Port 2C P2D 0-P2D 2 : Port 2D CLK : Address update clock input PSC : Pulse swallow control output output D 0-D 7 : Data input/output PWM 0-PWM 8 : Pulse-width modulation output EO : Error out RED : Character signal output GND 0-GND 2 : Ground RLS STP : Clock stop release signal input GREEN : Character signal output SCK 0, SCK 1 : Shift clock input/output HSCNT : Horizontal synchronizing signal counter input H SYNC : Horizontal synchronizing signal input SCL : Shift clock input/output SDA : Serial data input/output Sl 0, Sl 1 : Serial data input SO 0, SO1 : Serial data output I : Character signal output TMIN : Event input of basic timer 1 or 2 INT 0, INT NC : External interrupt request VCO : Local oscillation input V DD0 , V DD1 : MD 0-MD 3 : Operation mode select V PP : Program voltage application NC : No connection signal input Positive power supply V SYNC : Vertical synchronizing signal input OSC IN, OSC OUT : LC oscillation for IDC X IN , X OUT : Main clock oscillation P0A 0-P0A 3 : Port 0A XT IN, XT OUT : Watch timer oscillation P0B 0-P0B 3 : Port 0B P0C 0-P0C 3 : Port 0C P0D 0-P0D 3 : Port 0D P1A 0-P1A 3 : Port 1A P1B 0-P1B 3 : Port 1B 7 µPD17P068 CONTENTS 1. 2. PIN FUNCTIONS ................................................................................................................................. 9 1.1 1.2 Normal Operation Mode ........................................................................................................................... 9 PROM Programming Mode .................................................................................................................... 13 1.3 1.4 Pin Equivalent Circuits .......................................................................................................................... 14 Handling of Unused Pins ....................................................................................................................... 19 1.5 Notes on Using the CE and INTNC Pins (Only in Normal Operation Mode) ................................... 21 WRITE, READ, AND VERIFY OF ONE-TIME PROM (PROGRAM MEMORY) ............................ 22 2.1 Operation Modes in Program Memory Write/Read/Verify ................................................................. 23 2.2 2.3 PROM Write Procedure .......................................................................................................................... 24 PROM Read Procedure .......................................................................................................................... 25 3. ELECTRICAL SPECIFICATIONS .................................................................................................... 26 4. PACKAGE DRAWING ...................................................................................................................... 31 APPENDIX DEVELOPMENT TOOLS .................................................................................................... 32 8 µPD17P068 1. PIN FUNCTIONS 1.1 Normal Operation Mode (1) Port pins Pin Name P0A0 P0A1 P0A2 P0A3 Description 4-bit I/O port. These pins serve as a bit-selectable 4-bit input/output port. All these pins are set to input pins when power (VDD) is turned on, when clock is stopped, or when reset signal is input to the CE pin. I/O SCL I/O Input SO0 P0C0 P0C3 These pins serve as a 4-bit output port. The output state of each pin is undefined after power (VDD) is turned on. O Sl0 CMOS push-pull Input HSCNT CMOS push-pull Undefined output These pins serve as a 4-bit input port. I — Input with pulldown resistor P0D3 P1B2 These pins serve as a 4-bit output port. O N-ch open-drain Middle voltage, high current Undefined output ADC3 — — 4-bit I/O port. These pins serve as a bit-selectable 4-bit input/output port. CKOUT I/O CMOS push-pull Input RLSSTP P1B3 P1C0 P1C2 ADC2/XTIN ADC4 P1B0 P1B1 — ADC1/XTOUT P0D2 P1A0 P1A3 — l P0D0 P0D1 SCK0 CMOS push-pull P0B3 P0B2 Shared by SDA I/O P0B1 When Reset N-ch open drain 4-bit I/O port. These pins serve as a bit-selectable 4-bit input/output port. All these pins are set to input pins when power (VDD) is turned on, when clock is stopped, or when reset signal is input to the CE pin. P0B0 Output Type TMIN 4-bit I/O port. These pins serve as 4-bitselectable 4-bit I/O port. I/O CMOS push-pull Input P1C3 ADC5 ADC7 — P1D0 P1D3 These pins serve as a 4-bit output port. O P2A0 This pin serves as a 1-bit output port. O P2B0 P2B3 These pins serve as a 4-bit output port. O P2C0 P2C3 These pins serve as a 4-bit output port. O CMOS push-pull Undefined output — Undefined output PWM8 Undefined output PWM4 PWM7 Undefined output PWM0 PWM3 N-ch open-drain P2D0 P2D1 P2D2 Middle voltage N-ch open-drain Middle voltage N-ch open-drain These pins serve as a bit-selectable 3-bit input/output port. All these pins are set to input pins when power (VDD) is turned on, when clock is stopped, or when reset signal is input to the CE pin. Middle voltage SCK1 I/O CMOS push-pull Input SO1 Sl1 9 µPD17P068 (2) Non-port pins Pin Name EO Description This pin outputs signals from the charge pump of the PLL frequency synthesizer. If the frequency divided from the local oscillator (VCO) frequency is higher (lower) than the reference frequency, high (low) level is output from this pin, respectively. When the two frequencies match, this pin is placed in the high-impedance state. I/O Output Type When Reset Shared by O CMOS 3-state High-impedance — CMOS push-pull Output — — PSC This pin outputs pulse swallow control signal. This signal switches division ratio for the dedicated prescaler µPB595. O VCO This pin is the input of the local oscillator. The output signal coming from the local oscillator (VCO) in the tuner and divided by the dedicated prescaler µPB595 should be input to this pin, where the µPB595 is a two-module prescaler capable of frequency division up to 1 GHz. I — Internally pulled down HSCNT This pin is the input of the H sync signal counter. I — Input BLANK This active-high pin outputs blanking signals to delete video signals. O CMOS push-pull Low level output — This active-high pin outputs character data that correspond the R signal (one of the RGB signals of IDC). O CMOS push-pull Low level output — GREEN This active-high pin outputs character data that correspond the G signal (one of the RGB signals of IDC). O CMOS push-pull Low level output — BLUE This active-high pin outputs character data that correspond the B signal (one of the RGB signals of IDC). O CMOS push-pull Low level output — This pin outputs character data that correspond the I signal of IDC. O CMOS push-pull Input P0B2 HSYNC The H sync signals for IDC should be input to this pin in an active-low manner. I — Input — VSYNC The V sync signals for IDC should be input to this pin in an active-low manner. I — Input — These are the input and output pins of the LC oscillation circuit for IDC. Adjust the oscillation frequency to 10 MHz. — — I — RED I OSC IN OSC OUT — ADC 0 ADC 1 These are the analog input pins of the 6-bit resolution A/D converter. 10 P0D0/XT OUT P0D 1/XT IN P0D 2 ADC 3 ADC 5 ADC 7 — — Input ADC 2 ADC 4 P0B3 These are the analog input pins of the 6-bit resolution A/D converter. I — Input P0D 3 P1C 0 P1C 2 µPD17P068 Pin Name Description I/O Output Type When Reset PWM0 PWM3 PWM4 PWM7 P2C0 P2C3 These are the output pins of the 8-bit resolution D/A converter. O N-ch open-drain Middle-voltage Low-level output or high impedance PWM8 This pin is the input of basic timer 1 or 2. I — XTIN A 32.768-kHz crystal resonator for watch timer operation should be connected to these pins. — — CKOUT P2B0 P2B3 P2A0 TMIN XTOUT Shared by This pin outputs the signal to control the Input P1B3 P0D1/ADC2 — P0D0/ADC1 O CMOS push-pull Input I/O CMOS push-pull Input P1B1 watch timer. SCK0 P0A2 These pins input and output shift clocks. SCK1 P2D0 Sl0 P0B0 These pins input serial data. I — Input Sl1 P2D2 SO0 P0A3 These pins output serial data. O CMOS push-pull Input SO1 P2D1 SCL These pins input and output shift clocks. I/O N-ch open-drain Input P0A1 SDA These pins input and output serial data. I/O N-ch open-drain Input P0A0 INT0 This pin inputs interrupt request signal from external device. An interrupt request is issued at the rising or falling edge of the input signal applied to this pin. I — Input — I — Input — INTNC This pin inputs interrupt request signal with noise canceller. Using this pin to input signals with noise such as commands from a remote control unit simplifies programming processes. The interrupt request issuing timing is programmable to either rising or falling edge of the input signal to this pin. 11 µPD17P068 Pin Name Description I/O Output Type CE This pin selects a device to be activated, or resets this device. (1) Use as input of device selection signal When CE=high, PLL synthesizer and IDC operate. When CE=low, their operation are disabled (stops). (2) Use as reset input When CE changes from low to high, this device is reset in synchronization with the carry FF operation for the internal basic interval timer 0. I — Input — I — Input P1B2 — — — — — — — — These pins supply the ground level for this device. — — — — This pin should be left unconnected. — — — — RLSSTP This pin inputs the clock stop release When Reset Shared by signal. XIN XOUT VDD0 VDD1 GND0 GND2 NC 12 An 8-MHz crystal resonator for main clock generation should be connected to these pins. These pins supply positive power voltage for this device. The power supply voltage of 5 V ± 10 % should be applied to these pins when all functions operate. When IDC is disabled, the voltage range from 4.0 to 5.5 V is allowed. When clock is stopped, the applied voltage to these pins may be lowered down to 2.5 V. Because this device internally has the power-on reset circuit, the voltages applied to these pins are changed from 0 to 4.0 V, system reset sequence is started and the program is implemented from address 0H. To assure normal operations of the power-on reset circuit, the rise time from 0 to 4.0 V should be shorter than 500 ms. µPD17P068 1.2 PROM Programming Mode Pin Name D0 D7 Description 8-bit data input/output pins used in program memory write, read, verify modes. I/O I/O Output Type CMOS push-pull MD0 MD3 Input pins that select an operation mode in program memory write, read, verify modes. I — CLK Clock input for address update in program memory write, read, verify modes. I — VPP Programming voltage (+12.5 V) application pin in program memory write, read, verify modes. — — Positive power supply. +5 V should be applied to these pins in program memory write, read, verify modes. — — Ground pin — — VDD0 VDD1 GND0 GND2 Remark The other pins are not used in the PROM programming mode. How to handle the other pins are described in the section "PIN CONFIGURATION (2) PROM programming mode". 13 µPD17P068 1.3 Pin Equivalent Circuits (1) P0A (P0A 3/SO 0, P0A 2/SCK 0) P0B (P0B 2/l, P0B 1, P0B 0/Sl 0) (Input/output) P1B (P1B 2/RLS STP , P1B 1/CKOUT, P1B0) P1C (P1C 3, P1C 2/ADC 7, P1C 1/ADC6, P1C 0/ADC5) A/D converter (P1C/ADC only) VDD RESET (other than P1C) Read instruction (P1C only) VDD (2) P2D (P2D 2/Sl 1, P2D 1/SO1, P2D 0/SCK 1) : (Input/output) VDD RESET VDD 14 µPD17P068 (3) P0A (P0A 1/SCL, P0A 0/SDA) : (Input/output) VDD (4) P0C (P0C 3, P0C 2, P0C 1, P0C 0) P1D (P1D 3, P1D 2, P1D 1, P1D 0) RED, GREEN, BLUE, BLANK (Output) PSC VDD (5) P1A (P1A 3, P1A 2, P1A 1, P1A 0) P2A (P2A 0/PWM 8) P2B (P2B 3/PWM 7, P2B 2/PWM 6, P2B 1/PWM 5, P2B 0/PWM 4) (Output) P2C (P2C 3/PWM 3, P2C 2/PWM 2, P2C 1/PWM 1, P2C 0/PWM 0) (6) P0D (P0D 3/ADC 4, P0D 2/ADC 3, P0D 1/ADC 2/XT IN, P0D 0/ADC 1/XT OUT) : (Input) VDD High on-resistance 15 µPD17P068 (7) ADC 0 : (Input) VDD (8) P0B 3/HSCNT : (Input/output) VDD RESET Port VDD VDD H sync signal counter VDD 16 µPD17P068 (9) P1B 3/TMIN : (Input/output) VDD RESET Port VDD VDD Timer counter VDD (10) HSYNC , V SYNC , CE, INT 0, INT NC : (Schmitt triggered input) VDD 17 µPD17P068 (11) X IN, OSC IN : X OUT, OSC OUT : High on-resistance VDD VDD XIN, OSCIN XOUT, OSCOUT (12) EO : (Output) VDD (13) VCO : (Input) VDD VDD (Input) 18 µPD17P068 1.4 Handling of Unused Pins The following are recommended for handling unused pins. Table 1-1. Handling of Unused Pins (1/2) (a) Port pins Pin Name P0A0/SDA Input/Output Circuit Type Input/output Note 1 Recommended Handling when in Unused State Specify a general-purpose input port by software and connect each pin to VDD or GND through a resistor. Note 2 P0A1/SCL P0A2/SCK0 P0A3/SO0 P0B0/SI0 P0B1 P0B2/I P0B3/HSCNT P0C0-P0C3 CMOS push-pull output Open P0D0/ADC1/XTOUT Input Individually connect to GND through a resistor. Note 2 P0D1/ADC2/XTIN P0D2/ADC3, P0D3/ADC4 P1A0-P1A3 P1B0 N-ch open-drain output Input/output Note 1 Specify low-level output by software, then open. Specify a general-purpose input port by software and connect each pin to VDD or GND through a resistor. Note 2 P1B1/CKOUT P1B2/RLSSTP P1B3/TMIN P1C0/ADC5-P1C2/ADC7 P1C3 P1D0-P1D3 CMOS push-pull output Open P2A0/PWM8 N-ch open-drain output Specify low-level output by software, then open. Input/output Note 1 Specify a general-purpose input port by software and connect each pin P2B0/PWM4-P2B3/PWM7 P2C0/PWM0-P2C3/PWM3 P2D0/SCK1 to VDD or GND through a resistor. Note 2 P2D1/SO1 P2D2/SI1 Notes 1. Input ports go to input mode when the power supply rises, when the clock stops, and on CE reset. 2. Be careful of the fact that when an external pull-up (connection to VDD through a resistor) or pull-down (connection GND through a resistor) is made, if the pull-up or pull-down is done through a resistor with a high value, because the pin comes near to being in high impedance, the consumed (through) current increases. This also depends on the application circuit, but a typical value for a pull-up or pull-down resistor is a few tens of kΩ. 19 µPD17P068 Table 1-1. Handling of Unused Pins (2/2) (b) Pins other than ports Pin Name Input/Output Circuit Type Recommended Handling when in Unused State ADC0 Input Connect to VDD or GND through a resistor. Note BLANK Output Open BLUE Output Open CE Input Connect to VDD through a resistor. Note EO Output Open GREEN Output Open HSYNC Input Connect to VDD or GND through a resistor. Note INT0 Input Connect to VDD or GND through a resistor. Note INTNC Input Connect to VDD or GND through a resistor. Note OSCIN Input Connect to VDD through a resistor. Note OSCOUT Output Open PSC Output Open RED Output Open VCO Input with pull-down resistor Open VSYNC Input Connect to VDD or GND through a resistor. Note Note Be careful of the fact that when an external pull-up (connection to VDD through a resistor) or pull-down (connection GND through a resistor) is made, if the pull-up or pull-down is done through a resistor with a high value, because the pin comes near to being in high impedance, the consumed (through) current increases. This also depends on the application circuit, but a typical value for a pull-up or pull-down resistor is a few tens of kΩ. 20 µPD17P068 1.5 Notes on Using the CE and INTNC Pins (Only in Normal Operation Mode) In addition to the functions shown in 1.1 Normal Operation Mode, the CE pin also has the function of setting a test mode (for IC testing) in which the internal operations of the µ PD17P068 are tested. Also, the INT NC pin has the function of the VPP pin for program memory write/verify. When a voltage higher than VDD is applied to either of these pins, the test or program memory write/verify mode is set. This means that, even during normal operation, the µ PD17P068 may be set in the test mode if noise exceeding VDD is applied. For example, if the wiring length of the CE or INT NC pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. • Connect diode with low V F between V DD and CE/INT NC pin • Connect capacitor between V DD and CE/INTNC pin VDD Diode with low VF VDD VDD CE, INTNC VDD CE, INTNC 21 µPD17P068 2. WRITE, READ, AND VERIFY OF ONE-TIME PROM (PROGRAM MEMORY) The program memory contained in the µ PD17P068 is the 12160 × 16-bit one-time PROM that can electrically be written one time only. This PROM is accessed in 16 bits per word in normal operation mode, and in 8 bits per word in write, read, verify modes. The 16 bits of a word in normal mode are divided into higher 8 bits and lower 8 bits which are assigned to even and odd addresses, respectively. When the PROM is written, read, or verified, set this device into the PROM mode. In this mode, these pins are used as shown in the table below. Notice that no address input pins are provided. Addresses are automatically updated by the clock signal supplied from the CLK pin. Table 2-1. Pins Used in Program Memory Write, Read, and Verify Modes Pin Function VPP Programming voltage (+12.5 V) application CLK Address update clock input MD0-MD3 D0-D7 VDD0, VDD1 Operation mode selection 8-bit data input/output Power supply voltage (+5 V) application To write the internal PROM, use the NEC-specified PROM programming equipment (PROM programmer) and program adapter as listed below. PROM programmer Program adapter Remark AF-9703 (Ando Electric Corporation) AF-9704 (Ando Electric Corporation) AF-9705 (Ando Electric Corporation) AF-9706 (Ando Electric Corporation) AF-9808L (Ando Electric Corporation) For details on these PROM programmer and program adapter, consult with Ando Electric Corporation (03-3733-1151 Tokyo, Japan). 22 µPD17P068 2.1 Operation Modes in Program Memory Write/Read/Verify When +5 V is applied to the V DD pin and +12.5 V is applied to the V PP pin, this device enters the program memory write/read/verify modes. Operation mode is determined by the setting of MD0 to MD 3 pins as indicated in the table below. All input pins irrelevant to the program memory write/read/verify operation should be left unconnected or connected to GND via a pull-down resistor of 470 Ω (Refer to the section "PIN CONFIGURATION (2) PROM programming mode). " Table 2-2. Operation Modes in Program Memory Write/Read/Verify Pin States Operation Mode VPP +12.5 V Remark VDD +5 V MD0 MD1 MD2 MD3 H L H L Program memory address 0 clear L H H H Write L L H H Read, Verify H X H H Program inhibit X: L or H 23 µPD17P068 2.2 PROM Write Procedure Data can be written to the PROM in high speeds by using the following procedures. (1) Set the pins not used for programming as indicated in section "PIN CONFIGURATION (2) PROM programming mode." Set the CLK pin to low level. (2) Supply +5 V to the V DD and V PP pins. (3) Provide a 10- µ s wait state. (4) Program memory address 0 clear mode is entered. (5) Supply +6 V to the V DD pin, and +12.5 V to the V PP pin. (6) Program inhibit mode is entered. (7) Provide write data for 1 ms in write mode. (8) Program inhibit mode is entered. (9) Use the verify mode to test data. If the data has been written, proceed to (10). If not, repeat steps (7) to (9). (10) Provide write data (for additional writing) for 1 ms times the number of repeats performed between steps (7) to (9). (11) Program inhibit mode is entered. (12) Provide four pulses to the CLK pin to increment the address. (13) Repeat steps (7) to (12) until the last address is reached. (14) Program memory address 0 clear mode. (15) Supply +5 V to VDD and V PP pins. (16) Turn off the power for this device. The procedures from (2) to (12) are illustrated in the chart below. Repeat X times Write Additional write Verify Address increment VPP VPP VDD GND VDD + 1 VDD VDD GND CLK Hi-Z D0-D7 MD 0 MD 1 MD 2 MD 3 24 Hi-Z Data input Data output Hi-Z Hi-Z Data input µPD17P068 2.3 PROM Read Procedure Data can be read from the PROM by using the following procedures. (1) Set the pins not used for programming as indicated in section "PIN CONFIGURATION (2) PROM programming mode." Set the CLK pin to low level. (2) Supply +5 V to the V DD and V PP pins. (3) Provide a 10- µ s wait state. (4) Program memory address 0 clear mode is entered. (5) Supply +6 V to the V DD pin, and +12.5 V to the VPP pin. (6) Program inhibit mode is entered. (7) Use the verify mode to output data. Provide clock pulses to the CLK pin to output the data of an address. The address is automatically incremented every four clock pulses. Repeat the four-pulse cycles until the last address is reached. (8) Program inhibit mode is entered. (9) Program memory address 0 clear mode. (10) Supply +5 V to the V DD and V PP pins. (11) Turn off the power for this device. The procedures from (2) to (9) are illustrated in the chart below. VPP VPP VDD GND VDD +1 VDD VDD GND CLK Hi-Z Hi-Z Data output D0-D7 Data output MD 0 MD 1 "L" MD 2 MD 3 25 µPD17P068 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 ˚C) Parameter Symbol Conditions Supply voltage VDD Input voltage VI Output voltage VO Except for P1A, P2B, P2C High-level output current IOH Low-level output current IOL1 IOL2 Output withstand voltage VBDS Storage temperature Tstg Ratings Unit −0.3 to +6.0 V −0.3 to VDD + 0.3 V −0.3 to VDD + 0.3 V 1 pin −12 mA All pins −20 mA 1 pin (except for P1A) 12 mA All pins (except for P1A) 20 mA 1 pin (P1A only) 17 mA All pins (P1A only) 60 mA P1A, P2A, P2B, P2C 13 V −55 to +125 ˚C Caution Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (T A = 25 ˚C) Parameter Supply voltage Symbol Conditions VDD1 VDD2 Only CPU operates MIN. TYP. MAX. Unit 4.5 5.0 5.5 V 4.0 5.0 5.5 V 5.0 VDD3 Only watchdog timer operates (CPU stops) 2.3 Data retention voltage VDDR Clock stops 2.3 Output withstand voltage VBDS P1A, P2A, P2B, P2C Supply voltage rise time trise VDD = 0 → 4.5 V Input amplitude VIN VCO 26 5.5 V 5.5 V 12.5 V 3 500 ms 0.7 5.5 VP−P µPD17P068 DC Characteristics (Reference characteristics: T A = −40 to +85 ˚C, V Parameter Supply current Symbol IDD1 DD Conditions = 5 V ± 10 %) MIN. Operation of all functions TYP. MAX. Unit 11 23 mA 7 12 mA 6.5 9 mA 2.5 4.5 mA 5 10 µA 15 25 µA 2 15 µA VDD = 5 V, TA = 25 ˚C, f VCO = 20 MHz VIN = 0.7 VP-P, IDC operation OSCIN = 10 MHz, XIN pin square wave input (fIN = 8 MHz, VIN = VDD) IDD2 CPU and PLL operation VDD = 5 V, TA = 25 ˚C, f VCO = 20 MHz VIN = 0.7 VP-P, XIN pin square wave input (fIN = 8 MHz, VIN = VDD) IDD3 Only CPU operates VDD = 5 V, TA = 25 ˚C, X IN pin square wave input (fIN = 8 MHz, VIN = VDD) IDD4 HALT instruction VDD = 5 V, TA = 25 ˚C, X IN pin square wave input (fIN = 8 MHz, VIN = VDD) Data retention current IDDR1 Main clock stop, watch timer operation VDD = 2.5 V, TA = 25 ˚C Main clock stop, watch timer operation VDD = 5 V, TA = 25 ˚C IDDR2 Main clock stop, watch timer operation VDD = 5 V, TA = 25 ˚C High-level input voltage Low-level input voltage High-level output current VIH1 P0A, P0B, P1B, P1C, P2D 0.7VDD V VIH2 CE, INT0, INTNC, VSYNC, HSYNC 0.8VDD V VIH3 P0D 0.7VDD V VIL1 P0A, P0B, P0D, P1B, P1C, P2D 0.2 VDD VIL2 CE, INT0, INTNC, VSYNC, HSYNC 0.2 VDD IOH1 P0A2, P0A3, P0B, P0C, P1B, P1C, P1D, P2D, V V −1 −5 mA −1 −2.5 mA 1 10 mA BLANK, RED, GREEN, BLUE, PSC VOH = VDD − 1 V Low-level output current VOH = VDD − 1 V IOH2 EO IOL1 P0A2, P0A3, P0B, P0C, P1B, P1C, P1D, P2D, PSC VOL = 1 V IOL11 BLANK, RED, GREEN, BLUE VOL = 1 V 1 8.5 mA IOL2 EO VOL = 1 V 1 6 mA IOL3 P0A0, P0A1 VOL = 1 V 1 4.0 mA IOL4 PWM (P2A, P2B, P2C) VOL = 1 V 1 1.5 mA IOL5 P1A VOL = 1 V 15 30 mA High-level input current IIH VCO VIH = VDD 0.1 0.65 High-level output leakage ILOH P1A, P2A, P2B, P2C Output off leakage current IL EO Internal pull-down resistor 1.3 mA 0.5 µA ±10−3 ±1 µA VO = 12.5 V VO = VDD or 0 V RPD1 P0D (KEY) VIH = VDD 19 41 85 kΩ RPD2 P0D (KEY) VIH = VDD = 5 V 23 41 72 kΩ RPD3 P0D (KEY) VIH = VDD = 5 V, TA = 25 ˚C 29 41 47 kΩ 27 µPD17P068 AC Characteristics (Reference characteristics: T A = −40 to +85 ˚C, V Parameter Input frequency 1 Symbol DD Conditions fVCO VCO square wave input Input frequency 2 fTMR TMIN (P1B3) Input frequency 3 fHS HSCNT (P0B3) = 5 V ± 10 %) MAX. Unit VIN = 0.7 VP−P MIN. 0.7 20 MHz Duty 50 % 45 65 Hz 10 20 kHz A/D Converter Characteristics (Reference characteristics: TA = −10 to +50 ˚C, V Parameter Symbol Conditions A/D conversion absolute accuracy ADC0-ADC7 A/D conversion resolution ADC0-ADC7 A/D input impedance ADC0-ADC7 Parameter Low-level input voltage Symbol Except for CLK VIH2 CLK = 5 V ± 10 %) TYP. MAX. Unit ±1 ±1.5 LSB 1 DD bit MΩ = 6.0 ± 0.25 V, V PP = 12.5 ± 0.5 V) Conditions VIH1 DD 6 DC Programming Characteristics (TA = 25 ˚C, V High-level input voltage MIN. TYP. MAX. Unit 0.7 VDD MIN. TYP. VDD V VDD − 0.5 VDD V V VIL1 Except for CLK 0 0.3 VDD VIL2 CLK 0 0.4 V Input leakage current ILI VIN = VIL or VIH ±10 µA High-level output voltage VOH IOH = −1 mA Low-level output voltage VOL IOL = 1 mA 1.0 V VDD supply current IDD 30 mA VPP supply current IPP 30 mA MD0 = VIL, MD1 = VIH Cautions 1. VPP must not exceed +13.5 V including overshoot. 2. VDD should be applied before VPP and cut after VPP. 28 VDD − 1.0 V µPD17P068 AC Programming Characteristics (TA = 25 ˚C, V DD = 6.0 ± 2.5 V, V PP = 12.5 ± 0.5 V) Parameter Address setup time Note (vs. MD0↓) tAS Symbol Conditions MIN. 2 TYP. MAX. µs MD1 setup time (vs. MD0↓) tM1S 2 µs Data setup time (vs. MD0↓) tDS 2 µs Address hold time Note (vs. MD0↑) tAH 2 µs Data hold time (vs. MD0↑) tDH 2 µs MD0↑→ data output float delay time tDF 0 VPP setup time (vs. MD3↑) tVPS 2 µs VDD setup time (vs. MD3↑) tVDS 2 µs Initial program pulse width tPW 0.95 Additional program pulse width tOPW 0.95 MD0 setup time (vs. MD1↑) tM0S 2 130 1.0 Unit ns 1.05 ms 21.0 ms µs µs MD0↓→ data output delay time tDV MD0 = MD1 = VIL MD1 hold time (vs. MD0↑) tM1H tM1H + tM1R ≥ 50 µs MD1 recovery time (vs. MD0↓) tM1R Program counter reset time tPCR CLK input high-/low-level width tXH, tXL CLK input frequency fX Initial mode setting time tI 2 µs MD3 setup time (vs. MD1↑) tM3S 2 µs MD3 hold time (vs. MD1↓) tM3H 2 µs MD3 setup time (vs. MD0↓) tM3SR 2 µs Address Note → 1 2 µs 2 µs 10 µs µs 0.125 4.19 When program memory is read data output delay time Address Note → data output hold time tHAD tDAD 0 2 MD3 hold time (vs. MD0↑) tM3HR 2 MD3↓→ data output float delay time tDFR 130 MHz µs ns µs 2 µs Note The internal address increment (+1) is performed on the fall of the 3rd clock, where 4 clocks comprise one cycle. The internal clock is not connected to a pin. 29 µPD17P068 Program Memory Write Timing VPP tVPS VPP VDD tVDS GND VDD + 1 VDD VDD GND tXH CLK D0-D7 Hi-Z Hi-Z Data input tDS tI tDH Hi-Z Data output tDV tDF tXL Hi-Z Data input tDH tAH tDS Hi-Z Data input tAS MD0 tPW tM0S tM1R tOPW MD1 tPCR tM1S tM1H MD2 tM3H tM3S MD3 Program Memory Read Timing tVPS VPP VPP VDD tVDS GND VDD + 1 VDD VDD tXH GND CLK tDAD tHAD tXL Hi-Z Data output D0-D7 tDV tI MD0 MD1 "L" tPCR MD2 tM3SR MD3 30 Hi-Z Data output tM3HR tDFR µPD17P068 4. PACKAGE DRAWING 100 PIN PLASTIC QFP (14 20) A B 51 50 80 81 detail of lead end C D S Q R 31 30 100 1 F G H I J M P K M N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS INCHES A 23.2±0.2 0.913 +0.009 –0.008 B 20.0±0.2 0.787 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.2 0.677±0.008 F 0.8 0.031 G 0.6 0.024 H 0.30±0.10 0.012 +0.004 –0.005 I 0.15 0.006 J 0.65 (T.P.) 0.026 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P Q 2.7 0.106 R 0.125±0.075 5°±5° 0.005±0.003 5°±5° S 3.0 MAX. 0.119 MAX. S100GF-65-3BA-3 31 µPD17P068 APPENDIX DEVELOPMENT TOOLS The following tools are available to provide µ PD17P068’s program development environment. Hardware Product In-circuit emulator Description The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators common to the 17K series. The IE-17K and IE-17K-ET should be connected with the host computer (PC-9800 series or IBM PC/ATTM ) through an RS-232-C cable. The IE-17K EMU-17K should be installed to an extension slot in the host computer IE-17K-ET Note 1 (PC-9800 series). EMU-17K Note 2 SE board (SE-17008) Emulation probe Each of the three products function as a dedicated emulator for each device by connecting it with an individual system evaluation board (SE board). Using SIMPLEHOST which features an excellent user-machine interface, makes user’s debugging environment more powerful. If the EMU17K is used, user can monitor the contents of the data memory in real time. This SE board is for the µPD17068, 17P068, and 17008. This board can perform evaluations of user’s system. To debug user’s programs, use it together with an in-circuit emulator. This probe is used when emulating the µPD17P068GF. (EP-17068GF) Conversion socket This socket converts pin arrangement for the 100-pin plastic QFP (14 × 20 mm) to connect the emulation probe EP-17068GF to the target system. (EV-9200GF-100 Note 3 ) PROM programmer AF-9703 Note 4 These products write programs to the internal PROM of the µPD17P068. To perform programming, the program adapter AF-9808L is required to connect to the PROM programmer. AF-9704 Note 4 AF-9705 Note 4 AF-9706 Note 4 Program adapter This adapter is used together with the PROM programmer to program the PROM in the µPD17P068. (AF-9808L Note 4 ) Notes 1. Inexpensive type: Power supply is required to connect externally. 2. Manufactured by IC Corporation. For details, call 03-3447-3793 Tokyo, Japan. 3. If the EP-17068GF is purchased, one EV-9200GF-100 is attached as a companion product. EV-9200GF100s can separately be purchased in 5-piece units. 4. Manufactured by Ando Electric Corporation. For details, call 03-3733-1151 Tokyo, Japan. 32 µPD17P068 Software Product Host Computer Description OS This assembler can be used for all 17K series devices. 17K series assembler (AS17K) PC-9800 Series MS-DOSTM To develop program of the µPD17P068, the device file (AS17068) are also required. IBM PC/AT DOSTM PC This product is the device file for the µPD17P068. PC-9800 series MS-DOS IBM PC/AT PC DOS This device file is used Device file (AS17068) together with the assembler Media Ordering Code 5 inch 2HD µS5A10AS17K 3.5 inch 2HD µS5A13AS17K 5 inch 2HC µS7B10AS17K 3.5 inch 2HC µS7B13AS17K 5 inch 2HD µS5A10AS17068 3.5 inch 2HD µS5A13AS17068 5 inch 2HC AS17K. This software is used to µS7B10AS17068 3.5 inch 2HC µS7B13AS17068 5 inch 2HD µS5A10lE17K 3.5 inch 2HD µS5A13lE17K 5 inch 2HC µS7B10lE17K 3.5 inch 2HC µS7B13lE17K develop programs using an in-circuit emulator and the Support software (SIMPLEHOST) PC-9800 Series MS-DOS host computer. This product runs under Windows WindowsTM system and provides users with an excellent IBM PC/AT user-machine interface. PC DOS Remark These products run with the versions of the operation systems shown below. OS Version MS-DOS Ver.3.30 to Ver.5.00A Note PC DOS Ver.3.1 to Ver.5.0 Note Windows Ver.3.0 to Ver.3.1 Note With these products, the task swap function is disabled though the Ver.5.00/5.00A of MS-DOS and Ver.5.0 of the PC DOS support the task swap function. 33 µPD17P068 [MEMO] 34 µPD17P068 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 35 µPD17P068 Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SIMPLEHOST is a registered trademark of NEC Corp. MS-DOS and Windows are trademarks of Microsoft Corp. PC/AT and PC DOS are trademarks of IBM Corp. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 36