DATA SHEET MOS INTEGRATED CIRCUIT µPD6P4B 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION DESCRIPTION The µPD6P4B is a microcontroller for infrared remote control transmitters which is provided with a one-time PROM as the program memory. Because users can write programs for the µPD6P4B, it is ideal for program evaluation and small-scale production of the application systems using the µPD62, 63, 63A, or 64. When reading this document, also refer to the µPD62 Data Sheet (U14208E) and the µPD63, 63A, 64 Data Sheet (U11371E). FEATURES • Program memory (one-time PROM) : 1002 × 10 bits • Data memory (RAM) : 32 × 4 bits • Built-in carrier generation circuit for infrared remote control • 9-bit programmable timer : 1 channel • Command execution time : 16 µs (when operating at fX = 4 MHz: ceramic oscillation) • Stack level : 1 level (Stack RAM is for data memory RF as well.) • I/O pins (KI/O) : 8 units • Input pins (KI) : 4 units • Sense input pin (S0) : 1 unit • S1/LED pin (I/O) : 1 unit (In output mode, this is the remote control transmission display • Power supply voltage : VDD = 2.2 to 3.6 V (at fX = 4 MHz) • Operating ambient temperature : TA = –40 to +85 °C • Oscillator frequency : fX = 2.4 to 8 MHz pin.) VDD = 2.7 to 3.6 V (at fX = 8 MHz) • POC circuit APPLICATION Infrared remote control transmitter (for AV and household electric appliances) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13594EJ2V0DS00 (2nd edition) Date Published May 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1998,1999 µPD6P4B ORDERING INFORMATION Part Number Package µPD6P4BGS 20-pin plastic SOP (300 mil) µPD6P4BMC-5A4 20-pin plastic SSOP (300 mil) PIN CONFIGURATION (TOP VIEW) 20-pin Plastic SOP (300 mil) • µPD6P4BGS 20-pin Plastic SSOP (300 mil) • µPD6P4BMC-5A4 (1) Normal operating mode KI/O6 1 20 KI/O5 KI/O7 2 19 KI/O4 S0 3 18 KI/O3 S1/LED 4 17 KI/O2 REM 5 16 KI/O1 VDD 6 15 KI/O0 XOUT 7 14 KI3 XIN 8 13 KI2 GND 9 12 KI1 10 11 KI0 RESET 2 Data Sheet U13594EJ2V0DS00 µPD6P4B (2) PROM programming mode D6 1 20 D5 D7 2 19 D4 CLK 3 18 D3 4 17 D2 5 16 D1 VDD 6 15 D0 XOUT 7 14 MD3 XIN 8 13 MD2 GND 9 12 MD1 10 11 MD0 (L) VPP Caution Round brackets ( ) indicate the pins not used in the PROM programming mode. L : Connect each of these pins to GND via a pull-down resistor. BLOCK DIAGRAM REM S1/LED CARRIER GENERATOR CPU CORE 9-bit TIMER ONETIME PROM 4 PORT KI 4 KI0-KI3 8 PORT KI/O 8 KI/O0-KI/O7 2 PORT S 2 S0, S1/LED RAM RESET SYSTEM CONTROL XIN XOUT VDD GND Data Sheet U13594EJ2V0DS00 3 µPD6P4B LIST OF FUNCTIONS µPD6P4B Item ROM capacity 1002 × 10 bits One-time PROM RAM capacity 32 × 4 bits Stack 1 level (shared with RF of RAM) I/O pin Number of keys Key input (KI) : 4 pins Key I/O (KI/O) : 8 pins Key expansion input (S0, S1) : 2 pins Remote control transmitter display output (LED) : 1 pin (shared with S1 pin) 32 keys 48 keys (when expanded by key expansion input) 96 keys (when expanded by key expansion input and diode) Clock frequency Ceramic oscillation fX = 2.4 to 4 MHz fX = 4 to 8 MHzNote Instruction execution time 16 µs (at fX = 4 MHz) Carrier frequency fX/8, fX/16, fX/64, fX/96, fX/128, f X/192, no carrier (high level) Timer 9-bit programmable timer POC circuit Provided Supply voltage VDD = 2.2 to 3.6 V (fX = 2.4 to 4 MHz), VDD = 2.7 to 3.6 V (fX = 4 to 8 MHz) Operating ambient • T A = –40 to +85 °C temperature • T A = –20 to +70 °C (when using POC circuit) Package • 20-pin plastic SOP (300 mil) : 1 channel • 20-pin plastic SSOP (300 mil) Note It is necessary to design the application circuit so that the RESET pin goes low at a supply voltage of less than 2.7 V. 4 Data Sheet U13594EJ2V0DS00 µPD6P4B TABLE OF CONTENTS 1. PIN FUNCTIONS ......................................................................................................................... 6 1.1 Normal Operating Mode .................................................................................................................... 6 1.2 PROM Programming Mode ............................................................................................................... 7 1.3 INPUT/OUTPUT Circuits of Pins ...................................................................................................... 8 1.4 Dealing with Unused Pins ................................................................................................................ 9 1.5 Notes on Using KI Pin at Reset ........................................................................................................ 9 2. DIFFERENCES AMONG µPD62, 63, 63A, 64, AND µPD6P4B ................................................. 10 2.1 Program Memory (One-time PROM) ................................................................................................ 11 3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) .................................. 12 3.1 Operating Mode When Writing/Verifying Program Memory .......................................................... 12 3.2 Program Memory Writing Procedure .............................................................................................. 13 3.3 Program Memory Reading Procedure ............................................................................................. 14 4. ELECTRICAL SPECIFICATIONS ............................................................................................... 15 5. CHARACTERISTIC CURVE (REFERENCE VALUES) .............................................................. 21 6. APPLIED CIRCUIT EXAMPLE ................................................................................................... 23 7. PACKAGE DRAWINGS .............................................................................................................. 24 8. RECOMMENDED SOLDERING CONDITIONS .......................................................................... 26 APPENDIX A. DEVELOPMENT TOOLS ........................................................................................ 27 APPENDIX B. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT .......................... 28 Data Sheet U13594EJ2V0DS00 5 µPD6P4B 1. PIN FUNCTIONS 1.1 Normal Operating Mode Pin No. Symbol Function 1 2 15-20 KI/O0-KI/O7 These pins refer to the 8-bit I/O ports. I/O switching can be made in 8-bit units. In INPUT mode, a pull-down resistor is added. In OUTPUT mode, they can be used as the key scan output of the key matrix. 3 S0 Refers to the input port. Can also be used as the key return input of the key matrix. In INPUT mode, the availability of the pull-down resistor of the S 0 and S 1 ports can be specified by software in Output Format CMOS push-pullNote 1 — When Reset High-level output High-impedance (OFF mode) terms in 2-bit units. If INPUT mode is canceled by software, this pin is placed in OFF mode and enters the high-impedance state. 4 S1/LED Refers to the I/O port. In INPUT mode (S1), this pin can also be used as the key return input of the key matrix. The availability of the pull-down resistor of the S0 and S1 ports can be specified by software in 2-bit units. In OUTPUT mode (LED), it becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs the low level from the LED output synchronously with the REM signal. CMOS push-pull High-level output (LED) 5 REM Refers to the infrared remote control transmission output. The output is active high. Carrier frequency: fX/8, fX/64, fX/96, high-level, fX/16, fX/128, fX/192 (usable on software) CMOS push-pull Low-level output 6 VDD Refers to the power supply. — — 7 8 XOUT X IN These pins are connected to system clock ceramic resonators. — Low level (oscillation stopped) 9 GND — — 10 RESET Refers to the ground. Normally, this pin is a system reset input. By inputting a low level, the CPU can be reset. When resetting with the POC circuit a low level is output. A pull-up resistor is incorporated. — — 11-14 KI0-KI3Note 2 These pins refer to the 4-bit input ports. They can be used as the key return input of the key matrix. The use of the pull-down resistor can be specified by software in 4-bit units. — Input (low-level) Notes 1. Be careful about this because the drive capability of the low-level output side is held low. 2. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when RESET pin changes from low level to high level, or POC is released due to supply voltage startup). 6 Data Sheet U13594EJ2V0DS00 µPD6P4B 1.2 PROM Programming Mode Pin No. 1, 2 Symbol Function I/O D0-D 7 8-bit data input/output when writing/verifying program memory I/O CLK Clock input for updating address when writing/verifying program Input 15-20 3 memory 6 VDD Power Supply. – Supply +6 V to this pin when writing/verifying program memory. 7 XOUT Clock necessary for writing program memory. Connect 4 MHz ceramic – 8 XIN resonator to these pins. 9 GND GND – 10 VPP Supplies voltage for writing/verifying program memory. – Input Apply +12.5 V to this pin. 11-14 MD0-MD 3 Input for selecting operation mode when writing/verifying program memory. Input Data Sheet U13594EJ2V0DS00 7 µPD6P4B 1.3 INPUT/OUTPUT Circuits of Pins The input/output circuits of the µPD6P4B pins are shown in partially simplified forms below. (1) K I/O0-K I/O7 (4) S 0 VDD Input buffer Output latch data P-ch OFF mode N-chNote Selector output disable standby release Input buffer N-ch pull-down flag N-ch (5) S1/LED VDD Note The drive capability is held low. REM output latch (2) K I0-K I3 standby release P-ch output disable standby release Input buffer N-ch Input buffer pull-down flag N-ch N-ch pull-down flag (3) REM (6) RESET VDD VDD P-ch P-ch data Output latch N-ch Carrier generator Input buffer Internal reset signal other than POC N-ch POC circuit 8 Data Sheet U13594EJ2V0DS00 µPD6P4B 1.4 Dealing with Unused Pins The following connections are recommended for unused pins in the normal operation mode. Table 1-1. Connections for Unused Pins Connection Pin Inside the microcontroller KI/O INPUT mode OUTPUT mode — High-level output REM — S1/LED OUTPUT mode (LED) setting S0 OFF mode setting KI RESETNote Outside the microcontroller Open Directly connected to GND — Built-in POC circuit Open Note If the circuit is an applied one requiring high reliability, be sure to design it in such a manner that the RESET signal is entered externally. Caution The I/O mode and the terminal output level are recommended to be fixed by setting them repeatedly in each loop of the program. 1.5 Notes on Using K I Pin at Reset In order to prevent malfunction, be sure to input a low level to more than one of pins K I0 to KI3 when reset is released (when RESET pin changes from low level to high level, or POC is released due to supply voltage startup). Data Sheet U13594EJ2V0DS00 9 µPD6P4B 2. DIFFERENCES AMONG µPD62, 63, 63A, 64, AND µPD6P4B Table 2-1 shows the differences among the µPD62, 63, 63A, 64, and µPD6P4B. The only differences among these models are the program memory, supply voltage, system clock frequency, oscillation stabilization wait time, and POC circuit (mask option), and the CPU function and internal peripheral hardware are the same. The electrical characteristics also differ slightly. For the electrical characteristics, refer to the Data Sheet of each model. Table 2-1. Differences among µPD62, 63, 63A, 64, and µPD6P4B (1) When POC circuit (mask option) is provided to µ PD62, 63, 63A, and 64 Item ROM µPD6P4B One-time PROM µPD62, 63 µPD63A µPD64 Mask ROM 1002 × 10 bits 512 × 10 bits 768 × 10 bits 1002 × 10 bits (000H to 3E9H) (000H to 1FFH) (000H to 2FFH) (000H to 3E9H) 286/fX 52/fX 478/fX to 926/fX 246/fX to 694/fX VPP pin and operating mode select pin Provided Not provided Electrical specifications Some electrical specifications, such as data retention voltage and current Oscillation stabilization wait time • On releasing STOP mode by release condition • On releasing STOP or HALT mode by RESET input and at reset consumption, differ. For details, refer to Data Sheet of each model. (2) When POC circuit (mask option) is not provided to µ PD62, 63, 63A, and 64 Item ROM µPD6P4B µPD62, 63 µPD63A µPD64 One-time PROM Mask ROM 1002 × 10 bits 512 × 10 bits 768 × 10 bits 1002 × 10 bits (000H to 3E9) (000H to 1FFH) (000H to 2FFH) (000H to 3E9H) 286/fX 52/f X 478/fX to 926/fX 246/f X to 694/fX VPP pin and operating mode select pin Provided Not provided POC circuit Incorporated Not provided Supply voltage VDD = 2.2 to 3.6 V V DD = 1.8 to 3.6 V (TA = –40 to +85 °C) Oscillation stabilization wait time • On releasing STOP mode by release condition • On releasing STOP or HALT mode by RESET input and at reset (TA = –40 to +85 °C) System clock frequency • fX = 2.4 to 4 MHz • fX = 2.4 to 4 MHz • fX = 4 to 8 MHzNote Electrical specifications • fX = 2.4 to 8 MHz (V DD = 2.2 to 3.6 V) Some electrical specifications, such as data retention voltage and current consumption, differ. For details, refer to Data Sheet of each model. Note It is necessary to design the application circuit so that the RESET pin goes low when the supply voltage is less than 2.7 V. 10 Data Sheet U13594EJ2V0DS00 µPD6P4B 2.1 Program Memory (One-time PROM) ... 1002 steps × 10 bits This one-time PROM is configured with 10 bits per step and is addressed by the program counter. The program memory stores programs and table data. The 22 steps from addresses 3EAH through 3FFH constitute a test program area and must not be used. Figure 2-1. Program Memory Map 10 bits 000H 3E9H 3EAH 3FFH Test program areaNote Note Even if execution jumps to the test program area by mistake, it returns to address 000H. Data Sheet U13594EJ2V0DS00 11 µPD6P4B 3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) The program memory of the µPD6P4B is a one-time PROM of 1002 × 10 bits. To write or verify this program memory, the pins shown in Table 3-1 are used. Note that no address input pin is used. Instead, the address is updated by using the clock input from the CLK pin. Table 3-1. Pins Used to Write/Verify Program Memory Pin Name Function VPP Supplies voltage when writing/verifying program memory. Apply +12.5 V to this pin. VDD Power supply. Supply +6 V to this pin when writing/verifying program memory. CLK Inputs clock to update address when writing/verifying program memory. By inputting pulse four times to CLK pin, address of program memory is updated. MD0-MD 3 Input to select operation mode when writing/verifying program memory. D0-D 7 Inputs/outputs 8-bit data when writing/verifying program memory. XIN, X OUT Clock necessary for writing program memory. Connect 4 MHz ceramic resonator to this pin. 3.1 Operating Mode When Writing/Verifying Program Memory The µPD6P4B is set in the program memory write/verify mode when +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin after the µPD6P4B has been in the reset status (VDD = 5 V, VPP = 0 V) for a specific time. In this mode, the operating modes shown in Table 3-2 can be set by setting the MD0 through MD3 pins. Connect all the pins other than those shown in Table 3-1 to GND via pull-down resistor. Table 3-2. Setting Operation Mode Setting of Operating Mode VPP +12.5 V VDD +6 V Operation Mode MD0 MD1 MD2 MD3 H L H L Clear program address to 0 L H H H Write mode L L H H Verify mode H × H H Program inhibit mode ×: don’t care (L or H) 12 Data Sheet U13594EJ2V0DS00 µPD6P4B 3.2 Program Memory Writing Procedure The program memory is written at high speed in the following procedure. (1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the V DD pin. Keep the V PP pin low. (3) Supply 5 V to the V PP pin after waiting for 10 µ s. (4) Wait for 2 ms until oscillation of the ceramic resonator connected across the X IN and X OUT pins stabilizes. (5) Set the program memory address 0 clear mode by using the mode setting pins. (6) Supply 6 V to V DD and 12.5 V to V PP. (7) Set the program inhibit mode. (8) Write data to the program memory in the 1-ms write mode. (9) Set the program inhibit mode. (10) Set the verify mode. If the data have been written to the program memory, proceed to (11). If not, repeat steps (8) through (10). (11) Additional writing of (number of times of writing in (8) through (10): X) × 1 ms. (12) Set the program inhibit mode. (13) Input a pulse to the CLK pin four times to update the program memory address (+1). (14) Repeat steps (8) through (13) up to the last address. (15) Set the 0 clear mode of the program memory address. (16) Change the voltages on the V DD and V PP pins to 5 V. (17) Turn off power. The following figure illustrates steps (2) through (13) above. Repeated X time Oscillation stabilization wait time Reset Write Verify Additional write Address increment VPP VPP VDD VDD VDD+1 VDD GND GND CLK D0-D7 Hi-Z Data input Hi-Z Data output Hi-Z Data input Hi-Z MD0 MD1 MD2 MD3 Data Sheet U13594EJ2V0DS00 13 µPD6P4B 3.3 Program Memory Reading Procedure (1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the V DD pin. Keep the V PP pin low. (3) Supply 5 V to the V PP pin after waiting for 10 µ s. (4) Wait for 2 ms until oscillation of the ceramic resonator connected across the X IN and X OUT pins stabilizes. (5) Set the program memory address 0 clear mode by using the mode setting pins. (6) Supply 6 V to V DD and 12.5 V to V PP. (7) Set the program inhibit mode. (8) Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to the CLK pin four times. (9) Set the program inhibit mode. (10) Set the program memory address 0 clear mode. (11) Change the voltage on the V DD and V PP pins to 5 V. (12) Turn off power. The following figure illustrates steps (2) through (10) above. Reset VPP Oscillation stabilization wait time VPP VDD GND VDD VDD+1 VDD GND CLK D0-D7 Hi-Z Data output Data output MD0 MD1 "L" MD2 MD3 14 Data Sheet U13594EJ2V0DS00 Hi-Z µPD6P4B 4. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = +25 °C) Parameter Symbol Power supply voltage Test Conditions Rating Unit –0.3 to +7.0 V –0.3 to +13.5 V –0.3 to V DD + 0.3 V VDD VPP Input voltage VI Output voltage High-level output current KI/O, K I, S0, S1, RESET VO IOHNote REM –0.3 to V DD + 0.3 V –30 mA rms –20 mA Peak value –7.5 mA Peak value LED rms One KI/O pin Peak value rms Total of LED and KI/O pins Low-level output current IOL Note REM mA mA –9 mA Peak value –18 mA rms –12 mA Peak value 7.5 mA rms LED –5 –13.5 Peak value rms 5 mA 7.5 mA 5 mA Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note Work out the rms with: [rms] = [Peak value] × Duty. Caution Product quality may suffer if the absolute rating is exceeded for any parameter, even momentarily. In other words, an absolute maxumum rating is a value at which the possibility of psysical damage to the product cannnot be ruled out. Care must therefore be taken to ensure that the these ratings are not exceeded during use of the product. Recommended Power Supply Voltage Range (TA = –40 to +85 °C) Parameter Power supply voltage Symbol VDD Test Conditions fX = 2.4 to 4 MHz fX = 4 to 8 MHzNote MIN. TYP. MAX. Unit 2.2 3.0 3.6 V 2.7 3.0 3.6 V Note It is necessary to design the application circuit so that the RESET pin goes low when the supply voltage is less than 2.7 V. Data Sheet U13594EJ2V0DS00 15 µPD6P4B DC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Parameter High-level input voltage Low-level input voltage Symbol MAX. Unit VIH1 RESET Test Conditions 0.8 VDD MIN. TYP. VDD V VIH2 KI/O 0.65 VDD VDD V VIH3 K I , S 0 , S1 0.65 VDD VDD V VIL1 RESET 0 0.2 VDD V VIL2 KI/O 0 0.3 VDD V VIL3 K I , S 0 , S1 0 0.15 VDD V ILH1 KI VI = VDD, pull-down resistor not incorporated 3 µA ILH2 S 0, S 1 VI = VDD, pull-down resistor not incorporated 3 µA Low-level input leakage IUL1 KI VI = 0 V –3 µA current IUL2 KI/O VI = 0 V –3 µA IUL3 S 0, S 1 VI = 0 V –3 µA High-level output voltage VOH1 REM, LED, KI/O IOH = –0.3 mA Low-level output voltage VOL1 REM, LED IOL = 0.3 mA High-level input leakage current 0.8 VDD V 0.3 V VOL2 KI/O IOL = 15 µA High-level output current IOH1 REM VDD = 3.0 V, VOH = 1.0 V –5 –9 mA IOH2 KI/O VDD = 3.0 V, VOH = 2.2 V –2.5 –5 mA Low-level output current IOL1 KI/O VDD = 3.0 V, VOL = 0.4 V 30 70 µA VDD = 3.0 V, VOL = 2.2 V 100 220 Built-in pull-up resistor R1 RESET 25 50 Built-in pull-down resistor 0.4 V µA 100 kΩ R2 RESET 2.5 5 15 kΩ R3 K I , S 0 , S1 75 150 300 kΩ 250 500 kΩ 3.6 V R4 KI/O 130 Data hold power supply voltage VDDOR In STOP mode 1.2 Supply currentNote IDD1 Operating fX = 8 MHz, VDD = 3 V ± 10 % 1.4 2.8 mA mode fX = 4 MHz, VDD = 3 V ± 10 % 1.1 2.2 mA IDD2 IDD3 HALT mode STOP mode fX = 8 MHz, VDD = 3 V ± 10 % 1.3 2.6 mA fX = 4 MHz, VDD = 3 V ± 10 % 1.0 2.0 mA VDD = 3 V ± 10 % 1.0 8.0 µA VDD = 3 V ± 10 %, TA = 25 ˚C 1.0 2.0 µA Note The POC circuit current and the current flowing in the built-in pull-up resistor are not included. 16 Data Sheet U13594EJ2V0DS00 µPD6P4B AC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Parameter Symbol Test Conditions MIN. Instruction execution time t CY VDD = 2.7 to 3.6 V KI, S0, S1 high-level width Note 1 RESET low-level width TYP. Unit 27 µs 7.9 27 µs 10 µs HALT mode 10 µs STOP mode Note 2 µs 10 µs tH When canceling Standby mode MAX. 15.9 tRSL Notes 1. When using at fX = 4 MHz or higher, it is necessary to design the application circuit so that the RESET pin goes low when the supply voltage is less than 2.7 V. 2. 10 + 286/fX + oscillation growth time Remark tCY = 64/fX (fX: System clock oscillator frequency) POC CircuitNote 1 (TA = –20 to +70 °C) Parameter Symbol POC-detected voltageNote 2 VPOC POC circuit current IPOC Test Conditions MIN. TYP. MAX. Unit 1.8 2.0 2.2 V 1.2 1.5 µA Notes 1. Operates effectively under the conditions of fX = 2.4 to 4 MHz. 2. Refers to the voltage with which the POC circuit cancels an internal reset. If VPOC < VDD , the internal reset is canceled. From the time of VPOC ≥ VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the period of VPOC ≥ VDD lasts less than 1 ms, the internal reset may not take effect. System Clock Oscillator Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Parameter Oscillator frequency Symbol Test Conditions fX (ceramic resonator) Note MIN. TYP. MAX. Unit 2.4 3.64 4.0 MHz 2.4 3.64 8.0 MHz Note When using at fX = 4 MHz or higher, it is necessary to design the application circuit so that the RESET pin goes low when the supply voltage is less than 2.7 V. An external circuit example XIN XOUT Rd C1 C2 Data Sheet U13594EJ2V0DS00 17 µPD6P4B PROM Programming Mode DC Programming Characteristics (TA = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter High-level input voltage Symbol Test Conditions MIN. MAX. Unit VDD V VDD–0.5 VDD V 0 0.3 VDD V 0 0.4 V 10 µA VIH1 Other than CLK 0.7 VDD VIH2 CLK VIL1 Other than CLK VIL2 CLK ILI VIN = V IL or V IH High-level output voltage VOH IOH = –1 mA Low-level output voltage VOL IOL = 1.6 mA Low-level input voltage Input leakage current VDD supply current IDD VPP supply current IPP VDD–1.0 MD0 = V IL, MD1 = V IH Cautions 1. Keep VPP to within +13.5 V including overshoot. 2. Apply VDD before VPP and turns it off after VPP. 18 Data Sheet U13594EJ2V0DS00 TYP. V 0.4 V 30 mA 30 mA µPD6P4B AC Programming Characteristics (TA = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V) Symbol Note1 Address setup timeNote 2 (vs. MD0↓) Parameter tAS tAS Test Conditions MIN. 2 TYP. MAX. Unit µs MD1 setup time (vs. MD 0↓) tM1S tOES 2 µs Data setup time (vs. MD0↓) tDS tDS 2 µs tAH tAH 2 µs Data hold time (vs. MD0↑) tDH tDH 2 µs MD0↑→ data output float delay time tDF tDF 0 VPP setup time (vs. MD 3↑) tVPS tVPS 2 VDD setup time (vs. MD 3↑) tVDS tVCS 2 Initial program pulse width tPW tPW 0.95 Additional program pulse width tOPW tOPW 0.95 MD0 setup time (vs. MD 1↑) tMOS tCES 2 MD0↓→ data output delay time tDV tDV MD0 = MD1 = VIL MD1 hold time (vs. MD0↑) tM1H tOEH tM1H+tM1R ≥ 50 µs MD1 recovery time (vs. MD0↓) tM1R tOR Program counter reset time tPCR – CLK input high-, low-level width tXH, tXL – 0.125 CLK input frequency fX – Initial mode set time tI – 2 µs MD3 setup time (vs. MD1↑) tM3S – 2 µs MD3 hold time (vs. MD1↓) tM3H – 2 µs MD3 setup time (vs. MD0↓) tM3SR – When program memory is read 2 µs Address hold timeNote 2 (vs. MD0↑) 130 ns µs µs 1.0 1.05 ms 21.0 ms µs 1 µs 2 µs 2 µs 10 µs µs 8 MHz 2 µs 130 ns → data output delay time tOAD tACC When program memory is read AddressNote 2 → data output hold time tHAD tOH When program memory is read 0 MD3 hold time (vs. MD0↑) tM3HR – When program memory is read 2 MD3↓→ data output float delay time tDFR – When program memory is read Reset setup time tRES – 10 µs Oscillation stabilization wait timeNote 3 tWAIT – 2 ms AddressNote 2 µs 2 µs Notes 1. Equivalent symbol of the corresponding µPD27C256A (The µPD27C256A is a maintenance product.) 2. The internal address signal is incremented at the falling edge of the third clock of CLK. 3. Connect a 4 MHz ceramic resonator between the XIN and XOUT pins. Data Sheet U13594EJ2V0DS00 19 µPD6P4B Program Memory Write Timing t WAIT VPP VPP VDD GND VDD VDD+1 VDD GND t VPS t RES t VDS t XH CLK D0-D7 Hi-Z Data input t DS tt Hi-Z tDH Data output tDV tDF t XL Hi-Z Data input tDH t AH tDS Hi-Z Data input t AS MD0 t M1R tPW tMOS tOPW MD1 tPCR tM1S tM1H MD2 t M3S t M3H MD3 Program Memory Read Timing t WAIT tRES t VPS VPP VPP VDD GND VDD t VDS VDD+1 VDD t XH GND CLK tDAD t HAD t XL Hi-Z Hi-Z D0-D7 Data output Data output t DFR tDV tI t M3HR MD0 "L" MD1 t PCR MD2 t M3SR MD3 20 Data Sheet U13594EJ2V0DS00 Hi-Z µPD6P4B 5. CHARACTERISTIC CURVE (REFERENCE VALUES) IDD vs VDD (fX = 4 MHz) IDD vs VDD (fX = 8 MHz) (TA = 25 °C) 2 2 1.8 1.8 Power supply current IDD [mA] Power supply current IDD [mA] (TA = 25 °C ) 1.6 1.4 OPERATING mode 1.2 HALT mode 1.0 0.8 0.6 0.4 0.2 1.6 OPERATING mode 1.4 1.2 HALT mode 1.0 0.8 0.6 0.4 0.2 0 0 1 2 2.2 3 3.6 4 1 Power supply voltage VDD [V] IOL vs VOL (REM, LED) IOH vs VOH (REM) 9 –18 High-level output current IOH [mA] –20 8 7 6 5 4 3 2 3.6 4 (TA = 25 °C , VDD = 3.0 V) 10 –16 –14 –12 –10 –8 –6 –4 1 –2 0.6 1.2 1.8 2.4 0 VDD 3 Low-level output voltage VOL [V] VDD – 0.6 VDD – 1.2 VDD – 1.8 VDD – 2.4 VDD – 3 High-level output voltage VOH [V] IOH vs VOH (LED) (TA = 25 °C , VDD = 3.0 V) –10 –9 High-level output current IOH [mA] Low-level output current IOL [mA] 3 Power supply voltage VDD [V] (TA = 25 °C, VDD = 3.0 V) 0 2 2.2 –8 –7 –6 –5 –4 –3 –2 –1 0 VDD VDD – 0.6 VDD – 1.2 VDD – 1.8 VDD – 2.4 VDD – 3 High-level output voltage VOH [V] Data Sheet U13594EJ2V0DS00 21 µPD6P4B IOL vs VOL (KI/O) IOH vs VOH (KI/O) (TA = 25 °C, VDD = 3.0 V) High-level output current IOH [mA] Low-level output current IOL [ µ A] 320 280 240 200 160 120 80 40 0 (TA = 25 °C, VDD = 3.0 V) 0.6 1.2 1.8 2.4 3 –15 –14 –13 –12 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 VDD Low-level output voltage VOL [V] 22 VDD – 0.6 VDD – 1.2 VDD – 1.8 VDD – 2.4 VDD – 3 High-level output voltage VOH [V] Data Sheet U13594EJ2V0DS00 µPD6P4B 6. APPLIED CIRCUIT EXAMPLE Example of Application to System • Remote-control transmitter (40 keys; mode selection switch accommodated) + + KI/O6 KI/O5 KI/O7 KI/O4 S0 KI/O3 S1/LED KI/O2 REM KI/O1 VDD KI/O0 XOUT KI3 XIN KI2 GND KI1 RESET KI0 Mode selection switch Key matrix 8 × 5 = 40 keys • Remote-control transmitter (48 keys accommodated) + + KI/O6 KI/O5 KI/O7 KI/O4 S0 KI/O3 S1/LED KI/O2 REM KI/O1 VDD KI/O0 XOUT KI3 XIN KI2 GND KI1 RESET KI0 Key matrix 8 × 6 = 48 keys Remark When the POC circuit is used effectively, it is not necessary to connect the capacitor enclosed in the dotted lines. Data Sheet U13594EJ2V0DS00 23 µPD6P4B 7. PACKAGE DRAWINGS 20 PIN PLASTIC SOP (300 mil) 20 11 detail of lead end P 1 10 A H I G J L C D M M B K N E F NOTE ITEM Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 12.7±0.3 0.500±0.012 B 0.78 MAX. 0.031 MAX. C 1.27 (T.P.) 0.050 (T.P.) D 0.42 +0.08 –0.07 0.017 +0.003 –0.004 E 0.1±0.1 0.004±0.004 F 1.8 MAX. 0.071 MAX. G 1.55±0.05 0.061±0.002 H 7.7±0.3 0.303±0.012 I 5.6±0.2 0.220 +0.009 –0.008 J 1.1 0.043 K 0.22 +0.08 –0.07 0.009 +0.003 –0.004 L 0.6±0.2 0.024 +0.008 –0.009 M 0.12 0.005 N 0.10 0.004 P 3° +7° –3° 3° +7° –3° P20GM-50-300B, C-5 24 Data Sheet U13594EJ2V0DS00 µPD6P4B 20 PIN PLASTIC SSOP (300 mil) 20 11 detail of lead end F G T P L U E 1 10 A H J I S N S K C D M M B NOTE ITEM Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. 6.65±0.15 B 0.475 MAX. C 0.65 (T.P.) D 0.24 +0.08 −0.07 E 0.1±0.05 F 1.3±0.1 G 1.2 H 8.1±0.2 I J 6.1±0.2 1.0±0.2 K L 0.17±0.03 0.5 M 0.13 N 0.10 P 3° +5° −3° T U Data Sheet U13594EJ2V0DS00 MILLIMETERS A 0.25 0.6±0.15 S20MC-65-5A4-1 25 µPD6P4B 8. RECOMMENDED SOLDERING CONDITIONS Carry out the soldered packaging of this product under the following recommended conditions. For details of the soldering conditions, refer to information material Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than the recommended conditions, please consult one of our NEC sales representatives. Table 8-1. Soldering Conditions for Surface-Mount Type (1) µPD6P4BGS-×××: 20-pin plastic SOP (300 mil) Soldering Method Soldering Condition Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 secs. max. (210 °C min.), Number of times: Twice max. IR35-00-2 VPS Package peak temperature: 215 °C, Time: 40 secs. max. (200 °C min.), VP15-00-2 Number of times: Twice max. Wave soldering Solder bath temperature: 260 °C max., Time: 10 secs. max., Number of times: once, Preheating temperature: 120 °C max. (package surface temperature.) WS60-00-1 Partial heating Pin temperature: 300 °C or less ; time: 3 secs or less (for each side of the device) — Caution Do not use two or more soldering methods in combination (except partial heating). (2) µPD6P4BMC-5A4: 20-pin plastic SSOP (300 mil) Soldering Method Soldering Condition Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 secs. max. (210 °C min.), Number of times: Three times max. IR35-00-3 VPS Package peak temperature: 215 °C, Time: 40 secs. max. (200 °C min.), VP15-00-3 Number of times: Three times max. Wave soldering Solder bath temperature: 260 °C max., Time: 10 secs. max., Number of times: once, Preheating temperature: 120 °C max. (package surface temperature.) WS60-00-1 Partial heating Pin temperature: 300 °C or less ; time: 3 secs or less (for each side of the device) — Caution Do not use two or more soldering methods in combination (except partial heating). 26 Data Sheet U13594EJ2V0DS00 µPD6P4B APPENDIX A. DEVELOPMENT TOOLS A PROM programmer, program adapter, and emulator are provided for the µPD6P4B. Hardware • PROM programmer (AF-9704Note, AF-9705 Note, AF-9706Note) This PROM programmer supports the µPD6P4B. By connecting a program adapter to this PROM programmer, the µPD6P4B can be programmed. Note These are products of Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd (03-3733-1163). • Program adapter (PA-61P34, PA-61P34BMC) It is used to program the µPD6P4B in combination with AF-9704, AF-9705, or AF-9706. The usable package differs depending on the program adapter. • PA-61P34 : µPD6P4BGS • PA-61P34BMC : µPD6P4BGS, µPD6P4BMC-5A4 • Emulator (EB-6133Note) It is used to emulate the µPD6P4B. Note This is a product of Naito Densei Machida Mfg. Co., Ltd. For details, consult Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Software • Assembler (AS6133) • This is a development tool for remote control transmitter software. Part Number List of AS6133 Host Machine OS Supply Medium Part Number PC-9800 series (CPU: 80386 or more) MS-DOSTM (Ver. 5.0 to Ver. 6.2) 3.5-inch 2HD µS5A13AS6133 IBM PC/AT TM compatible MS-DOS (Ver. 6.0 to Ver. 6.22) 3.5-inch 2HC µS7B13AS6133 PC DOSTM (Ver. 6.1 to Ver. 6.3) Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this software. Data Sheet U13594EJ2V0DS00 27 µPD6P4B APPENDIX B. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (in the case of NEC transmission format in command one-shot transmission mode) Caution When using the NEC transmission format, please apply for a custom code at NEC. (1) REM output waveform (From <2> on, the output is made only when the key is kept pressed.) REM output 58.5 to 76.5 ms <1> 108 ms <2> 108 ms Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can be reduced by sending the reader code and the stop bit from the second time. (2) Enlarged waveform of <1> <3> REM output 9 ms 4.5 ms Custom code 8 bits 13.5 ms Leader code Custom code' 8 bits Data code 8 bits 18 to 36 ms Data code 8 bits Stop Bit 1 bit 27 ms 58.5 to 76.5 ms (3) Enlarged waveform of <3> REM output 4.5 ms 9 ms 0.56 ms 1.125 ms 2.25 ms 0 1 13.5 ms (4) Enlarged waveform of <2> REM output 2.25 ms 9 ms 11.25 ms Leader code 28 Data Sheet U13594EJ2V0DS00 0.56 ms Stop Bit 1 0 0 µPD6P4B (5) Carrier waveform (Enlarged waveform of each code’s high period) REM output 8.77 µ s 26.3 µ s 9 ms or 0.56 ms Carrier frequency : 38 kHz (6) Bit array of each code C0 C1 C2 C3 C4 C5 C6 C7 C0' C1' C2' C3' C4' C5' C6' C7' D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 = = = = = = = = C0 C1 C2 C3 C4 C5 C6 C7 or or or or or or or or Co C1 C2 C3 C4 C5 C6 C7 Leader code Custom code Custom code' Data code Data code Caution To prevent malfunction with other systems when receiving data in the NEC transmission format, not only fully decode (make sure to check Data Code as well) the total 32 bits of the 16-bit custom codes (Custom Code, Custom Code’) and the 16-bit data codes (Data Code, Data Code) but also check to make sure that no signals are present. Data Sheet U13594EJ2V0DS00 29 µPD6P4B NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 30 Data Sheet U13594EJ2V0DS00 µPD6P4B Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U13594EJ2V0DS00 31 µPD6P4B MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT and PC DOS are trademarks of IBM Corp. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8