NEC UPD75P218KB

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P218
4-BIT SINGLE-CHIP MICROCOMPUTER
The µPD75P218 is a one-time PROM version that can be written to only once or an EPROM version that allows
program writing, erasing, and rewriting, of the µPD75218 Note.
Since the program can be written by the user, the µPD75P218 is suitable for preproduction use during
system development, or limited production.
Read this material together with the µPD75218 materials.
Note Under development
FEATURES
•
•
•
•
•
•
•
µPD75218 compatible
On-chip 16K-byte mode/32K-byte mode switching function
Operates at the same power supply voltage range (2.7 to 6.0 V) as the mask ROM version µPD75218.
32640 × 8 bits of PROM
1024 × 4 bits of RAM
No pull-down resistor for Port 6
High breakdown voltage display output
• S0 to S8, T0 to T9 : On-chip pull-down resistor
• S9, T10 to T15
: Open drain
• No power-on reset circuit
Caution No mask-option pull-down resistor is provided.
ORDERING INFORMATION
Part Number
µPD75P218CW
Package
Quality Grade
64-pin plastic shrink DIP (750 mil)
Standard
µPD75P218GF-3BR
64-pin plastic QFP (14 × 20 mm)
Standard
µPD75P218KB
64-pin ceramic LCC with window (14 × 20 mm)
Standard
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The word “PROM” in this document refers to the common parts of the one-time PROM products and
EPROM products.
The information in this document is subject to change without notice.
Document No. IC-2541A
(O.D. No. IC-7962A)
Date Published March 1993 P
Printed in Japan
1991
1989
© NEC CORPORATION
µPD75P218
PIN CONFIGURATION (Top View)
P02/SO
P03/SI
P10/INT0/VPP
P11/INT1
P12/INT2
P13/TI0
P20
P21
P22
P23/BUZ
P30/MD0
P31/MD1
P32/MD2
P33/MD3
P60
P61
P62
P63
VDD
S4
S5
S6
S7
S8
S9
NC
VLOAD
T15/S10
T14/S11
T13/S12/PH0
T12/S13/PH1
T11/S14/PH2
T10/S15/PH3
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
RESET
P53
P52
P51
P50
XT2
XT1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P41
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
52
P01/SCK
P42
53
31
P00/INT4
P43
54
30
S0
PPO
55
29
S1
X1
56
28
S2
X2
57
27
S3
VSS
58
XT1
59
XT2
P50
mPD75P218GF-3BR
µPD75P218GF-3BR
26
VDD
25
S4
60
24
S5
61
23
S6
P51
62
22
S7
P52
63
21
S8
P53
64
1
S9
T5
T6
T7
NC
T4
VLOAD
T3
T15/S10
T2
T14/S11
8
T13/S12/PH0
7
T12/S13/PH1
6
T11/S14/PH2
5
T10/S15/PH3
4
T9
3
T8
2
20
9 10 11 12 13 14 15 16 17 18 19
T1
mPD75P218KB
µPD75P218KB
T0
RESET
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
µPD75P218CW
mPD75P218CW
P40
S3
S2
S1
S0
P00/INT4
P01/SCK
P02/SO
P03/SI
P10/INT0/VPP
P11/INT1
P12/INT2
P13/ TI0
P20
P21
P22
P23/BUZ
P30/MD0
P31/MD1
P32/MD2
P33/MD3
P60
P61
P62
P63
P40
P41
P42
P43
PPO
X1
X2
VSS
INTBT
TI0/P13
PROGRAM
COUNTER (15)
CY
ALU
4
P00 - P03
PORT 1
4
P10 - P13
PORT 2
4
P20 - P23
PORT 3
4
P30/MD0 P33/MD3
PORT 4
4
P40 - P43
PORT 5
4
P50 - P53
PORT 6
4
P60 - P63
SP (8)
SBS (2)
TIMER/EVENT
COUNTER
#0
PORT 0
BANK
INTT0
PRO
TIMER/PULSE
GENERATOR
INTTPG
SI/P03
SO/P02
SERIAL
INTERFACE
BLOCK DIAGRAM
BASIC
INTERVAL
TIMER
GENERAL REG.
PROM
PROGRAM
MEMORY
32640 ·x88BITS
BITS
DECODE
AND
CONTROL
SCK/P01
RAM
DATA MEMORY
1024 x· 44BITS
1024
BITS
10
T0 - T9
4
T10/S15/PH3 T13/S12/PH0
2
T14/S11,T15/S10
10
S0 - S9
INTSIO
FIP
CONTROLLER/
DRIVER
INT0/P10/VPP
INT1/P11
INT2/P12
INT4/P00
INTERRUPT
CONTROL
fx/2N
INTW
BUZ/P23
CLOCK
DIVIDER
SYSTEM CLOCK
GENERATOR
SUB
MAIN
XT1 XT2 X1 X2
STAND BY
CONTROL
VLOAD
CPU CLOCK
F
INTKS
PORTH
NC VDD VSS RESET
4
PH0 - PH3
3
µPD75P218
WATCH
TIMER
µPD75P218
1.
PIN FUNCTIONS
1.1
PORT PINS
Pin name
Input/
output
Shared
pin
P00
Input
INT4
P01
I/O
SCK
P02
I/O
SO
P03
Input
SI
P10
Input
INT0/VPP
P11
INT1
P12
INT2
P13
TI0
P20
4
I/O
–
P21
–
P22
–
P23
BUZ
P30 - P33
I/O
MD0 - MD3
P40 - P43
I/O
P50 - P53
Function
4-bit input port (PORT0).
4-bit input port (PORT1).
8-bit
I/O
When reset
×
Input
With noise elimination
function
Input
×
4-bit I/O port (PORT2).
Input
Programmable 4-bit I/O port (PORT3).
I/O can be specified bit by bit.
Input
–
4-bit I/O port (PORT4).
Can directly drive LEDs.
Data input/output pins
for the PROM write and
verify (Four low-order
bits).
Input
I/O
–
4-bit I/O port (PORT5).
Can directly drive LEDs.
Data input/output pins
for the PROM write and
verify (Four high-order
bits).
Input
P60 - P63
I/O
–
Programmable 4-bit I/O port (PORT6).
I/O can be specified bit by bit.
Suitable for key input.
PH0
Output
T13/S12
PH1
T12/S13
PH2
T11/S14
PH3
T10/S15
4-bit P-ch open drain high breakdown voltage large
current output port (PORTH).
Can directly drive LEDs.
×
×
Input
High
impedance
µPD75P218
1.2
NON-PORT PINS
Pin name
Input/
output
Shared
pin
Output
When reset
–
Note 1
High breakdown voltage large current output pin
for digit output
Low level
PH3 - PH0
Note 2
High breakdown voltage large current output pin
for digit/segment output
The remainder of the pins can be used as PORTH.
High
impedance
T0 - T9
T10/S15 T13/S12
Function
T14/S11,
T15/S10
–
High breakdown voltage large current output pin
for digit/segment output
Static output is also available.
S9
High breakdown voltage output pin for segment
output
Static output is also available.
S0 - S8
Note 1
High breakdown voltage output pin for segment
output
Low level
PPO
Output
–
TI0
Input
P13
Input for receiving external event pulse signal for timer/
event counter
SCK
I/O
P01
Serial clock I/O
Input
SO
I/O
P02
Serial data output or serial data I/O
Input
SI
Input
P03
Serial data input or normal input
Input
INT4
Input
P00
Edge detection vectored interrupt input
(either rising edge or falling edge detection)
INT0
Input
P10/VPP
INT1
Output for receiving pulse signal for timer/pulse generator
P11
Edge detection vectored interrupt input with noise elimination
(detection edge selectable)
INT2
Input
P12
Edge detection testable input (rising edge detection)
BUZ
I/O
P23
Fixed frequency output pin (for buzzer or system clock trimming)
X1, X2
–
Crystal/ceramic resonator connection for main system clock
generation.
When external clock is used, it is applied to X1, and its
reserve phase signal is applied to X2.
XT1, XT2
–
Crystal connection for subsystem clock generation.
When external clock is used, it is applied to XT1, and XT2 is open.
System reset input (low level active)
RESET
Input
–
MD0 - MD3
I/O
P30 - P33
Operation mode selection pins during the PROM write/verify cycles
VPP
P10/INT0
+12.5 V is applied as the programming voltage during the
PROM write/verify cycles
VLOAD
–
Pull-down resistor connection pin of FIP® controller/driver
VDD
–
Positive power supply. +6 V is applied as the programming
voltage during the PROM write/verify cycles
VSS
–
GND potential
–
No connection
NC
Note 3
High
impedance
Input
Note 1. On-chip pull-down resistor
2. Open drain output
3. When using a printed board with a µPD75216A, 75217, or 75218, connect the NC pin to the VPRE.
5
µPD75P218
1.3
PIN INPUT/OUTPUT CIRCUITS
The input/output circuit diagram for each µPD75P218 pin is shown in Fig. 1-1 in a simplified manner.
For the correspondence of the each pin and input/output type number, refer to Table 1-1.
Table 1-1 Pins and Input/Output Type Numbers
Pin name
I/O type
Pin name
P00/INT4
B
P50 - P53
E
P01/SCK
F
P60 - P63
E
P02/SO
G
T0 - T9
I-E
P03 - SI
B
T10/S15/PH3 - T13/S12/PH0
I-D
P10/INT0/VPP
B
T14/S11, T15/S10
I-D
P11/INT1, P12/INT2
S0 - S8
I-E
P13 - TI0
S9
I-D
P20 - P22
E
P23/BUZ
P30/MD0 - P33/MD3
E
P40 - P43
E
PPO
D
RESET
B
VLOAD
Remark I/O type enclosed with a circle indicates Schmitt triggered input.
6
I/O type
I-E
µPD75P218
Fig. 1-1 Pin Input/Output Circuit
TYPE A
TYPE F
VDD
Data
IN/OUT
Type D
P-ch
Output
disable
IN
Type B
N-ch
I/O circuit consisting of push-pull output of Type D and
Schmitt trigger of Type B
CMOS input buffer
TYPE B
TYPE G
VDD
P-ch output
disable
Data
P-ch
IN/OUT
IN
N-ch
Type B
Schmitt trigger input with hysteresis
I/O circuit that can switch the push-pull output or
N-ch open drain output (off for P-ch)
TYPE D
VDD
TYPE I-D
Data
P-ch
VDD
VDD
OUT
Data
Output
disable
P-ch
P-ch
N-ch
N-ch
OUT
Push-pull output which can be set to high-impedance
output (off for both P-ch and N-ch)
TYPE E
TYPE I-E
Data
Type D
VDD
IN/OUT
Output
disable
Data
P-ch
VDD
P-ch
OUT
N-ch
Type A
Pull-down resistor
VLOAD
I/O circuit consisting of push-pull output of Type D and
input buffer of Type A
7
µPD75P218
1.4
PROCESSING OF UNUSED PINS
Table 1-2 Recommended Connection of Unused Pins
Pin name
Recommended connection
P00/INT4
Connect to VSS
P01/SCK
Connect to VSS or VDD
P02/SO
P03/SI
P10/INT0/VPP
Connect to VSS
P11/INT1, P12/INT2
P13/T10
P20 - P22
Input state: Connect to VSS or VDD
P23/BUZ
Output state: Open
P30/MD0 - P33/MD3
P40 - P43
P50 - P53
P60 - P63
PPO
Open
S0 - S9
T15/S10, T14/S11
T0 - T9
T10/S15/PH3 - T13/S12/PH0
8
XT1
Connect to VSS or VDD
XT2
Open
VLOAD when no on-chip load resistor
Connect to VSS or VDD
µPD75P218
2.
DIFFERENCES BETWEEN THE µPD75P218 AND THE µPD75P216A, 75217, 75218
Part number
µPD75P216A
µPD75217
µPD75218
One-time PROM
16K × 8
Mask ROM
24K × 8
512 × 4
768 × 4
µPD75P218
Note
Item
ROM
RAM
FIP controller/driver
segments
Pull-down
resistors
P60 - P63
Pin connection
PROM
32K × 8
Mask ROM
32K × 8
1024 × 4
9 - 16 segments
digits
9 - 16 digits
Not available
Mask-option
Not available
S0 - S8, T0 - T9
On-chip
Mask-option
On-chip
SD9, T10 - T15
Not available
(open drain)
Mask-option
Not available
(open drain)
P10
INT0/V PP
(common use)
INT0 (common use)
INT0/V PP
(common use)
P30 - P33
MD0 - MD3
(common use)
No common use
MD0 - MD3
(common use)
Not available (NC)
Available
Not available (NC)
–10 to +70 ˚C
–40 to +85 ˚C
–40 to +70 ˚C
VPRE
Operating ambient temperature
Power supply voltage
Stack area
5 V ± 10 %
Bank 0
16K-byte mode/32K-byte
mode switching function
Package
2.7 - 6.0 V
Bank 0 - 2
Not available
64-pin plastic
shrink DIP
64-pin plastic shrink DIP
64-pin plastic QFP
Bank 0 - 3
Available
64-pin plastic
shrink DIP
64-pin plastic QFP
64-pin ceramic
LCC with window
Note Under development
9
µPD75P218
3.
16K-BYTE MODE/32K-BYTE MODE SWITCHING FUNCTION
16K-byte mode or 32K-byte mode can be selected by setting the stack bank selection register (SBS).
The µPD75P218 can then be used to evaluate the µPD75216A, µPD75217, and µPD75218.
3.1
DIFFERENCES BETWEEN 16K-BYTE MODE AND 32K-BYTE MODE
Table 3-1 16K-byte Mode and 32K-byte Mode Differences
Item
16K-byte Mode
32K-byte Mode
Stack operation at subroutine call
instruction execution
2-byte stack
3-byte stack
Stack area
Bank 0
Bank 0 to bank 3
CALL instruction
3 machine cycles
4 machine cycles
CALLF instruction
2 machine cycles
3 machine cycles
BRA instruction
Undefined operation
Normal operation
Program counter bit 14
0 fixed
Corresponds to branch instruction,
call instruction
Corresponding mask ROM version
µPD75216A (S-DIP, QFP)
µPD75217 (S-DIP, QFP)
µPD75218 (S-DIP, QFP)
TCALL instruction by GETI
CALLA instruction
10
µPD75P218
3.2
16K-BYTE MODE AND 32K-BYTE MODE SWITCHING
16K-byte mode and 32K-byte mode are switched by the stack bank selection register. The stack bank selection
register format is shown in Fig. 3-1.
The stack bank selection register is set by 4-bit memory manipulation instruction. RESET input sets bit 3 of the
stack bank selection register to “1” and changes from 32K-byte mode to 16K-byte mode. When 16K-byte mode is
used, manipulating the stack bank selection register is unnecessary. When 32K-byte mode is used, the stack bank
selection register must always be initialized to 00××B
Note 1
at the beginning of the program.
Fig. 3-1 Stack Bank Selection Register Format
Address
F84H
3
2
1
0
SBS3
SBS2
SBS1
SBS0
Symbol
SBS
Stack area specification
0
0
Memory bank 0
0
1
Memory bank 1
1
0
Memory bank 2
1
1
Memory bank 3
0
Be sure to write 0 to bit 2.
Mode change specification
0
32K-byte mode
1
16K-byte mode Note 2
Caution When using 32K-byte mode, execute a subroutine call instruction and an interrupt enable instruction after the stack bank selection register is set after RESET input.
Notes 1. Set the desired value in ××.
2. When the 16K-byte mode is used after RESET input, the stack bank selection register does not have
to be manipulated.
11
µPD75P218
4.
PROM (PROGRAM MEMORY) WRITE AND VERIFY
The PROM contained in the µPD75P218 is one-time PROM or EPROM for writing, erasing, and rewriting.
Table 4-1 shows the pin functions during the write and verify cycles. Note that it is not necessary to enter
an address, because the address is updated by pulsing the X1 clock pins.
Table 4-1 PROM Write and Verify Pin Functions
Pin Name
Function
VPP
Normally 2.7 to 6 V; 12.5 V is applied during the write/verify cycles.
X1, X2
After a write/verify write, the X1 and X2 clock pins are pulsed.
The inverted signal of the X1 should be input to the X2.
Note that these pins are also pulsed during a read.
MD0 - MD3
Operation mode selection pins during the write/verify cycles
P40 - P43 (Four low-order bits)
P50 - P53 (Four high-order bits)
8-bit data input/output pins during the write/verify cycles
VDD
Supply voltage
Normally 2.7 to 6 V; 6 V is applied during the write/verify cycles.
Cautions 1. The pins not used for write and verify should be processed as follows.
Port 0 - 2, Port 6, XT1
S0 - S9, T0 - T15
RESET, PPO, VLOAD



···· Connect to GND (directly connectable)
XT2 ········································· Open
2. An opaque film should be placed over the UV erase window of the µPD75P218KB except when
erasing the EPROM contents.
3. The µPD75P218CW/GF does not have a UV erase window, thus the PROM contents cannot be
erased with ultraviolet ray.
4.1
PROM WRITE AND VERIFY OPERATION
When +6 V and +12.5 V are applied to the VDD and VPP pins, respectively, the PROM is placed in the write/
verify mode. The operation is selected by the MD0 to MD3 pins, as shown in Table 4-2.
Table 4-2 PROM Write and Verify Operation Mode
Operation Mode Specification
Operation Mode
VPP
VDD
MD0
MD1
MD2
MD3
+12.5 V
+6 V
H
L
H
L
Clear program memory address to 0
L
H
H
H
Write mode
L
L
H
H
Verify mode
H
×
H
H
Program inhibit
×: Don’t care.
12
µPD75P218
4.2
PROM WRITE/VERIFY PROCEDURE
PROMs can be written at high speed using the following procedure: (see the following figure)
(1) Connect unused pins to VSS. Set the X1 pin low.
(2) Supply 5 volts to the VDD and VPP pins.
(3) Wait for 10 µs.
(4) Select the zero clear program memory address mode.
(5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins.
(6) Select the program inhibit mode.
(7) Write data in the 1 ms write mode.
(8) Select the program inhibit mode.
(9) Select the verify mode. If the data is correct, proceed to step (10). If not, repeat steps (7), (8) and (9).
(10) Perform one additional write (duration of 1 ms × number of writes at (7) to (9)).
(11) Select the program inhibit mode.
(12) Apply four pulses to the X1 pin to increment the program memory address by one.
(13) Repeat steps (7) to (12) until the end address is reached.
(14) Select the zero clear program memory address mode.
(15) Return the VDD and VPP pins back to + 5 volts.
(16) Turn off the power.
Fig. 4-1 PROM Write Timing
X repetition
Write
Verify
Additional write
Address
increment
VPP
VPP
VDD
VDD+1
VDD
VDD
X1
P40 - P43
P50 - P53
Input data
Output
data
Input data
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
X: number of writes performed at (7) to (9)
13
µPD75P218
4.3
PROM READ PROCEDURE
The PROM contents can be read in the verify mode by using the following procedure: (see the following
figure)
(1) Connect unused pins to VSS. Set the X1 pin low.
(2) Supply 5 volts to the VDD and VPP pins.
(3) Wait for 10 µs.
(4) Select the clear program memory address mode.
(5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins.
(6) Select the program inhibit mode.
(7) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored
in one address.
(8) Select the program inhibit mode.
(9) Select the clear program memory address mode.
(10) Return the VDD and VPP pins back to + 5 volts.
(11) Turn off the power.
Fig. 4-2 PROM Read Timing
VPP
VPP
VDD
VDD+1
VDD
VDD
X1
P40 - P43
P50 - P53
Output data
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
14
“L”
Output data
µPD75P218
4.4
ERASING METHOD
The program data contents of the µPD75P218KB are erased by lighting ultraviolet ray whose wavelength
is about 250 nm on the window. The minimum amount of radiation exposure required to erase the contents
completely is 15 W·s/cm2 (ultraviolet ray strength times erase time).
This corresponds to about 15 to 20 minutes when using a UV lamp on the market (wavelength 254 nm,
strength 12 mW/cm2).
Cautions 1. The programmed data contents may also be erased if the uncovered window is exposed to direct
sunlight or a fluorescent light even for several hours. Thus, to protect the data contents, cover
the window with an opaque film.
NEC attaches quality-tested shading film to the UV EPROM products for shipping.
2. For normal EPROM erase, the distance between the light source and the window should be 2.5
cm or less.
Remark The erase time may be prolonged if the UV lamp is old or if the device window is dirty.
15
µPD75P218
5.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Ta = 25 ˚C)
Parameter
Symbol
Ratings
Unit
VDD
–0.3 to +7.0
V
VLOAD
VDD – 40 to VDD + 0.3
V
VPP
–0.3 to +13.5
V
Input voltage
VI
–0.3 to VDD + 0.3
V
Output voltage
VO
Other than display pins
–0.3 to VDD + 0.3
V
VOD
Display pins
VDD – 40 to VDD + 0.3
V
IOH
Single pin; other than display pins
–15
mA
Single pin; S0 - S9
–15
mA
Single pin; T0 - T15
–30
mA
Total of all pins other than display
–20
mA
Total of all display pins
–120
mA
Single pin
17
mA
Total of all pins
60
mA
Power supply voltage
High-level output
current
Conditions
Low-level output
current
IOL
Operating temperature
Topt
–40 to +70
˚C
Storage temperature
Tstg
–65 to +150
˚C
Operating Power Supply Voltage (Ta = –40 to +70 ˚C)
Parameter
MIN.
MAX.
Unit
Note 2
6.0
V
Display controller
4.5
6.0
V
Timer/pulse generator
4.5
6.0
V
2.7
6.0
V
CPU
Conditions
Note 1
Other hardwares
Note 1
Notes 1. The CPU does not include the system clock oscillator, the display controller, or the timer/pulse
generator.
2. Varies according to the cycle time. See AC Characteristics.
16
µPD75P218
Main System Clock Configurations (Ta = –40 to +70 ˚C, V DD = 2.7 to 6.0 V)
Resonator
Recommended constants
Parameter
Conditions
Note 1
Ceramic
resonator
X1
Oscillation (fXX)
frequency
X2
Note 2
C1
C2
Oscillation
stabilization time
VDD = Oscillator
operating
voltage
range
X1
Note 2
C2
6.2
MHz
4
ms
6.2
MHz
10
ms
30
ms
2.0
6.2
MHz
81
250
ns
2.0
2.0
4.19
VDD = 4.5 to 6.0 V
Note 1
X1
Unit
Oscillation
stabilization time
External
clock
MAX.
Oscillation
frequency (fXX)
X2
C1
TYP.
After VDD reaches
the minimum
oscillator operating voltage range
Note 1
Crystal
resonator
MIN.
X1 input frequency (fX)
X2
X1 input highand low-level
width (tXH, tXL)
mPD74HCU04
Subsystem Clock Configurations (Ta = –40 to +70 ˚C, V DD = 2.7 to 6.0 V)
Resonator
Recommended constants
Parameter
Conditions
Note 1
Crystal
resonator
XT1
External
clock
Note 2
C4
XT1
TYP.
MAX.
Unit
32
32.768
35
kHz
1.0
2
s
10
s
Oscillation
frequency (fXT)
XT2
330 kW
C3
MIN.
VDD = 4.5 to 6.0 V
Oscillation
stabilization time
XT2
XT1 input
frequency (fXT)
32
100
kHz
XT1 input highand low-level
width (tXTH, tXTL)
5
15
µs
Open
Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics.
Refer to the AC Characteristics for the instruction execution time.
2. The oscillation stabilization time is the time required for the oscillation to stabilize after VDD is applied
and reaches the V DD spec or after STOP mode is released.
Capacitance (Ta = 25 ˚C, V DD = 0 V)
Parameter
Input capacitance
Output
capacitance
Other than
display output
Symbol
CIN
COUT
Display output
Input/Output capacitance
CIO
Conditions
MIN.
TYP.
MAX.
Unit
f = 1 MHz
15
pF
Unmeasured pins returned to 0 V
15
pF
35
pF
15
pF
17
µPD75P218
Recommended Oscillation Circuit Constants
Main System Clock: Ceramic Resonator (Ta = –40 to +70 ˚C)
Manufacturer
Murata
Part number
CSA×××MG
MAX.
MIN.
MAX.
2.00 - 2.44
30
30
2.7
6.0
On-chip
On-chip
30
30
On-chip
On-chip
30
30
On-chip
On-chip
30
30
On-chip
On-chip
30
30
On-chip
On-chip
2.45 - 3.50
CST×××MGW093
CSA×××MGU
2.51 - 6.00
CST×××MGWU
CSA×××MG
2.45 - 3.50
CST×××MGW
CSA×××MG
2.51 - 6.00
CST×××MGW
Kyocera
18
Oscillation voltage (V)
MIN.
CST×××MT
CSA×××MG093
Capacitance (pF)
Frequency
(MHz)
KBR – 2.0MS
2.0
47
47
KBR – 4.0MWS
4.0
33
33
KBR – 4.19MWS
4.19
KBR – 6.0MWS
6.0
3.0
3.3
2.7
6.0
µPD75P218
DC Characteristics (Ta = –40 to +70 ˚C, V DD = 2.7 to 6.0 V)
Parameter
MAX.
Unit
VIH1
All except ports 0, 1, 6; X1, X2, XT1, RESET
0.7VDD
VDD
V
VIH2
Port 0, 1, RESET
0.75VDD
VDD
V
VIH3
X1, X2, XT1
VDD – 0.4
VDD
V
VIH4
Port 6
0.65VDD
VDD
V
0.7VDD
VDD
V
Conditions
Symbol
High-level input voltage
Low-level input voltage
High-level output voltage
MIN.
VDD = 4.5 to 6.0 V
VIL1
All except ports 0, 1, 6; X1, X2, XT1, RESET
0
0.3VDD
V
VIL2
Port 0, 1, 6, RESET
0
0.2VDD
V
VIL3
X1, X2, XT1
0
0.4
V
VOH
All outputs
VDD = 4.5 to 6.0 V, IOH = –1 mA VDD – 1.0
IOH = –100 µA
Low-level output voltage
High-level input leakage
current
Low-level input leakage
current
High-level output leakage
TYP.
VOL
V
VDD – 0.5
V
2.0
V
VDD = 4.5 to 6.0 V, IOL = 1.6 mA
0.4
V
I OL = 400 µA
0.5
V
3
µA
20
µA
–3
µA
–20
µA
Port 4, 5
VDD = 4.5 to 6.0 V, IOL = 15 mA
All outputs
0.4
I LIH1
All except X1, X2, XT1
VIN = VDD
I LIH2
X1, X2, XT1
ILIL1
All except X1, X2, XT1
ILIL2
X1, X2, XT1
ILOH
All outputs
VOUT = VDD
3
µA
ILOL1
All except display
VOUT = 0 V
–3
µA
–10
µA
VIN = 0 V
current
Low-level output leakage
current
outputs
ILOL2
Display outputs
VOUT = VLOAD = VDD – 35 V
Display output current
IOD
S0-S9
VDD = 4.5 to 6.0 V
T0-T15
On-chip pull-down resistor
RL
Display outputs
Note 1
I DD1
6.0 MHz crystal
VDD = 5 V ± 10 %
oscillator
VDD = 3 V ± 10 %
Power supply current
I DD2
I DD1
–5.5
VOD = VDD – 2 V
–15
–22
VOD – V LOAD = 35 V
25
70
135
kΩ
Note 2
6.5
18.0
mA
Note 3
0.85
2.5
mA
V DD = 5 V ± 10 %
1350
4000
µA
V DD = 3 V ± 10 %
450
1350
µA
HALT mode
mA
VDD = 5 V ± 10 %
Note 2
4.0
12.0
mA
oscillator
VDD = 3 V ± 10 %
Note 3
0.55
1.5
mA
V DD = 5 V ± 10 %
900
2700
µA
V DD = 3 V ± 10 %
300
900
µA
100
300
µA
20
60
µA
I DD2
HALT mode
Note 4
I DD3
32kHz crystal
VDD = 3 V ± 10 %
HALT mode
V DD = 3 V ± 10 %
STOP mode
V DD = 3 V ± 10 %
oscillator
I DD5
mA
4.19 MHz crystal
C1 = C2 = 15 pF
I DD4
–3
5
15
µA
XT1 = 0 V
VDD = 5 V ± 10 %
0.5
20
µA
STOP mode
VDD = 3 V ± 10 %
0.1
10
µA
Notes 1. Does not include pull-down resistor current.
2. Value during high-speed operation and when the processor clock control (PCC) register is set to 0011.
3. Value during low-speed operation and when the PCC register is set to 0000.
4. Value when the system clock control register (SCC) is set to 1001, generation of the main system
clock pulse is stopped, and the CPU is operated by the subsystem clock pulse.
19
µPD75P218
AC Characteristics (Ta = –40 to +70 ˚C, V DD = 2.7 to 6.0 V)
Parameter
Symbol
Note 1
tCY
CPU clock cycle time
(minimum instruction execution time = 1 machine cycle)
TI0 input frequency
Main system
clock
MIN.
VDD = 4.5 to 6.0 V
Subsystem
clock
fTI
TI0 input low- and high-level
width
tTIH,
SCK cycle time
tKCY
SCK low- and high-level width
Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
tKL
0.67
32
µs
2.6
32
µs
125
µs
0
0.6
MHz
0
165
kHz
122
µs
3
µs
Input
0.8
µs
Output
0.95
µs
Input
3.2
µs
Output
3.8
µs
Input
0.4
µs
tTIL
tKH,
Unit
0.83
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
MAX.
114
TYP.
Output t KCY/2–50
ns
Input
µs
1.6
Output tKCY/2–150
ns
SI setup time (to SCK ↑)
tSIK
100
ns
SI hold time (from SCK ↑)
tKSI
400
ns
SCK ↓ → SO output delay
time
tKSO
Interrupt inputs
low- and high-level width
tINTH,
INT0
Note 2
µs
tINTL
INT1
2tCY
µs
10
µs
10
µs
VDD = 4.5 to 6.0 V
INT2,4
RESET low-level width
20
tRSL
300
ns
1000
ns
µPD75P218
Notes 1. The CPU clock (Φ) cycle time is deter-
tCY vs VDD
40
mined by the oscillator frequency of the
(Main system clock)
32
30
connected resonator, the system clock
control register (SCC), and the processor
6
clock control register (PCC).
5
characteristics for power supply voltage
4
VDD during the main system clock operation.
2. 2t CY or 128/fXX, depending on the setting
of the interrupt mode register (IM0).
Cycle time tCY ( m
s)
The right chart shows the cycle time tCY
Guaranteed
operating
range
3
2
1
0.5
0
1
2
3
4
5
6
Power supply voltage VDD (V)
21
µPD75P218
AC Timing Test Points (Except X1, XT1)
0.75 VDD
0.75 VDD
Test points
0.2 VDD
0.2 VDD
Clock Timing
1/fX
tXL
tXH
VDD – 0.4 V
X1 input
0.4 V
1/fXT
tXTL
tXTH
VDD – 0.4 V
XT1 input
0.4 V
TI0 Timing
1/fT1
tTIL
TI0
22
tTIH
µPD75P218
Serial Transfer Timing
tKCY
tKL
tKH
SCK
tSIK
SI
tKSI
Input data
tKSO
Output data
SO
Interrupt Input Timing
tINTL
tINTH
INT0, 1, 2, 4
RESET Input Timing
tRSL
RESET
23
µPD75P218
Data Memory STOP Mode Low Voltage Data Retention Characteristics (Ta = –40 to +70 ˚C)
Parameter
Data retention voltage
Data retention current
Conditions
Symbol
MIN.
VDDDR
Note 1
IDDDR
Release signal SET time
tSREL
Oscillation stabilization time Note 2
tWAIT
TYP.
MAX.
2.0
VDDDR = 2.0 V
0.1
Unit
6.0
V
10
µA
µs
0
Release by RESET input
217/fx
ms
Release by interrupt request
Note 3
ms
Notes 1. Does not include pull-down resistor current.
2. The oscillation stabilization WAIT time is the time during which the CPU operation is stopped to
prevent unstable operation while the oscillation is started.
3. The WAIT time depends on the setting of the basic interval timer mode register (BTM) according to
the following table.
WAIT time
BTM3
BTM2
BTM1
BTM0
(fXX = 6.0 MHz)
–
0
–
0
0
–
1
1
–
0
1
1
0
220/fXX
1
217/fXX
1
215/fXX
1
213/fXX
(fXX = 4.19 MHz)
(approx. 175 ms)
220/fXX
(approx. 250 ms)
(approx. 21.8 ms)
217/fXX
(approx. 31.3 ms)
(approx. 5.46 ms)
215/fXX
(approx. 7.82 ms)
(approx. 1.37 ms)
213/fXX
(approx. 1.95 ms)
Data Retention Timing (STOP mode is released by RESET input)
Internal reset
operation
HALT mode
Operation
mode
STOP mode
Data retention mode
VDD
tSREL
VDDDR
Execution of
STOP instruction
RESET
tWAIT
Data Retention Timing (STOP mode is released by interrupt signal)
HALT mode
Operation
mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
Execution of
STOP mode
Standby release signal
(Interrupt request)
tWAIT
24
µPD75P218
DC Programming Characteristics (Ta = 25 ± 5 ˚C, V DD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)
Parameter
Symbol
High-level input voltage
Low-level input voltage
Conditions
MAX.
Unit
0.7VDD
VDD
V
VDD – 0.5
VDD
V
V
All except X1, X2
VIH2
X1, X2
VIL1
All except X1, X2
0
0.3VDD
VIL2
X1, X2
0
0.4
V
10
µA
ILI
VIN = VIL or VIH
High-level output voltage
VOH
IOH = –1 mA
Low-level output voltage
VOL
IOL = 1.6 mA
VDD power supply current
IDD
VPP power supply current
IPP
2.
TYP.
VIH1
Input leakage current
Cautions 1.
MIN.
VDD – 1.0
V
MD0 = VIL, MD1 = VIH
0.4
V
30
mA
30
mA
VPP must not exceed +13.5 V, including overshoot.
VDD is to be applied prior to VPP and to be removed after VPP is removed.
AC Programming Characteristics (Ta = 25 ± 5 ˚C, V DD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)
Parameter
Address setup time Note 2 (to MD0 ↓)
Conditions
MIN.
TYP.
MAX.
Unit
Symbol
Note 1
tAS
tAS
2
µs
MD1 setup time
(to MD0 ↓)
TM1S
tOES
2
µs
Data setup time
(to MD0 ↓)
tDS
tDS
2
µs
Address hold time Note 2 (from MD0 ↑)
TAH
tAH
2
µs
(from MD0 ↑)
tDH
tDH
2
µs
MD0 ↑ → data output float delay time
tDF
tDF
0
VPP setup time
(to MD3 ↑)
tVPS
tVPS
2
µs
VDD setup time
(to MD3 ↑)
tVDS
tVCS
2
µs
Initialized program pulse width
tPW
tPW
0.95
Additional program pulse width
tOPW
tOPW
0.95
tM0S
tCES
2
tDV
tDV
MD0 = MD1 = VIL
(to MD0 ↑)
tM1H
tOEH
tM1H + tM1R ≥ 50 µs
(from MD0 ↓)
tM1R
Data hold time
MD0 setup time
(to MD1 ↑)
MD0 ↓ → data output delay time
130
1.0
ns
1.05
ms
21.0
ms
µs
1
µs
2
µs
tOR
2
µs
tPCR
–
10
µs
tXH, tXL
–
0.125
µs
X1 input frequency
fX
–
Initial mode set time
tI
–
2
µs
(to MD1 ↑)
tM3S
–
2
µs
(from MD1 ↓)
tM3H
–
2
µs
(to MD0 ↓)
tM3SR
–
During program read cycle
2
µs
Address Note 2 → Data output delay time
tDAD
tACC
During program read cycle
2
µs
Address Note 2 → Data output hold time
tHAD
tOH
During program read cycle
0
(from MD0 ↑)
tM3HR
–
During program read cycle
2
µs
MD3 ↓ → Data output float delay time
tDFR
–
During program read cycle
2
µs
MD1 hold time
MD1 recovery time
Program counter reset time
X1 input low- and high-level width
MD3 setup time
MD3 hold time
MD3 setup time
MD3 hold time
4.19
130
MHz
ns
Notes 1. These symbols correspond to those of the µPD27C256A.
2. The internal address signal is incremented by the rising edge of the fourth X1 pulse; it is not
connected to an external pin.
25
µPD75P218
Program Memory Write Timing
tVPS
VPP
VPP
VDD
tVDS
VDD
VDD+1
VDD
tXH
X1
P40 - P43
P50 - P53
tDS
tI
tXL
Output
data
Input data
tOH
tDV
Input data
tDS
tDF
Input data
tDH
tAH
tAS
MD0
tPW
tM1R
tM0S
tOPW
MD1
tPCR
tM1S
tM1H
MD2
tM3H
tM3S
MD3
Program Memory Read Timing
tVPS
VPP
VPP
VDD
tVDS
VDD
VDD+1
VDD
tXH
X1
tXL
tDAD
tHAD
P40 - P43
P50 - P53
Output data
tDV
tI
MD1
tPCR
MD2
tM3SR
26
tDFR
tM3HR
MD0
MD3
Output data
µPD75P218
PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
1
32
A
K
H
J
I
L
G
6.
F
D
N
M
NOTE
M
B
C
ITEM MILLIMETERS
R
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
58.68 MAX.
2.311 MAX.
B
1.78 MAX.
0.070 MAX.
2) Item "K" to center of leads when formed parallel.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
17.0
0.669
M
0.25 +0.10
–0.05
0.010+0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
P64C-70-750A,C-1
27
µPD75P218
64 PIN PLASTIC QFP (14×20)
A
B
33
32
64
1
20
19
detail of lead end
F
Q
5°±5°
D
C
S
51
52
G
H
I M
J
M
P
K
N
L
P64GF-100-3B8,3BE,3BR-1
NOTE
Each lead centerline is located within 0.20
mm (0.008 inch) of its true position (T.P.) at
maximum material condition.
28
ITEM
MILLIMETERS
INCHES
A
23.6 ± 0.4
0.929 ± 0.016
B
20.0 ± 0.2
0.795+0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
1.0
0.039
H
0.40 ± 0.10
0.016 +0.004
–0.005
I
0.20
0.008
J
1.0 (T.P.)
0.039 (T.P.)
K
1.8 ± 0.2
0.071–0.009
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.12
0.005
P
2.7
Q
0.1 ± 0.1
S
3.0 MAX.
+0.008
0.106
0.004 ± 0.004
0.119 MAX.
µPD75P218
64 PIN CERAMIC WQFN
A
K
Q
C
D
B
T
S
W
64
U
H
I
1
M
R
F
E
G
J
X64KW-100A-2
NOTE
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
20.0 ± 0.4
0.787+0.017
–0.016
B
19.0
0.748
C
13.2
0.520
D
14.0 ± 0.4
0.551 ± 0.016
E
1.64
0.065
F
2.14
0.084
G
3.556 MAX.
0.140 MAX.
H
0.7 ± 0.10
0.028+0.004
–0.005
I
0.10
0.004
J
1.0 (T.P.)
0.039 (T.P.)
K
1.0 ± 0.2
0.039+0.009
–0.008
Q
C 0.25
C 0.010
R
1.0
0.039
S
1.0
0.039
T
R 3.0
R 0.118
U
12.0
0.472
W
0.8 ± 0.2
0.031 –0.008
+0.009
29
µPD75P218
7.
RECOMMENDED SOLDERING CONDITIONS
The following conditions (See table below) must be met when soldering this product.
Please consult with our sales offices in case other soldering process is used, or in case soldering is done
under different conditions.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(IEI-1207).
TYPE OF SURFACE MOUNT DEVICE
µPD75P218GF-3BR
Soldering Process
Soldering Conditions
Symbol
Wave Soldering
Solder temperature: 260 ˚C or lower,
Flow time: 10 seconds or less,
Exposure limit Note: 7 days (10 hour pre-baking is required at 125 ˚C
afterwards)
Number of flow processes: 1
WS60-107-1
Infrared Ray Reflow
Peak temperature of package surface: 230 ˚C or lower
Reflow time: 30 seconds or less (210 ˚C or higher),
Number of reflow processes: 1
Exposure limit Note: 7 days (10 hour pre-baking is required at 125 ˚C
afterwards)
IR30-107-1
VPS
Peak temperature of package surface: 215 ˚C or lower
Reflow time: 40 seconds or less (200 ˚C or higher),
Number of reflow processes: 1
Exposure limit Note: 7 days (10 hour pre-baking is required at 125 ˚C
afterwards)
VP15-107-1
Partial Heating
Method
Pin temperature: 300 ˚C or lower,
Time: 3 seconds or less (Per side of the package)
–
Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 ˚C and
relative humidity at 65 % or less.
Caution Do not apply more than one soldering method at any one time, except for "Partial heating method".
TYPE OF THROUGH HOLE DEVICE
µPD75P218CW
Soldering Process
Soldering Conditions
Wave Soldering
(only lead part)
Solder temperature: 260 ˚C or lower,
Flow time: 10 seconds or less
Partial Heating
Method
Pin temperature: 260 ˚C or lower,
Time: 10 seconds or less
Caution This wave soldering should be applied only to lead part, and do not jet molten solder on the surface
of package.
30
µPD75P218
APPENDIX DEVELOPMENT TOOLS
The following development tools are provided for the development of a system which employs the
µPD75P218.
Language processor
RA75X relocatable assembler
This program converts symbolic source code for the µPD75000 series of
microcomputers into executable absolute address object code.
There are also functions such as generating a symbol table and optimizing
branch instructions automatically.
Host machine
Part number
OS
PC-9800 series
IBM PC series
Distribution media
MS-DOSTM
Ver. 3.10
to
Ver. 3.30C
3.5-inch 2HD
µS5A13RA75X
5-inch 2HD
µS5A10RA75X
PC DOSTM
(Ver. 3.1)
5-inch 2HC
µS7B10RA75X
PROM programming tools
Hardware
PG-1500
PA-75P216ACW
The PG-1500 PROM programmer is used together with an accessory board
and optional program adapter. It allows the user to program a single chip
microcomputer containing PROM and typical 256K-bit to 1M-bit PROMs
from a keyboard or a remote control.
PROM programmer adapter dedicated to µPD75P218CW.
Connect the programmer adapter to PG-1500 for use.
PA-75P218GF
PROM programmer adapter dedicated to µPD75P218GF.
Connect the programmer adapter to PG-1500 for use.
PA-75P218KB
PROM programmer adapter dedicated to µPD75P218KB.
Connect the programmer adapter to PG-1500 for use.
Software
PG-1500 controller
This program enables the host machine to control the PG-1500 through the
serial and parallel interfaces.
Host machine
Part number
OS
PC-9800 series
IBM PC series
Distribution media
MS-DOS
Ver. 3.10
to
Ver. 3.30C
3.5-inch 2HD
µS5A13PG1500
5-inch 2HD
µS5A10PG1500
PC DOS
(Ver. 3.1)
5-inch 2HC
µS7B10PG1500
31
µPD75P218
Debugging tools
Hardware
IE-75000-R Note 1
IE-75000-R-EM Note 2
The IE-75000-R-EM is an emulation board for the IE-75000-R and IE-75001-R.
The IE-75000-R contains the emulation board. The emulation board is used
together with the IE-75000-R or IE75001-R to evaluate the µPD75P218.
IE-75001-R
The IE-75001-R is an in-circuit emulator available for the 75X series.
This emulator is used together with the IE-75000-R-EMNote 2 emulation
board and emulation probe to develop application systems of the
µPD75P218. For efficient debugging, the emulator is connected to the host
machine and PROM programmer.
EP-75216ACW-R
Emulation probe for the µPD75P218CW.
Connect this probe to the IE-75000-R or IE-75001-R for use.
EP-75216AGF-R
Emulation probe for the µPD75P218GF. Connect this probe to the
IE-75000-R or IE-75001-R for use.
A 64-pin conversion socket, the EV-9200G-64, attached to the probe
facilitates the connection of the probe with the user system.
EV-9200G-64
Software
The IE-75000-R is an in-circuit emulator available for the 75X series.
This emulator is used together with the emulation probe to develop
application systems of the µPD75P218. For efficient debugging, the emulator is connected to the host machine and PROM programmer.
IE control program
This program enables the host machine to control the IE-75000-R or
IE-75001-R on the host machine through the RS-232-C interface.
Host machine
Part number
OS
PC-9800 series
IBM PC series
Distribution media
3.5-inch 2HD
µS5A13IE75X
to
Ver. 3.30C
5-inch 2HD
µS5A10IE75X
PC DOS
(Ver. 3.1)
5-inch 2HC
µS7B10IE75X
MS-DOS
Ver. 3.10
Notes 1. Provided only for maintenance purposes.
2. The IE-75000-R-EM is an option.
Remark NEC is not responsible for the operation of the IE control program and assembler unless it runs on
any host machine with the operation system listed above.
32
Configuration of Development Tools
In-circuit emulator
Emulation probe
IE-75000-R
IE-75001-R Note 1
Centronics interface
IE-75000-R-EM
RS-232-C
Host machine
PC-9800 series
IBM PC series
(Symbolic debugging
possible)
EP-75216ACW-R
EP-75216AGF-R
IE control
program
Note 2
User system
PROM version
PG-1500
controller
PROM
programmer
mµPD75P216ACW
PD75P216ACW
mµPD75P218CW/GF/KB
PD75P218CW/GF/KB
PG-1500
Programmer adapter
Relocatable
assembler
PA-75P216ACW
PA-75P218GF
PA-75P218KB
33
µPD75P218
Notes 1. IE-75001-R is not provided with IE-75000-R-EM (option).
2. EV-9200G-64
µPD75P218
[MEMO]
34
µPD75P218
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and transported in an antistatic container, static shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should be grounded using wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to
be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to
the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being
an output pin. All handling related to the unused pins must be judged device by device and related
specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS does
not define the initial operation status of the device. Immediately after the power source is turned
ON, the devices with reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset
signal is received. Reset operation must be executed immediately after power-on for devices having
reset function.
35
µPD75P218
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4 92.6
FIP R is a trademark of NEC Corporation.
MS-DOSTM is a trademark of Microsoft Corporation.
PC DOSTM is a trademark of IBM Corporation.
36