DATA SHEET MOS INTEGRATED CIRCUIT µPD432937 2M-BIT CMOS SYNCHRONOUS FAST SRAM 64K-WORD BY 36-BIT PIPELINED OPERATION / HSTL INTERFACE Description The µPD432937 is a 65,536-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell. The µPD432937 integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (K). The µPD432937 is suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory. The µPD432937GF is packaged in 100-pin plastic LQFP for high density and low capacitive loading. Features • 3.3 V (Chip) / 1.6 V (I/O) Supply • Synchronous operation • Internally self-timed write control • Burst read / write : Interleaved burst sequence • Fully registered inputs and outputs for 4-1-1-1 pipelined burst operation • All registers triggered off positive clock edge • Three chip enables for easy depth expansion • Common I/O using three state outputs • Internally controlled burst advance • Free running active high and active low echo clock outputs • AND tree testability • Power down mode : ZZ pin used to place SRAM in power down mode. Stop clock method for power down mode. Part number • µPD432937 Class Clock Maximum supply current Supply voltage frequency Active Standby Chip I/O MHz mA mA V V A28 360 420 60 3.3 ± 0.2 1.6 + 0.1/ A29 350 400 A31 325 A33 300 A36 275 A40 250 350 − 0.15 50 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14018EJ3V0DS00 (3rd edition) Date Published January 2000 NS CP(K) Printed in Japan The mark ★ shows major revised points. © 1999 µPD432937 Ordering Information Part number Clock frequency Package MHz • µPD432937GF-A28 360 µPD432937GF-A29 350 µPD432937GF-A31 325 µPD432937GF-A33 300 µPD432937GF-A36 275 µPD432937GF-A40 250 2 100-PIN PLASTIC LQFP (14 x 20) Data Sheet M14018EJ3V0DS00 µPD432937 Pin Configuration (Marking Side) /××× indicates active low signal. 100-PIN PLASTIC LQFP (14 x 20) A9 A8 NC /RESET /AC NC VDDQ /GW K VSS VDD /CE2 /K VDDQ ZZ RES CE2 /CE A7 A6 [ µPD432937GF ] 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 1 80 I/OP2 I/O17 2 79 I/O16 I/O18 3 78 I/O15 VDDQ 4 77 VDDQ VSSQ 5 76 VSSQ I/O19 6 75 I/O14 I/O20 7 74 I/O13 I/O21 8 73 I/O12 I/O22 9 72 I/O11 VSSQ 10 71 VSSQ VDDQ 11 70 VDDQ I/O23 12 69 I/O10 I/O24 13 68 I/O9 /KQA 14 67 VSS VDD 15 66 /KQB KQA 16 65 VDD VSS 17 64 KQB I/O25 18 63 I/O8 I/O26 19 62 I/O7 VDDQ 20 61 VDDQ VSSQ 21 60 VSSQ I/O27 22 59 I/O6 I/O28 23 58 I/O5 I/O29 24 57 I/O4 I/O30 25 56 I/O3 VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ I/O31 28 53 I/O2 I/O32 29 52 I/O1 I/OP4 30 51 I/OP1 TO A15 A14 A13 A12 A11 A10 VREF NC VDD VSS /TE VREF A0 A1 A2 A3 A4 A5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC • Remark Refer to Package Drawing for 1-pin index mark. Data Sheet M14018EJ3V0DS00 3 µPD432937 Pin Identification Symbol Pin number Description A0 - A15 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 Synchronous Address Input I/O1 - I/O32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, Synchronous Data In, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 Synchronous Data Out I/OP1 - I/OP4 51, 80, 1, 30 Synchronous Data In (Parity), Synchronous Data Out (Parity) KQA, /KQA, KQB, /KQB 16, 14, 64, 66 Echo Clock Output /AC 85 Synchronous Address Status Input /CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input /GW 88 Synchronous Global Write Input K, /K 89, 93 Differential Input Clock Pair /RESET 84 Asynchronous Input Initialize internal state at power up ZZ 95 Asynchronous Power Down State Input /TE 39 Test Enable Input TO 50 Test Output VREF 38, 43 Input Reference Voltage VDD 15, 41, 65, 91 Power Supply VSS 17, 40, 67, 90 Ground VDDQ 4, 11, 20, 27, 54, 61, 70, 77, 87, 94 Output Buffer Power Supply VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground NC 31, 42, 83, 86 No Connection RES 96 Reserved It must be tied LOW during normal operation 4 Data Sheet M14018EJ3V0DS00 µPD432937 Block Diagram A0 - A15 16 Address register 16 A0, A1 Binary Q1 A1’ counter and logic CLR Q0 A0’ K /AC /RESET 14 Row and column decoders Advance control Write driver Write controller Memory matrix 1,024 rows 64 × 36 columns /GW (2,359,296 bits) /CE CE2 /CE2 /OE Data output enable, Data output strobe 36 36 Output registers Output buffers Strobe_Out Input registers 36 I/O1 - I/O32 I/OP1 - I/OP4 Echo clock registers /K Echo clock buffers 4 KQA, /KQA KQB, /KQB ZZ Power down control Burst Sequence Interleaved Burst Sequence Table External Address A15 - A2, A1, A0 1st Burst Address A15 - A2, A1, /A0 2nd Burst Address A15 - A2, /A1, A0 3rd Burst Address A15 - A2, /A1, /A0 Data Sheet M14018EJ3V0DS00 5 µPD432937 Synchronous Truth Table Operation /CE CE2 /CE2 /AC /GW I/O Address H × × L × Hi-Z None L L × L × Hi-Z None L × H L × Hi-Z None Read Cycle / Begin Burst L H L L H Hi-Z External Read Cycle / Continue Burst × × × H × Hi-Z Current Read Cycle / Continue Burst × × × H × Hi-Z Current Read Cycle / Continue Burst × × × H × Data-out Next Read Cycle / Continue Burst × × × H × Data-out Next Read Cycle / Continue Burst × × × H × Data-out Next Read Cycle / Continue Burst × × × H × Data-out None Write Cycle / Begin Burst L H L L L Hi-Z External Write Cycle / Continue Burst × × × H L Data-in Current Write Cycle / Continue Burst × × × H L Data-in Current Write Cycle / Continue Burst × × × H L Data-in Next Write Cycle / Continue Burst × × × H × Data-in Next Write Cycle / Continue Burst × × × H × Hi-Z Next Deselected Deselected Deselected Note Note Note Note Deselect status is held until new “Begin Burst” entry. Remark × : don’t care Asynchronous Truth Table ZZ /RESET /TE I/O Operation H H H Hi-Z Sleep Mode × L H Hi-Z Reset × × L Hi-Z Test Mode L H H Data-out Read L H H Data-in Write Remark × : don’t care 6 Data Sheet M14018EJ3V0DS00 µPD432937 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Conditions MIN. TYP. MAX. Unit Note VDD –0.5 +4.0 V VDDQ –0.5 VDD V Input voltage VIN –0.5 VDDQ + 0.5 V 1 Input / Output voltage VI/O –0.5 VDDQ + 0.5 V 1 Operating ambient temperature TA 0 70 °C Storage temperature Tstg –55 +125 °C Output supply voltage Note 1. –1.0 V (MIN.) (Pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to 70 °C) Parameter • Symbol MIN. TYP. MAX. Unit VDD 3.1 3.3 3.5 V VDDQ 1.45 1.6 1.7 V High level input voltage VIH VREF + 0.1 VDDQ + 0.3 V Low level input voltage VIL –0.3 VREF – 0.1 V Input reference voltage VREF 0.725 VDDQ / 2 0.85 V MIN. TYP. MAX. Unit Supply voltage Output supply voltage • Conditions Note 1 Note 1. –1.0 V (MIN.) (Pulse width : 2 ns) Recommended AC Operating Conditions (TA = 0 to 70 °C) Parameter Symbol Conditions Input reference voltage VREF(RMS) –5 % +5 % V Low level input voltage VIL –0.3 VREF – 0.2 V High level input voltage VIH VREF + 0.2 VDDQ + 0.3 V MAX. Unit Note Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. Input capacitance CIN VIN = 0 V 7 pF Input / Output capacitance CI/O VI/O = 0 V 7 pF Clock input capacitance Cclk Vclk = 0 V 7 pF Note 1 Note 1. Cclk is for both K and /K. Remark These parameters are periodically sampled and not 100% tested. Data Sheet M14018EJ3V0DS00 7 µPD432937 • DC Characteristics (TA = 0 to 70 °C, VDD = 3.3 V ± 0.2 V) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current ILI VIN = 0 V to VDD –2 +2 µA I/O leakage current ILO VI/O = 0 V to VDD, Output disabled. –2 +2 µA Operating supply current IDD Device selected, Cycle = MAX., -A28 420 mA VIN ≤ 0.2 V or VIN ≥ VDDQ – 0.2 V -A29 400 -A31 400 -A33 350 -A36 350 -A40 350 All outputs toggling, Cycle = MAX., -A28 450 CL = 20 pF -A29 437 -A31 406 -A33 374 -A36 343 -A40 311 Device deselected, Cycle = MAX., -A28 150 VIN ≤ 0.2 V or VIN ≥ VDDQ – 0.2 V, -A29 150 All inputs are static. -A31 150 -A33 110 -A36 110 -A40 110 Device deselected, -A28 60 Cycle = 0 MHz, -A29 60 VIN ≤ 0.2 V or VIN ≥ VDDQ – 0.2 V, -A31 60 All inputs are static. -A33 50 -A36 50 -A40 50 ISB2 Sleep Mode (ZZ = VIH), All inputs are static. 5.0 High level output voltage VOH VDDQ = 1.45 to 1.7 V, IOH = –1 mA Low level output voltage VOL VDDQ = 1.45 to 1.7 V, IOL = +1 mA Operating VDDQ supply IDDQ current Standby supply current ISB ISB1 Note 1. See next page. 8 Data Sheet M14018EJ3V0DS00 VDDQ – 0.4 mA mA mA mA V 0.4 V Note 1 µPD432937 • AC Characteristics (TA = 0 to 70 °C, VDD = 3.3 V ± 0.2 V, VDDQ = 1.45 to 1.7 V) AC Test Conditions Input waveform (Rise / Fall time : 1.0 V / ns) VDDQ VDDQ/2 Test points VDDQ/2 VDDQ/2 Test points VDDQ/2 0V Output waveform Output load condition VREF = VDDQ / 2 VREF = VDDQ / 2 VREF µ PD432937 50 Ω ZO = 50 Ω OUT Test point CL : 20 pF Remark CL includes capacitances of the probe and jig, and stray capacitances. Data Sheet M14018EJ3V0DS00 9 µPD432937 • Read and Write Cycle Parameter Symbol -A28 -A29 -A31 -A33 -A36 -A40 Unit (360 MHz) (350 MHz) (325 MHz) (300 MHz) (275 MHz) (250 MHz) MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Clock cycle time TKHKH 2.77 − 2.85 − 3.07 − 3.3 − 3.6 − 4.0 − ns Clock high pulse width TKHKL 1.03 − 1.06 − 1.15 − 1.24 − 1.36 − 1.49 − ns Clock low pulse width TKLKH 1.03 − 1.06 − 1.15 − 1.24 − 1.36 − 1.49 − ns Clock (K) to clock (/K) TKHKB 1.28 1.55 1.33 1.60 1.43 1.72 1.55 1.86 1.69 2.04 1.87 2.24 ns Clock to echo clock (/KQ) TKHKE 1.1 2.0 1.1 2.1 1.1 2.3 1.1 2.6 1.1 2.9 1.1 3.2 ns TQVKE 0.9 − 0.9 − 0.9 − 0.9 − 0.9 − 0.9 − ns TKEQX 0.9 − 0.9 − 0.9 − 0.9 − 0.9 − 0.9 − ns TAVKH 0.75 − 0.8 − 0.9 − 1.0 − 1.1 − 1.3 − ns TADSVKH 0.75 − 0.8 − 0.9 − 1.0 − 1.1 − 1.3 − ns low Output setup to echo clock (/KQ) Output hold from echo clock (/KQ) Setup time Address Address status Hold time Data-in TDVKH 0.85 − 0.9 − 1.0 − 1.1 − 1.2 − 1.4 − ns Global write TWVKH 0.75 − 0.8 − 0.9 − 1.0 − 1.1 − 1.3 − ns Chip enable TCVKH 0.75 − 0.8 − 0.9 − 1.0 − 1.1 − 1.3 − ns Address TKHAX 2.65 − 2.8 − 3.1 − 3.4 − 3.8 − 4.2 − ns TKHADSX 0.40 − 0.45 − 0.55 − 0.65 − 0.8 − 0.9 − ns Address status Data-in TKHDX 0.30 − 0.35 − 0.45 − 0.55 − 0.7 − 0.85 − ns Global write TKHWX 0.40 − 0.45 − 0.55 − 0.65 − 0.8 − 0.9 − ns Chip enable TKHCX 2.65 − 2.8 − 3.1 − 3.4 − 3.8 − 4.2 − ns TZZR 2 − 2 − 2 − 2 − 2 − 2 − clocks ZZ recovery time 10 Data Sheet M14018EJ3V0DS00 Note µPD432937 READ - READ - WRITE K /K /AC Address A3 A2 A1 /GW /CEs Note D1(A3) D2(A3) D3(A3) D4(A3) Data In Q1(A1) Q2(A1) Q3(A1) Q4(A1) Data Out Q1(A2) Q2(A2) Q3(A2) Q4(A2) KQ /KQ Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence. READ - DESELECT (standby) - READ K /K /AC Address A1 A3 A2 /GW /CEs Note Data In Data Out Q1(A1) Q2(A1) Q3(A1) Q4(A1) Q1(A3) Q2(A3) Q3(A3) Q4(A3) KQ /KQ Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Remark Qn(A1) refers to output from address A1. Q1-Q4 refer to outputs according to burst sequence. Data Sheet M14018EJ3V0DS00 11 µPD432937 WRITE - WRITE - READ K /K /AC Address A3 A2 A1 /GW /CEs Note Data In D1(A1) D2(A1) D3(A1) D4(A1) D1(A2) D2(A2) D3(A2) D4(A2) Q1(A3) Q2(A3) Q3(A3) Q4(A3) Data Out KQ /KQ Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Remark Qn(A3) refers to output from address A3. Q1-Q4 refer to outputs according to burst sequence. DUAL BANK READ K /K /AC Address A1 A3 A2 /GW /CE Data Out Bank 1 Q1(A1) Q2(A1) Q3(A1) Q4(A1) Data Out Bank 2 Q1(A3) Q2(A3) Q3(A3) Q4(A3) Q1(A2) Q2(A2) Q3(A2) Q4(A2) /KQ Bank 1 /KQ Bank 2 CE2, /CE2 Bank 1 Bank 2 Bank 1 Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence. 12 Data Sheet M14018EJ3V0DS00 µPD432937 STOP CLOCK OPERATION (READ) K /K /AC Address A2 A1 /GW /CEs Note Data In Q1(A1) Q2(A1) Q3(A1) Q4(A1) Data Out Q1(A2) Q2(A2) Q3(A2) Q4(A2) KQ /KQ Power down state (ISB1) Invalid clocks Wakeup cycles Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence. STOP CLOCK OPERATION (WRITE) K /K /AC Address A2 A1 /GW /CEs Note Data In D1(A1) D2(A1) D3(A1) D4(A1) D1(A2) D2(A2) D3(A2) D4(A2) Data Out KQ /KQ Power down state (ISB1) Invalid clocks Wakeup cycles Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Data Sheet M14018EJ3V0DS00 13 µPD432937 STOP CLOCK OPERATION (DESELECT) K /K /AC A2 Address /GW /CEs Note Data In Data Out Q1(A1) Q2(A1) Q3(A1) Q4(A1) Q1(A2) Q2(A2) Q3(A2) Q4(A2) KQ /KQ Power down state (ISB1) Invalid clocks Wakeup cycles Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence. POWER DOWN CYCLE (using ZZ) K /K Address A1 A2 /AC /GW /CE1 CE2 /CE2 KQ /KQ Data Out Q1(A1) Q2(A1) Q3(A1) Q4(A1) TZZR ZZ Remark Qn(A1) refers to output from address A1. Q1-Q4 refer to outputs according to burst sequence. 14 Data Sheet M14018EJ3V0DS00 µPD432937 POWER DOWN CYCLE (using STOP CLOCK Method) K Address A2 A1 /AC /GW /CE1 CE2 /CE2 KQ Data Out Q1(A1) Q2(A1) Q3(A1) Q4(A1) Remark Qn(A1) refers to output from address A1. Q1-Q4 refer to outputs according to burst sequence. Data Sheet M14018EJ3V0DS00 15 µPD432937 READ CYCLE TKHKH TKHKL VIH K VIL TKHKB TKLKH /K TADSVKH TKHADSX /AC TKHAX TAVKH Address A1 A2 TWVKH TKHWX /GW TCVKH TKHCX /CEs Note Data In Q1(A1) Data Out Q2(A1) Q3(A1) Q4(A1) Q1(A2) Q2(A2) TQVKE Q3(A2) TKEQX KQ /KQ TKHKE Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence. 16 Data Sheet M14018EJ3V0DS00 Q4(A2) µPD432937 WRITE CYCLE TKHKH TKHKL VIH K VIL TKHKB TKLKH /K TADSVKH TKHADSX /AC TKHAX TAVKH Address A1 A2 TWVKH TKHWX /GW TCVKH TKHCX /CEs Note Data In TDVKH TKHDX D1(A1) D2(A1) D3(A1) D4(A1) D1(A2) D2(A2) D3(A2) D4(A2) Data Out KQ /KQ Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Data Sheet M14018EJ3V0DS00 17 µPD432937 TIMING DIAGRAM REFERENCE for CENTERED ECHO CLOCK TKHKH K TKHKB /K Data[18:1] D1 D1 D1 D2 D2 D2 D3 D3 D3 Latest data /KQ Earliest echo clock Earliest data KQ Latest echo clock RESET OPERATION K /AC /RESET 8 cycles 4 cycles Power-On /RESET de-asserts First cycle from /RESET de-asserted Remark This device needs this RESET OPERATION after power-up. 18 Data Sheet M14018EJ3V0DS00 µPD432937 Testability Testability in this device is achieved by the use of a cascaded AND tree structure. Test mode is selected by asserting the Test Enable pin (/TE) low. When in Test Mode, the all of the pins of this device that make an actual connection with the die, with the exception of /TE, Test Out (TO), VDD, VDDQ, VREF, VSS and all clock pins, act as inputs to a large, cascaded AND tree structure to produce a single output on the Test Out (TO) pin. Input voltages during test mode are operated off VDDQ. During test mode, VREF will operate as normal within the range specified in the DC Characteristic section earlier in this document. A simplified illustration of this AND tree is shown below. By walking specific values around the pins of this device, open connections between the circuit board and this device can be detected on the TO pin. When /TE is deasserted, the device operates in a normal manner. AND TREE STRUCTURE EXAMPLE I/O pad I/O pad I/O pad Test out /TE I/O pad I/O pad I/O pad Truth Table for /TE and TO Pins /TE TO Mode 0 AND of all listed inputs Test Mode 1 Hi-Z Normal Mode Data Sheet M14018EJ3V0DS00 19 µPD432937 Test input assignments for µPD432937 (64 K words x 36 bits), 100 pin plastic LQFP 20 Signal Pin Signal Pin Signal Pin Signal Pin I/OP3 1 I/O31 28 A10 44 I/O3 56 I/O17 2 A7 99 A11 45 I/O4 57 I/O18 3 A6 100 A12 46 I/O5 58 I/O19 6 I/O32 29 A1 36 I/O6 59 I/O20 7 I/OP4 30 A0 37 I/O7 62 I/O21 8 A5 32 RES 96 I/O8 63 I/O22 9 /CE 98 /RESET 84 I/O9 68 I/O23 12 /CE2 92 A13 47 I/O10 69 I/O24 13 ZZ 95 A14 48 I/O11 72 I/O25 18 A4 33 A15 49 I/O12 73 I/O26 19 A3 34 A9 81 I/O13 74 I/O27 22 A2 35 A8 82 I/O14 75 I/O28 23 CE2 97 I/OP1 51 I/O15 78 I/O29 24 /GW 88 I/O1 52 I/O16 79 I/O30 25 /AC 85 I/O2 53 I/OP2 80 Data Sheet M14018EJ3V0DS00 µPD432937 Package Drawing 100-PIN PLASTIC LQFP (14x20) A B 80 81 51 50 detail of lead end S C D R Q 31 30 100 1 F G H I J M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 22.0±0.2 B 20.0±0.2 C 14.0±0.2 D 16.0±0.2 F 0.825 G 0.575 H 0.32 +0.08 −0.07 I J 0.13 0.65 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.06 −0.05 N 0.10 P 1.4 Q 0.125±0.075 R +7° 3° −3° S 1.7 MAX. S100GF-65-8ET-1 Data Sheet M14018EJ3V0DS00 21 µPD432937 Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the µPD432937. Type of Surface Mount Devices µPD432937GF : 100-PIN PLASTIC LQFP (14 x 20) 22 Data Sheet M14018EJ3V0DS00 µPD432937 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14018EJ3V0DS00 23 µPD432937 • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8