NEC UPD703015AYGC

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703014A, 703014AY, 703015A,
703015AY, 703017A, 703017AY
TM
V850/SA1
32-/16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY (V850/SA1) are 32-/16-bit singlechip microcontrollers that include the CPU core of the V850 FamilyTM, and peripheral functions such as ROM/RAM,
timer/counters, serial interfaces, an A/D converter, a timer, and a DMA controller.
In addition to its high real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1
includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions,
all of which are instructions suited to digital servo control applications. As a real-time control system, this device
provides a high-level cost performance ideal for applications ranging from low-power camcorders and other AV
equipment to portable telephone equipment such as cellular phones and personal handyphone systems (PHS).
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SA1 User’s Manual Hardware:
U12768E
TM
U10243E
V850 Family User’s Manual Architecture:
FEATURES
{ Interrupts and exception
{ Number of instructions: 74
{ Minimum instruction execution time:
External: 8, internal: 23, exception: 1
59 ns (@ 17 MHz operation with main system clock (fXX))
{ I/O lines Total: 85
50 ns (@ 20 MHz operation with main system clock (fXX))
30.5 µs (@ 32.768 kHz operation with subsystem clock (fXT))
{ Timer/counters
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set:
16-bit timer:
2 channels
8-bit timer:
4 channels
{ Watch timer: 1 channel
Signed multiplication, saturation operations, 32-bit
{ Watchdog timer: 1 channel
shift instructions, bit manipulation instructions,
{ Serial interface (SIO)
load/store instructions
Asynchronous serial interface (UART)
{ Memory space:
Clocked serial interface (CSI)
I2C bus interface
16 MB linear address space
Memory block allocation function: 2 MB per block
{ External bus interface: 16-bit data bus
(µPD703014AY, 703015AY, 703017AY)
{ A/D converter: 12 channels
{ DMA controller: 3 channels
Address bus: Separate output enabled
{ RTP: 8 bits × 1 channel or 4 bits × 2 channels
{ Internal memory
Mask ROM: 64 KB (µPD703014A, 703014AY)
{ Power-saving functions: HALT/IDLE/STOP modes
128 KB (µPD703015A, 703015AY)
{ Packages: 100-pin plastic LQFP (14 × 14)
256 KB (µPD703017A, 703017AY)
121-pin plastic FBGA (12 × 12)
RAM: 4 KB
(µPD703014A, 703014AY, 703015A, 703015AY)
8 KB (µPD703017A, 703017AY)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14526EJ2V0DS00 (2nd edition)
Date Published September 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
2000
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
APPLICATIONS
{ Low-power portable devices
Cellular phones, PHSs, and camcorders
ORDERING INFORMATION
Part Number
Internal ROM
µPD703014AGC-×××-8EU
100-pin plastic LQFP (fine-pitch) (14 × 14)
64 KB (Mask ROM)
µPD703014AF1-×××-EA6
121-pin plastic FBGA (12 × 12)
64 KB (Mask ROM)
µPD703014AYGC-×××-8EU
100-pin plastic LQFP (fine-pitch) (14 × 14)
64 KB (Mask ROM)
µPD703014AYF1-×××-EA6
121-pin plastic FBGA (12 × 12)
64 KB (Mask ROM)
µPD703015AGC-×××-8EU
100-pin plastic LQFP (fine-pitch) (14 × 14)
128 KB (Mask ROM)
µPD703015AF1-×××-EA6
121-pin plastic FBGA (12 × 12)
128 KB (Mask ROM)
µPD703015AYGC-×××-8EU
100-pin plastic LQFP (fine-pitch) (14 × 14)
128 KB (Mask ROM)
µPD703015AYF1-×××-EA6
121-pin plastic FBGA (12 × 12)
128 KB (Mask ROM)
µPD703017AGC-×××-8EU
100-pin plastic LQFP (fine-pitch) (14 × 14)
256 KB (Mask ROM)
µPD703017AF1-×××-EA6
121-pin plastic FBGA (12 × 12)
256 KB (Mask ROM)
µPD703017AYGC-×××-8EU
100-pin plastic LQFP (fine-pitch) (14 × 14)
256 KB (Mask ROM)
µPD703017AYF1-×××-EA6
121-pin plastic FBGA (12 × 12)
256 KB (Mask ROM)
Remark
2
Package
××× indicates ROM code suffix.
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
PIN CONFIGURATION
100-pin plastic LQFP (fine-pitch) (14 × 14)
µPD703014AGC-×××-8EU
µPD703014AYGC-×××-8EU
µPD703015AGC-×××-8EU
µPD703015AYGC-×××-8EU
µPD703017AGC-×××-8EU
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P20/SI2
P15/SCK1/ASCK0
P14/SO1/TXD0
P13/SI1/RXD0
P12/SCK0/SCLNote 2
P11/SO0
P10/SI0/SDANote 2
P07/INTP6
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
µPD703017AYGC-×××-8EU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P71/ANI1
P70/ANI0
AVREF
AVSS
AVDD
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BVSS
BVDD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P107/RTP7/A12
P110/A1
P111/A2
P112/A3
P113/A4
RESET
P114/XT1
XT2
VDD
X2
X1
VSS
CLKOUT
P120/WAIT
P90/LBEN/WRL
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P96/HLDRQ
P40/AD0
P41/AD1
P42/AD2
P43/AD3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P21/SO2
P22/SCK2
P23/RXD1
P24/TXD1
P25/ASCK1
VDD
VSS
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10
P33/TI11
P34/TO0/A13
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
ICNote 1
P100/RTP0/A5
P101/RTP1/A6
P102/RTP2/A7
P103/RTP3/A8
P104/RTP4/A9
P105/RTP5/A10
P106/RTP6/A11
Notes 1. Connect the IC pin directly to VSS.
2. Applies to the µPD703014AY, 703015AY, and 703017AY only.
Data Sheet U14526EJ2V0DS00
3
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
121-pin plastic FBGA (12 × 12)
µPD703014AF1-×××-EA6
µPD703015AF1-×××-EA6
µPD703017AF1-×××-EA6
µPD703014AYF1-×××-EA6
µPD703015AYF1-×××-EA6
µPD703017AYF1-×××-EA6
Top View
Bottom View
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N
N M L K J H G F E D C B A
Pin
Pin
Pin
Pin
Pin
Pin
Pin Name
Pin Name
Pin Name
Pin Name
Pin Name
Pin Name
Number
Number
Number
Number
Number
Number
A1
P20
B8
P83
D2
VDD
G11
P60
K13
BVDD
M7
VSS
A2
P15
B9
P80
D3
VSS
G12
P56
L1
P104
M8
VSS
A3
VSS
B10
P75
D11
AVDD
G13
P57
L2
P105
M9
P92
A4
P13
B11
AVSS
D12
AVDD
H1
P34
L3
RESET
M10
P95
A5
P11
B12
AVSS
D13
AVDD
H2
P37
L4
VDD
M11
P41
A6
P06
B13
P71
E1
P25
H3
P35
L5
VSS
M12
P45
A7
P03
C1
P22
E2
VDD
H11
P55
L6
X2
M13
P44
A8
P00
C2
P23
E3
P30
H12
P53
L7
P90
N1
P107
A9
P81
C3
VSS
E11
AVDD
H13
P54
A10
P76
C4
P24
E12
P64
J1
IC
A11
P73
C5
P07
E13
P65
J2
A12
P72
C6
P04
F1
P26
J3
A13
AVSS
C7
P01
F2
P27
J11
P52
B1
P21
C8
P82
F3
P33
J12
P50
B2
P14
C9
P77
F11
P63
J13
P51
B3
VSS
C10
P74
F12
P61
K1
P101
B4
P12
C11
AVSS
F13
P62
K2
B5
P10
C12
P70
G1
P31
K3
B6
P05
C13
AVREF
G2
P32
B7
P02
D1
VDD
G3
P36
Note
L8
P120
N2
P110
Note
L9
P93
N3
P112
IC
Note
L10
P96
N4
VDD
P100
L11
BVSS
N5
XT1
L12
BVSS
N6
VSS
L13
BVSS
N7
VSS
M1
P106
N8
M2
P111
N9
P91
P102
M3
P113
N10
P94
P103
M4
VDD
N11
P40
K11
P46
M5
XT2
N12
P42
K12
P47
M6
X1
N13
P43
CLKOUT
Connect the IC pin directly to VSS.
Remarks 1. Alternate function names are omitted. The alternate functions are identical to the 100-pin plastic
LQFP.
2. Connect the D4 pin directly to VSS.
4
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
PIN IDENTIFICATION
A1 to A21:
Address Bus
P90 to P96:
Port 9
AD0 to AD15:
Address/Data Bus
P100 to P107:
Port 10
ADTRG:
AD Trigger Input
P110 to P114:
Port 11
ANI0 to ANI11:
Analog Input
P120:
Port 12
ASCK0, ASCK1:
Asynchronous Serial Clock
RD:
Read
ASTB:
Address Strobe
RESET:
Reset
AVDD:
Analog VDD
RTP0 to RTP7:
Real-time Port
AVREF:
Analog Reference Voltage
RTPTRG:
RTP Trigger
AVSS:
Analog VSS
R/W:
Read/Write Status
BVDD:
Power Supply for Bus Interface
RXD0, RXD1:
Receive Data
BVSS:
Ground for Bus Interface
SCK0 to SCK2:
CLKOUT:
Clock Output
SCL
DSTB:
Data Strobe
SDA
HLDAK:
Hold Acknowledge
SI0 to SI2:
Serial Input
HLDRQ:
Hold Request
SO0 to SO2:
Serial Output
IC:
Internally Connected
TI00, TI01, TI10, :
Timer Input
INTP0 to INTP6:
Interrupt Request From Peripherals
TI11, TI2 to TI5
LBEN:
Lower Byte Enable
TO0 to TO5:
Timer Output
NMI:
Non-maskable Interrupt Request
TXD0, TXD1:
Transmit Data
P00 to P07:
Port 0
UBEN:
Upper Byte Enable
P10 to P15:
Port 1
VDD:
Power Supply
P20 to P27:
Port 2
VSS:
Ground
P30 to P37:
Port 3
WAIT:
Wait
P40 to P47:
Port 4
WRH:
Write Strobe High Level Data
P50 to P57:
Port 5
WRL:
Write Strobe Low Level Data
P60 to P65:
Port 6
X1, X2:
Crystal for Main Clock
P70 to P77:
Port 7
XT1, XT2:
Crystal for Sub-clock
P80 to P83:
Port 8
Note
Note
:
Note
:
Serial Clock
Serial Clock
Serial Data
Applies to the µPD703014AY, 703015AY, and 703017AY only.
Data Sheet U14526EJ2V0DS00
5
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
INTERNAL BLOCK DIAGRAM
NMI
INTP0 to INTP6
Mask
ROM
CPU
INTC
HLDRQ (P96)
HLDAK (P95)
Instruction
queue
PC
ASTB (P94)
DSTB/RD (P93)
R/W/WRH (P92)
UBEN (P91)
LBEN/WRL (P90)
WAIT
Note 1
TI00, TI01,
TI10, TI11
TO0, TO1
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
Timer/counters
16-bit timer:
TM0, TM1
8-bit timer:
TM2 to TM5
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO2
SI2
SCK2
2
Multiplier
16 x 16 32
System
registers
RAM
Note 2
SIO
SO0
SI0/SDANote 3
SCK0/SCLNote 3
32-bit
barrel shifter
BCU
ALU
A1 to A12
(P100 to P107, P110 to P113)
A13 to A15 (P34 to P36)
General registers
32 bits x 32
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
Note 3
CSI0/I C
CSI1/UART0
Port
CSI2
RTP
CLKOUT
A/D
converter
X1
DMAC: 3 ch
AVDD
AVREF
AVSS
ANI0 to ANI11
ADTRG
UART1
RTP0 to RTP7
RTPTRG
TXD1
RXD1
ASCK1
P120
P114
P110 to P113
P100 to P107
P90 to P96
P80 to P83
P70 to P77
P60 to P65
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P15
P00 to P07
CG
Watch timer
XT1 (P114)
XT2
RESET
VDD
VSS
BVDD
BVSS
Watchdog
timer
IC
Notes 1. µPD703014A, 703014AY: 64 KB
µPD703015A, 703015AY: 128 KB
µPD703017A, 703017AY: 256 KB
2. µPD703014A, 703014AY, 703015A, 703015AY: 4 KB
µPD703017A, 703017AY: 8 KB
3. Applies to the µPD703014AY, 703015AY, and 703017AY only.
6
X2
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
CONTENTS
1.
PIN FUNCTIONS.................................................................................................................................. 8
1.1
Port Pins..................................................................................................................................................... 8
1.2
Non-Port Pins........................................................................................................................................... 11
1.3
Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 14
2.
ELECTRICAL SPECIFICATIONS...................................................................................................... 18
3.
PACKAGE DRAWINGS..................................................................................................................... 42
4.
RECOMMENDED SOLDERING CONDITIONS ............................................................................... 44
Data Sheet U14526EJ2V0DS00
7
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
1. PIN FUNCTIONS
1.1 Port Pins
(1/3)
Pin Name
P00
I/O
PULL
I/O
Yes
P01
Function
Port 0
8-bit I/O port
Input/output can be specified in 1-bit units.
NMI
INTP0
P02
INTP1
P03
INTP2
P04
INTP3
P05
INTP4/ADTRG
P06
INTP5/RTPTRG
P07
INTP6
P10
I/O
Yes
P11
Port 1
6-bit I/O port
Input/output can be specified in 1-bit units.
SI0/SDA
Note
SO0
Note
P12
SCK0/SCL
P13
SI1/RXD0
P14
SO1/TXD0
P15
SCK1/ASCK0
P20
I/O
Yes
P21
Port 2
8-bit I/O port
Input/output can be specified in 1-bit units.
SI2
SO2
P22
SCK2
P23
RXD1
P24
TXD1
P25
ASCK1
P26
TI2/TO2
P27
TI3/TO3
P30
P31
I/O
Yes
Port 3
8-bit I/O port
Input/output can be specified in 1-bit units.
TI00
TI01
P32
TI10
P33
TI11
P34
TO0/A13
P35
TO1/A14
P36
TI4/TO4/A15
P37
TI5/TO5
Note Applies to the µPD703014AY, 703015AY, and 703017AY only.
Remark
8
Alternate Function
PULL: On-chip pull-up resistor
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(2/3)
Pin Name
P40
I/O
PULL
I/O
No
P41
Function
Port 4
8-bit I/O port
Input/output can be specified in 1-bit units.
Alternate Function
AD0
AD1
P42
AD2
P43
AD3
P44
AD4
P45
AD5
P46
AD6
P47
AD7
P50
I/O
No
P51
Port 5
8-bit I/O port
Input/output can be specified in 1-bit units.
AD8
AD9
P52
AD10
P53
AD11
P54
AD12
P55
AD13
P56
AD14
P57
AD15
P60
I/O
No
P61
Port 6
6-bit I/O port
Input/output can be specified in 1-bit units.
A16
A17
P62
A18
P63
A19
P64
A20
P65
A21
P70
Input
No
P71
Port 7
8-bit input port
ANI0
ANI1
P72
ANI2
P73
ANI3
P74
ANI4
P75
ANI5
P76
ANI6
P77
ANI7
P80
P81
Input
No
Port 8
4-bit input port
ANI8
ANI9
P82
ANI10
P83
ANI11
Remark
PULL: On-chip pull-up resistor
Data Sheet U14526EJ2V0DS00
9
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(3/3)
Pin Name
P90
I/O
PULL
I/O
No
P91
Function
Port 9
7-bit I/O port
Input/output can be specified in 1-bit units.
Alternate Function
LBEN/WRL
UBEN
P92
R/W/WRH
P93
DSTB/RD
P94
ASTB
P95
HLDAK
P96
HLDRQ
P100
I/O
Yes
P101
Port 10
8-bit I/O port
Input/output can be specified in 1-bit units.
RTP0/A5
RTP1/A6
P102
RTP2/A7
P103
RTP3/A8
P104
RTP4/A9
P105
RTP5/A10
P106
RTP6/A11
P107
RTP7/A12
P110
I/O
Yes
P111
P112
Port 11
5-bit I/O port
Input/output can be specified in 1-bit units.
P114 is fixed as input only.
P113
Input
No
P120
I/O
No
10
A2
A3
A4
P114
Remark
A1
XT1
Port 12
1-bit I/O port
PULL: On-chip pull-up resistor
Data Sheet U14526EJ2V0DS00
WAIT
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
1.2 Non-Port Pins
(1/3)
Pin Name
A1 to A4
I/O
PULL
Output
Yes
Function
Low-order address bus used for external memory expansion
Alternate Function
P110 to P113
A5 to A12
P100/RTP0 to
P107/RTP7
A13
P34/TO0
A14
P35/TI1
A15
P36/TI4/TO4
A16 to A21
Output
No
High-order address bus used for external memory expansion
P60 to P65
AD0 to AD7
I/O
No
16-bit multiplexed address/data bus used for external memory
expansion
P40 to P47
AD8 to AD15
P50 to P57
ADTRG
Input
Yes
A/D converter external trigger input
P05/INTP4
ANI0 to ANI7
Input
No
Analog input to A/D converter
P70 to P77
ANI8 to ANI11
Input
No
ASCK0
Input
Yes
P80 to P83
Serial clock input for UART0 and UART1
ASCK1
P15/SCK1
P25
ASTB
Output
No
AVDD
−
−
Positive power supply for A/D converter
−
AVREF
Input
−
Reference voltage input for A/D converter
−
AVSS
−
−
Ground potential for A/D converter
−
BVDD
−
−
Positive power supply for bus interface
−
BVSS
−
−
Ground potential for bus interface
−
CLKOUT
Output
−
Internal system clock output
−
DSTB
Output
No
External data strobe signal output
P93/RD
HLDAK
Output
No
Bus hold acknowledge output
P95
HLDRQ
Input
No
Bus hold request input
P96
INTP0 to INTP3
Input
Yes
External interrupt request input (analog noise elimination)
P01 to P04
External interrupt request input (digital noise elimination)
P05/ADTRG
INTP4
External address strobe signal output
P94
INTP5
P06/RTPTRG
INTP6
P07
LBEN
Output
No
External data bus’s low-order byte enable signal output
P90/WRL
NMI
Input
Yes
Non-maskable interrupt request input
P00
RD
Output
No
Read strobe signal output
P93/DSTB
Input
−
Output
Yes
RESET
RTP0 to RTP7
Remark
System reset input
Real-time output port
−
P100/A5 to P107/A12
PULL: On-chip pull-up resistor
Data Sheet U14526EJ2V0DS00
11
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(2/3)
Pin Name
RTPTRG
R/W
RXD0
I/O
PULL
Function
Input
Yes
RTP external trigger input
P06/INTP5
Output
No
External read/write status output
P92/WRH
Input
Yes
Serial receive data input for UART0 and UART1
P13/SI1
RXD1
SCK0
Alternate Function
P23
I/O
Yes
Serial clock I/O (3-wire type) for CSI0 to CSI2
P12
SCK1
P15/ASCK0
SCK2
P22
2
2
SDA
SI0
Note
I C serial clock I/O
SCL
Input
Yes
P12/SCK0
Note
I C serial transmit/receive data I/O
P10/SI0
Serial receive data input (3-wire type) for CSI0 to CSI2
P10
SI1
P13/RXD0
SI2
P20
SO0
Output
Yes
Serial transmit data output (3-wire type) for CSI0 to CSI2
P11
SO1
P14/TXD0
SO2
P21
TI00
External capture trigger input and external count clock input
for TM0
P30
TI01
External capture trigger input for TM0
P31
TI10
External capture trigger input and external count clock input
for TM1
P32
TI11
External capture trigger input for TM1
P33
TI2
External count clock input for TM2
P26/TO2
TI3
External count clock input for TM3
P27/TO3
TI4
External count clock input for TM4
P36/TO4/A15
TI5
External count clock input for TM5
P37/TO5
Pulse signal output for TM0 and TM1
P34/A13, P35/A14
TO2
Pulse signal output for TM2
P26/TI2
TO3
Pulse signal output for TM3
P27/TI3
TO4
Pulse signal output for TM4
P36/TI4/A15
TO5
Pulse signal output for TM5
P37/TI5
Serial transmit data output for UART0 and UART1
P14/SO1
TO0, TO1
TXD0
Input
Output
Output
Yes
Yes
Yes
TXD1
UBEN
P24
Output
No
High-order byte enable signal output for external data bus
VDD
−
−
Positive power supply pin
−
VSS
−
−
Ground potential
−
Note Applies to the µPD703014AY, 703015AY, and 703017AY only.
Remark
12
PULL: On-chip pull-up resistor
Data Sheet U14526EJ2V0DS00
P91
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(3/3)
Pin Name
I/O
PULL
WAIT
Input
No
Control signal input for inserting wait in bus cycle
P120
WRH
Output
No
High-order byte write strobe signal output for external data
bus
P92/R/W
Low-order byte write strobe signal output for external data bus
P90/LBEN
WRL
X1
Input
X2
−
XT1
Input
XT2
−
IC
−
Remark
No
Function
Alternate Function
−
Resonator connection for main clock
−
No
Resonator connection for subsystem clock
P114
−
−
Internally connected (connect directly to VSS)
−
PULL: On-chip pull-up resistor
Data Sheet U14526EJ2V0DS00
13
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
1.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are show in Table 1-1. For
the input/output schematic circuit diagram of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuits (1/2)
Pin
Alternate Function
P00
NMI
P01 to
P04
INTP0 to INTP3
P05
INTP4/ADTRG
P06
INTP5/RTPTRG
P07
INTP6
P10
SI0/SDA
P11
SO0
Note
I/O Circuit Type
8-A
Input:
Connect to VSS
Output: Leave open
10-A
Input:
Connect to VDD or VSS
Output: Leave open
26
Note
Recommended Connection of Unused Pins
P12
SCK0/SCL
10-A
P13
SI1/RXD0
8-A
P14
SO1/TXD0
26
P15
SCK1/ASCK0
10-A
P20
SI2
8-A
P21
SO2
26
P22
SCK2
10-A
P23
RXD1
8-A
P24
TXD1
5-A
P25
ASCK1
8-A
P26, P27
TI2/TO2, TI3/TO3
P30, P31
TI00, TI01
P32, P33
TI10, TI11
P34, P35
TO0/A13, TO1/A14
5-A
P36
TI4/TO4/A15
8-A
P37
TI5/TO5
P40 to
P47
AD0 to AD7
P50 to
P57
AD8 to AD15
P60 to
P65
A16 to A21
P70 to
P77
ANI0 to ANI7
P80 to
P83
ANI8 to ANI11
5
Input:
Connect to BVDD or BVSS
Output: Leave open
9
Connect to AVSS or AVDD
Note Applies to the µPD703014AY, 703015AY, and 703017AY only.
14
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Table 1-1. Types of Pin I/O Circuits (2/2)
Pin
Alternate Function
I/O Circuit Type
Recommended Connection of Unused Pins
5
Input:
Connect to BVDD or BVSS
Output: Leave open
RTP0/A5 to RTP7/A12
26
Input:
Connect to VDD or VSS
Output: Leave open
P110 to
P113
A1 to A4
5-A
P114
XT1
16
P120
WAIT
5
Input:
Connect to BVDD or BVSS
Output: Leave open
P90
LBEN/WRL
P91
UBEN
P92
R/W/WRH
P93
DSTB/RD
P94
ASTB
P95
HLDAK
P96
HLDRQ
P100 to
P107
AVREF
−
−
Connect to AVSS
CLKOUT
−
4
Leave open
RESET
−
2
X2
−
−
Leave open (when external clock is input to X1 pin)
XT2
−
16
Leave open
IC
−
–
Always connect directly to VSS
−
Data Sheet U14526EJ2V0DS00
15
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Figure 1-1. Pin Input/Output Circuits (1/2)
Type 2
Type 5-A
VDD
Pullup
enable
P-ch
VDD
Data
IN
P-ch
IN/OUT
Output
disable
N-ch
Schmitt-triggered input with hysteresis characteristics
Input
enable
Type 8-A
Type 4
VDD
VDD
Data
Pullup
enable
P-ch
OUT
Output
disable
P-ch
VDD
Data
P-ch
N-ch
IN/OUT
Output
disable
N-ch
Push-pull output that can be set for high-impedance output
(both P-ch and N-ch off)
Type 5
Type 9
VDD
Data
P-ch
P-ch
IN/OUT
Output
disable
IN
N-ch
Comparator
–
N-ch
VREF (threshold voltage)
Input enable
Input
enable
16
+
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Figure 1-1. Pin Input/Output Circuits (2/2)
Type 10-A
Type 26
VDD
Pullup
enable
Pullup
enable
P-ch
VDD
Data
VDD
P-ch
VDD
Data
P-ch
P-ch
IN/OUT
Open drain
Output disable
N-ch
IN/OUT
Open drain
Output
disable
N-ch
Type 16
Feedback cut-off
P-ch
XT1
XT2
Data Sheet U14526EJ2V0DS00
17
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Supply voltage
Input voltage
Symbol
Ratings
Unit
VDD
–0.5 to +4.6
V
AVDD
–0.5 to +4.6
V
BVDD
–0.5 to +4.6
V
AVSS
–0.5 to +0.5
V
BVSS
–0.5 to +0.5
VI1
VI2
Clock input voltage
Analog input voltage
Analog reference input voltage
Output current, low
Output current, high
Output voltage
VK
VIAN
AVREF
IOL
IOH
VO1
VO2
Conditions
Note 1
Note 2
X1, XT1, VDD = 2.7 to 3.6 V
Note 3 (AVDD)
AVREF
V
Note 4
–0.5 to VDD + 0.5
Note 4
–0.5 to BVDD + 0.5
Note 4
–0.5 to VDD + 1.0
V
V
V
Note 4
V
Note 4
V
–0.5 to AVDD + 0.5
–0.5 to AVDD + 0.5
Per pin
4.0
mA
Total for P00 to P07, P10 to P15, P20 to
P25
25
mA
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
25
mA
Total for P40 to P47, P90 to P96, P120,
CLKOUT
25
mA
Total for P50 to P57, P60 to P65
25
mA
Per pin
–4.0
mA
Total for P00 to P07, P10 to P15, P20 to
P25
–25
mA
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
–25
mA
Total for P40 to P47, P90 to P96, P120,
CLKOUT
–25
mA
Total for P50 to P57, P60 to P65
–25
Note 1, VDD = 2.7 to 3.6 V
Note 2, BVDD = 2.7 to 3.6 V
mA
Note 4
–0.5 to VDD + 0.5
Note 4
–0.5 to BVDD + 0.5
V
V
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Notes 1. Ports 0, 1, 2, 3, 10, 11, 12, RESET, and their alternate-function pins.
2. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins.
3. Ports 7, 8, and their alternate-function pins.
4. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions
1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC,
and GND. Open-drain pins or open-collector pins, however, can be directly connected to
each other. Direct connection of the output pins between an IC product and an external
circuit is possible, if the output pins can be set to the high-impedance state and the output
timing of the external circuit is designed to avoid output conflict.
18
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Input capacitance
CI
I/O capacitance
CIO
Output capacitance
CO
Conditions
fC = 1 MHz
Unmeasured pins returned to 0 V
MIN.
TYP.
MAX.
Unit
15
pF
15
pF
15
pF
Operating Conditions
Internal Operation Clock Frequency
Supply Voltage (VDD)
Operating Ambient Temperature (TA)
2 MHz ≤ fXX ≤ 17 MHz
2.7 to 3.6 V
–40 to +85°C
2 MHz ≤ fXX ≤ 20 MHz
3.0 to 3.6 V
–40 to +85°C
fXT = 32.768 kHz
2.7 to 3.6 V
–40 to +85°C
Data Sheet U14526EJ2V0DS00
19
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Recommended Oscillator
(1) Main system clock oscillator (TA = –40 to +85°C)
(a) Connection of ceramic resonator or crystal resonator
X1
Parameter
Oscillation frequency
Oscillation stabilization time
Symbol
fXX
X2
Conditions
MIN.
VDD = 2.7 to 3.6 V
2
VDD = 3.0 to 3.6 V
2
TYP.
MAX.
Unit
17
MHz
20
MHz
19
Upon reset release
2 /fXX
s
Upon STOP mode release
Note
s
Note The TYP value differs depending on the setting of the oscillation stabilization time select register (OSTS).
Caution Ensure that the duty of oscillation waveform is between 45% and 55%.
Remarks 1. Connect the oscillator as close as possible to the X1 and X2 pins.
2. Do not route the wiring near broken lines.
3. Sufficiently evaluate the matching between the oscillator and resonator.
(b) External clock input
X1
X2
Open
High-speed CMOS inverter
External clock
Cautions
1. Connect the high-speed CMOS inverter as close as possible to the X1 pin.
2. Sufficiently evaluate the matching between the µPD703014A, 703014AY, 703015A,
703015AY, 703017A, 703017AY and the high-speed CMOS inverter.
20
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(2) Subsystem clock oscillator (TA = –40 to +85°C)
(a) Connection of crystal resonator
XT1
Parameter
Oscillation frequency
Symbol
XT2
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
fXT
Oscillation stabilization time
10
s
Remarks 1. Connect the oscillator as close as possible to the XT1 and XT2 pins.
2. Do not route the wiring near broken lines.
3. Sufficiently evaluate the matching between the oscillator and resonator.
(b) External clock input
XT1
XT2
High-speed CMOS inverter
Cautions
1. Connect the high-speed CMOS inverter as close as possible to the XT2 pin.
2. Sufficiently evaluate the matching between the µPD703014A, 703014AY, 703015A,
703015AY, 703017A, 703017AY and the high-speed CMOS inverter.
Data Sheet U14526EJ2V0DS00
21
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
DC Characteristics
(1) Operating conditions (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V) (1/2)
Parameter
Input voltage, high
Input voltage, low
Output voltage, high
Output voltage, low
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
0.7VDD
VDD
V
VIH1
Pins other than below
VIH2
Note 1
0.7AVDD
AVDD
V
VIH3
Note 2
0.75VDD
VDD
V
VIH4
X1, XT1 (P114), XT2
0.8VDD
VDD
V
VIL1
Pins other than below
VSS
0.3VDD
V
VIL2
Note 1
AVSS
0.3AVDD
V
VIL3
Note 2
VSS
0.2VDD
V
VIL4
X1, XT1 (P114), XT2
VSS
0.2VDD
V
VOH1
Note 3
IOH = –3 mA
0.8VDD
V
VOH2
Note 4
IOH = –1 mA
0.8VDD
V
VOL1
Note 3
IOL = 1.6 mA
0.4
V
VOL2
Note 4
IOL = 1.6 mA
0.4
V
0.4
V
(Except pins
P10 and P12)
Input leakage current, high
Input leakage current, low
VOL3
P10, P12
IOL = 3 mA
ILIH
VI = VDD = AVDD
= BVDD
Pins other than below
5
µA
X1, XT1, XT2
20
µA
VI = 0 V
Pins other than below
–5
µA
X1, XT1, XT2
–20
µA
ILIL
Output leakage current, high
ILOH
VO = VDD = AVDD = BVDD
5
µA
Output leakage current, low
ILOL
VO = 0 V
–5
µA
IDD1
Normal
operation
fXX = 17 MHz
All peripheral functions
operating
17
30
mA
IDD2
HALT mode
fXX = 17 MHz
All peripheral functions
operating
8
20
mA
IDD3
IDLE mode
fXX = 17 MHz
Watch timer operating
1
4
mA
IDD4
STOP mode (subsystem oscillator, watch
timer operating)
8
60
µA
STOP mode (subsystem oscillator
stopped (XT1 = VSS))
1
60
µA
Supply current
22
Note 5
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(1) Operating conditions (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V) (2/2)
Parameter
Supply current
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Note 5
Pull-up resistance
IDD5
Subsystem clock normal operation mode
fXT = 32.768 kHz (main system clock
stopped)
40
140
µA
IDD6
Subsystem clock IDLE mode
fXT = 32.768 kHz (main system clock
stopped, watch timer operating)
8
60
µA
RL
VIN = 0 V
30
100
kΩ
10
Notes 1. P70 to P77, P80 to P83, and their alternate-function pins.
2. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET, and their
alternate-function pins.
3. CLKOUT, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P120, and their alternate-function pins.
4. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, and their alternatefunction pins.
5. The TYP. value of VDD is 3.3 V. The current consumed by the output buffer is not included.
Data Sheet U14526EJ2V0DS00
23
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(2) Operating conditions (TA = –40 to +85°C, VDD = AVDD = BVDD = 3.0 to 3.6 V, VSS = AVSS = BVSS = 0 V) (1/2)
Parameter
Input voltage, high
Input voltage, low
Output voltage, high
Output voltage, low
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
0.7VDD
VDD
V
VIH1
Pins other than below
VIH2
Note 1
0.7AVDD
AVDD
V
VIH3
Note 2
0.75VDD
VDD
V
VIH4
X1, XT1 (P114), XT2
0.8VDD
VDD
V
VIL1
Pins other than below
VSS
0.3VDD
V
VIL2
Note 1
AVSS
0.3AVDD
V
VIL3
Note 2
VSS
0.2VDD
V
VIL4
X1, X2, XT1 (P114), XT2
VSS
0.2VDD
V
VOH1
Note 3
IOH = –3 mA
0.8VDD
V
VOH2
Note 4
IOH = –1 mA
0.8VDD
V
VOL1
Note 3
IOL = 1.6 mA
0.4
V
VOL2
Note 4
IOL = 1.6 mA
0.4
V
0.4
V
(Except pins
P10 and P12)
Input leakage current, high
Input leakage current, low
VOL3
P10, P12
IOL = 3 mA
ILIH
VI = VDD = AVDD
= BVDD
Pins other than below
5
µA
X1, XT1, XT2
20
µA
VI = 0 V
Pins other than below
–5
µA
X1, XT1, XT2
–20
µA
ILIL
Output leakage current, high
ILOH
VO = VDD
5
µA
Output leakage current, low
ILOL
VO = 0 V
–5
µA
IDD1
Normal
operation
fXX = 20 MHz
All peripheral functions
operating
20
35
mA
IDD2
HALT mode
fXX = 20 MHz
All peripheral functions
operating
9
22
mA
IDD3
IDLE mode
fXX = 20 MHz
Watch timer operating
1.2
4.5
mA
IDD4
STOP mode (subsystem oscillator, watch
timer operating)
8
60
µA
STOP mode (subsystem oscillator
stopped (XT1 = VSS))
1
60
µA
Supply current
24
Note 5
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(2) Operating conditions (TA = –40 to +85°C, VDD = AVDD = BVDD = 3.0 to 3.6 V, VSS = AVSS = BVSS = 0 V) (2/2)
Parameter
Supply current
Note 5
Pull-up resistance
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
IDD5
Subsystem clock normal operation mode
fXT = 32.768 kHz (main system clock
stopped)
40
140
µA
IDD6
Subsystem clock IDLE mode
fXT = 32.768 kHz (main system clock
stopped, watch timer operating)
8
60
µA
RL
VIN = 0 V
30
100
kΩ
10
Notes 1. P70 to P77, P80 to P83, and their alternate-function pins.
2. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET and their
alternate-function pins.
3. CLKOUT, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P120, and their alternate-function pins.
4. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, and their alternatefunction pins.
5. The TYP. value of VDD is 3.3 V. The current consumed by the output buffer is not included.
Data Sheet U14526EJ2V0DS00
25
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
TYP.
1.8
MAX.
Unit
3.6
V
60
µA
Data retention voltage
VDDDR
STOP mode
Data retention current
IDDDR
VDDDR [V]
Supply voltage rise time
tRVD
200
µs
Supply voltage fall time
tFVD
200
µs
Supply voltage hold time
(from STOP mode setting)
tHVD
0
ms
STOP release signal input time
tDREL
0
ms
Data retention high-level input voltage
VIHDR
All input ports
VIHn
VDDDR
V
Data retention low-level input voltage
VILDR
All input ports
0
VILn
V
1
Remarks 1. TYP. values are reference values for when TA = 25°C.
2. n = 1 to 4
Setting STOP mode
tFVD
tRVD
VDD
tHVD
RESET
(input)
VIHDR
NMI, INTP0 to INTP3
(input)
VIHDR
NMI, INTP0 to INTP3 (input)
(when STOP mode is released
at rising edge)
Caution
VDDDR
VILDR
Shifting to STOP mode and restoring from STOP mode must be performed at VDD = 2.7 V min.
(fXX = 17 MHz) and VDD = 3.0 V min. (fXX = 20 MHz), respectively.
26
tDREL
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
AC Characteristics
AC Test Input Waveforms
(1) P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, and their alternate-function pins
VDD
0.7VDD
0.7VDD
Test points
0.3VDD
0V
0.3VDD
(2) P70 to P77, P80 to P83, and their alternate-function pins
AVDD
0.7AVDD
0.7AVDD
Test points
0V
0.3AVDD
0.3AVDD
(3) P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET, and their
alternate-function pins
VDD
0.75VDD
0.75VDD
Test points
0V
0.2VDD
0.2VDD
(4) X1, XT1 (P114), XT2
VDD
0.8VDD
0.8VDD
Test points
0V
0.2VDD
0.2VDD
AC Test Output Test Points
0.8VDD
0.8VDD
Test points
0.4 V
0.4 V
Data Sheet U14526EJ2V0DS00
27
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Load conditions
DUT
(Device under test)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance
of the device to 50 pF or less by inserting a buffer or by some other means.
28
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Clock Timing
(1) Operating conditions (TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load
capacitance: CL = 50 pF)
Parameter
X1 input cycle
Symbol
tCYX
Conditions
<1>
XT1 input cycle
X1 input high-level width
tWXH
<2>
XT1 input high-level width
X1 input low-level width
tWXL
<3>
tXR
<4>
MAX.
Unit
58.8
ns
28.5
µs
26.4
ns
12.8
µs
26.4
ns
µs
12.8
XT1 input low-level width
X1 input rise time
MIN.
0.5 (tCYX –
ns
tWXH – tWXL)
X1 input fall time
tXF
<5>
0.5 (tCYX –
tWXH – tWXL)
CLKOUT output cycle
tCYK
<6>
58.8 ns
CLKOUT high-level width
tWKH
<7>
0.4tCYK – 10
CLKOUT low-level width
tWKL
<8>
0.4tCYK
CLKOUT rise time
tKR
<9>
10
ns
CLKOUT fall time
tKF
<10>
10
ns
ns
31.2 µs
ns
– 10
ns
Remarks 1. T = tCYK
2. Ensure that the duty is between 45% and 55%.
(2) Operating conditions (TA = –40 to +85°C, VDD = BVDD = 3.0 to 3.6 V, VSS = BVSS = 0 V, Output pin load
capacitance: CL = 50 pF)
Parameter
X1 input cycle
Symbol
tCYX
Conditions
<1>
XT1 input cycle
X1 input high-level width
tWXH
<2>
XT1 input high-level width
MIN.
MAX.
Unit
50.0
ns
28.5
µs
22.5
ns
12.8
µs
22.5
ns
tWXL
<3>
X1 input rise time
tXR
<4>
0.5 (tCYX –
tWXH – tWXL)
ns
X1 input fall time
tXF
<5>
0.5 (tCYX –
ns
X1 input low-level width
XT1 input low-level width
µs
12.8
tWXH – tWXL)
31.2 µs
CLKOUT output cycle
tCYK
<6>
50.0 ns
CLKOUT high-level width
tWKH
<7>
0.4tCYK – 10
CLKOUT low-level width
tWKL
<8>
0.4tCYK – 10
CLKOUT rise time
tKR
<9>
10
ns
CLKOUT fall time
tKF
<10>
10
ns
ns
ns
Remarks 1. T = tCYK
2. Ensure that the duty is between 45% and 55%.
Data Sheet U14526EJ2V0DS00
29
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Clock Timing
<1>
<2>
<3>
X1, XT1 (input)
<4>
<5>
<6>
<7>
<8>
CLKOUT (output)
<9>
<10>
(1) Timing of pins other than CLKOUT, ports 4, 5, 6, and 9
(TA = –40 to +85°°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Output rise time
tOR
<11>
20
ns
Output fall time
tOF
<12>
20
ns
(2) Timing of pins other than CLKOUT, ports 4, 5, 6, and 9
(TA = –40 to +85°°C, VDD = BVDD = 3.0 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Output rise time
tOR
<11>
20
ns
Output fall time
tOF
<12>
20
ns
0.8VDD
0.8VDD
Output signal
0.4 V
0.4 V
<12>
30
<11>
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Bus Timing (CLKOUT Asynchronous)
(TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB↓)
tSAST
<13>
0.5T – 15
ns
Address hold time (from ASTB↓)
tHSTA
<14>
0.5T – 15
ns
Address float from DSTB↓
tFDA
<15>
2
ns
Data input setup time from address
tSAID
<16>
(2 + n)T – 25
ns
Data input setup time from DSTB↓
tSDID
<17>
(1 + n)T – 25
ns
Delay time from ASTB↓ to DSTB↓
tDSTD
<18>
0.5T – 15
ns
Data input hold time (from DSTB↑)
tHDID
<19>
0
ns
Address output time from DSTB↑
tDDA
<20>
(1 + i)T – 15
ns
Delay time from DSTB↑ to ASTB↑
tDDST1
<21>
0.5T – 15
ns
Delay time from DSTB↑ to ASTB↓
tDDST2
<22>
(1.5 + i)T – 15
ns
DSTB low-level width
tWDL
<23>
(1 + n)T – 15
ns
ASTB high-level width
tWSTH
<24>
T – 15
ns
Data output time from DSTB↓
tDDOD
<25>
Data output setup time (to DSTB↑)
tSODD
<26>
(1 + n)T – 20
ns
Data output hold time (from DSTB↑)
tHDOD
<27>
T – 15
ns
WAIT setup time (to address)
tSAWT1
<28>
n≥1
1.5T – 25
ns
tSAWT2
<29>
n≥1
(1.5 + n)T – 25
ns
tHAWT1
<30>
n≥1
(0.5 + n)T
ns
tHAWT2
<31>
n≥1
(1.5 + n)T
ns
tSSTWT1
<32>
n≥1
T – 25
ns
tSSTWT2
<33>
n≥1
(1 + n)T – 25
ns
tHSTWT1
<34>
n≥1
nT
ns
tHSTWT2
<35>
n≥1
(1 + n)T
ns
HLDRQ high-level width
tWHQH
<36>
T + 10
ns
HLDAK low-level width
tWHAL
<37>
T – 15
ns
Bus output delay time from HLDAK↑
tDHAC
<38>
0
ns
Delay time from HLDRQ↓ to HLDAK↓
tDHQHA1
<39>
Delay time from HLDRQ↑ to HLDAK↑
tDHQHA2
<40>
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
15
0.5T
ns
(2n + 7.5)T + 25
ns
1.5T + 25
ns
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. i: Number of idle states inserted after the read cycle (0 or 1).
4. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
Data Sheet U14526EJ2V0DS00
31
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Bus Timing (CLKOUT Synchronous)
(TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT↑ to address
tDKA
<41>
0
19
ns
Delay time from CLKOUT↑ to address
float
tFKA
<42>
–12
7
ns
Delay time from CLKOUT↓ to ASTB
tDKST
<43>
–12
7
ns
Delay time from CLKOUT↑ to DSTB
tDKD
<44>
–5
14
ns
Data input setup time (to CLKOUT↑)
tSIDK
<45>
15
ns
Data input hold time (from CLKOUT↑)
tHKID
<46>
5
ns
Data output delay time from CLKOUT↑
tDKOD
<47>
WAIT setup time (to CLKOUT↓)
tSWTK
<48>
15
ns
WAIT hold time (from CLKOUT↓)
tHKWT
<49>
5
ns
HLDRQ setup time (to CLKOUT↓)
tSHQK
<50>
15
ns
HLDRQ hold time (from CLKOUT↓)
tHKHQ
<51>
5
ns
Delay time from CLKOUT↑ to bus float
tDKF
<52>
19
ns
Delay time from CLKOUT↑ to HLDAK
tDKHA
<53>
19
ns
19
ns
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
32
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output)
<41>
A16 to A21 (output),
A1 to A15 (output), Note
<16>
<45>
<46>
<42>
AD0 to AD15 (I/O)
Hi-Z
Address
Data
<43>
<43>
<14>
<13>
<19>
ASTB (output)
<24>
<44>
<18>
<21>
<15>
<17>
<44>
<20>
<22>
DSTB (output),
RD (output)
<32> <48>
<34>
<33>
<35>
<49>
<23>
<48>
<49>
WAIT (input)
<28>
<30>
<29>
<31>
Note R/W (output), UBEN (output), LBEN (output)
Remark WRL and WRH are high level.
Data Sheet U14526EJ2V0DS00
33
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output)
<41>
A16 to A21 (output),
A1 to A15 (output), Note
<47>
AD0 to AD15 (I/O)
Address
Data
<43>
<13>
<14>
<43>
ASTB (output)
<24>
<21>
<44>
<18>
<25>
<44>
<27>
<26>
DSTB (output),
WRL (output),
WRH (output)
<32> <48>
<34>
<33>
<35>
<49>
<23>
<48>
WAIT (input)
<28>
<30>
<29>
<31>
Note R/W (output), UBEN (output), LBEN (output)
Remark RD is high level.
34
Data Sheet U14526EJ2V0DS00
<49>
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Bus Hold
TH
TH
TH
TI
CLKOUT (output)
<50>
<50> <51>
<36>
HLDRQ (input)
<53>
<53>
<39>
<40>
HLDAK (output)
<52>
<37>
<38>
Hi-Z
A16 to A19 (output), Note
A1 to A15 (output)
AD0 to AD15 (I/O)
Data
Hi-Z
Hi-Z
ASTB (output)
Hi-Z
DSTB (output), RD (output),
WRL (output), WRH (output)
Remark R/W (output), UBEN (output), LBEN (output)
Data Sheet U14526EJ2V0DS00
35
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Reset/Interrupt Timing
(TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
RESET high-level width
tWRSH
<54>
500
ns
RESET low-level width
tWRSL
<55>
500
ns
NMI high-level width
tWNIH
<56>
500
ns
NMI low-level width
tWNIL
<57>
INTPn high-level width
tWITH
<58>
INTPn low-level width
tWITL
<59>
500
ns
n = 0 to 3 (analog noise
elimination)
500
ns
n = 4 to 6 (digital noise
elimination)
3T + 20
ns
n = 0 to 3 (analog noise
elimination)
500
ns
n = 4 to 6 (digital noise
elimination)
3T + 20
ns
Remark T = 1/fXX
Reset
<54>
<55>
<56>
<57>
<58>
<59>
RESET (input)
Interrupt
NMI (input)
INTPn (input)
Remark n = 0 to 6
36
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
TIn Input Timing
(TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
TIn0, TIn1 high-level width
Symbol
<60>
tTIHn
n = 0, 1
n = 2 to 5
TIn high-level width
TIn0, TIn1 low-level width
Conditions
tTILn
<61>
TIn low-level width
n = 0, 1
n = 2 to 5
MIN.
MAX.
Note
Unit
2Tsam + 20
ns
3T + 20
ns
Note
2Tsam + 20
ns
3T + 20
ns
Note Tsam (count clock cycle) can be selected from the following by setting the PRMn2 to PRMn0 bits of prescaler
mode register n, n1 (PRMn, PRMn1).
For n = 0 (TM0): Tsam = 2T, 4T, 16T, 64T, 256T, or 1/INTWTI cycle
For n = 1 (TM1): Tsam = 2T, 4T, 16T, 32T, 128T, or 256T cycle
However, when the TIn0 valid edge is selected as the count clock cycle, Tsam = 2T.
Remark T = 1/fXX
<60>
<61>
Tln
Remark n = 00, 01, 10, 11, 2 to 5
Data Sheet U14526EJ2V0DS00
37
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
CSI Timing
(1) Master mode (TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance:
CL = 50 pF)
Parameter
SCKn cycle time
Symbol
Conditions
MIN.
MAX.
Unit
tKCY1
<62>
400
ns
SCKn high-/low-level width
tKH1, tKL1
<63>
140
ns
SIn setup time (to SCKn↑)
tSIK1
<64>
50
ns
SIn hold time (from SCKn↑)
tKSI1
<65>
50
ns
Delay time from SCKn↓ to SOn output
tKSO1
<66>
60
ns
Remark n = 0 to 2
(2) Slave mode (TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance:
CL = 50 pF)
Parameter
SCKn cycle time
Symbol
Conditions
MIN.
MAX.
Unit
tKCY2
<62>
400
ns
tKH2, tKL2
<63>
140
ns
SIn setup time (to SCKn↑)
tSIK2
<64>
50
ns
SIn hold time (from SCKn↑)
tKSI2
<65>
50
ns
Delay time from SCKn↓ to SOn output
tKSO2
<66>
SCKn high-/low-level width
60
Remark n = 0 to 2
<62>
<63>
<63>
SCKn (I/O)
<64>
SIn (input)
<65>
Input data
<66>
SOn (output)
Output data
Remark n = 0 to 2
38
Data Sheet U14526EJ2V0DS00
ns
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
UART Timing (TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance:
CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASCKn cycle time
tKCY13
<67>
200
ns
ASCKn high-level width
tKH13
<68>
80
ns
ASCKn low-level width
tKL13
<69>
80
ns
Remark n = 0, 1
<67>
<68>
<69>
ASCKn (input)
Remark n = 0 or 1
Data Sheet U14526EJ2V0DS00
39
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
I C Bus Mode (µPD703014AY, 703015AY, 703017AY only)
2
(TA = –40 to +85°C, VDD = 2.7 to 3.6 V, VSS = 0 V)
Parameter
Symbol
Normal Mode
High-Speed Mode
Unit
MIN.
MAX.
MIN.
MAX.
0
100
0
400
kHz
SCL clock frequency
fCLK
Bus-free time (between
stop/start conditions)
tBUF
<70>
4.7
–
1.3
–
µs
Hold time
tHD:STA
<71>
4.0
–
0.6
–
µs
SCL clock low-level width
tLOW
<72>
4.7
–
1.3
–
µs
SCL clock high-level width
tHIGH
<73>
4.0
–
0.6
–
µs
Setup time for start/restart
conditions
tSU:STA
<74>
4.7
–
0.6
–
µs
Data hold
time
tHD:DAT
<75>
5.0
–
–
–
µs
Note 1
CBUS
compatible
master
Note 2
2
0
I C mode
Note 2
Note 3
0.9
0
–
Note 4
Data setup time
tSU:DAT
<76>
250
–
100
SDA and SCL signal rise
time
tR
<77>
–
1000
20 + 0.1Cb
SDA and SCL signal fall
time
tF
<78>
–
300
20 + 0.1Cb
Stop condition setup time
tSU:STO
<79>
4.0
–
Capacitance load of each
bus line
Cb
–
400
µs
–
ns
Note 5
300
ns
Note 5
300
ns
0.6
–
µs
–
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
2. The system requires a minimum of 300 ns hold time internally for the SDA signal (at VIHmin.. of SCL
signal) in order to occupy the undefined area at the falling edge of SCL.
3. If the system does not extend the SCL signal low hold time (tLOW), only the maximum data hold time (tHD:
DAT)
needs to be satisfied.
2
2
4. The high-speed mode I C bus can be used in the normal-mode I C bus system. In this case, set the
high-speed mode I2C bus so that it meets the following conditions.
• If the system does not extend the SCL signal's low state hold time:
tSU:DAT ≥ 250 ns
• If the system extends the SCL signal's low state hold time:
Transmit the following data bit to the SDA line prior to the SCL line release (tRmax. + tSU:DAT = 1000 +
250 = 1250 ns: Normal mode I2C bus specification).
5.
Cb: Total capacitance of one bus line (unit: pF)
Remark The maximum operating frequency of the µPD703014AY, 703015AY, and 703017AY is 17 MHz.
40
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
I C Bus Mode (µPD703014AY, 703015AY, 703017AY only)
2
<72>
<73>
SCL (I/O)
<78> <77>
<75>
<76>
<74>
<71>
<71>
<79>
SDA (I/O)
<70>
<77>
<78>
Restart
condition
Start
Stop
condition condition
Stop
condition
A/D Converter (TA = –40 to +85°C, VDD = AVDD = AVREF = 2.7 to 3.6 V, VSS = AVSS = 0 V, Output pin load
capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
Resolution
MIN.
TYP.
MAX.
Unit
10
10
10
bit
±0.8
%FSR
100
µs
±0.4
%FSR
±0.4
%FSR
±4
LSB
±4
LSB
2.7
3.6
V
AVSS
AVREF
V
Note 1
Overall error
Conversion time
Zero-scale error
Full-scale error
tCONV
5
Note 1
Note 1
Integral linearity error
Note 2
Differential linearity error
Note 2
Analog reference voltage
AVREF
AVREF = AVDD
Analog input voltage
VIAN
AVREF current
AIREF
360
500
µA
Power supply current
AIDD
1
3
mA
Notes 1. Excluding quantization error (±0.05 %FSR)
2. Excluding quantization error (±0.5 LSB)
Remark LSB: Least Significant Bit
FSR: Full Scale Range
Data Sheet U14526EJ2V0DS00
41
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
3. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C D
R
Q
26
25
100
1
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
16.00±0.20
B
14.00±0.20
C
14.00±0.20
D
16.00±0.20
F
1.00
G
1.00
H
0.22 +0.05
−0.04
I
J
0.08
0.50 (T.P.)
K
1.00±0.20
L
0.50±0.20
M
0.17 +0.03
−0.07
N
0.08
P
1.40±0.05
Q
0.10±0.05
R
3° +7°
−3°
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
42
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
121-PIN PLASTIC FBGA (12x12)
w
E
S B
ZE
ZD
B
13
12
11
10
9
8
7
6
5
4
3
2
1
A
D
NM L K J HG F E DC B A
w
INDEX MARK
S A
A
y1
A2
S
S
y
S
e
φb
A1
φx
M
S AB
ITEM
D
MILLIMETERS
12.00±0.10
E
12.00±0.10
w
0.20
A
1.48±0.10
A1
A2
0.35±0.06
1.13
e
0.80
b
0.50 +0.05
−0.10
x
y
y1
ZD
ZE
0.08
0.10
0.20
1.20
1.20
P121F1-80-EA6
Data Sheet U14526EJ2V0DS00
43
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
4. RECOMMENDED SOLDERING CONDITIONS
The µPD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY should be soldered and mounted
under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 4-1. Surface Mounting Type Soldering Conditions
100-pin plastic LQFP (fine-pitch) (14 × 14)
(1) µPD703014AGC-×××
×××-8EU:
×××
100-pin plastic LQFP (fine-pitch) (14 × 14)
×××-8EU:
×××
µPD703014AYGC-×××
×××-8EU: 100-pin plastic LQFP (fine-pitch) (14 × 14)
×××
µPD703015AGC-×××
100-pin plastic LQFP (fine-pitch) (14 × 14)
×××-8EU:
×××
µPD703015AYGC-×××
×××-8EU: 100-pin plastic LQFP (fine-pitch) (14 × 14)
×××
µPD703017AGC-×××
100-pin plastic LQFP (fine-pitch) (14 × 14)
×××-8EU:
×××
µPD703017AYGC-×××
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
Note
Exposure limit: 7 days (after that, prebake at 125°C for 10 hours)
IR35-107-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
Note
Exposure limit: 7 days (after that, prebake at 125°C for 10 hours)
VP15-107-2
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
121-pin plastic FBGA (12 × 12)
(2) µPD703014AF1-×××
×××-EA6:
×××
121-pin plastic FBGA (12 × 12)
×××-EA6:
×××
µPD703014AYF1-×××
×××-EA6: 121-pin plastic FBGA (12 × 12)
×××
µPD703015AF1-×××
121-pin plastic FBGA (12 × 12)
×××-EA6:
×××
µPD703015AYF1-×××
×××-EA6: 121-pin plastic FBGA (12 × 12)
×××
µPD703017AF1-×××
121-pin plastic FBGA (12 × 12)
×××-EA6:
×××
µPD703017AYF1-×××
Soldering Method
Soldering Conditions
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
Note
Exposure limit: 7 days (after that, prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Recommended
Condition
Symbol
IR35-107-2
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
44
Data Sheet U14526EJ2V0DS00
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
[MEMO]
Data Sheet U14526EJ2V0DS00
45
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Caution
2
2
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use
2
2
these components in an I C system, provided that the system conforms to the I C Standard
Specification as defined by Philips.
Reference document
Note
Electrical Characteristics for Microcomputer (IEI-601)
This document number is that of the Japanese version.
Related document µPD70F3017A, 70F3017AY Data Sheet (U14527E)
V850 Family and V850/SA1 are trademarks of NEC Corporation.
46
Data Sheet U14526EJ2V0DS00
Note
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
Data Sheet U14526EJ2V0DS00
47
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4