NEC UPD703201

PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µPD703201, 703201Y, 703204, 703204Y,
70F3201, 70F3201Y, 70F3204, 70F3204Y
TM
TM
V850ES/SA2 , V850ES/SA3
32-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703201, 703201Y, 70F3201, and 70F3201Y (V850ES/SA2), µPD703204, 703204Y, 70F3204, and
70F3204Y (V850ES/SA3) are products in the V850 Family
TM
of 32-bit single-chip microcontrollers, and include
peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, and a
DMA controller.
In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/SA2
and V850ES/SA3 include instructions suited to digital servo control applications such as multiplication instructions
executed via a hardware multiplier, saturation instructions, and bit manipulation instructions. As a real-time control
system, this device provides a high-level cost performance ideal for ultra-low-power DVC and portable audio
applications.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850ES/SA2, V850ES/SA3 User’s Manual Hardware:
To be prepared
V850ES User’s Manual Architecture:
To be prepared
FEATURES
{ Number of instructions: 83
{ Minimum instruction execution time:
59 ns (@ 17 MHz operation with main system clock (fXX))
74 ns (@ 13.5 MHz operation with main system clock (fXX))
{ Interrupts and exceptions
Non-maskable interrupts: 2 sources
Maskable interrupts:
38 sources (µPD703201, 70F3201)
{ General-purpose registers: 32 bits × 32 registers
39 sources (µPD703201Y, 70F3201Y)
{ Instruction set:
39 sources (µPD703204, 70F3204)
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
40 sources (µPD703204Y, 70F3204Y)
Software exceptions: 32 sources
Exception trap: 1 source
{ I/O lines Total: 82 (V850ES/SA2)
{ Memory space:
102 (V850ES/SA3)
64 MB linear address space
Memory block division function:
2 MB, 2 MB, 4 MB, 8 MB = Total four blocks
{ External bus interface: 16-bit data bus
Address bus: Separate output enabled
{ Internal memory
Mask ROM:
{ Timer/counters
16-bit timer: 2 channels
8-bit timer: 4 channels
{ Real-time counter (for watch): 1 channel
{ Watchdog timer: 1 channel
256 KB (µPD703201, 703201Y,
703204, 703204Y)
Flash memory: 256 KB (µPD70F3201, 70F3201Y,
70F3204, 70F3204Y)
RAM: 16 KB
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U15436EJ1V0PM00 (1st edition)
Date Published June 2001 N CP(K)
Printed in Japan
©
2001
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
{ D/A converter: 8-bit resolution × 2 channels
{ Serial interface (SIO)
Asynchronous serial interface (UART): 2 channels
{ DMA controller: 4 channels
Clocked serial interface (CSI):
{ Power save functions: HALT/IDLE/STOP/Backup
4 channels (V850ES/SA2),
modes
{ ROM correction: Four points can be corrected
5 channels (V850ES/SA3)
{ Packages: 100-pin plastic LQFP (14 × 14)
2
I C bus interface: 1 channel
(µPD703201Y, 703204Y, 70F3201Y, 70F3204Y)
(V850ES/SA2)
121-pin plastic FBGA (12 × 12)
{ A/D converter:
10-bit resolution × 12 channels (V850ES/SA2)
(V850ES/SA3)
10-bit resolution × 16 channels (V850ES/SA3)
APPLICATIONS
{ Low-power portable devices
DVCs, portable audios
ORDERING INFORMATION
Part Number
Internal ROM
µPD703201GC-×××-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
256 KB (mask ROM)
µPD703201YGC-×××-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
256 KB (mask ROM)
µPD703204F1-×××-EA6
121-pin plastic FBGA (12 × 12)
256 KB (mask ROM)
µPD703204YF1-×××-EA6
121-pin plastic FBGA (12 × 12)
256 KB (mask ROM)
µPD70F3201GC-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
256 KB (flash memory)
µPD70F3201YGC-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
256 KB (flash memory)
µPD70F3204F1-EA6
121-pin plastic FBGA (12 × 12)
256 KB (flash memory)
µPD70F3204YF1-EA6
121-pin plastic FBGA (12 × 12)
256 KB (flash memory)
Remark
2
Package
××× indicates ROM code suffix.
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
PIN CONFIGURATION
• V850ES/SA2
100-pin plastic LQFP (fine-pitch) (14 × 14)
µPD703201GC-×××-8EU
µPD703201YGC-×××-8EU
µPD70F3201GC-8EU
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
P05/INTP4
P04/INTP3/TI5
P03/INTP2/TI4
P02/INTP1/TI3
P01/INTP0/TI2
P46/INTP11/TO1
P45/INTP10/TI1/TCLR1
P44/INTP01/TO0
P43/INTP00/TI0/TCLR0
P42/SCK0/SCLNote 1
P41/SO0/SDANote 1
P40/SI0
PDH5/A21
µPD70F3201YGC-8EU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PDH4/A20
PDH3/A19
PDH2/A18
PDH1/A17
PDH0/A16
PDL15/AD15
PDL14/AD14
PDL13/AD13
PDL12/AD12
PDL11/AD11
PDL10/AD10
EVDD
EVSS
IC/FLMD0Notes 2, 3
PDL9/AD9
PDL8/AD8
PDL7/AD7
PDL6/AD6
PDL5/AD5/FLMD1Note 2
PDL4/AD4
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
PCT7
P96/A6/TO4
P97/A7/TO5
P98/A8/RXD1
P99/A9/TXD1
P910/A10/SI2
P911/A11/SO2
P912/A12/SCK2
P913/A13/SI3
P914/A14/SO3
P915/A15/SCK3
EVSS
EVDD
PCS0/CS0
PCS1/CS1
PCS2/CS2
PCS3/CS3
PCM0/WAIT
PCM1/CLKOUT
PCM2/HLDAK
PCM3/HLDRQ
PCT0/WR0
PCT1/WR1
PCT4/RD
PCT5
PCT6/ASTB
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AVREF0
AVDD
AVSS
P80/ANO0
P81/ANO1
AVREF1
P00/NMI
P30/SI1/RXD0
P31/SO1/TXD0
P32/SCK1
VDD
VSS
X1
X2
RESET
XT1
XT2
VSSBU
VDDBU
P90/A0
P91/A1
P92/A2/INTP5
P93/A3/INTP6
P94/A4/TO2
P95/A5/TO3
Notes 1. SCL and SDA are valid only for the µPD703201Y and 70F3201Y.
2. FLMD0 and FLMD1 are valid only for the µPD70F3201 and 70F3201Y.
3. IC:
Connect directly to VSS (µPD703201, 703201Y).
FLMD0: Connect to VSS in normal mode (µPD70F3201, 70F3201Y).
Preliminary Product Information U15436EJ1V0PM
3
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
• V850ES/SA3
121-pin plastic FBGA (12 × 12)
µPD703204F1-×××-EA6
µPD70F3204F1-EA6
µPD703204YF1-×××-EA6
µPD70F3204YF1-EA6
(1/2)
Top View
Bottom View
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N
Pin No.
Pin Name
N M L K J H G F E D C B A
Pin No.
Pin Name
Pin No.
A1
P70/ANI0
B8
PCD3
D2
AVREF1
A2
P71/ANI1
B9
P02/INTP1/TI3
D3
P00/NMI
A3
P73/ANI3
B10
P46/INTP11/TO1
D11
PDH0/A16
Note
A4
P713/ANI13
B11
P42/SCK0/SCL
D12
PDH2/A18
A5
P76/ANI6
B12
P40/SI0
D13
PDH1/A17
A6
P78/ANI8
B13
PDH4/A20
E1
P30/SI1/RXD0
A7
P711/ANI11
C1
P80/ANO0
E2
P31/SO1/TXD0
A8
P04/INTP3/TI5
C2
AVSS
E3
P32/SCK1
A9
PCD2
C3
P74/ANI4
E11
PDL14/AD14
A10
P45/INTP10/TI1/TCLR1
C4
P714/ANI14
E12
PDH6/A22
A11
P43/INTP00/TI0/TCLR0
C5
P715/ANI15
E13
PDL15/AD15
Note
A12
P41/SO0/SDA
C6
P79/ANI9
F1
VSS
A13
PDH5/A21
C7
P05/INTP4
F2
X1
B1
AVDD
C8
P03/INTP2/TI4
F3
VDD
B2
AVREF0
C9
PCD1
F11
PDL11/AD11
B3
P72/ANI2
C10
P01/INTP0/TI2
F12
PDL13/AD13
B4
P712/ANI12
C11
P44/INTP01/TO0
F13
PDL12/AD12
B5
P75/ANI5
C12
PDH3/A19
G1
RESET
B6
P77/ANI7
C13
PDH7/A23
G2
XT1
B7
P710/ANI10
D1
P81/ANO1
G3
X2
Note SCL and SDA are valid only for µPD703204Y and 70F3204Y.
Remark
4
Pin Name
Connect the D4 pin directly to VSS.
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2/2)
Pin No.
Pin Name
G11
EVSS
G12
PDL10/AD10
G13
Pin No.
K13
Pin Name
Pin No.
Pin Name
PDL3/AD3
M7
PCS4
L1
P93/A3/INTP6
M8
PCM0/WAIT
EVDD
L2
P94/A4/TO2
M9
PCM2/HLDAK
H1
VSSBU
L3
P911/A11/SO2
M10
PCT3
H2
VDDBU
L4
P914/A14/SO3
M11
PCT4/RD
H3
XT2
L5
P915/A15/SCK3
M12
PCT7
H11
PDL8/AD8
L6
EVDD
M13
PDL0/AD0
Notes 1, 2
H12
IC/FLMD0
L7
PCS0/CS0
N1
P96/A6/TO4
H13
PDL9/AD9
L8
PCS2/CS2
N2
P98/A8/RXD1
J1
P20/SI4
L9
PCM4
N3
P910/A10/SI2
J2
P91/A1
L10
PCT2
N4
P912/A12/SCK2
J3
P90/A0
L11
PCT0/WR0
N5
PCS7
Note 1
J11
PDL5/AD5/FLMD1
L12
PDL1/AD1
N6
PCS6
J12
PDL7/AD7
L13
PDL2/AD2
N7
PCS1/CS1
J13
PDL6/AD6
M1
P95/A5/TO3
N8
PCS3/CS3
K1
P22/SCK4
M2
P97/A7/TO5
N9
PCM5
K2
P92/A2/INTP5
M3
P99/A9/TXD1
N10
PCM3/HLDRQ
K3
P21/SO4
M4
P913/A13/SI3
N11
PCT1/WR1
K11
PCM1/CLKOUT
M5
EVSS
N12
PCT5
K12
PDL4/AD4
M6
PCS5
N13
PCT6/ASTB
Notes 1. FLMD0 and FLMD1 are valid only for µPD70F3204Y and 70F3204Y.
2. IC: Connect directly to VSS (µPD703204, 703204Y).
FLMD0: Connect to VSS in normal mode (µPD70F3204, 70F3204Y).
Preliminary Product Information U15436EJ1V0PM
5
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
PIN IDENTIFICATION
A0 to A23:
Address bus
PCD1 to PCD3:
Port CD
AD0 to AD15:
Address/data bus
PCM0 to PCM5:
Port CM
ADTRG:
AD trigger input
PCS0 to PCS7:
Port CS
ANI0 to ANI15:
Analog input
PCT0 to PCT7:
Port CT
ANO0, ANO1:
Analog output
PDH0 to PDH7:
Port DH
ASTB:
Address strobe
PDL0 to PDL15:
Port DL
AVDD:
Analog VDD
RD:
Read
AVREF0, AVREF1:
Analog reference voltage
RESET:
Reset
AVSS:
Analog VSS
RXD0, RXD1:
Receive data
CLKOUT:
Clock output
SCK0 to SCK4:
Serial clock
CS0 to CS3:
Chip select
SCL:
Serial clock
EVDD:
Power supply for port
SDA:
Serial data
EVSS:
Ground for port
SI0 to SI4:
Serial input
FLMD0, FLMD1:
Flash programming mode
SO0 to SO4:
Serial output
HLDAK:
Hold acknowledge
TCLR0, TCLR1:
Timer clear input
HLDRQ:
Hold request
TI0 to TI5:
Timer input
IC:
Internally connected
TO0 to TO5:
Timer output
INTP0 to INTP6:
Interrupt request from peripherals
TXD0, TXD1:
Transmit data
INTP00, INTP01,:
Interrupt request to timer
INTP10, INTP11
VDD:
Power supply
VDDBU:
Power supply for backup
NMI:
Non-maskable interrupt request
VSS:
Ground
P00 to P05:
Port 0
VSSBU:
Ground for backup
P20 to P22:
Port 2
WAIT:
Wait
P30 to P32:
Port 3
WR0:
Write strobe low level data
P40 to P46:
Port 4
WR1:
Write strobe high level data
P70 to P715:
Port 7
X1, X2:
Crystal for main clock
P80, P81:
Port 8
XT1, XT2:
Crystal for subclock
P90 to P915:
Port 9
6
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
INTERNAL BLOCK DIAGRAM
• V850ES/SA2
NMI
INTP0 to INTP6
INTP00, INTP01,
INTP10, INTP11
TCLR0, TCLR1
TI0, TI1
ROM
CPU
INTC
Timer/counter
16-bit timer:
2 ch
Note 1
PC
RAM
32-bit barrel
shifter
16 KB
System
registers
TO0, TO1
Instruction
queue
Multiplier
16 × 16 → 32
BCU
ALU
General-purpose
TI2 to TI5
TO2 to TO5
ROM
correction
Timer/counter
8-bit timer:
4 ch
registers 32-bits × 32
HLDRQ
HLDAK
ASTB
RD
WAIT
WR0, WR1
CS0 to CS3
A0 to A21
AD0 to AD15
DMAC
SIO
SO0 to SO3
SI0 to SI3
SCK0 to SCK3
CSI: 4 ch
Ports
D/A
converter
TXD0, TXD1
X1
CG
I2CNote 2: 1 ch
Note 2
SCL
Real-time
counter
Watchdog
timer
Notes 1. µPD703201, 703201Y:
µPD70F3201, 70F3201Y:
AVDD
AVREF0
AVSS
ANI0 to ANI11
Note 2
X2
XT1
ANO0, ANO1
AVREF1
PCS0 to PCS3
PCM0 to PCM3
PCT0, PCT1, PCT4 to PCT7
PDH0 to PDH5
PDL0 to PDL15
P90 to P915
P80, P81
P70 to P711
P40 to P46
P30 to P32
P00 to P05
UART: 2 ch
RXD0, RXD1
SDA
CLKOUT
A/D
converter
XT2
RG
RESET
ICNote 3
FLMD0Note 4, FLMD1Note 4
VDD
VSS
VDDBU
VSSBU
EVDD
EVSS
256 KB (mask ROM)
256 KB (flash memory)
2. Applies to the µPD703201Y and 70F3201Y only.
3. Applies to the µPD703201 and 703201Y only.
4. Applies to the µPD70F3201 and 70F3201Y only.
Preliminary Product Information U15436EJ1V0PM
7
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
• V850ES/SA3
NMI
INTP0 to INTP6
INTP00, INTP01,
INTP10, INTP11
TCLR0, TCLR1
TI0, TI1
ROM
CPU
INTC
Timer/counter
16-bit timer:
2 ch
Note 1
PC
RAM
32-bit barrel
shifter
16 KB
System
registers
TO0, TO1
Instruction
queue
HLDRQ
HLDAK
ASTB
RD
WAIT
WR0, WR1
CS0 to CS3
A0 to A23
AD0 to AD15
Multiplier
16 × 16 → 32
BCU
ALU
General-purpose
TI2 to TI5
TO2 to TO5
Timer/counter
8-bit timer:
4 ch
ROM
correction
registers 32-bits × 32
DMAC
SIO
SO0 to SO4
SI0 to SI4
SCK0 to SCK4
CSI: 5 ch
Ports
D/A
converter
TXD0, TXD1
Real-time
counter
Watchdog
timer
Notes 1. µPD703204, 703204Y:
256 KB (mask ROM)
µPD70F3204, 70F3204Y: 256 KB (flash memory)
2. Applies to the µPD703204Y and 70F3204Y only.
3. Applies to the µPD703204 and 703204Y only.
4. Applies to the µPD70F3204 and 70F3204Y only.
8
X2
Preliminary Product Information U15436EJ1V0PM
AVDD
AVREF0
AVSS
ANI0 to ANI15
XT1
ANO0, ANO1
AVREF1
I2CNote 2:1 ch
Note 2
PCS0 to PCS7
PCM0 to PCM5
PCT0 to PCT7
PDH0 to PDH7
PDL0 to PDL15
PCD1 to PCD3
P90 to P915
P80, P81
P70 to P715
P40 to P46
P30 to P32
P20 to P22
P00 to P05
RXD0, RXD1
SCL
X1
CG
UART: 2 ch
SDANote 2
CLKOUT
A/D
converter
XT2
RG
RESET
ICNote 3
FLMD0Note 4, FLMD1Note 4
VDD
VSS
VDDBU
VSSBU
EVDD
EVSS
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
CONTENTS
1.
2.
PIN FUNCTIONS ................................................................................................................................11
1.1
Port Pins ................................................................................................................................................... 11
1.2
Non-Port Pins........................................................................................................................................... 14
1.3
Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 18
FUNCTION BLOCKS .........................................................................................................................22
2.1
Internal Units............................................................................................................................................ 22
3.
CPU FUNCTIONS................................................................................................................................25
4.
MEMORY MAP ...................................................................................................................................26
5.
EXTERNAL BUS INTERFACE FUNCTION.....................................................................................28
6.
INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION ..............................................31
7.
CLOCK GENERATION FUNCTION..................................................................................................34
8.
POWER SAVE FUNCTION ...............................................................................................................35
9.
TIMER/COUNTER FUNCTION...........................................................................................................37
10. REAL-TIME COUNTER FUNCTION .................................................................................................40
11. WATCHDOG TIMER FUNCTION......................................................................................................41
12. SERIAL INTERFACE FUNCTION.....................................................................................................42
12.1 3-Wire Serial I/O (CSIn)............................................................................................................................ 42
12.2 Asynchronous Serial Interface (UART0 and UART1) ........................................................................... 44
12.3 I C Bus (I C) (µPD703201Y, 703204Y, 70F3201Y, 70F3204Y) ................................................................ 45
2
2
13. A/D CONVERTER...............................................................................................................................46
14. D/A CONVERTER...............................................................................................................................48
15. DMA FUNCTION.................................................................................................................................49
16. ROM CORRECTION FUNCTION ......................................................................................................50
17. RESET FUNCTION.............................................................................................................................51
18. FLASH MEMORY (µPD70F3201, 70F3201Y, 70F3204, 70F3204Y) ............................................52
19. INSTRUCTION SET LIST..................................................................................................................54
19.1 Conventions ............................................................................................................................................. 54
Preliminary Product Information U15436EJ1V0PM
9
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
19.2 Instruction Set (In Alphabetical Order) ..................................................................................................57
20. ELECTRICAL SPECIFICATIONS (TARGET VALUES) ................................................................. 64
21. PACKAGE DRAWINGS..................................................................................................................... 92
APPENDIX DEVELOPMENT TOOLS ..................................................................................................... 94
10
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
1. PIN FUNCTIONS
1.1 Port Pins
(1/3)
Pin Name
P00
I/O
I/O
PULL
Yes
P01
Function
Port 0
6-bit I/O port
Input/output can be specified in 1-bit units.
Alternate Function
NMI
INTP0/TI2
P02
INTP1/TI3
P03
INTP2/TI4
P04
INTP3/TI5
INTP4
P05
[P20]
I/O
Yes
[P21]
[P22]
P30
I/O
Yes
P31
P32
P40
I/O
Yes
P41
P42
Port 2
3-bit I/O port
Input/output can be specified in 1-bit units.
N-ch open drain can be specified in 1-bit units (P21, P22 only).
Port 3
3-bit I/O port
Input/output can be specified in 1-bit units.
N-ch open drain can be specified in 1-bit units (P31, P32 only).
Port 4
7-bit I/O port
Input/output can be specified in 1-bit units.
N-ch open drain can be specified in 1-bit units (P41, P42 only).
[SI4]
[SO4]
[SCK4]
SI1/RXD0
SO1/TXD0
SCK1
SI0
SO0/SDANote
SCK0/SCLNote
P43
INTP00/TI0/TCLR0
P44
INTP01/TO0
P45
INTP10/TI1/TCLR1
P46
INTP11/TO1
P70
P71
Input
No
Port 7
12-bit input port (V850ES/SA2)
16-bit input port (V850ES/SA3)
ANI0
ANI1
P72
ANI2
P73
ANI3
P74
ANI4
P75
ANI5
P76
ANI6
P77
ANI7
P78
ANI8
P79
ANI9
P710
ANI10
P711
ANI11
[P712]
[ANI12]
[P713]
[ANI13]
[P714]
[ANI14]
[P715]
[ANI15]
Note Applies to the µPD703201Y, 703204Y, 70F3201Y, and 70F3204Y only.
Remarks 1. PULL: On-chip pull-up resistor
2. Pins in brackets ([ ]) are only for the V850ES/SA3.
Preliminary Product Information U15436EJ1V0PM
11
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2/3)
Pin Name
P80
I/O
Input
PULL
No
P81
P90
I/O
Yes
P91
P92
P93
Function
Alternate Function
Port 8
2-bit input port
ANO0
Port 9
16-bit I/O port
Input/output can be specified in 1-bit units.
N-ch open drain can be specified in 1-bit units (P911, P912,
P914, P915 only).
A0
ANO1
A1
A2/INTP5
A3/INTP6
P94
A4/TO2
P95
A5/TO3
P96
A6/TO4
P97
A7/TO5
P98
A8/RXD1
P99
A9/TXD1
P910
A10/SI2
P911
A11/SO2
P912
A12/SCK2
P913
A13/SI3
P914
A14/SO3
P915
A15/SCK3
[PCD1]
I/O
No
[PCD2]
Port CD
3-bit I/O port
Input/output can be specified in 1-bit units.
–
–
–
[PCD3]
PCM0
I/O
No
PCM1
4-bit I/O port (V850ES/SA2)
6-bit I/O port (V850ES/SA3)
Input/output can be specified in 1-bit units.
WAIT
CLKOUT
PCM2
HLDAK
PCM3
HLDRQ
[PCM4]
–
[PCM5]
–
PCS0
PCS1
PCS2
I/O
No
Port 10
4-bit I/O port (V850ES/SA2)
8-bit I/O port (V850ES/SA3)
Input/output can be specified in 1-bit units.
PCS3
CS0
CS1
CS2
CS3
[PCS4]
–
[PCS5]
–
[PCS6]
–
[PCS7]
–
Remarks 1. PULL: On-chip pull-up resistor
2. Pins in brackets ([ ]) are only for the V850ES/SA3.
12
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(3/3)
Pin Name
PCT0
I/O
I/O
PULL
No
PCT1
[PCT2]
Function
Port CT
6-bit I/O port (V850ES/SA2)
8-bit I/O port (V850ES/SA3)
Input/output can be specified in 1-bit units.
Alternate Function
WR0
WR1
–
[PCT3]
–
PCT4
RD
PCT5
–
PCT6
ASTB
–
PCT7
PDH0
I/O
No
PDH1
PDH2
Port DH
6-bit I/O port (V850ES/SA2)
8-bit I/O port (V850ES/SA3)
Input/output can be specified in 1-bit units.
A16
A17
A18
PDH3
A19
PDH4
A20
PDH5
A21
[PDH6]
[A22]
[PDH7]
[A23]
PDL0
PDL1
I/O
No
Port DL
16-bit I/O port
Input/output can be specified in 1-bit units.
AD0
AD1
PDL2
AD2
PDL3
AD3
PDL4
AD4
PDL5
AD5/FLMD1Note
PDL6
AD6
PDL7
AD7
PDL8
AD8
PDL9
AD9
PDL10
AD10
PDL11
AD11
PDL12
AD12
PDL13
AD13
PDL14
AD14
PDL15
AD15
Note Applies to the µPD70F3201, 70F3201Y, 70F3204, and 70F3204Y only.
Remarks 1. PULL: On-chip pull-up resistor
2. Pins in brackets ([ ]) are only for the V850ES/SA3.
Preliminary Product Information U15436EJ1V0PM
13
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
1.2 Non-Port Pins
(1/4)
Pin Name
A0
I/O
Output
PULL
Yes
Function
Address bus for external memory (when using separate bus)
Alternate Function
P90
A1
P91
A2
P92/INTP5
A3
P93/INTP6
A4
P94/TO2
A5
P95/TO3
A6
P96/TO4
A7
P97/TO5
A8
P98/RXD1
A9
P99/TXD1
A10
P910/SI2
A11
P911/SO2
A12
P912/SCK2
A13
P913/SI3
A14
P914/SO3
A15
P915/SCK3
A16 to A21,
[A22, A23]
Output
No
Address bus for external memory
PDH0 to PDH5,
[PDH6, PDH7]
AD0 to AD4
I/O
No
Address/data bus for external memory
PDL0 to PDL4
AD5
PDL5/FLMD1Note
AD6 to AD15
PDL6 to PDL15
ANI0
Input
No
Analog voltage input for A/D converter
P70
ANI1
P71
ANI2
P72
ANI3
P73
ANI4
P74
ANI5
P75
ANI6
P76
ANI7
P77
ANI8
P78
ANI9
P79
ANI10
P710
ANI11
P711
[ANI12]
[P712]
[ANI13]
[P713]
[ANI14]
[P714]
[ANI15]
[P715]
Note Applies to the µPD70F3201, 70F3201Y, 70F3204, and 70F3204Y only.
Remarks 1. PULL: On-chip pull-up resistor
2. Pins in brackets ([ ]) are only for the V850ES/SA3.
14
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2/4)
Pin Name
I/O
ANO0
Output
PULL
No
Function
Analog voltage output for D/A converter
ANO1
Alternate Function
P80
P81
ASTB
Output
AVDD
–
AVREF0
Input
No
–
PCT6
–
Positive power supply for A/D converter (same potential as VDD)
–
–
Reference voltage input for A/D converter
–
Reference voltage input for D/A converter
–
AVREF1
AVSS
Address strobe signal output for external memory
–
Ground potential for A/D, D/A converters (same potential as VSS)
–
CLKOUT
Output
No
Internal system clock output
PCM1
CS0 to CS3
Output
No
Chip select output
PCS0 to PCS3
EVDD
EVSS
Note 1
FLMD0
–
–
Positive power supply for external devices (same potential as
VDD)
–
–
–
Ground potential for external devices (same potential as VSS)
–
Flash programming mode lead-in pins
–
Input
No
Note 1
PDL5/AD5
FLMD1
HLDAK
Output
No
HLDRQ
Input
No
IC
–
INTP0 to INTP3
Input
–
Yes
INTP4
Bus hold acknowledge output
PCM2
Bus hold request input
PCM3
Internally connected (directly connect to VSS). (µPD703201,
703201Y, 703204, and 703204Y only)
External interrupt request input (maskable, analog noise
elimination)
–
P01/TI2 to P04/TI5
P05
INTP5
P92/A2
INTP6
P93/A3
INTP00
Input
Yes
Capture trigger input (TM0)
INTP01
P43/TI0/TCLR0
P44/TO0
INTP10
Capture trigger input (TM1)
P45/TI1/TCLR1
P46/TO1
INTP11
NMI
Input
Yes
External interrupt input (non-maskable, analog noise elimination)
P00
RD
Output
No
Read strobe signal output for external memory
PCT4
RESET
Input
–
RXD0
Input
Yes
I/O
Yes
RXD1
System reset input
Serial receive data input (UART0)
–
P30/SI1
Serial receive data input (UART1)
P98/A8
Serial clock I/O (CSI0)
P42/SCLNote 2
SCK1
Serial clock I/O (CSI1)
P32
SCK2
Serial clock I/O (CSI2)
P912/A12
SCK3
Serial clock I/O (CSI3)
P915/A15
[SCK4]
Serial clock I/O (CSI4)
[P22]
SCK0
Note 2
2
SCL
I/O
Yes
Serial clock I/O (I C)
P42/SCK0
SDANote 2
I/O
Yes
Serial transmit/receive data I/O (I2C)
P41/SO0
Notes 1. Applies to the µPD70F3201, 70F3201Y, 70F3204, and 70F3204Y only.
2. Applies to the µPD703201Y, 703204Y, 70F3201Y, and 70F3204Y only.
Remarks 1. PULL: On-chip pull-up resistor
2. Pins in brackets ([ ]) are only for the V850ES/SA3.
Preliminary Product Information U15436EJ1V0PM
15
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(3/4)
Pin Name
SI0
I/O
PULL
Function
Alternate Function
Serial receive data input (CSI0)
P40
SI1
Serial receive data input (CSI1)
P30/RXD0
SI2
Serial receive data input (CSI2)
P910/A10
SI3
Serial receive data input (CSI3)
P913/A13
[SI4]
Serial receive data input (CSI4)
[P20]
Serial transmit data output (CSI0)
P41/SDANote
SO1
Serial transmit data output (CSI1)
P31/TXD0
SO2
Serial transmit data output (CSI2)
P911/A11
SO3
Serial transmit data output (CSI3)
P914/A14
[SO4]
Serial transmit data output (CSI4)
[P21]
Timer clear input (TM0)
P43/INTP00/TI0
Timer clear input (TM1)
P45/INTP10/TI1
External event/clock input (TM0)
P43/INTP00/TCLR0
TI1
External event/clock input (TM1)
P45/INTP10/TCLR1
TI2
External event/clock input (TM2)
P01/INTP0
TI3
External event/clock input (TM3)
P02/INTP1
TI4
External event/clock input (TM4)
P03/INTP2
TI5
External event/clock input (TM5)
P04/INTP3
Timer output (TM0)
P44/INTP01
TO1
Timer output (TM1)
P46/INTP11
TO2
Timer output (TM2)
P94/A4
TO3
Timer output (TM3)
P95/A5
TO4
Timer output (TM4)
P96/A6
TO5
Timer output (TM5)
P97/A7
Serial transmit data output (UART0)
P31/SO1
Serial transmit data output (UART1)
P99/A9
SO0
TCLR0
Input
Output
Input
Yes
Yes
Yes
TCLR1
TI0
TO0
TXD0
Input
Output
Output
Yes
Yes
Yes
TXD1
VDD
–
–
Positive power supply pin for internal functions (except for
subclock oscillator, RTC, and internal RAM)
–
VDDBU
–
–
Positive power supply pin for backup (for subclock oscillator,
RTC and internal RAM)
–
VSS
–
–
Ground potential for internal functions (except for subclock
oscillator, RTC, and internal RAM)
–
VSSBU
–
–
Ground potential for backup (for subclock oscillator, RTC and
internal RAM)
–
WAIT
Input
No
External wait input
PCM0
WR0
Output
No
Write strobe for external memory (lower 8 bits)
PCT0
Write strobe for external memory (higher 8 bits)
PCT1
WR1
Note Applies to the µPD703201Y, 703204Y, 70F3201Y, and 70F3204Y only.
Remarks 1. PULL: On-chip pull-up resistor
2. Pins in brackets ([ ]) are only for the V850ES/SA3.
16
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(4/4)
Pin Name
X1
X2
XT1
XT2
Remark
I/O
Input
PULL
No
Function
Connecting resonator for main clock
–
Input
Alternate Function
–
–
No
Connecting resonator for subclock
–
–
–
PULL: On-chip pull-up resistor
Preliminary Product Information U15436EJ1V0PM
17
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
1.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are show in Table 1-1. For the
schematic circuit diagram of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuits (1/2)
Pin
Alternate Function
I/O Circuit Type
Recommended Connection of Unused Pins
5-W
Input: Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P00
NMI
P01 to P04
INTP0/TI2 to INTP3/TI5
P05
INTP4
[P20]
[SI4]
5-W
[P21]
[SO4]
10-E
[P22]
[SCK4]
10-F
P30
SI1/RXD0
5-W
P31
SO1/TXD0
10-E
P32
SCK1
10-F
P40
SI0
P41
P42
SO0/SDA
5-W
Note
10-F
Note
SCK0/SCL
10-F
P43
INTP00/TI0/TCLR0
5-W
P44
INTP01/TO0
P45
INTP10/TI1/TCLR1
P46
INTP11/TO1
P70 to
P711,
[P712 to
P715]
ANI0 to ANI15
9
P80, P81
ANO0, ANO1
34
P90, P91
A0, A1
5-A
P92, P93
A2/INTP5, A3/INTP6
5-W
P94 to P97
A4/TO2 to A7/TO5
5-A
P98
A8/RXD1
5-W
P99
A9/TXD1
5-A
P910
A10/SI2
5-W
P911
A11/SO2
10-E
P912
A12/SCK2
10-F
P913
A13/SI3
5-W
P914
A14/SO3
10-E
P915
A15/SCK3
10-F
[PCD1 to
PCD3]
–
PCM0
WAIT
PCM1
CLKOUT
PCM2
HLDAK
Independently connect to AVDD or AVSS via a resistor.
Input: Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
5
Note Applies to the µPD703201Y, 703204Y, 70F3201Y, and 70F3204Y only.
Remark
18
Pins in brackets ([ ]) are only for the V850ES/SA3.
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Table 1-1. Types of Pin I/O Circuits (2/2)
Pin
Alternate Function
PCM3
5
HLDRQ
[PCM4]
–
[PCM5]
–
PCS0 to
PCS3
I/O Circuit Type
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD or EVSS via a
resistor.
Output: Leave open.
CS0 to CS3
[PCS4 to
PCS7]
–
PCT0,
PCT1
WR0, WR1
[PCT2,
PCT3]
–
PCT4
RD
PCT5
–
PCT6
ASTB
PCT7
–
PDH0 to
PDH5,
[PDH6,
PDH7]
A16 to A21, [A22, A23]
PDL0 to
PDL4
AD0 to AD4
PDL5
AD5/FLMD1Note 1
PDL6 to
PDL15
AD6 to AD15
AVDD
–
–
AVREF0
–
–
Connect to AVSS via a resistor.
–
AVREF1
–
–
Connect to AVSS via a resistor.
AVSS
–
–
–
EVDD
–
–
–
EVSS
–
–
–
FLMD0Note 1
–
–
–
Note 2
IC
–
–
–
RESET
–
2
–
VDD
–
–
–
VDDBU
–
–
–
VSS
–
–
–
VSSBU
–
–
–
X1
–
–
–
X2
–
–
–
XT1
–
16
Connect to VSSBU via a resistor.
XT2
–
16
Leave open.
Notes 1. Applies to the µPD70F3201, 70F3201Y, 70F3204, and 70F3204Y only.
2. Applies to the µPD703201, 703201Y, 703204, and 703204Y only.
Remark
Pins in brackets ([ ]) are only for the V850ES/SA3.
Preliminary Product Information U15436EJ1V0PM
19
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Figure 1-1. Pin I/O Circuits (1/2)
Type 2
Type 5-W
EVDD
Pullup
enable
P-ch
EVDD
Data
P-ch
IN
IN/OUT
Output
disable
N-ch
Schmitt-triggered input with hysteresis characteristics
Input
enable
Type 9
Type 5
EVDD
Data
P-ch
P-ch
IN
+
IN/OUT
Output
disable
N-ch
N-ch
Comparator
–
AVREF0 (threshold voltage)
Input enable
Input
enable
Type 5-A
Pullup
enable
Data
EVDD
Type 10-E
EVDD
Pullup
enable
P-ch
P-ch
EVDD
EVDD
Data
P-ch
P-ch
IN/OUT
Output
disable
Input
enable
20
N-ch
IN/OUT
Open drain
Output disable
Input
enable
Preliminary Product Information U15436EJ1V0PM
N-ch
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Figure 1-1. Pin I/O Circuits (2/2)
Type 10-F
Type 34
EVDD
Pullup
enable
P-ch
P-ch
EVDD
Data
Analog output voltage
IN/OUT
N-ch
P-ch
IN/OUT
Open drain
N-ch
Output
disable
Input enable
Input
enable
Type 16
Feedback cut-off
P-ch
XT1
XT2
Preliminary Product Information U15436EJ1V0PM
21
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
2. FUNCTION BLOCKS
2.1 Internal Units
Each internal unit of the V850ES/SA2 and V850ES/SA3 is described below.
(1) CPU
The CPU uses five-stage pipeline control to enable 1-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32
bits), helps accelerate processing of complex instructions.
(2) Bus control unit (BCU)
The BCU starts the required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the
BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is
stored in an internal instruction queue.
(3) ROM
This consists of a 256 KB mask ROM or flash memory mapped to the address space 0000000H to 003FFFFH.
This area can be accessed by the CPU in 1-clock cycle when an instruction is fetched.
(4) RAM
This consists of a 16 KB RAM mapped to the address space 3FFB000H to 3FFEFFFH. This area can be
accessed by the CPU in 1-clock cycle.
(5) Interrupt controller (INTC)
This controller services hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware
and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and
multiple servicing control can be performed for interrupt sources.
(6) Clock generator (CG)
The clock generator includes two types of oscillators, one for the main clock (fXX) and one for the subclock (fXT),
generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, fXX/16, and fXX/32), and supplies one of them as the
operating clock for the CPU (fCPU). The subclock can only be selected as the operation clock of the real-time
counter.
(7) Timer/counter
A two-channel 16-bit timer/event counter and a four-channel 8-bit timer/event counter are incorporated, which
enables measurement of pulse intervals and frequency as well as programmable pulse output.
Two channels of the 8-bit timer/event counter can be connected via a cascade connection to enable use as a
16-bit timer.
22
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(8) Real-time counter (for watch)
This counter counts the reference time period (1 second) for watch counting by using the 32.768 kHz subclock
or the main clock. At the same time, the real-time counter can also be used as an interval timer that uses the
main clock as a source clock. This counter includes week, date, hour, minute, and second counters, and is
capable of counting up to 4,095 weeks.
(9) Watchdog timer
This timer detects inadvertent program loops, system abnormalities, etc.
It can also be used as an interval timer.
When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an overflow
occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an
overflow occurs.
(10)Serial interface (SIO)
The V850ES/SA2 and V850ES/SA3 incorporate three kinds of serial interfaces: asynchronous serial interfaces
(UART0 and UART1), clocked serial interfaces (V850E/SA2: CSI0 to CSI3, V850ES/SA3: CSI0 to CSI4), and
2
2
an I C bus interface (I C). The V850ES/SA2 is capable of using up to 4 channels and the V850ES/SA3 is
capable of using up to 5 channels simultaneously. Among these channels, one channel can be switched
2
between UART and CSI, and other one channel can be switched between CSI and I C.
For UART0 and UART1, data is transferred via the TXDO, TXD1, RXD0, and RXD1 pins.
For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins.
For CSI4, data is transferred via the SO4, SI4, and SCK4 pins (V850ES/SA3 only).
2
For I C, data is transferred via the SDA and SCL pins.
I C is incorporated in the µPD703201Y, 703204Y, 70F3201Y and 70F3204Y only.
2
UART includes an on-chip dedicated baud rate generator.
(11)A/D converter
This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins for the V850ES/SA2 and
16 for the V850ES/SA3. Conversion is performed using the successive approximation method.
(12)D/A converter
A two-channel 8-bit resolution D/A converter is incorporated. This D/A converter uses the R string method.
(13)DMA controller
A 4-channel DMA controller is incorporated. Data is transferred between internal RAM, on-chip peripheral I/O,
and external memory based on interrupt requests by the on-chip peripheral I/O.
(14)ROM correction
This is a function that replaces a part of the program in the mask ROM with a program in the internal RAM for
execution. Four points can be corrected.
Preliminary Product Information U15436EJ1V0PM
23
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(15)Ports
The ports function as both general-purpose ports and control pins, as shown below.
Port
P0
Note
I/O
6-bit I/O
Port Function
Generalpurpose port
Control Function
NMI, external interrupt, timer input
P2
3-bit I/O
Serial interface
P3
3-bit I/O
Serial interface
P4
7-bit I/O
Serial interface, timer I/O, timer trigger
P7
12-bit input (V850ES/SA2)
16-bit input (V850ES/SA3)
A/D converter analog input
P8
2-bit input
D/A converter analog output
P9
16-bit I/O
External address bus, serial interface, timer output, external
interrupt
PCDNote
3-bit I/O
–
PCM
4-bit I/O (V850ES/SA2)
6-bit I/O (V850ES/SA3)
External bus interface
PCS
4-bit I/O (V850ES/SA2)
8-bit I/O (V850ES/SA3)
Chip select output
PCT
6-bit I/O (V850ES/SA2)
8-bit I/O (V850ES/SA3)
External bus interface
PDH
6-bit I/O (V850ES/SA2)
8-bit I/O (V850ES/SA3)
External address bus
PDL
16-bit I/O
External address/data bus
Note V850ES/SA3 only
24
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
3. CPU FUNCTIONS
The CPU of the V850ES/SA2 and V850ES/SA3 is based on RISC architecture and executes most instructions in a
1-clock cycle by using a 5-stage pipeline.
The features of the CPU are as follows.
{ Minimum instruction execution time: 59 ns (@ 17 MHz operation with main system clock (fXX))
74 ns (@ 13.5 MHz operation with main system clock (fXX))
{ Address space: 64 MB linear
• Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB = Total four blocks
{ General-purpose registers: 32 bits × 32
{ Internal 32-bit architecture
{ 5-stage pipeline control
{ Multiplication/division instructions
{ Saturation operation instructions
{ 1-clock 32-bit shift instruction
{ Load/store instructions with long/short format
{ Internal memory
• Mask ROM:
256 KB (µPD703201, 703201Y, 703204, 703204Y)
Flash memory: 256 KB (µPD70F3201, 70F3201Y, 70F3204, 70F3204Y)
• RAM: 16 KB
{ Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
Preliminary Product Information U15436EJ1V0PM
25
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
4. MEMORY MAP
The memory maps of the V850ES/SA2 and V850ES/SA3 are shown below.
{ Address Space
Image 63
4 GB
Data space
Peripheral I/O area
Program space
Image 1
Peripheral I/O area
Internal RAM area
Programmable peripheral
I/O areaNote or
reserved area
Internal RAM area
Programmable peripheral
I/O area
Reserved area
64 MB
Reserved area
64 MB
Image 0
External memory area
External memory area
Internal ROM area
(external memory area)
16 MB
Internal ROM area
(external memory area)
Note The programmable peripheral I/O area in the data space can only be used for image 4n (n = 0 to 15). It
cannot be used for other images (reserved area).
Remark Internal ROM: 256 KB (0000000H to 003FFFFH)
Internal RAM: 16 KB (3FFB000H to 3FFEFFFH)
26
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
{ Data Memory Map
3FFFFFFH
On-chip peripheral area
(4 KB)
(80 KB)
3FFFFFFH
3FFF000H
3FFEFFFH
3FEC000H
3FEBFFFH
Internal RAM area
(16 KB)
3FFB000H
3FFAFFFH
Reserved area
Reserved area
1000000H
0FFFFFFH
3FEC000H
External memory areaNote 1
(8 MB)
CS3
External memory area
(4 MB)
CS2
0800000H
07FFFFFH
0400000H
03FFFFFH
01FFFFFH
External memory area
(2 MB)
CS1
0200000H
01FFFFFH
(2 MB)
CS0
External memory area
(1 MB)
0100000H
00FFFFFH
Internal ROM areaNote 2
(1 MB)
0000000H
0000000H
Notes 1. In the V850ES/SA2, this area is the 4 MB space of 0800000H to 0BFFFFFH (0C00000H to
0FFFFFFH is an image of 0800000H to 0BFFFFFH).
2. This area is used as an external memory area during data write access.
Preliminary Product Information U15436EJ1V0PM
27
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
5. EXTERNAL BUS INTERFACE FUNCTION
The V850ES/SA2 and V850ES/SA3 incorporate an external bus interface function that can be used to connect
memories, such as ROM or RAM, and peripheral I/O externally.
The external bus interface function has the following features.
{ Separate bus/multiplexed bus output selectable
{ 8-bit/16-bit data bus sizing function
{ Chip select function for four spaces
{ Wait function
• Programmable wait function
• External wait function
{ Idle state function
{ Bus hold function
The following pins are used for the external bus interface.
Table 5-1. List of Bus Control Pins (When Multiplexed Bus Is Selected)
Bus Control Pin
Alternate Function
I/O
PDL0 to PDL15
I/O
A16 to A23
PDH0 to PDH7
Output
WAIT
PCM0
Input
External wait control
CLKOUT
PCM1
Output
Internal system clock
CS0 to CS3
PCS0 to PCS3
Output
Chip select
WR0, WR1
PCT0, PCT1
Output
Write strobe signal
RD
PCT4
Output
Read strobe signal
ASTB
PCT6
Output
Address strobe signal
HLDRQ
PCM3
Input
HLDAK
PCM2
Output
AD0 to AD15
Note
Function
Address/data bus
Address bus
Bus hold control
Note A16 to A21 in the V850ES/SA2.
Table 5-2. List of Bus Control Pins (When Separate Bus Is Selected)
Bus Control Pin
Alternate Function
I/O
AD0 to AD15
PDL0 to PDL15
I/O
A0 to A15
P90 to P915
Output
Address bus
A16 to A23
PDH0 to PDH7
Output
Address bus
WAIT
PCM0
Input
External wait control
CLKOUT
PCM1
Output
Internal system clock
CS0 to CS3
PCS0 to PCS3
Output
Chip select
WR0, WR1
PCT0, PCT1
Output
Write strobe signal
RD
PCT4
Output
Read strobe signal
HLDRQ
PCM3
Input
HLDAK
PCM2
Output
Note
Function
Data bus
Bus hold control
Note A16 to A21 in the V850ES/SA2.
28
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
The number of basic clocks required for accessing each area in the address space is as follows.
Table 5-3. Number of Access Clocks
Area (Bus Width)
Internal ROM
(32 Bits)
Internal RAM
(32 Bits)
External Memory
(16 Bits)
Instruction fetch (normal access)
1
1 or 2
3 + nNote
Instruction fetch (branch)
2
1 or 2
3 + nNote
Operand data access
3
1
3 + nNote
Bus Cycle Type
Note 2 + n clocks when the separate bus is selected. n is the number of waits.
Figure 5-1. Example of Timing In Separate Bus Mode (Read → Write)
T1
T2
T1
T2
CLKOUT (output)
A0 to A23 (output)
Address
Address
RD (output)
WR0, WR1 (output)
AD0 to AD15 (I/O)
Data
Data
WAIT (input)
Remark The broken lines indicates the high-impedance state
Preliminary Product Information U15436EJ1V0PM
29
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Figure 5-2. Example of Timing In Multiplexed Bus Mode (Read → Write)
T1
T2
T3
T1
T2
T3
CLKOUT (output)
A0 to A23 (output)
AD0 to AD15 (I/O)
Address
Address
Data
Address
Address
ASTB (output)
WR0, WR1 (output)
RD (output)
WAIT (input)
Remark The broken lines indicate the high-impedance state.
30
Preliminary Product Information U15436EJ1V0PM
Data
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
6. INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
The features of the interrupt servicing/exception processing function are as follows.
{ Interrupt
• Non-maskable interrupt: 2 sources
• Maskable interrupt
µPD703201, 70F3201:
External 8, internal 30 sources
µPD703201Y, 70F3201Y: External 8, internal 31 sources
µPD703204, 70F3204:
External 8, internal 31 sources
µPD703204Y, 70F3204Y: External 8, internal 32 sources
• 8-level programmable priority control
• Mask specification for the interrupt request according to priority
• Mask specification for each maskable interrupt request
• Noise elimination, edge detection, and valid edge specification of an external interrupt request
{ Exceptions
• Software exception: 32 sources
• Exception trap: 2 sources (illegal op code exception, debug trap)
Table 6-1 shows the interrupt/exception sources.
Preliminary Product Information U15436EJ1V0PM
31
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Table 6-1. Interrupt Source List (1/2)
Type
Classification
Default
Priority
Name
Interrupt
−
RESET
NonInterrupt
maskable
−
NMI
−
INTWDT
Reset
Trigger
RESET pin input
Genera- Exception
ting Unit
Code
Handler
Address
Restored
PC
Interrupt
Control
Register
0000H
00000000H
Undefined
−
−
0010H
00000010H
nextPC
−
WDT
0020H
Pin
WDT overflow (WDTRES) WDT
Software Exception
exception
−
NMI pin valid edge input
WDT overflow
Note
TRAP0n
TRAP instruction
−
00000020H
nextPC
−
Note
00000040H
nextPC
−
Note
004nH
−
TRAP1n
TRAP instruction
−
005nH
00000050H
nextPC
−
Exception Exception
trap
−
ILGOP/
DBG0
Illegal op code/
DBTRAP instruction
−
0060H
00000060H
nextPC
−
Maskable Interrupt
0
INTWDTM
Internal timer overflow
WDT
0080H
00000080H
nextPC
WDTIC
1
INTP0
INTP0 pin valid edge
input
Pin
0090H
00000090H
nextPC
PIC0
2
INTP1
INTP1 pin valid edge
input
Pin
00A0H
000000A0H
nextPC
PIC1
3
INTP2
INTP2 pin valid edge
input
Pin
00B0H
000000B0H
nextPC
PIC2
4
INTP3
INTP3 pin valid edge
input
Pin
00C0H
000000C0H
nextPC
PIC3
5
INTP4
INTP4 pin valid edge
input
Pin
00D0H
000000D0H
nextPC
PIC4
6
INTP5
INTP5 pin valid edge
input
Pin
00E0H
000000E0H
nextPC
PIC5
7
INTP6
INTP6 pin valid edge
input
Pin
00F0H
000000F0H
nextPC
PIC6
8
INTRTC
RTC interrupt
RTC
0100H
00000100H
nextPC
RTCIC
9
INTCC00
CC00 capture trigger
input/match between
TM0 and CC00
TM0
0110H
00000110H
nextPC
CCIC00
10
INTCC01
CC01 capture trigger
input/match between
TM0 and CC01
TM0
0120H
00000120H
nextPC
CCIC01
11
INTOVF0
TM0 overflow
TM0
0130H
00000130H
nextPC
OVFIC0
12
INTCC10
CC10 capture trigger
input/match between
TM1 and CC10
TM1
0140H
00000140H
nextPC
CCIC10
13
INTCC11
CC11 capture trigger
input/match between
TM1 and CC11
TM1
0150H
00000150H
nextPC
CCIC11
14
INTOVF1
TM1 overflow
TM1
0160H
00000160H
nextPC
OVFIC1
15
INTTM2
Match between TM2 and TM2
CR2/TM2 overflow
0170H
00000170H
nextPC
TMIC2
16
INTTM3
Match between TM3 and TM3
CR3/TM3 overflow
0180H
00000180H
nextPC
TMIC3
Note
Note n: Value of 0 to FH
32
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Table 6-1. Interrupt Source List (2/2)
Type
Classification
Maskable Interrupt
Default
Priority
Name
Trigger
Genera- Exception
ting Unit
Code
Handler
Address
Restored Interrupt
PC
Control
Register
17
INTTM4
Match between TM4 and TM4
CR4/TM4 overflow
0190H
00000190H
nextPC
TMIC4
18
INTTM5
Match between TM5 and TM5
CR5/TM5 overflow
01A0H
000001A0H
nextPC
TMIC5
19
INTCSI0
CSI0 transfer end
01B0H
000001B0H
nextPC
CSIIC0
Note 1
2
CSI0
2
20
INTIIC
I C transfer end
IC
01C0H
000001C0H
nextPC
IICIC0
21
INTCSI1
CSI1 transfer end
CSI1
01D0H
000001D0H
nextPC
CSIIC1
22
INTSRE0
UART0 receive error
UART0
01E0H
000001E0H
nextPC
SREIC0
23
INTSR0
UART0 receive end
UART0
01F0H
000001F0H
nextPC
SRIC0
24
INTST0
UART0 transfer end
UART0
0200H
00000200H
nextPC
STIC0
25
INTCSI2
CSI2 transfer end
CSI2
0210H
00000210H
nextPC
CSIIC2
26
INTSRE1
UART1 receive error
UART1
0220H
00000220H
nextPC
SREIC1
27
INTSR1
UART1 receive end
UART1
0230H
00000230H
nextPC
SRIC1
28
INTST1
UART1 transmit end
UART1
0240H
00000240H
nextPC
STIC1
29
INTCSI3
CSI3 transfer end
CSI3
0250H
00000250H
nextPC
CSIIC3
30
INTCSI4Note 2 CSI4 transfer end
CSI4
0260H
00000260H
nextPC
CSIIC4
31
INTAD
A/D conversion end
ADC
0270H
00000270H
nextPC
ADIC
32
INTDMA0
DMA0 transfer end
DMA
0280H
00000280H
nextPC
DMAIC0
33
INTDMA1
DMA1 transfer end
DMA
0290H
00000290H
nextPC
DMAIC1
34
INTDMA2
DMA2 transfer end
DMA
02A0H
000002A0H
nextPC
DMAIC2
35
INTDMA3
DMA3 transfer end
DMA
02B0H
000002B0H
nextPC
DMAIC3
36
INTROV
RTC overflow
RTC
02C0H
000002C0H
nextPC
ROVIC
37
INTBRG
BRG match
BRG
02D0H
000002D0H
nextPC
BRGIC
Note 1. Valid for the µPD703201Y, 70F3201Y, 703204Y and 70F3204Y only.
2. Valid for the V850E/SA3 only.
Remarks 1.
Default Priority:
Priority that applies when two or more maskable interrupt requests occur at the
same time. The highest priority is 0.
Restored PC:
The value of the PC saved to EIPC or FEPC when interrupt servicing/exception
processing is started. However, the value of the restored PC saved when an
interrupt is acknowledged during division instruction (DIV, DIVH, DIVU, DIVHU)
execution is the value of the PC of the current instruction (DIV, DIVH, DIVU,
DIVHU).
nextPC:
The value of the PC to be processed after an interrupt/exception.
2. The execution address of the illegal instruction when an illegal op code exception occurs is
calculated with (Restored PC − 4).
Preliminary Product Information U15436EJ1V0PM
33
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
7. CLOCK GENERATION FUNCTION
The clock generation function has the following features.
{ Main clock oscillator
• 2 to 17 MHz (@ VDD = 2.3 to 2.7 V operation)
• 2 to 13.5 MHz (@ VDD = 2.2 to 2.7 V operation)
{ Subclock oscillator
• 32.768 kHz (@ VDD = 2.2 to 2.7 V operation)
{ Internal system clock generation
• 6 levels (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32)
{ Peripheral clock generation
{ Clock output function
The following figure shows the configuration of the clock generation function.
FRC bit
XT1
XT2
Subclock
oscillator
fXT
fXT
fX/26 to fX/29
Prescaler 3
RTC clock
A/D converter
IDLE mode
MFRC bit
CK2 to CK0 bits
X2
Main clock
oscillator
fX
IDLE
control
fXX
Prescaler 2
HALT mode
fXX/32
fXX/16
Main clock
oscillator
stop control
fXX/8
fXX/4
fXX/2
STOP mode
Selector
X1
HALT fCPU
control
fCLK
fXX
Prescaler 1
WDT clock control
CLKOUT
Port CM
Remark fX, fXX: Main clock frequency
fXT: Subclock frequency
fCPU: CPU clock frequency
fCLK: Internal system clock frequency
fXW: Watchdog timer clock frequency
34
Preliminary Product Information U15436EJ1V0PM
fXX to fXX/512
fXW
CPU clock
Internal system
clock
Peripheral clock
WDT clock
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
8. POWER SAVE FUNCTION
The V850ES/SA2 and V850ES/SA3 have the following power save functions to realize an effective low-powerconsuming system.
{ HALT mode:
Only the clock of the CPU is stopped in this mode.
{ IDLE mode:
All operations on the chip other than oscillator operation are stopped in this mode.
{ STOP mode:
All operations on the chip other than subclock oscillator operation are stopped in this mode.
{ Backup mode:
The power supply other than for the subclock oscillator, real-time counter, and internal
RAM can be disconnected.
The following table shows the operating states of the on-chip peripheral functions in each mode.
Parameter
HALT Mode
IDLE Mode
VDD, EVDD, AVDD
Power supplied
VDDBU
Power supplied
CPU operation
Stopped
On-chip peripheral function
operation
Enabled
Main clock oscillator operation
Enabled
Subclock oscillator operation
Enabled
Real-time counter function,
RAM retention
Enabled
Release condition
• Non-maskable interrupt request
• Unmasked maskable interrupt request
• RESET pin input
STOP Mode
Backup Mode
Power OFF possible
Stopped
Stopped
Preliminary Product Information U15436EJ1V0PM
RESET pin input
after power is
supplied
35
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
• Backup mode overview
The V850ES/SA2 and V850ES/SA3 are put in backup mode by stopping supplying power other than the backup
power supply (VDDBU) in STOP mode.
The backup power supply supplies power only to the subclock oscillator, real-time counter, and internal RAM, as
shown in the figure below. Other on-chip functions including the CPU cannot operate since the power supply is
stopped.
Power supply
for backup
VDDBU
Backup power
supply status
flag (BPSF)
Power supply
for operation
VDD
CPU
AVDD
A/D
converter
EVDD
Connect to
VSS in backup
mode
I/O
function
ROM
RAM
Real-time
counter
Peripheral
function
Subclock
oscillator
Main clock
oscillator
VSSBU
D/A
converter
VSS
AVSS
EVSS
In backup mode, subclock oscillator operation, real-time counter count operation, and internal RAM data
retention are enabled.
If the voltage is lower than the data retention voltage in backup mode, a backup power supply status flag (BPSF)
is set and that internal RAM retention data can be detected as invalid. When this flag is set, the real-time
counter and the RAM should be initialized at reset start.
RESET (input)
VDD, EVDD, AVDD
VDDBU
(VDDBU is lower than
data retention voltage)
Backup power
supply status flag
(BPSF)
CPU status
Normal STOP Reset
operation mode mode
Backup mode
Reset Oscillation
mode stabilization
BPSF STOP
clear execution
36
Preliminary Product Information U15436EJ1V0PM
Normal
operation
BPSF confirmed
BPSF
(set → initialization) cleared
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
9. TIMER/COUNTER FUNCTION
The timer/counter function has the following features.
{ 16-bit timer/counter (TM0, TM1)
• Capture/compare common registers: 2 for each
• Interrupt request sources
• Capture/match interrupt requests: 2 sources for each
• Overflow interrupt requests: 1 source for each
• Timer/counter count clock sources: 2 types
(Selection of external pulse input or internal system clock division)
• Either free-running mode or overflow stop mode can be selected as the operation mode when the
timer/counter overflows
• Timer/counter can be cleared by a match of the timer/counter and a compare register
• External pulse outputs: 1 for each
{ 8-bit timers (TM2 to TM5)
• Stand-alone mode (mode in which a single timer is used)
• Interval timer
• External event counter
• Square-wave output
• PWM output
• Cascade connection mode (mode in which two timers are used connected in cascade: 16-bit resolution)
• 16-bit resolution interval timer
• 16-bit resolution external event counter
• 16-bit resolution square-wave output
Preliminary Product Information U15436EJ1V0PM
37
µ
!!
"
#
fXX
Selector
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
fXX/256
Clear & start
TMn (16 bits)
TCLRn
TCLRn/TIn/INTPn0
INTPn1
Note 1
Note 2
INTPn0
INTOVn
Note 3
Note 3
Note 3
Note 2
CCn0
CCn1
S
Note 4
R
Q
Q
Selector
TIn
TOnNote 1
INTCCn0
INTCCn1
$
%
!
!
!
&
%#
$!
'!
%
(
)
**+
,
-
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2) TM2 to TM5
Mask circuit
8-bit compare
register n (CRn)
Selector
Match
TIn
Count clockNote
8-bit counter n OVF
(TMn)
Selector
INTTMn
S
INV Q
Selector
Internal bus
R
TOn
Clear
3
S
Q
R
Selector
TCLn2 TCLn1 TCLn0
Invert
level
TCEn TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn
Timer clock
select register n (TCLn)
Timer mode control
register n (TMCn)
Internal bus
Note The count clock is set by the TCLn register.
• When n = 2, 3
• When n = 4, 5
fXX/4
fXX/4
fXX/8
fXX/8
fXX/16
fXX/16
fXX/32
fXX/32
fXX/128
fXX/128
fXX/512
fXX/256
Remarks 1. “
]” is a signal that can be directly connected to a port.
2. n = 2 to 5
Preliminary Product Information U15436EJ1V0PM
39
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
10. REAL-TIME COUNTER FUNCTION
The real-time counter function has the following features.
{ Includes counters of weeks, days, hours, minutes, and seconds, and can count up to 4,095 weeks.
{ Counters of weeks, days, hours, minutes, and seconds can be read during operation and while operation is
stopped.
{ Week counter overflow interrupt request occurrence (INTROV)
{ Interval interrupt request occurrence (INTRTC) at a fixed interval (can be selected from the following)
0.015625 seconds, 0.03125 seconds, 0.0625 seconds, 0.125 seconds, 0.25 seconds, 0.5 seconds, 1 second,
1 minute, 1 hour, 1 day
{ When subclock (fXT) is selected, operable only with power supply to VDDBU.
The following figure shows the configuration of the real-time counter function.
fXT
6
fX/2 to
fX/29
Selector
Count clock = 32.768 kHz
Subcounter
(15 bits)
1 second
Second counter
(6 bits)
1 minute
1 hour
Minute counter
(6 bits)
Selector
0.015625 seconds/0.03125 seconds/0.0625 seconds/0.125 seconds/
0.25 seconds/0.5 seconds
INTRTC
Week counter
(12 bits)
INTROV
1 day
Hour counter
(5 bits)
Day counter
(3 bits)
Count enable/
disable circuit
Second counter
write buffer
Minute counter
write buffer
Hour counter
write buffer
Day counter
write buffer
Internal bus
Remark fX:
Main clock frequency
fXT: Subclock frequency
40
Preliminary Product Information U15436EJ1V0PM
Week counter
write buffer
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
11. WATCHDOG TIMER FUNCTION
The watchdog timer has the following functions.
{ Watchdog timer
{ Interval timer
{ Timer for oscillation stabilization
The following figure shows the configuration of the watchdog timer function.
OSCMD
RUN
Clear
13-bit divider
fXW/213
fXW/212
fXW/211
fXW/210
fXW/29
fXW/28
fXW/27
fXW/26
fXW/25
Clear
Selector
fXW
8-bit counter
INTWDTM
OVF
Output
control
INTWDT
WDTRES
OSTOVF
OSTS0 to OSTS2,
WDCS0 to WDCS2
WDTM3, WDTM4
Remarks 1. WDTRES:
Reset signal triggered by WDT overflow
OSTOVF:
Overflow signal for oscillation stabilization
OSCMD:
Timer mode signal for oscillation stabilization
fXW:
Watchdog timer clock frequency
2. During counting of oscillation stabilization time: fXW = fX/2
Other than above:
fXW = fXX/2
Preliminary Product Information U15436EJ1V0PM
41
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
12. SERIAL INTERFACE FUNCTION
The V850ES/SA2 and V850ES/SA3 include the following three types of serial interfaces.
Type
V850ES/SA2
V850ES/SA3
3-wire serial I/O
4 channels (CSI0 to CSI3)
5 channels (CSI0 to CSI4)
Asynchronous serial interface
2 channels (UART0, UART1)
I2C busNote
1 channel (I2C)Note
Note Available only in the µPD703201Y, 703204Y, 70F3201Y, and 70F3204Y.
Some functions are used alternately as follows.
• CSI0/I C
2
• CSI1/UART0
• CSI2
• UART1
• CSI3
• CSI4 (V850ES/SA3 only)
12.1 3-Wire Serial I/O (CSIn)
Remark In this section, the value of n is as follows.
n = 0 to 3 (V850ES/SA2)
n = 0 to 4 (V850ES/SA3)
The 3-wire serial I/O (CSIn) transfers data using following three lines.
• SCKn (serial clock)
• SOn (serial data output)
• SIn (serial data input)
The 3-wire serial I/O (CSIn) has the following features.
{ Transfer data length: Fixed to 8 bits
{ Transfer data MSB/LSB first can be switched
{ Transfer clock can be selected from eight clocks (seven master clocks, one slave clock)
{ Transmit/receive mode or receive-only mode can be specified
{ On-chip 8-bit transmit buffer
{ Transfer data transmit/receive timing with respect to the transfer clock can be changed
42
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
The following figure shows the configuration of the 3-wire serial I/O (CSIn).
CKSn0 to CKSn2
Selector
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
TOFm
INTCSIn
Transfer clock controller
CSOTn
SCKn
Transfer mode controller
CSIEn, TRMDn, DIRn,
CKPn, DAPn
Transfer data controller
Transmit buffer (SOTBn)
SIn
Selector
SOn
SOn latch
Shift register (SIOn)
Remarks 1. When n = 0: m = 2
When n = 1: m = 3
When n = 2: m = 4
When n = 3: m = 5
When n = 4: m = 5 (V850ES/SA3 only)
2. fXX: Main clock frequency
Preliminary Product Information U15436EJ1V0PM
43
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
12.2 Asynchronous Serial Interface (UART0 and UART1)
The asynchronous serial interface (UART0 and UART1) has the following features.
{ Two modes
• Operation stop mode (used when serial transfers are not performed to enable a reduction in power
consumption)
• Asynchronous serial interface mode
{ Full-duplex transmission
{ 2-pin configuration
• TXD0 and TXD1: Transmit data output pins
• RXD0 and RXD1: Receive data input pins
{ 3 types of interrupt sources
• Receive error interrupt (INTSRE0 and INTSRE1)
• Receive end interrupt (INTSR0 and INTSR1)
• Transmit end interrupt (INTST0 and INTST1)
{ Character length: 7 bits/8 bits
{ Parity function: Odd, even, 0, none
{ Transmission stop bit: 1 bit/2 bits
{ On-chip baud rate generator
The following figure shows the configuration of the asynchronous serial interface (UART0 and UART1).
Internal bus
Asynchronous serial interface
mode register n (ASIMn)
RXDn
Receive
buffer (RXBn)
Transmit
buffer (TXBn)
Receive
shift register
Transmit
shift register
Reception control
parity check
Addition of transmission
control parity
TXDn
INTSTn
INTSRn
Parity
Framing
Overrun
INTSREn
BRGn
Remark n = 0, 1
44
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
12.3 I C Bus (I C) (µPD703201Y, 703204Y, 70F3201Y, 70F3204Y)
2
2
2
The I C bus has the following features.
{ Two modes
• Operation stop mode (used when serial transfers are not performed to enable a reduction in power
consumption)
• I C bus mode (supporting multi masters)
2
2
The following figure shows the configuration of the I C bus
Internal bus
IIC status register 0
(IICS)
MSTS
ALD
EXC
COI
TRC
ACKD
STD
SPD
IIC control register
(IICC)
Slave address
register (SVA)
SDA
IICE
Match
signal
Noise
eliminator
LREL
WREL
SPIE
WTIM
ACKE
STT
SPT
CLEAR
SET
SO latch
IIC shift register
(IIC)
D Q
CL1,
CL0
Data hold
time correction
circuit
N-ch open
drain output
ACK detector
Wake up controller
ACK detector
Start condition
detector
Stop condition
detector
SCL
Noise
eliminator
Interrupt request
signal generator
Serial clock counter
INTIIC
Serial clock wait
controller
Serial clock controller
N-ch open
drain output
fxx
Prescaler
TM4 output
CLD
DAD
SMC
DFC
CL1
CL0
IIC clock select
register (IICCL)
CLX
IIC function expansion
register (IICX)
Internal bus
Remark fXX: Main clock frequency
Preliminary Product Information U15436EJ1V0PM
45
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
13. A/D CONVERTER
The A/D converter has the following features.
{ 10-bit resolution
{ 12 channels (V850ES/SA2)
16 channels (V850ES/SA3)
{ Successive comparison approximation method
{ Power fail detection function available
{ Operation voltage: AVDD = AVREF0 = 2.2 to 2.7 V
{ Analog input voltage: AVSS to AVREF0
{ Conversion rate: 9.5 to 1.50 µs
The following figure shows the configuration of the A/D converter.
ADS0 to ADS3
ANI0
ANI1
ANI2
Analog input side
C array
Selector
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
INTAD
Controller
Successive approximation
register (SAR)
Reference side
C array
Comparator
A/D conversion result
register (ADCR)
ANI12Note
AVREF0
ANI13Note
AVDD
ANI14Note
AVSS
ANI15Note
Note V850ES/SA3 only
46
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
The following figure shows the configuration of the power fail detection function.
ADS0 to ADS3
PFCM
PFEN
ANI0
ANI1
ANI6
ANI7
ANI8
ANI9
Selector
ANI4
ANI5
A/D converter
Comparator
Selector
ANI2
ANI3
INTAD
ANI10
ANI11
ANI12Note
Power-fail comparison
threshold value register (PFT)
ANI13Note
ANI14Note
ANI15Note
Note V850ES/SA3 only
Preliminary Product Information U15436EJ1V0PM
47
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
14. D/A CONVERTER
The D/A converter has the following features.
{ 8-bit resolution × 2 channels (DAC0, DAC1)
{ R string method
{ Conversion time: 20 µs max. (AVREF1 = 2.2 to 2.7 V)
{ Analog output voltage: AVREF1 × m/256 (m = 0 to 255; Value set in the DACSn register)
{ Operation mode: Normal mode/real-time output mode
Remark n = 0, 1
The following figure shows the configuration of the D/A converter.
DACS0
DACS0 write
DAMD0
INTTM2
DACE0
AVREF1
R string resistor
ANO0
AVSS
DACS1
DACS1 write
DAMD1
INTTM3
DACE1
R string resistor
48
Preliminary Product Information U15436EJ1V0PM
ANO1
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
15. DMA FUNCTION
The DMA function has the following features.
{ Transfer unit: 8 bits/16 bits
16
{ Maximum transfer count: 65,536 (2 ) times
{ Transfer type: 2-cycle transfer
{ Transfer mode: Single transfer
{ Transfer request: Request via interrupt from on-chip peripheral I/O or external pins, request via software trigger
{ Transfer object: On-chip peripheral I/O, internal RAM, external memory
The relationship between the transfer type and transfer object is shown below (√: Transfer enabled, ×: Transfer
disabled).
Transfer Destination
On-Chip Peripheral I/O
Internal RAM
External Memory
On-chip peripheral I/O
√
√
√
Internal RAM
√
×
√
External memory
√
√
√
Transfer Source
The following figure shows the configuration of the DMA function.
V850ES core
CPU
IRIF
Internal
RAM
On-chip peripheral
I/O
BCU
On-chip peripheral I/O bus
Data control
block
Address control
block
DSAnH/
DSAnL
DDAnH/
DDAnL
INTDMAn
DMARQn
DMACTVn
Count control
block
Channel control
block
External bus
External
I/O
External
RAM
DBCn
DCHCn
DADCn
DMAC
External
ROM
Remark n = 0 to 3
Preliminary Product Information U15436EJ1V0PM
49
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
16. ROM CORRECTION FUNCTION
The ROM correction function is a function that replaces part of a program in the mask ROM with a program in the
internal RAM for execution.
First, the address where the program replacement should start (correction address) is set in the correction address
register (CORADn). When the CPU reads the instruction of the address set in CORADn, the instruction is replaced
with the DBTRAP instruction and the program jumps to 00000060H.
A value that is the address saved in the DBPC minus 2 (address to which ROM correction generated) is compared
with the address set in CORADn, and the program jumps to the correction program on the corresponding RAM. After
executing the correction program, a restore address is set in the DBPC, the DBRET instruction is executed, and then
execution is restored to the normal program.
Up to four correction addresses can be specified in CORADn.
Remark n = 3
The following figure shows the configuration of ROM correction.
Instruction address bus
Correction address
register (CORADn)
Comparator
Correction control
register (CORENn bit)
DBTRAP instruction
generation block
ROM
(1 MB space)
Instruction replacement block
Remark n = 0 to 3
50
Preliminary Product Information U15436EJ1V0PM
Instruction data bus
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
17. RESET FUNCTION
When a low-level signal is input to the RESET pin or the watchdog timer overflows (WDTRES), a system reset is
applied and the various on-chip hardware devices are reset to their initial states.
When the RESET pin goes from low level to high level, or when the WDTRES signal is automatically canceled, the
reset state is released.
When reset is released via RESET pin input, the CPU starts execution of the program after securing the oscillation
19
stabilization time (OSTS register reset value: 2 /fXX).
When reset is released by the WDTRES signal, the main clock oscillator does not stop and oscillation stabilization
time is not inserted.
The following figure shows the configuration of the reset function.
RESET
Count clock
Reset signal
Reset controller
Watchdog timer
Overflow
Interrupt function
Stop
Preliminary Product Information U15436EJ1V0PM
51
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
18. FLASH MEMORY (µPD70F3201, 70F3201Y, 70F3204, 70F3204Y)
The µPD70F3201 and 70F3201Y, and 70F3204 and 70F3204Y are the flash memory versions of the V850ES/SA2
and V850ES/SA3, respectively, and incorporate 256 KB of flash memory.
Writing to flash memory can be performed while the device is mounted on the target system (on board). Writing is
performed using a dedicated flash programmer connected to the target system or to a writing adapter.
The flash memory has the following features.
{ Flash memory: 256 KB (4 KB × 4 blocks, 60 KB × 4 blocks)
{ Erasure/writing possible using single power supply (VDD = 2.2 to 2.7 V)
{ Erasure unit
• Overall area batch erasure (256 KB)
• Block units erasure (4 KB/block, 60 KB/block)
{ Erasure/writing method
• Serial mode (using CSI0 or UART0)
• Self-programming mode
52
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
An overview of flash memory programming is shown below.
{ Pins used in programming
• Power supply pins (VDD, EVDD, AVDD, VSS, EVSS, AVSS, VDDBU, VSSBU)
• Mode pins (FLMD0, FLMD1)
• Clock supply pins (X1, X2)
• Serial communication pins (SCK0, SO0, SI0 or RXD0, TXD0)
• RESET pin
{ Programming timing
The following figure shows the programming timing (overview) when using UART.
VDD
VDD
0V
VDD
RESET (input)
0V
VDD
FLMD1 (input)
0V
VDD
FLMD0 (input)
0V
(UART mode only)
VDD
RXD0 (input)
0V
VDD
TXD0 (output)
0V
Oscillation
stabilization
Power
ON
Reset
release
Communication
mode selection
Flash control command communication
(erasure, writing, etc.)
Preliminary Product Information U15436EJ1V0PM
53
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
19. INSTRUCTION SET LIST
19.1 Conventions
(1) Register symbols used to describe operands
Register Symbol
Explanation
reg1
General-purpose register:
Used as source register.
reg2
General-purpose register:
Used mainly as destination register. Also used as source register in some
instructions.
reg3
General-purpose register:
Used mainly to store the remainder of division results and the higher 32 bits of
multiplication results.
bit#3
3-bit data for specifying the bit number
immX
X bit immediate data
dispX
X bit displacement data
regID
System register number
vector
5-bit data that specifies the trap vector (00H to 1FH)
cccc
4-bit data that shows the condition code
sp
Stack pointer (r3)
ep
Element pointer (r30)
listX
X item register list
(2) Register symbols used to describe opcodes
Register Symbol
Explanation
R
1-bit data of the code that specifies reg1 or regID
r
1-bit data of the code that specifies reg2
w
1-bit data of the code that specifies reg3
d
1-bit displacement data
I
1-bit immediate data (indicates the higher bits of immediate data)
i
1-bit immediate data
cccc
4-bit data that shows the condition codes
CCCC
4-bit data that shows the condition codes of the Bcond instruction
bbb
3-bit data for specifying the bit number
L
1-bit data that specifies a program register in the register list
S
1-bit data that specifies a system register in the register list
54
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(3) Register symbols used in operation
Register Symbol
Explanation
←
Input for
GR [ ]
General-purpose register
SR [ ]
System register
zero-extend (n)
Expand n with zeros until word length.
sign-extend (n)
Expand n with signs until word length.
load-memory (a, b)
Read size b data from address a.
store-memory (a, b, c)
Write data b into address a in size c.
load-memory-bit (a, b)
Read bit b of address a.
store-memory-bit (a, b, c)
Write c to bit b of address a.
saturated (n)
Execute saturated processing of n (n is a 2’s complement).
If, as a result of calculations,
n ≥ 7FFFFFFFH, let it be 7FFFFFFFH.
n ≤ 80000000H, let it be 80000000H.
result
Reflects the results in a flag.
Byte
Byte (8 bits)
Half-word
Halfword (16 bits)
Word
Word (32 bits)
+
Addition
–
Subtraction
ll
Bit concatenation
×
Multiplication
÷
Division
%
Remainder from division results
AND
Logical product
OR
Logical sum
XOR
Exclusive OR
NOT
Logical negation
logically shift left by
Logical shift left
logically shift right by
Logical shift right
arithmetically shift right by
Arithmetic shift right
(4) Register symbols used in an execution clock
Register Symbol
Explanation
i
If executing another instruction immediately after executing the first instruction (issue).
r
If repeating execution of the same instruction immediately after executing the first instruction (repeat).
l
If using the results of instruction execution in the instruction immediately after the execution (latency).
Preliminary Product Information U15436EJ1V0PM
55
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(5) Register symbols used in flag operations
Identifier
Explanation
(Blank)
No change
0
Clear to 0
X
Set or cleared in accordance with the results.
R
Previously saved values are restored.
(6) Condition codes
Condition Name
(cond)
Condition Expression
Condition Code
(cccc)
Explanation
V
0 0 0 0
OV = 1
Overflow
NV
1 0 0 0
OV = 0
No overflow
C/L
0 0 0 1
CY = 1
Carry
Lower (less than)
NC/NL
1 0 0 1
CY = 0
No carry
Not lower (greater than or equal)
Z/E
0 0 1 0
Z=1
Zero
Equal
NZ/NE
1 0 1 0
Z=0
Not zero
Not equal
NH
0 0 1 1
(CY or Z) = 1
Not higher (less than or equal)
H
1 0 1 1
(CY or Z) = 0
Higher (greater than)
N
0 1 0 0
S=1
Negative
P
1 1 0 0
S=0
Positive
T
0 1 0 1
SA
1 1 0 1
SAT = 1
Saturated
LT
0 1 1 0
(S xor OV) = 1
Less than signed
GE
1 1 1 0
(S xor OV) = 0
Greater than or equal signed
—
Always (unconditional)
LE
0 1 1 1
((S xor OV) or Z) = 1
Less than or equal signed
GT
1 1 1 1
((S xor OV) or Z) = 0
Greater than signed
56
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
19.2 Instruction Set (In Alphabetical Order)
(1/6)
Mnemonic
Operand
Opcode
Operation
Flags
Execution
Clock
ADD
ADDI
i
r
l
CY OV S
Z SAT
reg1,reg2
rrrrr001110RRRRR
GR[reg2]←GR[reg2]+GR[reg1]
1
1
1
×
×
×
×
imm5,reg2
rrrrr010010iiiii
GR[reg2]←GR[reg2]+sign-extend(imm5)
1
1
1
×
×
×
×
imm16,reg1,reg2
rrrrr110000RRRRR
GR[reg2]←GR[reg1]+sign-extend(imm16)
1
1
1
×
×
×
×
i i i i i i i i i i i i i i i i
AND
reg1,reg2
rrrrr001010RRRRR
GR[reg2]←GR[reg2]AND GR[reg1]
1
1
1
0
×
×
ANDI
imm16,reg1,reg2
rrrrr110110RRRRR
GR[reg2]←GR[reg1]AND zero-extend(imm16)
1
1
1
0
0
×
2
2
2
i i i i i i i i i i i i i i i i
Bcond
disp9
ddddd1011dddc ccc
if conditions are satisfied
Note 1 then PC←PC+sign-extend(disp9)
When conditions
are satisfied
When conditions
Note 2 Note 2 Note 2
1
1
1
1
1
1
×
0
×
×
1
1
1
×
0
×
×
4
4
4
3
3
3
are not satisfied
BSH
reg2,reg3
rrrrr11111100000
GR[reg3]←GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll
wwwww01101000010 GR[reg2] (7 : 0) ll GR[reg2] (15 : 8)
BSW
reg2,reg3
rrrrr11111100000
GR[reg3]←GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR
wwwww01101000000 [reg2] (23 : 16) ll GR[reg2] (31 : 24)
CALLT
imm6
0000001000iiiiii
CTPC←PC+2(return PC)
CTPSW←PSW
adr←CTBP+zero-extend(imm6 logically shift left by 1)
PC←CTBP+zero-extend(Load-memory(adr,Half-word))
CLR1
bit#3, disp16[reg1]
10bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd
Z flag←Not(Load-memory-bit(adr,bit#3))
×
Note 3 Note 3 Note 3
Store-memory-bit(adr,bit#3,0)
reg2,[reg1]
rrrrr111111RRRRR
adr←GR[reg1]
0000000011100100
Z flag←Not(Load-memory-bit(adr,reg2))
3
3
×
3
Note 3 Note 3 Note 3
Store-memory-bit(adr,reg2,0)
CMOV
cccc,imm5,reg2,reg3
rrrrr111111iiiii
if conditions are satisfied
wwwww011000cccc0
then GR[reg3]←sign-extended(imm5)
1
1
1
1
1
1
else GR[reg3]←GR[reg2]
cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R R R R
if conditions are satisfied
wwwww011001cccc0 then GR[reg3]←GR[reg1]
else GR[reg3]←GR[reg2]
CMP
reg1,reg2
imm5,reg2
CTRET
DBRET
rrrrr001111RRRRR
result←GR[reg2]–GR[reg1]
1
1
1
×
×
×
×
rrrrr010011iiiii
result←GR[reg2]–sign-extend(imm5)
1
1
1
×
×
×
×
0000011111100000
PC←CTPC
3
3
3
R
R
R
R
R
0000000101000100
PSW←CTPSW
0000011111100000
PC←DBPC
3
3
3
R
R
R
R
R
0000000101000110
PSW←DBPSW
Preliminary Product Information U15436EJ1V0PM
57
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2/6)
Mnemonic
Operand
Opcode
Operation
Execution
Flags
Clock
DBTRAP
1111100001000000
DBPC←PC+2 (restored PC)
i
r
l
3
3
3
1
1
1
CY OV S
Z SAT
DBPSW←PSW
PSW.NP←1
PSW.EP←1
PSW.ID←1
PC←00000060H
DI
0000011111100000
PSW.ID←1
0000000101100000
DISPOSE
imm5,list12
0000011001iiiiiL
sp←sp+zero-extend(imm5 logically shift left by 2)
n+1 n+1 n+1
LLLLLLLLLLL00000
GR[reg in list12]←Load-memory(sp,Word)
Note 4 Note 4 Note 4
sp←sp+4
repeat 2 steps above until all regs in list12 is loaded
imm5,list12,[reg1]
0000011001iiiiiL
sp←sp+zero-extend(imm5 logically shift left by 2)
LLLLLLLLLLLRRRRR R[reg in list12]←Load-memory(sp,Word)
n+3 n+3 n+3
Note 4 Note 4 Note 4
Note 5 sp←sp+4
repeat 2 steps above until all regs in list12 is loaded
PC←GR[reg1]
DIV
reg1,reg2,reg3
rrrrr111111RRRRR
GR[reg2]←GR[reg2}÷GR[reg1]
35 35 35
wwwww01011000000 GR[reg3]←GR[reg2]%GR[reg1]
DIVH
reg1,reg2
reg1,reg2,reg3
rrrrr000010RRRRR
GR[reg2]←GR[reg2]÷GR[reg1]Note 6
35 35 35
×
×
×
rrrrr111111RRRRR
Note 6
35 35 35
×
×
×
34 34 34
×
×
×
34 34 34
×
×
×
0
×
×
GR[reg2]←GR[reg2]÷GR[reg1]
wwwww01010000000 GR[reg3]←GR[reg2]%GR[reg1]
DIVHU
reg1,reg2,reg3
rrrrr111111RRRRR
GR[reg2]←GR[reg2]÷GR[reg1]Note 6
wwwww01010000010 GR[reg3]←GR[reg2]%GR[reg1]
DIVU
reg1,reg2,reg3
rrrrr111111RRRRR
GR[reg2]←GR[reg2]÷GR[reg1]
wwwww01011000010 GR[reg3]←GR[reg2]%GR[reg1]
EI
1000011111100000
PSW.ID←0
1
1
1
Stop
1
1
1
GR[reg3]←GR[reg2](15 : 0) ll GR[reg2] (31 : 16)
1
1
1
rrrrr11110dddddd
GR[reg2]←PC+4
2
2
2
ddddddddddddddd0
PC←PC+sign-extend(disp22)
0000000101100000
HALT
0000011111100000
0000000100100000
HSW
reg2,reg3
rrrrr11111100000
wwwww01101000100
JARL
disp22,reg2
Note 7
JMP
[reg1]
00000000011RRRRR
PC←GR[reg1]
3
3
3
JR
disp22
0000011110dddddd
PC←PC+sign-extend(disp22)
2
2
2
rrrrr111000RRRRR
adr←GR[reg1]+sign-extend(disp16)
1
1
Note
dddddddddddddddd
GR[reg2]←sign-extend(Load-memory(adr,Byte))
rrrrr11110bRRRRR
adr←GR[reg1]+sign-extend(disp16)
dddddddddddddd1
GR[reg2]←zero-extend(Load-memory(adr,Byte))
ddddddddddddddd0
Note 7
LD.B
LD.BU
disp16[reg1],reg2
disp16[reg1],reg2
Notes 8, 10
58
Preliminary Product Information U15436EJ1V0PM
11
1
1
Note
11
×
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(3/6)
Mnemonic
Operand
Opcode
Operation
Execution
Flags
Clock
LD.H
disp16[reg1],reg2
rrrrr111001RRRRR
adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd0
GR[reg2]←sign-extend(Load-memory(adr,Half-
i
r
l
1
1
Note
CY OV S
Z SAT
11
Note 8 word))
LDSR
reg2,regID
rrrrr111111RRRRR
SR[regID]←GR[reg2]
0000000000100000
Other than regID = PSW
1
1
1
regID = PSW
1
1
1
1
1
Note
×
×
×
×
0
×
×
×
Note 12
LD.HU
disp16[reg1],reg2
rrrrr111111RRRRR
adr←GR[reg1]+sign-exend(disp16)
ddddddddddddddd1
GR[reg2]←zero-extend(Load-memory(adr,half-word)
11
Note 8
LD.W
disp16[reg1],reg2
rrrrr111001RRRRR
adr←GR[reg1]+sign-exend(disp16)
ddddddddddddddd1
GR[reg2]←Load-memory(adr,Word)
1
1
Note
11
Note 8
MOV
reg1,reg2
rrrrr000000RRRRR
GR[reg2]←GR[reg1]
1
1
1
imm5,reg2
rrrrr010000iiiii
GR[reg2]←sign-extend(imm5)
1
1
1
imm32,reg1
00000110001RRRRR GR[reg1]←imm32
2
2
2
1
1
1
GR[reg2]←GR[reg1]+(imm16 ll 0 )
1
1
1
GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
1
4
5
GR[reg3] ll GR[reg2]←GR[reg2]xsign-extend(imm9)
1
4
5
GR[reg2]←GR[reg2]Note 6xGR[reg1]Note 6
i i i i i i i i i i i i i i i i
i i i i i i i i i i i i i i i i
MOVEA
imm16,reg1,reg2
rrrrr110001RRRRR
GR[reg2]←GR[reg1]+sign-extend(imm16)
i i i i i i i i i i i i i i i i
MOVHI
imm16,reg1,reg2
rrrrr110010RRRRR
16
i i i i i i i i i i i i i i i i
MUL
reg1,reg2,reg3
rrrrr111111RRRRR
wwwww01000100000
imm9,reg2,reg3
rrrrr111111iiiii
wwwww01001IIII00
Note 13
MULH
reg1,reg2
imm5,reg2
MULHI
imm16,reg1,reg2
rrrrr000111RRRRR
1
1
2
GR[reg2]←GR[reg2]
Note 6
1
1
2
GR[reg2]←GR[reg1]
Note 6
1
1
2
GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
1
4
5
GR[reg3] ll GR[reg2]←GR[reg2]xzero-extend(imm9)
1
4
5
0000000000000000 Pass at least one clock cycle doing nothing.
1
1
1
1
1
1
3
3
3
rrrrr010111iiiii
rrrrr110111RRRRR
xsign-extend(imm5)
ximm16
i i i i i i i i i i i i i i i i
MULU
reg1,reg2,reg3
rrrrr111111RRRRR
wwwww01000100010
imm9,reg2,reg3
rrrrr111111iiiii
wwwww01001IIII10
Note 13
NOP
NOT
reg1,reg2
rrrrr000001RRRRR
NOT1
bit#3,disp16[reg1]
01bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd
GR[reg2]←NOT(GR[reg1])
Z flag←Not(Load-memory-bit(adr,bit#3))
×
Note 3 Note 3 Note 3
Store-memory-bit(adr,bit#3,Z flag)
reg2,[reg1]
rrrrr111111RRRRR
adr←GR[reg1]
0000000011100010
Z flag←Not(Load-memory-bit(adr,reg2))
3
3
3
×
Note 3 Note 3 Note 3
Store-memory-bit(adr,reg2,Z flag)
Preliminary Product Information U15436EJ1V0PM
59
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(4/6)
Mnemonic
Operand
Opcode
Operation
Execution
Flags
Clock
i
r
l
CY OV S
Z SAT
OR
reg1,reg2
rrrrr001000RRRRR
GR[reg2]←GR[reg2]OR GR[reg1]
1
1
1
0
×
×
ORI
imm16,reg1,reg2
rrrrr110100RRRRR
GR[reg2]←GR[reg1]OR zero-extend(imm16)
1
1
1
0
×
×
i i i i i i i i i i i i i i i i
PREPARE list12,imm5
0000011110iiiiiL
Store-memory(sp–4,GR[reg in list12],Word)
LLLLLLLLLLL00001 sp←sp–4
n+1 n+1 n+1
Note 4 Note 4 Note 4
repeat 1 step above until all regs in list12 is stored
sp←sp-zero-extend(imm5)
list12,imm5,
Note 14
sp/imm
0000011110iiiiiL
Store-memory(sp–4,GR[reg in list12],Word)
LLLLLLLLLLLff011
sp←sp–4
imm16/imm32
repeat 1 step above until all regs in list12 is stored
Note 4 Note 4 Note 4
Note16 Note16 Note16
Note 15 sp←sp-zero-extend(imm5)
ep←sp/imm
RETI
0000011111100000 if PSW.EP=1
0000000101000000 then PC
n+2 n+2 n+2
3
3
3
R
R
R
R
1
1
1
×
0
×
×
1
1
1
×
0
×
×
1
1
1
×
×
×
×
R
←EIPC
PSW ←EIPSW
else if PSW.NP=1
then
PC
←FEPC
PSW ←FEPSW
else
PC
←EIPC
PSW ←EIPSW
SAR
reg1,reg2
rrrrr111111RRRRR
GR[reg2]←GR[reg2]arithmetically shift right
0000000010100000
imm5,reg2
rrrrr010101iiiii
by GR[reg1]
GR[reg2]←GR[reg2]arithmetically shift right
by zero-extend (imm5)
SASF
cccc,reg2
rrrrr1111110cccc
if conditions are satisfied
0000001000000000
then GR[reg2]←(GR[reg2]Logically shift left by 1)
OR 00000001H
else GR[reg2]←(GR[reg2]Logically shift left by 1)
OR 00000000H
SATADD
reg1,reg2
SATSUB
SATSUBI
imm16,reg1,reg2
×
rrrrr000110RRRRR
GR[reg2]←saturated(GR[reg2]+GR[reg1])
1
1
1
imm5,reg2
rrrrr010001iiiii
GR[reg2]←saturated(GR[reg2]+sign-extend(imm5)
1
1
1
×
×
×
×
×
reg1,reg2
rrrrr000101RRRRR
GR[reg2]←saturated(GR[reg2]–GR[reg1])
1
1
1
×
×
×
×
×
rrrrr110011RRRRR
GR[reg2]←saturated(GR[reg1]–sign-extend(imm16)
1
1
1
×
×
×
×
×
rrrrr000100RRRRR
GR[reg2]←saturated(GR[reg1]–GR[reg2])
1
1
1
×
×
×
×
×
rrrrr1111110cccc
If conditions are satisfied
1
1
1
0000000000000000
then GR[reg2]←00000001H
3
3
3
i i i i i i i i i i i i i i i i
SATSUBR reg1,reg2
SETF
cccc,reg2
else GR[reg2]←00000000H
SET1
bit#3,disp16[reg1]
00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd
Z flag←Not (Load-memory-bit(adr,bit#3))
×
Note 3 Note 3 Note 3
Store-memory-bit(adr,bit#3,1)
reg2,[reg1]
rrrrr111111RRRRR
adr←GR[reg1]
0000000011100000
Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,1)
60
Preliminary Product Information U15436EJ1V0PM
3
3
3
Note 3 Note 3 Note 3
×
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(5/6)
Mnemonic
Operand
Opcode
Operation
Execution
Flags
Clock
SHL
reg1,reg2
rrrrr111111RRRRR
i
r
l
CY OV S
Z SAT
GR[reg2]←GR[reg2] logically shift left by GR[reg1]
1
1
1
×
0
×
×
GR[reg2]←GR[reg2] logically shift left
1
1
1
×
0
×
×
GR[reg2]←GR[reg2] logically shift right by GR[reg1]
1
1
1
×
0
×
×
GR[reg2]←GR[reg2] logically shift right
1
1
1
×
0
×
×
1
1
Note 9
1
1
Note 9
1
1
Note 9
1
1
Note 9
1
1
Note 9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GR[reg2]←SR[regID]
1
1
1
0000000011000000
imm5,reg2
rrrrr010110iiiii
by zero-extend(imm5)
SHR
reg1,reg2
rrrrr111111RRRRR
0000000010000000
imm5,reg2
rrrrr010100iiiii
by zero-extend(imm5)
SLD.B
disp7[ep],reg2
rrrrr0110ddddddd
adr←ep+zero-extend(disp7)
GR[reg2]←sign-extend(Load-memory(adr,Byte))
SLD.BU
disp4[ep],reg2
rrrrr0000110dddd
adr←ep+zero-extend(disp4)
Note 17 GR[reg2]←zero-extend(Load-memory(adr,Byte))
SLD.H
disp8[ep],reg2
rrrrr1000ddddddd
adr←ep+zero-extend(disp8)
Note 18 GR[reg2]←sign-extend(Load-memory(adr,Halfword))
SLD.HU
disp5[ep],reg2
r r r r r 0 0 0 0 1 1 1 d d d d adr←ep+zero-extend(disp5)
Notes 17, 19 GR[reg2]←zero-extend(Load-memory(adr,Halfword))
SLD.W
disp8[ep],reg2
rrrrr1010dddddd0
adr←ep+zero-extend(disp8)
Note 20 GR[reg2]←Load-memory(adr,Word)
SST.B
reg2,disp7[ep]
rrrrr0111ddddddd
adr←ep+zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
SST.H
reg2,disp8[ep]
rrrrr1001ddddddd
adr←ep+zero-extend(disp8)
Note 18 Store-memory(adr,GR[reg2],Half-word)
SST.W
reg2,disp8[ep]
rrrrr1010dddddd1
adr←ep+zero-extend(disp8)
Note 20 Store-memory(adr,GR[reg2],Word)
ST.B
ST.H
reg2,disp16[reg1]
reg2,disp16[reg1]
rrrrr111010RRRRR
adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd
Store-memory(adr,GR[reg2],Byte)
rrrrr111011RRRRR
adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd0
Store-memory (adr,GR[reg2], Half-word)
Note 8
ST.W
reg2,disp16[reg1]
rrrrr111011RRRRR
adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd1
Store-memory (adr,GR[reg2], Word)
Note 8
STSR
regID,reg2
rrrrr111111RRRRR
0000000001000000
SUB
reg1,reg2
rrrrr001101RRRRR
GR[reg2]←GR[reg2]–GR[reg1]
1
1
1
×
×
×
×
SUBR
reg1,reg2
rrrrr001100RRRRR
GR[reg2]←GR[reg1]–GR[reg2]
1
1
1
×
×
×
×
SWITCH
reg1
00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1)
5
5
5
PC←(PC+2) + (sign-extend
(Load-memory (adr,Half-word)))
logically shift left by 1
Preliminary Product Information U15436EJ1V0PM
61
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(6/6)
Mnemonic
Operand
Opcode
Operation
Execution
Flags
Clock
SXB
reg1
00000000101RRRRR
GR[reg1]←sign-extend
i
r
l
1
1
1
1
1
1
3
3
3
1
1
1
3
3
3
CY OV S
Z SAT
(GR[reg1] (7 : 0))
SXH
reg1
00000000111RRRRR
GR[reg1]←sign-extend
(GR[reg1] (15 : 0))
TRAP
vector
00000111111iiiii
EIPC
←PC+4 (Restored PC)
0000000100000000
EIPSW
←PSW
ECR.EICC ←Interrupt Code
PSW.EP
←1
PSW.ID
←1
PC
←00000040H (when vector is 00H to
0FH)
00000050H (when vector is 10H to
1FH)
TST
reg1,reg2
rrrrr001011RRRRR
TST1
bit#3,disp16[reg1]
11bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
reg2, [reg1]
result←GR[reg2] AND GR[reg1]
dddddddddddddddd
Z flag←Not (Load-memory-bit (adr,bit#3))
rrrrr111111RRRRR
adr←GR[reg1]
0000000011100110
Z flag←Not (Load-memory-bit (adr,reg2))
0
×
×
×
Note 3 Note 3 Note 3
3
3
×
3
Note 3 Note 3 Note 3
XOR
reg1,reg2
rrrrr001001RRRRR
GR[reg2]←GR[reg2] XOR GR[reg1]
1
1
1
0
×
×
XORI
imm16,reg1,reg2
rrrrr110101RRRRR
GR[reg2]←GR[reg1] XOR zero-extend (imm16)
1
1
1
0
×
×
i i i i i i i i i i i i i i i i
ZXB
reg1
00000000100RRRRR
GR[reg1]←zero-extend (GR[reg1] (7 : 0))
1
1
1
ZXH
reg1
00000000110RRRRR
GR[reg1]←zero-extend (GR[reg1] (15 : 0))
1
1
1
Notes 1.
dddddddd: Higher 8 bits of disp9.
2.
3 clocks if the final instruction includes the PSW write access.
3.
If there is no wait state (3 + the number of read access wait states).
4.
n is the total number of list X load registers. (According to the number of wait states. Also, if there are
no wait states, n is the number of list X registers.)
5.
RRRRR: Other than 00000.
6.
The lower halfword data only is valid.
7.
ddddddddddddddddddddd: The higher 21 bits of disp22.
8.
ddddddddddddddd: The higher 15 bits of disp16.
9.
According to the number of wait states (1 if there are no wait states).
10. b: Bit 0 of disp16.
11. According to the number of wait states (2 if there are no wait states).
12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic
description and in the opcode differs from other instructions.
rrrrr
= regID specification
RRRRR = reg2 specification
13. i i i i i : Lower 5 bits of imm9.
I I I I : Lower 4 bits of imm9.
14. sp/imm: Specified by bits 19 and 20 of the sub-opcode.
62
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Notes 15. ff = 00: Load sp in ep.
01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
16. If imm = imm32, n + 3 clocks.
17. r r r r r : Other than 00000.
18. ddddddd: Higher 7 bits of disp8.
19. dddd: Higher 4 bits of disp5.
20. dddddd: Higher 6 bits of disp8.
Preliminary Product Information U15436EJ1V0PM
63
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
20. ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Supply voltage
Input voltage
Symbol
Ratings
Unit
VDD
–0.5 to +3.6
V
AVDD
–0.5 to +3.6
V
EVDD
–0.5 to +3.6
V
VDDBU
–0.5 to +3.6
V
AVSS
–0.5 to +0.5
V
EVSS
–0.5 to +0.5
V
VSSBU
–0.5 to +0.5
V
VI
Clock input voltage
VK
VKT
Analog input voltage
VIAN
Conditions
Other than X1, XT1, and port 7
XT1, VDDBU = 2.2 to 2.7 V
Port 7
AVREF
AVREF0, AVREF1
Output current, low
IOL
Per pin
IOH
Note
X1, VDD = 2.2 to 2.7 V
Analog reference voltage
Output current, high
–0.5 to EVDD + 0.3Note
–0.5 to VDD + 0.3
Note
–0.5 to VDDBU + 0.3
V
V
V
Note
V
Note
V
–0.5 to AVDD + 0.3
–0.5 to AVDD + 0.3
4
mA
Total for all pins
100
mA
Per pin
–4
mA
–100
mA
–0.5 to VDD + 0.3 V
V
–40 to +85
°C
T.B.D.
°C
–65 to +150
°C
T.B.D.
°C
Total for all pins
Output voltage
VO
VDD = 2.5 V ±0.2 V
Operating ambient
temperature
TA
Normal operation mode
Storage temperature
Tstg
Flash programming mode
µPD703201, 703201Y, 703204, 703204Y
µPD70F3201, 70F3201Y, 70F3204,
70F3204Y
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions
1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC,
and GND. Open-drain pins or open-collector pins, however, can be directly connected to
each other. Direct connection of the output pins between an IC product and an external
circuit is possible, if the output pins can be set to the high-impedance state and the output
timing of the external circuit is designed to avoid output conflict.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
64
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Capacitance (TA = 25°C, VDD = AVDD = EVDD = VDDBU = VSS = AVSS = EVSS = VSSBU = 0 V)
Parameter
Symbol
Input capacitance
CI
I/O capacitance
CIO
Output capacitance
CO
Conditions
MIN.
TYP.
fX = 1 MHz
Unmeasured pins returned to 0 V
MAX.
Unit
10
pF
10
pF
10
pF
MAX.
Unit
Operating Conditions (VDD = AVDD = EVDD = VDDBU)
Parameter
Internal system clock frequency
Symbol
fCLK
Conditions
MIN.
TYP.
@ VDD = 2.3 to 2.7 V, operation with main
clock
0.0625
17
MHz
@ VDD = 2.2 to 2.7 V, operation with main
clock
0.0625
13.5
MHz
Preliminary Product Information U15436EJ1V0PM
65
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Recommended Oscillator
(1) Main clock oscillator (TA = –40 to +85°C)
(a) Connection of ceramic resonator or crystal resonator
X1
Parameter
Oscillation frequency
Symbol
fX (fXX)
Oscillation stabilization time
X2
Conditions
MIN.
VDD = 2.3 to 2.7 V
2
VDD = 2.2 to 2.7 V
2
TYP.
MAX.
Unit
17
MHz
13.5
MHz
19
Upon reset release
2 /fX
s
Upon STOP mode release
Note
s
Note The TYP. value differs depending on the setting of the oscillation stabilization time select register (OSTS).
Caution Ensure that the duty of the oscillation waveform is between 45% and 55%.
Remarks 1. Connect the oscillator as close as possible to the X1 and X2 pins.
2. Do not route the wiring near broken lines.
3. For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
(b) External clock input
X1
X2
Open
High-speed CMOS inverter
External clock
Cautions
1. Connect the high-speed CMOS inverter as close as possible to the X1 pin.
2. Sufficiently evaluate the matching between the V850ES/SA2, V850ES/SA3 and the highspeed CMOS inverter.
66
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2) Subclock oscillator (TA = –40 to +85°C)
(a) Connection of crystal resonator
XT1
Parameter
Oscillation frequency
Symbol
XT2
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
fXT
Oscillation stabilization time
10
s
Caution Ensure that the duty of the oscillation waveform is between 45% and 55%.
Remarks 1. Connect the oscillator as close as possible to the XT1 and XT2 pins.
2. Do not route the wiring near broken lines.
3. For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
Preliminary Product Information U15436EJ1V0PM
67
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
DC Characteristics
(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V) (1/2)
Parameter
Input voltage, high
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VIH1
Note 1
0.7EVDD
EVDD
V
VIH2
Note 2
T.B.D.
EVDD
V
VIH3
Note 3
0.7AVDD
AVDD
V
VIH4
X1
0.8VDD
VDD
V
VIH5
XT1, XT2
0.8VDDBU
VDDBU
V
VIL1
Note 1
EVSS
0.3EVDD
V
VIL2
Note 2
EVSS
T.B.D.
V
VIL3
Note 3
AVSS
0.3AVDD
V
VIL4
X1
VSS
0.2VDD
V
VIL5
XT1, XT2
VSSBU
0.2VDDBU
V
VOH1
Note 4
IOH = –1 mA
0.8EVDD
V
VOH2
Note 5
IOH = –3 mA
0.8EVDD
V
VOL1
Note 4 (Except pins
P40 and P42)
IOL = 1.6 mA
0.4
V
VOL2
P40, P42
IOL = 3 mA
0.4
V
VOL3
Note 5
IOL = 1.6 mA
0.4
V
Input leakage current, high
ILIH
VIN = VDD = EVDD = VDDBU
5
µA
Input leakage current, low
ILIL
VIN = 0 V
–5
µA
Output leakage current, high
ILOH
VO = VDD = EVDD = VDDBU
5
µA
Output leakage current, low
ILOL
VO = 0 V
–5
µA
Input voltage, low
Output voltage, high
Output voltage, low
Notes 1. P21, P31, P90, P91, P94 to P97, P99, P911, P914, PCD1 to PCD3, PCM0 to PCM5, PCS0 to PCS7,
PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 (and their alternate-function pins)
2. RESET, P00 to P05, P20, P22, P30, P32, P40 to P46, P92, P93, P98, P910, P912, P913, P915 (and
their alternate-function pins)
3. P70 to P715, P80, P81 (and their alternate-function pins)
4. P00 to P05, P20 to P22, P30 to P32, P40 to P46, PCD1 to PCD3, PCM4 to PCM5, PCS4 to PCS7,
PCT2, PCT3, PCT5, PCT7 (and their alternate-function pins)
5. P90 to P915, PCM0 to PCM3, PCS0 to PCS3, PCT0, PCT1, PCT4, PCT6, PDH0 to PDH7, PDL0 to
PDL15 (and their alternate-function pins)
68
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V) (2/2)
Parameter
Supply current
Symbol
IDD1
IDD2
IDD3
IDD4
IDD5
Pull-up resistance
RL
Conditions
MIN.
TYP.
MAX.
Unit
Normal
operation
All peripheral
functions
operating
VDD = 2.3 to 2.7 V,
fXX = fCLK = 17 MHz
T.B.D.
T.B.D.
mA
fXX = fCLK = 13.5 MHz
T.B.D.
T.B.D.
mA
HALT mode
All peripheral
functions
operating
VDD = 2.3 to 2.7 V,
fXX = fCLK = 17 MHz
T.B.D.
T.B.D.
mA
fXX = fCLK = 13.5 MHz
T.B.D.
T.B.D.
mA
IDLE mode
RTC operating
VDD = 2.3 to 2.7 V,
fXX = fCLK = 17 MHz
T.B.D.
T.B.D.
mA
fXX = fCLK = 13.5 MHz
T.B.D.
T.B.D.
mA
Subclock oscillator,
RTC operating
T.B.D.
T.B.D.
µA
Subclock oscillator
stopped (XT1 = VSS)
T.B.D.
T.B.D.
µA
fXT = 32.768 kHz,
RTC operating
T.B.D.
T.B.D.
µA
Subclock oscillation
stopped (XT1 = VSS)
T.B.D.
T.B.D.
µA
30
100
kΩ
STOP mode
Backup mode
VIN = 0 V
Preliminary Product Information U15436EJ1V0PM
10
69
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Data Retention Characteristics
(1) In STOP mode (TA = –40 to +85°C, VSS = AVSS = EVSS = VSSBU = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
1.8
MAX.
Unit
2.7
V
T.B.D.
µA
Data retention voltage
VDDDR1
STOP mode
Data retention current
IDDDR1
VDD = AVDD = EVDD = VDDBU =
VDDDR1
Supply voltage rise time
tRVD1
200
µs
Supply voltage fall time
tFVD1
200
µs
Supply voltage hold time
(from STOP mode setting)
tHVD1
0
ms
STOP release signal input time
tDREL1
0
ms
Data retention high-level input voltage
VIHDR1
All input ports
VIHn
VDDDR1
V
Data retention low-level input voltage
VILDR1
All input ports
0
VILn
V
T.B.D.
Remark n = 1 to 5
Setting STOP mode
tFVD1
tRVD1
VDD
tHVD1
RESET
(input)
VIHDR1
NMI, INTP0 to INTP6
(input)
VIHDR1
NMI, INTP0 to INTP6 (input)
(when STOP mode is released
at rising edge)
Caution
VDDDR1
VILDR1
Shifting to STOP mode and restoring from STOP mode must be performed at VDD = 2.3 V min.
(fCLK = 17 MHz) and VDD = 2.2 V min. (fCLK = 13.5 MHz), respectively.
70
tDREL1
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2) In backup mode (TA = –40 to +85°°C, VSS = AVSS = EVSS = VSSBU = VDD = AVDD = EVDD = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
1.6
MAX.
Unit
2.7
V
T.B.D.
µA
Data retention voltage
VDDDR2
Backup mode
Data retention current
IDDDR2
VDDBU = VDDDR2
Backup supply voltage rise time
tRVD2
T.B.D.
µs
Backup supply voltage fall time
tFVD2
T.B.D.
µs
Mode setting time from RESET↓ to
VDD↓
tHVD2
T.B.D.
ms
Mode release signal input time from
VDD↑ to RESET↑
tDREL2
T.B.D.
ms
T.B.D.
Caution Shifting to backup mode and restoring from backup mode must be performed at VDD = 2.3 V min.
(fCLK = 17 MHz) and VDD = 2.2 V min. (fCLK = 13.5 MHz), respectively.
Setting STOP mode
Note
VDD, EVDD, AVDD
tHVD1
tHVD2
tDREL2
0V
tHVD2
tFVD2
VDDBU
VDDDR2
0.8EVDD
RESET (input)
0.2EVDD
Note Shifting to backup mode and restoring from backup mode must be performed at VDD = 2.3 V min. (fCLK = 17
MHz) and VDD = 2.2 V min. (fCLK = 13.5 MHz), respectively.
Preliminary Product Information U15436EJ1V0PM
71
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
AC Characteristics
AC test input measurement points (VDD, AVDD, EVDD, VDDBU)
VDD
VIH
VIH
Measurement points
0V
VIL
VIL
AC test output measurement points
VOH
VOH
Measurement points
VOL
VOL
Load conditions
DUT
(Device under test)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, reduce the load
capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
72
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Clock Timing
(1) Operating conditions (TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.3 to 2.7 V, VSS = AVSS = EVSS =
VSSBU = 0 V, CL = 50 pF)
Parameter
X1 input cycle
Symbol
tCYX
Conditions
<1>
XT1 input cycle
X1 input high-level width
tWXH
<2>
XT1 input high-level width
X1 input low-level width
tWXL
<3>
XT1 input low-level width
MIN.
MAX.
Unit
58.8
ns
28.5
µs
26.4
ns
12.8
µs
26.4
ns
12.8
µs
X1 input rise time
tXR
<4>
0.5 (tCYX –
tWXH – tWXL)
ns
X1 input fall time
tXF
<5>
0.5 (tCYX –
tWXH – tWXL)
ns
CLKOUT output cycle
tCYK
<6>
58.8 ns
CLKOUT high-level width
tWKH
<7>
0.5tCYK – 5
ns
CLKOUT low-level width
tWKL
<8>
0.5tCYK – 5
ns
CLKOUT rise time
tKR
<9>
5
ns
CLKOUT fall time
tKF
<10>
5
ns
16 µs
Remark Ensure that the duty for the X1 and XT1 input waveforms is between 45% and 55%.
(2) Operating conditions (TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS =
VSSBU = 0 V, CL = 50 pF)
Parameter
X1 input cycle
Symbol
tCYX
Conditions
<1>
XT1 input cycle
X1 input high-level width
tWXH
<2>
XT1 input high-level width
X1 input low-level width
tWXL
<3>
XT1 input low-level width
MIN.
MAX.
Unit
T.B.D.
ns
T.B.D.
µs
T.B.D.
ns
T.B.D.
µs
T.B.D.
ns
T.B.D.
µs
X1 input rise time
tXR
<4>
T.B.D.
ns
X1 input fall time
tXF
<5>
T.B.D.
ns
CLKOUT output cycle
tCYK
<6>
T.B.D.
CLKOUT high-level width
tWKH
<7>
T.B.D.
ns
CLKOUT low-level width
tWKL
<8>
T.B.D.
ns
CLKOUT rise time
tKR
<9>
T.B.D.
ns
CLKOUT fall time
tKF
<10>
T.B.D.
ns
T.B.D.
Remark Ensure that the duty for the X1 and XT1 input waveforms is between 45% and 55%.
Preliminary Product Information U15436EJ1V0PM
73
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Clock timing
<1>
<2>
<3>
X1, XT1 (input)
<4>
<5>
<6>
<7>
<8>
CLKOUT (output)
<9>
74
Preliminary Product Information U15436EJ1V0PM
<10>
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Bus Timing
(1) Multiplexed bus mode
(a) CLKOUT asynchronous: In multiplexed bus mode
(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB↓)
tSAST
<11>
0.5T – 15
ns
Address hold time (from ASTB↓)
tHSTA
<12>
0.5T – 15
ns
Delay time from RD↓ to address float
tFRDA
<13>
2
ns
Data input setup time from address
tSAID
<14>
(2 + n)T – 25
ns
Data input setup time from RD↓
tSRID
<15>
(1 + n)T – 25
ns
Delay time from ASTB↓ to RD↓, WRm↓
tDSTRDWR
<16>
0.5T – 15
ns
Data input hold time (from RD↑)
tHRDID
<17>
0
ns
Address output time from RD↑
tDRDA
<18>
(1 + i)T – 15
ns
Delay time from RD, WRm↑ to ASTB↑
tDRDWRST
<19>
0.5T – 15
ns
Delay time from RD↑ to ASTB↓
tDRDST
<20>
(1.5 + i)T – 15
ns
RD, WRm low-level width
tWRDWRL
<21>
(1 + n)T – 15
ns
ASTB high-level width
tWSTH
<22>
T – 15
ns
Data output time from WRm↓
tDWROD
<23>
Data output setup time (to WRm↑)
tSODWR
<24>
(1 + n)T – 20
ns
Data output hold time (from WRm↑)
tHWROD
<25>
T – 15
ns
WAIT setup time (to address)
tSAWT1
<26>
n≥1
1.5T – 25
ns
tSAWT2
<27>
n≥1
(1.5 + n)T – 25
ns
tHAWT1
<28>
n≥1
(0.5 + n)T
ns
tHAWT2
<29>
n≥1
(1.5 + n)T
ns
tSSTWT1
<30>
n≥1
T – 25
ns
tSSTWT2
<31>
n≥1
(1 + n)T – 25
ns
tHSTWT1
<32>
n≥1
nT
ns
tHSTWT2
<33>
n≥1
(1 + n)T
ns
HLDRQ high-level width
tWHQH
<34>
T + 10
ns
HLDAK low-level width
tWHAL
<35>
T – 15
ns
Delay time from HLDAK↑ to bus output
tDHAC
<36>
–3
ns
Delay time from HLDRQ↓ to HLDAK↓
tDHQHA1
<37>
1.5T
(2n + 7.5)T + 25
ns
Delay time from HLDRQ↑ to HLDAK↑
tDHQHA2
<38>
0.5T
1.5T + 25
ns
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
15
ns
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3.
m = 0, 1
4. i: Number of idle states inserted after the read cycle (0 or 1).
5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from
X1.
Preliminary Product Information U15436EJ1V0PM
75
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(b) CLKOUT synchronous: In multiplexed bus mode
(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Delay time from CLKOUT↑ to address
Symbol
Conditions
MIN.
MAX.
Unit
tDKA
<39>
0
19
ns
Delay time from CLKOUT↑ to address float tFKA
<40>
–12
7
ns
Delay time from CLKOUT↓ to ASTB
tDKST
<41>
–12
7
ns
Delay time from CLKOUT↑ to RD, WRm
tDKRDWR
<42>
–5
14
ns
Data input setup time (to CLKOUT↑)
tSIDK
<43>
15
ns
Data input hold time (from CLKOUT↑)
tHKID
<44>
5
ns
Data output delay time from CLKOUT↑
tDKOD
<45>
WAIT setup time (to CLKOUT↓)
tSWTK
<46>
15
ns
WAIT hold time (from CLKOUT↓)
tHKWT
<47>
5
ns
HLDRQ setup time (to CLKOUT↓)
tSHQK
<48>
15
ns
HLDRQ hold time (from CLKOUT↓)
tHKHQ
<49>
5
ns
Delay time from CLKOUT↑ to bus float
tDKF
<50>
19
ns
Delay time from CLKOUT↑ to HLDAK
tDKHA
<51>
19
ns
19
ns
Remarks 1. m = 0, 1
2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from
X1.
76
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait): In Multiplexed Bus Mode
T1
T2
TW
T3
CLKOUT (output)
<39>
A16 to A23 (output),
A0 to A15 (output)
<14>
<43>
<44>
<40>
AD0 to AD15 (I/O)
Hi-Z
Address
Data
<41>
<12>
<11>
<41>
<17>
ASTB (output)
<22>
<42>
<16>
<19>
<13>
<15>
<42>
<18>
<20>
RD (output)
<30> <46>
<32>
<31>
<33>
<47>
<21>
<46>
<47>
WAIT (input)
<26>
<28>
<27>
<29>
Remark WR0 and WR1are high level.
Preliminary Product Information U15436EJ1V0PM
77
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait): In Multiplexed Bus Mode
T1
T2
TW
T3
CLKOUT (output)
<39>
A16 to A23 (output),
A0 to A15 (output)
<45>
AD0 to AD15 (I/O)
Address
Data
<41>
<12>
<11>
<41>
ASTB (output)
<22>
<19>
<42>
<16>
<23>
<42>
<24>
<25>
WR0 (output),
WR1 (output)
<30> <46>
<32>
<31>
<33>
<47>
<21>
<46>
<47>
WAIT (input)
<26>
<28>
<27>
<29>
Remark RD is high level.
78
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Bus Hold: In Multiplexed Bus Mode
TH
TH
TH
TI
CLKOUT (output)
<48>
<48> <49>
<34>
HLDRQ (input)
<51>
<51>
<37>
<38>
HLDAK (output)
<50>
<35>
<36>
Hi-Z
A16 to A23 (output)
A0 to A15 (output)
AD0 to AD15 (I/O)
ASTB (output)
RD (output),
WR0 (output), WR1 (output)
Data
Hi-Z
Hi-Z
Hi-Z
Preliminary Product Information U15436EJ1V0PM
79
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2) In separate bus mode
(a) Read cycle (CLKOUT asynchronous): In separate bus mode
(TA = –40 to +85°°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to RD↓)
tSARD
<52>
0.5T – 15
ns
Address hold time (from RD↑)
tHARD
<53>
2
ns
RD low-level width
tWRDL
<54>
(1.5 + n) T – 10
ns
Data setup time (to RD↑)
tSISD
<55>
20
ns
Data hold time (from RD↑)
tHISD
<56>
0
ns
Data setup time (to address)
tSAID
<57>
(2 + n) T – 25
ns
WAIT setup time (to RD↓)
tSRDWT1
<58>
0.5T – 20
ns
tSRDWT2
<59>
(0.5 + n) T – 20
ns
tHRDWT1
<60>
0.5T
ns
tHRDWT2
<61>
(0.5 + n) T
ns
tSAWT1
<62>
T – 20
ns
tSAWT2
<63>
(1 + n) T – 20
ns
tHAWT1
<64>
T
ns
tHAWT2
<65>
(1 + n) T
ns
WAIT hold time (from RD↓)
WAIT setup time (to address)
WAIT hold time (from address)
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency)
2. n: Number of wait clocks inserted in bus cycle
The sampling timing changes when a programmable wait is inserted.
3. The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input
from X1.
(b) Read cycle (CLKOUT synchronous): In separate bus mode
(TA = –40 to +85°°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
19
ns
Delay time from CLKOUT↑ to address, CS tDKSA
<66>
0
Data input setup time (to CLKOUT↑)
tSISDK
<67>
15
ns
Data input hold time (from CLKOUT↑)
tHKISD
<68>
5
ns
Delay time from CLKOUT↓↑ to RD
tDKSR
<69>
0
WAIT setup time (to CLKOUT↑)
tSWTK
<70>
15
ns
WAIT hold time (from CLKOUT↑)
tHKWT
<71>
5
ns
19
ns
Remark The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from
X1.
80
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(c) Write cycle (CLKOUT asynchronous): In separate bus mode
(TA = –40 to +85°°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to WRm↓)
tSAW
<72>
T – 15
ns
Address hold time (from WRm↑)
tHAW
<73>
0.5T – 10
ns
WRm low-level width
tWWRL
<74>
(0.5 + n) T – 10
ns
Data output time from WRm↓
tDOSDW
<75>
–5
ns
Data setup time (to WRm↑)
tSOSDW
<76>
(0.5 + n) T – 10
ns
Data hold time (from WRm↑)
tHOSDW
<77>
0.5T – 10
ns
Data setup time (to address)
tSAOD
<78>
T – 25
ns
WAIT setup time (to WRm↓)
tSWRWT1
<79>
20
ns
tSWRWT2
<80>
nT – 20
ns
tHWRWT1
<81>
0
ns
tHWRWT2
<82>
nT
ns
tSAWT1
<83>
T – 20
ns
tSAWT2
<84>
(1 + n) T – 20
ns
tHAWT1
<85>
T
ns
tHAWT2
<86>
(1 + n) T
ns
WAIT hold time (from WRm↓)
WAIT setup time (to address)
WAIT hold time (from address)
Remarks 1. m = 0, 1
2. T = 1/fCPU (fCPU: CPU operation clock frequency)
3. n: Number of wait clocks inserted in bus cycle
The sampling timing changes when a programmable wait is inserted.
4. The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input
from X1.
(d) Write cycle (CLKOUT synchronous): In separate bus mode
(TA = –40 to +85°°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT↑ to address, CS tDKSA
<87>
0
19
ns
Delay time from CLKOUT↑ to data output
tDKSD
<88>
0
19
ns
Delay time from CLKOUT↑↓ to WRm
tDKSW
<89>
0
19
ns
WAIT setup time (to CLKOUT↑)
tSWTK
<90>
15
ns
WAIT hold time (from CLKOUT↑)
tHKWT
<91>
5
ns
Remarks 1. m = 0, 1
2. The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input
from X1.
Preliminary Product Information U15436EJ1V0PM
81
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Read Cycle (CLKOUT Asynchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output)
CS0 to CS3 (output)
A0 to A23 (output)
<53>
<57>
AD0 to AD15 (I/O)
Hi-Z
Hi-Z
<56>
<52>
<55>
<54>
RD (output)
<61>
<59>
<60>
<58>
WAIT (input)
<62>
<64>
<63>
<65>
82
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Read Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output)
<66>
<66>
CS0 to CS3 (output)
A0 to A23 (output)
<67>
AD0 to AD15 (I/O)
<68>
Hi-Z
Hi-Z
<69>
<69>
RD (output)
<70>
<71>
<70>
<71>
WAIT (input)
Preliminary Product Information U15436EJ1V0PM
83
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Write Cycle (CLKOUT Asynchronous, 1 Wait): In Separate Bus Mode
TW
T1
T2
CLKOUT (output)
CS0 to CS3 (output)
A0 to A23 (output)
<73>
<78>
AD0 to AD15 (I/O)
Hi-Z
Hi-Z
<75>
<77>
<72>
<76>
<74>
WR0, WR1 (output)
<82>
<80>
<79> <81>
WAIT (input)
<83>
<85>
<84>
<86>
84
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Write Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output)
<87>
<87>
CS0 to CS3 (output)
A0 to A23 (output)
<88>
<88>
AD0 to AD15 (I/O)
Hi-Z
Hi-Z
<89>
<89>
WR0, WR1 (output)
<90>
<91>
<90>
<91>
WAIT (input)
Preliminary Product Information U15436EJ1V0PM
85
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Reset/Interrupt Timing
(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
RESET high-level width
tWRSH
<92>
500
ns
RESET low-level width
tWRSL
<93>
500
ns
NMI high-level width
tWNIH
<94>
500
ns
NMI low-level width
tWNIL
<95>
500
ns
INTPn high-level width
tWITH
<96>
n = 0 to 6 (analog noise
elimination)
500
ns
INTPn low-level width
tWITL
<97>
n = 0 to 6 (analog noise
elimination)
500
ns
Remark T = 1/fXX
Reset
<92>
<93>
RESET (input)
Interrupt
<94>
<95>
<96>
<97>
NMI (input)
INTPn (input)
Remark n = 0 to 6
86
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Timer Timing
(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Symbol
TIn high-level width
Conditions
n = 0, 1
n = 2 to 5
TIn low-level width
n = 0, 1
n = 2 to 5
MIN.
MAX.
Unit
2T + 20
ns
40
ns
2T + 20
ns
40
ns
TCLRn high-level width
n = 0, 1
2T + 20
ns
TCLRn low-level width
n = 0, 1
2T + 20
ns
INTPnm high-level width
tWITH
nm = 00, 01, 10, 11
2T + 20
ns
INTPnm low-level width
tWITL
nm = 00, 01, 10, 11
2T + 20
ns
Remark T = 1/fXX
Preliminary Product Information U15436EJ1V0PM
87
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
CSI Timing
(1) Master mode
(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle time
tKCY1
<98>
Output
200
ns
SCKn high-/low-level width
tKH1,
tKL1
<99>
Output
tKCY1/2 – 10
ns
SIn setup time (to SCKn↑)
tSIK1
<100>
30
ns
SIn hold time (from SCKn↑)
tKSI1
<101>
30
ns
Delay time from SCKn↓ to SOn output
tKSO1
<102>
30
ns
Remark n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3)
(2) Slave mode
(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle time
tKCY2
<98>
Output
200
ns
SCKn high-/low-level width
tKH2,
tKL2
<99>
Output
90
ns
SIn setup time (to SCKn↑)
tSIK2
<100>
50
ns
SIn hold time (from SCKn↑)
tKSI2
<101>
50
ns
Delay time from SCKn↓ to SOn output
tKSO2
<102>
50
Remark n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3)
<98>
<99>
<99>
SCKn (I/O)
<100>
SIn (input)
Hi-Z
<101>
Input data
<102>
SOn (output)
Output data
Remark n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3)
88
Preliminary Product Information U15436EJ1V0PM
Hi-Z
ns
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
I C Bus Mode (µPD703201Y, 703204Y, 70F3201Y, 70F3204Y only)
2
(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V)
Parameter
Symbol
Normal Mode
High-Speed Mode
Unit
MIN.
MAX.
MIN.
MAX.
0
100
0
400
kHz
SCL clock frequency
fCLK
Bus-free time (between
stop/start conditions)
tBUF
<103>
4.7
–
1.3
–
µs
Hold timeNote 1
tHD:STA
<104>
4.0
–
0.6
–
µs
SCL clock low-level width
tLOW
<105>
4.7
–
1.3
–
µs
SCL clock high-level width
tHIGH
<106>
4.0
–
0.6
–
µs
Setup time for start/restart
conditions
tSU:STA
<107>
4.7
–
0.6
–
µs
Data hold
time
tHD:DAT
<108>
5.0
–
–
–
µs
0Note 2
–
0Note 2
0.9Note 3
µs
CBUS
compatible
master
I2C mode
Data setup time
tSU:DAT
SDA and SCL signal rise time
<109>
tR
250
<110>
–
Note 4
–
100
1,000
–
ns
Note 5
300
ns
Note 5
300
ns
20 + 0.1Cb
SDA and SCL signal fall time
tF
<111>
–
300
20 + 0.1Cb
Stop condition setup time
tSU:STO
<112>
4.0
–
0.6
–
µs
Pulse width with spike
suppressed by input filter
tSP
<113>
–
–
0
50
ns
Capacitance load of each bus
line
Cb
–
400
–
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
2. The system requires a minimum of 300 ns hold time internally for the SDA signal (at VIHmin.. of SCL
signal) in order to occupy the undefined area at the falling edge of SCL.
3. If the system does not extend the SCL signal low hold time (tLOW), only the maximum data hold time (tHD:
DAT)
needs to be satisfied.
2
2
4. The high-speed-mode I C bus can be used in a normal-mode I C bus system. In this case, set the high2
speed-mode I C bus so that it meets the following conditions.
• If the system does not extend the SCL signal's low state hold time:
tSU:DAT ≥ 250 ns
• If the system extends the SCL signal's low state hold time:
Transmit the following data bit to the SDA line prior to releasing the SCL line (tRmax. + tSU:DAT = 1,000
2
+ 250 = 1,250 ns: Normal mode I C bus specification).
5.
Cb: Total capacitance of one bus line (unit: pF)
Preliminary Product Information U15436EJ1V0PM
89
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
I C Bus Mode (µPD703201Y, 703204Y, 70F3201Y, 70F3204Y only)
2
<105> <106>
SCL (I/O)
<111> <110>
<108>
<109> <107>
<104>
<113>
<112>
<104>
SDA (I/O)
<103>
Stop
condition
<110>
<111>
Start
condition
Restart
condition
Stop
condition
A/D Converter
(TA = –40 to +85°C, VDD = AVDD = AVREF0 = 2.2 to 2.7 V, AVSS = VSS = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
Resolution
MIN.
TYP.
MAX.
Unit
10
10
10
bit
T.B.D.
%FSR
Note 1
Overall error
Conversion time
tCONV
µs
T.B.D.
Note 1
Zero-scale error
T.B.D.
%FSR
T.B.D.
%FSR
T.B.D.
LSB
T.B.D.
LSB
2.2
2.7
V
AVSS
AVREF
V
Full-scale error Note 1
Integral linearity error
Note 2
Differential linearity error
Note 2
Analog reference voltage
AVREF
AVREF0 = AVDD
Analog input voltage
VIAN
AVREF0 current
AIREF0
T.B.D.
µA
AVDD power supply current
AIDD
T.B.D.
mA
Notes 1. Excluding quantization error (±0.05 %FSR)
2. Excluding quantization error (±0.5 LSB)
Remark LSB: Least Significant Bit
FSR: Full Scale Range
90
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
D/A Converter
(TA = –40 to +85°°C, VDD = AVDD = AVREF1 = 2.2 to 2.7 V, AVSS = VSS = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
Resolution
Note
Overall error
MIN.
TYP.
MAX.
Unit
8
8
8
bit
T.B.D.
%FSR
T.B.D.
µs
Load conditions: 2 MΩ, 30 pF
AVREF1 = VDD
Settling time
Output resistance
T.B.D.
Analog reference voltage
AVREF
AVREF1 = VDD
AVREF1 current
AVREF1
Per channel
2.2
kΩ
2.7
T.B.D.
V
mA
Note Excludes quantization error (±0.05%FSR).
Preliminary Product Information U15436EJ1V0PM
91
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
21. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C D
R
Q
26
25
100
1
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
16.00±0.20
B
14.00±0.20
C
14.00±0.20
D
16.00±0.20
F
1.00
G
1.00
H
0.22 +0.05
−0.04
I
J
0.08
0.50 (T.P.)
K
1.00±0.20
L
0.50±0.20
M
0.17 +0.03
−0.07
N
0.08
P
1.40±0.05
Q
0.10±0.05
R
3° +7°
−3°
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
92
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
121-PIN PLASTIC FBGA (12x12)
w
E
S B
ZE
ZD
B
13
12
11
10
9
8
7
6
5
4
3
2
1
A
D
NM L K J HG F E DC B A
w
INDEX MARK
S A
A
y1
A2
S
S
y
S
e
φb
A1
φx
M
S AB
ITEM
D
MILLIMETERS
12.00±0.10
E
12.00±0.10
w
0.20
A
1.48±0.10
A1
A2
0.35±0.06
1.13
e
0.80
b
0.50 +0.05
−0.10
x
y
y1
ZD
ZE
0.08
0.10
0.20
1.20
1.20
P121F1-80-EA6
Preliminary Product Information U15436EJ1V0PM
93
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
APPENDIX DEVELOPMENT TOOLS
(1) Hardware
Product Name
Description
Note
In-circuit emulator
IE-V850ES-××
(provisional name)
In-circuit emulator for V850ES
In-circuit emulator option board
IE-703204-MC-EM1Note
(provisional name)
Option board to emulate V850ES/SA2,
V850ES/SA3 peripheral functions in combination
with in-circuit emulator
Emulation probe
V850ES/SA2
Note
Emulation probe for 100-pin LQFP
V850ES/SA3
Note
Emulation probe for 121-pin FBGA
Power supply unit
IE-70000-MC-PS-B
Power supply for in-circuit emulator
PC interface board
IE-70000-CD-IF-A
Interface board for connection to PC (for PCMCIA)
IE-70000-PCI-IF
Interface board for connection to PC (for PCI)
Note
Flash programmer for writing a program to a singlepower-supply flash memory product.
V850ES/SA2
Note
Program adapter for 100-pin LQFP
V850ES/SA3
Note
Program adapter for 121-pin FBGA
Flash programmer
Program adapter
Note Under development
(2) Software
Product Name
Description
Compiler
CA850
C compiler compliant with ANSI-C
Debugger
ID850
Debugger used in combination with in-circuit
emulator
Real-time OS
RX850
Real-time OS compliant with µITRON specifications
Device file
V850ES/SA2
DF703201Note
Definition file for V850ES/SA2
V850ES/SA3
Note
Definition file for V850ES/SA3
DF703204
Note Under development
94
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
[MEMO]
Preliminary Product Information U15436EJ1V0PM
95
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Caution
2
2
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use
2
2
these components in an I C system, provided that the system conforms to the I C Standard
Specification as defined by Philips.
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
V850 Family, V850ES/SA2, and V850ES/SA3 are trademarks of NEC Corporation.
TRON stands for The Real-time Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
96
Preliminary Product Information U15436EJ1V0PM
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
Preliminary Product Information U15436EJ1V0PM
97
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed: µPD70F3201, 70F3201Y, 70F3204, 70F3204Y
The customer must judge the need for license: µPD703201, 703201Y, 703204, 703204Y
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8