NEC UPD78C14G

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78C14(A)
8-BIT SINGLE-CHIP MICROCONTROLLER (WITH A/D CONVERTER)
The µPD78C14(A) is a single-chip, CMOS 8-bit microcontroller in which a 16-bit ALU, a ROM, a RAM, an A/D converter,
a multifunction timer/event counter, and a serial interface are all integrated. Moreover, a 48-Kbyte external expansion
memory (ROM/RAM) can be connected.
Since the µPD78C14(A) uses the CMOS construction, its operations are performed with low power consumption. By
using the standby function, functions such as data retention are performed with lower power consumption.
For details on functions, refer to the User’s Manual listed below. Please read it before starting design work.
87AD series µPD78C18 User’s Manual: IEU-1314
FEATURES
High reliability as compared with µPD78C14
159 instructions: 87AD instruction set
Multiply and divide instructions, 16-bit arithmetic operation instructions
Instruction cycle: 0.8 µs at 15 MHz
Internal ROM: 16384 W x 8
Internal RAM: 256 W x 8
Direct addressing to an external memory (ROM/RAM) up to 64 Kbytes
Highly accurate 8-bit A/D converter: Eight analog inputs
General-purpose serial interface: Asynchronous, synchronous, and I/O interface modes
Multifunction 16-bit timer/event counter
Two 8-bit timers
I/O lines: 44
Interrupt functions: Three external, eight internal
• Non-maskable interrupt: 1
• Maskable interrupts: 10
Zero-cross detection function (two inputs)
Standby functions: HALT mode, Hardware/software STOP mode
ORDERING INFORMATION
Part number
µPD78C14G(A)-xxx-36
µPD78C14GF(A)-xxx-3BE
µPD78C14L(A)-xxx
Package
64-pin plastic QUIP
64-pin plastic QFP (14 x 20 mm)
68-pin plastic QFJ (950 x 950 mil)
Quality grade
Special
Special
Special
Remark xxx is a ROM code suffix.
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No. IC-2813B
(O.D. No. IC-8242B)
Date Published May 1995 P
Printed in Japan
H The mark
*
shows revised points.
©
©
1991
1994
µPD78C14(A)
Pin Configuration (Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
STOP
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
ALE
WR
RD
AVDD
VAREF
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AVSS
PD2
PD1
PD0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
ALE
WR
RD
AVDD
VAREF
AN7
AN6
AN5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
µ PD78C14G(A)-XXX-36
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0/TxD
PC1/RxD
PC2/SCK
PC3/INT2
PC4/TO
PC5/CI
PC6/CO0
PC7/CO1
NMI
INT1
MODE1
RESET
MODE0
X2
X1
VSS
51 50 49 48 47 46 454443 42 41 40 39 38 37 36 35 34 33
52
32
53
31
54
30
55
29
56
28
57
27
µ PD78C14GF(A)-XXX-3BE
58
26
59
25
60
24
61
23
62
22
63
21
641 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 1718 19 20
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0/TxD
PC1/RxD
PC2/SCK
PC3/INT2
PC4/TO
PC5/CI
PC6/CO0
PC7/CO1
NMI
PD3
PD4
PD5
PD6
PD7
STOP
VDD
PA0
PA1
PA2
PA3
PA4
PA5
2
AN4
AN3
AN2
AN1
AN0
AVSS
VSS
X1
X2
MODE0
RESET
MODE1
INT1
IC
PA6
PA5
PA4
PA3
PA2
PA1
PA0
VDD
STOP
PD7
PD6
PD5
PD4
PD3
PD2
IC
µPD78C14(A)
9 8 7 6 5 4 3 2 1 68 67 66 6564 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
µ PD78C14L(A)-XXX
19
51
20
50
21
49
22
48
23
47
24
46
25
45
44
26
2728 29 30 3132 33 34 35 36 37 38 39 4041 42 43
PD1
PD0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
ALE
WR
RD
AVDD
IC
VAREF
AN7
PC7/CO1
NMI
INT1
MODE1
RESET
MODE0
X2
X1
VSS
AVSS
AN0
AN1
AN2
AN3
AN4
AN5
AN6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0/TxD
PC1/RxD
PC2/SCK
PC3/INT2
IC
PC4/TO
PC5/CI
PC6/CO0
3
NMI
INT1
INT.
CONTROL
8
4
TIMER
PC4/TO
AN7-0
VAREF
VDD
AVSS
TIMER
EVENT
COUNTER
8
8
8
8
8
MAIN
G.R
16
8
8
PROGRAM
MEMORY
ALT (16 K-BYTE)
G.R
Note
DATA
MEMORY
(256-BYTE)
8
8
INTERNAL DATA BUS
16
16
6
LATCH
LATCH
PSW
8
PD7-0/AD7-0
PC7-0
PB7-0
PA7-0
8
INST.REG
8
PF7-0/AB15-8
8
16
A/D
CONVERTER
8
14
8
8
8
8
8
PC5/CI
PC6/CO0
PC7/CO1
8
8
8/16
PC3/INT2/TI
PORT F
SERIAL I/O
8
PORT D
PC0/TxD
PC1/RxD
PC2/SCK
PORT C
X2
8
PORT B
OSC
PORT A
16
LATCH
INC/DEC
PC
SP
EA
V
A
B
C
E
D
H
L
EA'
V'
A'
B'
C'
E'
D'
H'
L'
BUFFER
Block Diagram
4
X1
16
INST.
DECODER
ALU
(8/16)
16
READ/WRITE
CONTROL
SYSTEM
CONTROL
STANDBY
CONTROL
Note
DATA MEMORY can only be used when RAE bit of MM register is set to 1.
External memory is necessary when 0 is set.
VDD
VSS
µPD78C14(A)
RD WR ALE MODE1 MODE0 RESET STOP
µPD78C14(A)
CONTENTS
1.
DIFFERENCES BETWEEN µPD78C14(A) AND µPD78C14 ...................................................6
2.
PIN FUNCTIONS ......................................................................................................................7
3.
2.1
Pin Function List .........................................................................................................................7
2.2
Pin Input/Output Circuits ...........................................................................................................9
2.3
Recommended Connections for Unused Pins....................................................................... 13
INSTRUCTION SET ................................................................................................................14
3.1
Operand Expression Format/Description Method .................................................................14
3.2
Instruction Code Description ..................................................................................................16
3.3
Instruction Execution Time......................................................................................................17
4.
LIST OF MODE REGISTERS .................................................................................................29
5.
ELECTRICAL SPECIFICATIONS ..........................................................................................30
6.
CHARACTERISTIC CURVES (reference value) ...................................................................41
7.
PACKAGE DRAWINGS .........................................................................................................44
8.
RECOMMENDED SOLDERING CONDITIONS .....................................................................47
APPENDIX DEVELOPMENT TOOLS ............................................................................................49
5
µPD78C14(A)
1. DIFFERENCES BETWEEN µPD78C14(A) AND µPD78C14
µPD78C14(A)
µPD78C14
Quality grade
Special
Standard
Electrical
Input leakage current
Input leakage current
specifications
(AN7-0; ±1 µA (MAX.)
AN7-0; ±10 µA (MAX.)
Part number
Item
Package
• 64-pin plastic QUIP
• 64-pin plastic shrink DIP
• 64-pin plastic QFP
• 64-pin plastic QUIP
(14 x 20 mm, thickness: 2.05 mm)
• 68-pin plastic QFJ
• 64-pin plastic QUIP (straight)
• 64-pin plastic QFP
(14 x 20 mm, thickness: 2.05 mm)
• 64-pin plastic QFP
(14 x 20 mm, thickness: 2.70 mm)
• 68-pin plastic QFJ
6
µPD78C14(A)
2. PIN FUNCTIONS
2.1 Pin Function List
Pin
PA7-PA0
Input/Output
Input/Output
(Port A)
PB7-PB0
PC1/RxD
PC2/SCK
These 8 pins constitute an 8-bit I/O port and input/output can be specified in bit
units.
Input/Output
(Port B)
PC0/TxD
Function
These 8 pins constitute an 8-bit I/O port and input/output can be specified in bit
units.
Input/Output,
Port C
Transmit Data
Output
These 8 pins constitute an 8-bit I/O
This pin outputs serial data.
Input/Output,
port and input/output can be specified
Receive Data
Input
in bit units.
This pin inputs serial data.
Input/Output,
Serial Clock
Input/Output
This pin inputs/outputs serial clock. It becomes an output pin when an internal
clock is used or an input pin when an
external clock is used.
PC3/INT2/TI
Input/Output,
Interrupt Request/Timer Input
Input, Input
This pin inputs edge triggering (falling
edge) maskable interrupt or external
clock for timer. This pin is also shared
with zero-cross detection pin for AC input.
PC4/TO
Input/Output,
Timer Output
Output
This pin outputs square waves in which
one cycle of the internal clock forms a
half cycle, indicating the timer’s counting
time.
PC5/CI
Input/Output,
Counter Input
Input
This pin inputs external pulse for timer/
event counter.
PC6/CO0
Input/Output,
Counter Output 0,1
PC7/CO1
Output
This pin outputs programmable square
PD7-PD0/
Input/Output,
AD7-AD0
Input/Output
wave by timer/event counter.
PF7-PF0/
Input/Output,
AB15-AB8
Output
Port D
Address/Data Bus
These 8 pins constitute an 8-bit I/O
These pins function as multiplexed
port and input/output can be
address/data bus when using an
specified in byte units.
external memory.
Port F
Address Bus
These 8 pins constitute an 8-bit I/O
These pins function as address bus when
port and input/output can be specified
using an external memory.
in bit units.
WR
Output
This is a strobe signal output to write data in external memory. This signal
(Write
becomes high level except during the data write machine cycle for external memory.
Strobe)
This signal becomes output high impedance when the RESET signal is low or in
the hardware STOP mode.
7
µPD78C14(A)
(Continued)
Pin
RD
Input/Output
Output
(Read
Function
This is a strobe signal output to read data from external memory. This signal
becomes high level except during the data read machine cycle for external memory.
Strobe)
This signal becomes output high impedance when the RESET signal is low or in
the hardware STOP mode.
ALE
Output
(Address
This is a strobe signal to externally latch the low-order address information
output to pins PD7-PD0 to access the external memory. This signal becomes
Latch
output high impedance when the RESET signal is low or in the hardware STOP
Enable)
mode.
MODE0
Input/Output
When both pins MODE0 and MODE1 are set to 1Note, these pins synchronize to
MODE1
(Mode)
NMI
Set the MODE0 pin to 0 (low level) and MODE1 pin to 1 (high level)Note.
the ALE and a control signal is output.
Input
This pin inputs the edge triggering (falling edge) nonmaskable interrupt.
Input
This pin inputs edge triggering (rising edge) maskable interrupt. This pin is also
(NonMaskable
Interrupt)
INT1
(Interrupt
shared with zero-cross detection pin for AC input.
Request)
AN7-AN0
Input
(Analog
These eight pins input analog signals for the A/D converter. Pins AN7-AN4 can
be used as edge detection (falling edge) input.
Input)
Input
VAREF
(Reference
This pin inputs the reference voltage for the A/D converter and controls the
operation for the A/D converter.
Voltage)
AVDD
Power supply pin for the A/D converter
(Analog
VDD)
AVSS
Ground pin for the A/D converter
(Analog
VSS)
X1, X2
These are crystal connecting pins for the system clock oscillation. When a clock
(Crystal)
is externally supplied, input it through pin X1. Input the clock to X1 and its reverse
phase to X2.
RESET
Input
This pin inputs the active-low reset input signal.
Input
This pin inputs control signal of the hardware STOP mode. When the low level
(Reset)
STOP
(Stop)
of this signal is input, the oscillator stops to operate.
VDD
Positive power supply pin
VSS
Ground pin
Note Pull-up with the following external resistor:
4 (kΩ) ≤ R ≤ 0.4 tCYC (kΩ)
Example
tCYC (unit: ns)
4 (kΩ) ≤ R ≤ 26 (kΩ): tCYC = 66 (ns) at 15 MHz
4 (kΩ) ≤ R ≤ 33 (kΩ): tCYC = 83 (ns) at 12 MHz
8
µPD78C14(A)
2.2 Pin Input/Output Circuits
Schematic input/output circuits of the pins are shown in Table 2-1 and figures from (1) to (11).
Table 2-1. Name of Type No.
Pin
Type No.
Pin
Type No.
PA0-7
5
RESET
2
PB0-7
5
RD
4
PC0-1
5
WR
4
PC2/SCK
8
ALE
4
PC3/INT2
10
STOP
2
PC4-7
5
MODE0
11
PD0-7
5
MODE1
11
PF0-7
5
AN0-3
7
NMI
2
AN4-7
12
INT1
9
VAREF
13
9
µPD78C14(A)
(1) Type 1
VDD
P-ch
IN
N-ch
(2) Type 2
IN
(3) Type 4
VDD
output data
P-ch
OUT
N-ch
output disable
(4) Type 5
output data
Type 4
output disable
Type 1
10
IN/OUT
µPD78C14(A)
(5) Type 7
AVDD
P-ch
+
IN
N-ch
–
AVDD
sampling
C
AVSS
AVSS
reference voltage
(from voltage tap of serial resistor string)
(6) Type 8
output data
Type 5
output disable
N-ch
N-ch
IN/OUT
Type 2
MCC
(7) Type 9
self bias
enable
IN
Type 1
data
(8) Type 10
output data
output disable
Type 5
self bias
enable
N-ch
Type 9
IN/OUT
N-ch
MCC
11
µPD78C14(A)
(9) Type 11
IN/OUT
output data
N-ch
Type 1
(10) Type 12
Type 7
IN
edge detection circuit
Type 2
(11) Type 13
Type 1
IN
STOP Mode
P-ch
AVSS
12
µPD78C14(A)
2.3 Recommended Connections for Unused Pins
Pin
Recommended connection
PA7-0
PB7-0
PC7-0
Connect to VDD or VSS via resistor.
PD7-0
PF7-0
RD
WR
Leave unconnected.
ALE
STOP
VDD
INT1, NMI
Connect to VDD or VSS.
AVDD
Connect to VDD.
VAREF
Connect to VSS.
AVSS
AN7-0
Connect to AVSS or AVDD.
13
µPD78C14(A)
3. INSTRUCTION SET
3.1 Operand Expression Format/Description Method
Expression format
Description method
r
V, A, B, C, D, E, H, L
r1
EAH, EAL, B, C, D, E, H, L
r2
A, B, C
sr
PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB,
MC, MF, TXB, TM0, TM1, ZCM
sr1
PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3
sr2
PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM
sr3
ETM0, ETM1
sr4
ECNT, ECPT
rp
SP, B, D, H
rp1
V, B, D, H, EA
rp2
SP, B, D, H, EA
rp3
B, D, H
rpa
B, D, H, D+, H+, D–, H–
rpa1
B, D, H
rpa2
B, D, H, D+, H+, D–, H–, D+byte, H+A, H+B, H+EA, H+byte
rpa3
D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte
wa
8-bit immediate data
word
16-bit immediate data
byte
8-bit immediate data
bit
3-bit immediate data
f
CY, HC, Z
irf
NMI Note, FT0, FT1, F1, F2, FE0, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7,
SB
Note NMI can be also described as FNMI.
14
µPD78C14(A)
Remarks
1. sr to sr4 (special register)
PA
: PORT A
2. rp to rp3 (register pair)
ETMM : TIMER/EVENT
CY : CARRY
B
: BC
HC : HALF CARRY
D
: DE
Z
: PORT B
PC
: PORT C
PD
: PORT D
COUNTER OUTPUT
H
: HL
PF
: PORT F
MODE
V
: VA
MA
: MODE A
ANM
: A/D CHANNEL MODE
EA
: EXTENDED
MB
: MODE B
CR0
: A/D CONVERSION
MC
: MODE C
to
MCC : MODE CONTROL C
COUNTER MODE
: STACK POINTER
PB
EOM
: TIMER/EVENT
ACCUMULATOR
RESULT 0 to 3
CR3
4. f (flag)
SP
: ZERO
5. irf (interrupt flag)
NMI : NMI INPUT
FT0 : INTFT0
FT1 : INTFT1
3. rpa to rpa3 (rp addressing)
F1
: INTF1
: INTF2
MF
: MODE F
TXB
: Tx BUFFER
B
: (BC)
F2
MM
: MEMORY MAPPING
RXB
: Rx BUFFER
D
: (DE)
FE0 : INTFE0
TM0
: TIMER REG0
SMH
: SERIAL MODE High
H
: (HL)
FE1 : INTFE1
TM1
: TIMER REG1
SML
: SERIAL MODE Low
D+
: (DE)+
FEIN: INTFEIN
TMM : TIMER MODE
MKH
: MASK High
H+
: (HL)+
FAD : INTFAD
ETM0 : TIMER/EVENT
MKL
: MASK Low
D–
: (DE)–
FSR : INTFSR
ZCM
: ZERO CROSS MODE
COUNTER REG0
ETM1 : TIMER/EVENT
COUNTER REG1
ECNT : TIMER/EVENT
COUNTER UPCOUNTER
ECPT : TIMER/EVENT
COUNTER CAPTURE
H–
: (HL)–
FST : INTFST
D++
: (DE)++
ER : ERROR
H++
: (HL)++
D+byte : (DE+byte)
OV : OVERFLOW
AN4 : ANALOG INPUT
H+A
: (HL+A)
to
H+B
: (HL+B)
AN7
H+EA : (HL+EA)
SB
4 to 7
: STANDBY
H+byte : (HL+byte)
15
µPD78C14(A)
3.2 Instruction Code Description
r1
r
R2
0
0
0
0
1
1
1
1
R1
0
0
1
1
0
0
1
1
reg
V
A
B
C
D
E
H
L
R0
0
1
0
1
0
1
0
1
rpa
T2
0
0
0
0
1
1
1
1
r2
r
T1
0
0
1
1
0
0
1
1
reg
EAH
EAL
B
C
D
E
H
L
T0
0
1
0
1
0
1
0
1
sr
S5 S4 S3 S2 S1 S0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Special-reg
PA
PB
PC
PD
PF
MKH
MKL
ANM
SMH
SML
EOM
ETMM
TMM
MM
MCC
MA
MB
MC
MF
TXB
RXB
TM0
TM1
CR0
CR1
CR2
CR3
ZCM
sr3
sr1
Special-reg
0
1
ETM0
ETM1
V0
0
1
A0
0
1
0
1
0
1
0
1
1
0
1
0
1
addressing
C2
0
0
1
1
0
1
1
1
1
C1
1
1
0
0
1
0
0
1
1
C0
0
1
0
1
1
0
1
0
1
addressing
I4 I3
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 0
I2
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
I1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
C3
0
0
0
0
1
1
1
1
1
sr
(BC)
(DE)
(HL)
(DE)+
(HL)+
(DE)–
(HL)–
(DE+byte)
(HL+A)
(HL+B)
(HL+EA)
(HL+byte)
Special-reg
ECNT
ECPT
rp1
rpa2
INTF
NMI
FT0
FT1
F1
F2
FE0
FE1
FEIN
FAD
FSR
FST
ER
OV
AN4
AN5
AN6
AN7
SB
I0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
f
P1
P0
reg-pair
Q2
Q1
Q0
reg-pair
F2
F1
F0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
SP
BC
DE
HL
EA
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
VA
BC
DE
HL
EA
0
0
0
1
0
1
1
0
0
0
1
0
rp2
rpa
(DE)
(HL)
(DE)++
(HL)++
(DE+byte)
(HL+A)
(HL+B)
(HL+EA)
(HL+byte)
P2
rp
rpa1
irf
rp
16
A1
0
0
1
1
0
0
1
1
1
0
0
1
1
rpa3
sr2
sr4
U0
A2
0
0
0
0
1
1
1
1
0
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
rp3
flag
—
CY
HC
Z
µPD78C14(A)
3.3 Instruction Execution Time
In the following table, one state consists of three clock cycles. So, when the 15 MHz clock is used, one state becomes
200 ns (= 3 x 1/15 µs). Execution time of the 4-state instruction, the shortest instruction, becomes 0.8 µs.
17
Instruction group
18
Instruction code
Mnemonic
State
Operand
B1
B3
B2
Operation
B4
r1, A
0 0 0 1 1 T2 T1 T0
4
r1 ← A
A, r1
0 0 0 0 1 T2 T1 T0
4
A ← r1
*
sr, A
01001101
1 1 S5 S4 S3 S2 S1 S0
10
sr ← A
*
A, sr1
01001100
1 1 S5 S4 S3 S2 S1 S0
10
A ← sr1
r, word
01110000
0 1 1 0 1 R2 R1 R0
Low Adrs
High Adrs
17
r ← (word)
word, r
01110000
0 1 1 1 1 R2 R1 R0
Low Adrs
High Adrs
17
(word) ← r
r, byte
0 1 1 0 1 R2 R1 R0
7
r ← byte
sr2, byte
01100100
Data
14
sr2 ← byte
Data
13
(V. wa) ← byte
Skip
condition
MOV
*
Data
S3 0 0 0 0 S2 S1 S0
MVIW
*
wa, byte
01110001
Offset
MVIX
*
rpa1, byte
0 1 0 0 1 0 A1 A0
Data
10
(rpa1) ← byte
STAW
*
wa
01100011
Offset
10
(V. wa) ← A
LDAW
*
wa
00000001
Offset
10
A ← (V. wa)
STAX
*
rpa2
A3 0 1 1 1 A2 A1 A0
Data
LDAX
*
rpa2
A3 0 1 0 1 A2 A1 A0
Data
Note 1
Note 1
Note 3
7/13
Note 3
7/13
(rpa2) ← A
A ← (rpa2)
EXX
00010001
4
B', C ↔ C', D ↔ D'
{BE ↔
↔ E', H ↔ H', L ↔ L'
EXA
00010000
4
V, A ↔ V', A', EA ↔ EA'
EXH
01010000
4
H, L ↔ H', L'
BLOCK
00110001
13
(C+1)
(DE)+ ← (HL)+, C ← C–1
End if borrow
rp3, EA
1 0 1 1 0 1 P1 P0
4
rp3L ← EAL, rp3H ← EAH
EA, rp3
1 0 1 0 0 1 P1 P0
4
EAL ← rp3L, EAH ← rp3H
DMOV
µPD78C14(A)
16-bit data
transfer
8-bit data transfer
MVI
Instruction group
Instruction code
Mnemonic
State
Operand
B1
sr3, EA
01001000
B2
B3
Operation
B4
1 1 0 1 0 0 1 U0
14
sr3 ← EA
1 1 0 0 0 0 0 V0
14
EA ← sr4
20
(word) ← C, (word+1) ← B
Skip
condition
DMOV
16-bit data transfer
EA, sr4
SBCD
word
SDED
word
00101110
20
(word) ← E, (word+1) ← D
SHLD
word
00111110
20
(word) ← L, (word+1) ← H
SSPD
word
00001110
20
(word) ← SPL, (word+1) ← SPH
STEAX
rpa3
01001000
1 0 0 1 C3 C2 C1 C0
Data
LBCD
word
01110000
00011111
Low Adrs
LDED
word
LHLD
00011110
Low Adrs
High Adrs
Note 3
Note 2
14/20
(rpa3) ← EAL, (rpa3+1) ← EAH
20
C ← (word), B ← (word+1)
00101111
20
E ← (word), D ← (word+1)
word
00111111
20
L ← (word), H ← (word+1)
LSPD
word
00001111
20
SPL ← (word), SPH ← (word+1)
LDEAX
rpa3
01001000
PUSH
rp1
1 0 1 1 0 Q2 Q1 Q0
13
(SP–1)← rp1H, (SP–2)← rp1L
SP ← SP–2
POP
rp1
1 0 1 0 0 Q2 Q1 Q0
10
rp1L ← (SP), rp1H ← (SP+1)
SP ← SP+2
rp2, word
0 P2 P1 P0 0 1 0 0
10
rp2 ← word
LXI
*
1 0 0 0 C3 C2 C1 C0
Low Byte
Note 2
Data
High Byte
High Adrs
Note 3
14/20
EAL ← (rpa3), EAH ← (rpa3+1)
10101000
17
C ← (PC+3+A)
B ← (PC+3+A+1)
01100000
1 1 0 0 0 R2 R1 R0
8
A ← A+r
r, A
0100
8
r ← r+A
A, r
1101
8
A ← A+r+CY
r, A
0101
8
r ← r+A+CY
A, r
ADD
ADC
19
µPD78C14(A)
01001000
TABLE
8-bit arithmetic
operation (register)
01110000
Instruction group
20
Instruction code
Mnemonic
State
Operand
B1
B2
B3
Operation
B4
Skip
condition
1 0 1 0 0 R2 R1 R0
8
A ← A+r
No
Carry
r, A
0010
8
r ← r+A
No
Carry
A, r
1110
8
A ← A–r
r, A
0110
8
r ← r–A
A, r
1111
8
A ← A–r–CY
r, A
0111
8
r ← r–A–CY
A, r
1011
8
A ← A–r
No
Borrow
r, A
0011
8
r ← r–A
No
Borrow
A, r
1 0 0 0 1 R2 R1 R0
8
A←A r
r, A
0000
8
r←r A
A, r
1001
8
A←A r
r, A
0001
8
r←r A
A, r
1 0 0 1 0 R2 R1 R0
8
A←A r
r, A
0001
8
r←r A
A, r
1 0 1 0 1 R2 R1 R0
8
A–r–1
r, A
0010
8
r–A–1
A, r
1011
8
A–r
Borrow
r, A
0011
8
r–A
Borrow
A, r
1110
8
A–r
No Zero
r, A
0110
8
r–A
No Zero
A, r
01100000
ADDNC
SUB
SBB
<
ANA
<
>
ORA
>
XRA
>
8-bit arithmetic operation (register)
SUBNB
>
GTA
No
Borrow
No
Borrow
LTA
µPD78C14(A)
NEA
Instruction group
B1
B2
B3
Operation
B4
Skip
condition
8
A–r
Zero
r, A
0111
8
r–A
Zero
ONA
A, r
1100
8
A r
No Zero
OFFA
A, r
1101
8
A r
Zero
ADDX
rpa
1 1 0 0 0 A2 A1 A0
11
A ← A+(rpa)
ADCX
rpa
1101
11
A ← A+(rpa)+CY
ADDNCX
rpa
1010
11
A ← A+(rpa)
SUBX
rpa
1110
11
A ← A–(rpa)
SBBX
rpa
1111
11
A ← A–(rpa)–CY
SUBNBX
rpa
1011
11
A ← A–(rpa)
ANAX
rpa
1 0 0 0 1 A2 A1 A0
11
A ← A (rpa)
ORAX
rpa
1001
11
A ← A (rpa)
XRAX
rpa
1 0 0 1 0 A2 A1 A0
11
A ← A (rpa)
GTAX
rpa
1 0 1 0 1 A2 A1 A0
11
A–(rpa)–1
No
Borrow
LTAX
rpa
1011
11
A–(rpa)
Borrow
NEAX
rpa
1110
11
A–(rpa)
No Zero
EQAX
rpa
1111
11
A–(rpa)
Zero
ONAX
rpa
1100
11
A (rpa)
No Zero
OFFAX
rpa
1101
11
A (rpa)
Zero
01100000
EQA
01110000
No
Carry
No
Borrow
<
>
>
<
µPD78C14(A)
<
21
1 1 1 1 1 R2 R1 R0
A, r
<
8-bit arithmetic
operation (register)
State
Operand
<
8-bit arithmetic operation (memory)
Instruction code
Mnemonic
Instruction group
22
Instruction code
Mnemonic
B1
*
ADI
*
ACI
*
Arithmetic operation of immediate data
State
Operand
ADINC
*
SUI
*
SBI
*
SUINB
r, byte
01110100
0 1 0 0 0 R2 R1 R0
sr2, byte
0110
S3 1 0 0 0 S2 S1 S0
A, byte
01010110
r, byte
01110100
0 1 0 1 0 R2 R1 R0
sr2, byte
0110
S3 1 0 1 0 S2 S1 S0
A, byte
00100110
r, byte
01110100
0 0 1 0 0 R2 R1 R0
sr2, byte
0110
S3 0 1 0 0 S2 S1 S0
A, byte
01100110
r, byte
01110100
0 1 1 0 0 R2 R1 R0
sr2, byte
0110
S3 1 1 0 0 S2 S1 S0
A, byte
01110110
r, byte
01110100
0 1 1 1 0 R2 R1 R0
sr2, byte
0110
S3 1 1 1 0 S2 S1 S0
A, byte
00110110
r, byte
01110100
0 0 1 1 0 R2 R1 R0
sr2, byte
0110
S3 0 1 1 0 S2 S1 S0
A, byte
00000111
r, byte
01110100
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
0 0 0 0 1 R2 R1 R0
Data
Skip
condition
7
A ← A+byte
11
r ← r+byte
20
sr2 ← sr2+byte
7
A ← A+byte+CY
11
r ← r+byte+CY
20
sr2 ← sr2+byte+CY
7
A ← A+byte
No
Carry
11
r ← r+byte
No
Carry
20
sr2 ← sr2+byte
No
Carry
7
A ← A–byte
11
r ← r–byte
20
sr2 ← sr2–byte
7
A ← A–byte–CY
11
r ← r–byte–CY
20
sr2 ← sr2–byte–CY
7
A ← A–byte
No
Borrow
11
r ← r–byte
No
Borrow
20
sr2 ← sr2–byte
No
Borrow
7
A← A
11
r←r
<
01000110
Operation
B4
byte
byte
µPD78C14(A)
*
A, byte
B3
<
ANI
B2
Instruction group
Instruction code
Mnemonic
B1
*
LTI
*
NEI
EQI
23
0 0 0 1 1 R2 R1 R0
sr2, byte
0110
S3 0 0 1 1 S2 S1 S0
A, byte
00010110
r, byte
01110100
0 0 0 1 0 R2 R1 R0
sr2, byte
0110
S3 0 0 1 0 S2 S1 S0
A, byte
00100111
r, byte
01110100
0 0 1 0 1 R2 R1 R0
sr2, byte
0110
S3 0 1 0 1 S2 S1 S0
A, byte
00110111
r, byte
01110100
0 0 1 1 1 R2 R1 R0
sr2, byte
0110
S3 0 1 1 1 S2 S1 S0
A, byte
01100111
r, byte
01110100
0 1 1 0 1 R2 R1 R0
sr2, byte
0110
S3 1 1 0 1 S2 S1 S0
A, byte
01110111
r, byte
01110100
0 1 1 1 1 R2 R1 R0
sr2, byte
0110
S3 1 1 1 1 S2 S1 S0
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
7
A ← A byte
11
r ← r byte
20
sr2 ← sr2 byte
7
A ← A byte
11
r ← r byte
20
sr2 ← sr2 byte
7
A–byte–1
No
Borrow
11
r–byte–1
No
Borrow
14
sr2–byte–1
No
Borrow
7
A–byte
Borrow
11
r–byte
Borrow
14
sr2–byte
Borrow
7
A–byte
No
Zero
11
r–byte
No
Zero
14
sr2–byte
No
Zero
7
A–byte
Zero
11
r–byte
Zero
14
sr2–byte
Zero
µPD78C14(A)
*
01110100
sr2 ← sr2 byte
<
GTI
r, byte
Data
20
<
*
00010111
Data
<
XRI
A, byte
S3 0 0 0 1 S2 S1 S0
<
*
01100100
B4
<
ORI
sr2, byte
B3
Skip
condition
<
*
B2
Operation
<
ANI
Arithmetic operation of immediate data
State
Operand
Instruction group
24
Instruction code
Mnemonic
B1
B3
Operation
B4
Skip
condition
7
A byte
No
Zero
11
r byte
<
No
Zero
14
sr2 byte
<
No
Zero
7
A byte
Zero
11
r byte
<
Zero
14
sr2 byte
Zero
14
A ← A+(V.wa)
1101
14
A ← A+(V.wa)+CY
wa
1010
14
A ← A+(V.wa)
SUBW
wa
1110
14
A ← A–(V.wa)
SBBW
wa
1111
14
A ← A–(V.wa)–CY
SUBNBW
wa
1011
14
A ← A–(V.wa)
ANAW
wa
10001000
14
A ← A (V.wa)
ORAW
wa
1001
14
A ← A (V.wa)
XRAW
wa
10010000
14
A ← A (V.wa)
GTAW
wa
10101000
14
A–(V.wa)–1
No
Borrow
LTAW
wa
1011
14
A–(V.wa)
Borrow
NEAW
wa
1110
14
A–(V.wa)
No
Zero
EQAW
wa
1111
14
A–(V.wa)
Zero
ONAW
wa
1100
14
A (V.wa)
No
Zero
01110100
0 1 0 0 1 R2 R1 R0
sr2, byte
0110
S3 1 0 0 1 S2 S1 S0
A, byte
01010111
r, byte
01110100
0 1 0 1 1 R2 R1 R0
sr2, byte
0110
S3 1 0 1 1 S2 S1 S0
ADDW
wa
01110100
11000000
ADCW
wa
ADDNCW
*
OFFI
Data
Data
Data
offset
<
r, byte
ONI
Data
<
01000111
<
Arithmetic operation of
immediate data
B2
A, byte
*
No
Carry
No
Borrow
<
>
>
Arithmetic operation of working register
State
Operand
µPD78C14(A)
<
Instruction group
Instruction code
Mnemonic
B1
01110100
11011000
B3
Operation
B4
Skip
condition
Zero
Offset
14
A (V.wa)
Data
19
(V.wa) ← (V.wa) byte
*
wa, byte
00000101
ORIW
*
wa, byte
0001
19
(V.wa) ← (V.wa) byte
GTIW
*
wa, byte
0010
13
(V.wa)–byte–1
No
Borrow
LTIW
*
wa, byte
0011
13
(V.wa)–byte
Borrow
NEIW
*
wa, byte
0110
13
(V.wa)–byte
No Zero
EQIW
*
wa, byte
0111
13
(V.wa)–byte
Zero
ONIW
*
wa, byte
0100
13
(V.wa) byte
No Zero
OFFIW
*
wa, byte
0101
13
(V.wa) byte
Zero
EADD
EA, r2
01110000
0 1 0 0 0 0 R1 R0
11
EA ← EA+r2
DADD
EA, rp3
0100
1 1 0 0 0 1 P1 P0
11
EA ← EA+rp3
DADC
EA, rp3
1101
11
EA ← EA+rp3+CY
DADDNC
EA, rp3
1010
11
EA ← EA+rp3
ESUB
EA, r2
0000
0 1 1 0 0 0 R1 R0
11
EA ← EA–r2
DSUB
EA, rp3
0100
1 1 1 0 0 1 P1 P0
11
EA ← EA–rp3
DSBB
EA, rp3
1111
11
EA ← EA–rp3–CY
DSUBNB
EA, rp3
1011
11
EA ← EA–rp3
DAN
EA, rp3
1 0 0 0 1 1 P1 P0
11
EA ← EA rp3
DOR
EA, rp3
1001
11
EA ← EA rp3
DXR
EA, rp3
1 0 0 1 0 1 P1 P0
11
EA ← EA rp3
Offset
<
ANIW
>
<
Arithmetic operation of working register
wa
B2
<
OFFAW
<
No
Carry
No
Borrow
<
>
<
25
µPD78C14(A)
16-bit arithmetic operation
State
Operand
Instruction group
16-bit arithmetic operation
B3
Operation
B4
Skip
condition
1 0 1 0 1 1 P1 P0
11
EA–rp3–1
No
Borrow
EA, rp3
1011
11
EA–rp3
Borrow
DNE
EA, rp3
1110
11
EA–rp3
No Zero
DEQ
EA, rp3
1111
11
EA–rp3
Zero
DON
EA, rp3
1100
11
EA rp3
No Zero
DOFF
EA, rp3
1101
11
EA rp3
Zero
MUL
r2
0 0 1 0 1 1 R1 R0
32
EA ← A×r2
DIV
r2
0011
59
EA ← EA÷r2, r2 ← The Remainder
INR
r2
0 1 0 0 0 0 R1 R0
4
r2 ← r2+1
Carry
wa
00100000
16
(V.wa) ← (V.wa)+1
Carry
rp
0 0 P1 P0 0 0 1 0
7
rp ← rp+1
EA
10101000
7
EA ← EA+1
r2
0 1 0 1 0 0 R1 R0
4
r2 ← r2–1
Borrow
wa
00110000
16
(V.wa) ← (V.wa)–1
Borrow
rp
0 0 P1 P0 0 0 1 1
7
rp ← rp–1
EA
10101001
7
EA ← EA–1
DAA
01100001
4
Decimal Adjust Accumulator
STC
01001000
00101011
8
CY ← 1
CLC
00101010
8
CY ← 0
NEGA
00111010
8
A ← A+1
DGT
EA, rp3
DLT
*
01110100
01001000
Offset
<
Multiply/
divide
B2
<
Decrement/Increment
State
Operand
B1
INRW
INX
DCR
DCRW
*
Offset
DCX
µPD78C14(A)
Other arithmetic
operation
26
Instruction code
Mnemonic
Instruction group
Instruction code
Mnemonic
State
Operand
B1
01001000
RLD
B2
17
Rotate Left Digit
1001
17
Rotate Right Digit
Rotation shift
Skip
condition
r2
0 1 R1 R0
8
r2m+1 ← r2m, r20 ← CY, CY ← r27
RLR
r2
0 0 R1 R0
8
r2m—1 ← r2m, r27 ← CY, CY ← r20
SLL
r2
0 0 1 0 0 1 R1 R0
8
r2m+1 ← r2m, r20 ← 0, CY ← r27
SLR
r2
0 0 R1 R0
8
r2m—1 ← r2m, r27 ← 0, CY ← r20
SLLC
r2
0 0 0 0 0 1 R1 R0
8
r2m+1 ← r2m, r20 ← 0, CY ← r27
Carry
SLRC
r2
0 0 R1 R0
8
r2m—1 ← r2m, r27 ← 0, CY ← r20
Carry
DRLL
EA
10110100
8
EAn+1 ← EAn, EA0 ← CY, CY ← EA15
DRLR
EA
0000
8
EAn—1 ← EAn, EA15 ← CY, CY ← EA0
DSLL
EA
10100100
8
EAn+1 ← EAn, EA0 ← 0, CY ← EA15
DSLR
EA
0000
8
EAn—1 ← EAn, EA15 ← 0, CY ← EA0
10
PC ← word
00100001
4
PCH ← B, PCL ← C
word
11
10
PC ← PC+1+jdisp 1
word
0100111
10
PC ← PC+2+jdisp
8
PC ← EA
16
(SP–1) ← (PC+3)H, (SP–2) ← (PC+3)L
PC ← word, SP ← SP–2
17
(SP–1) ← (PC+2)H, (SP–2)← (PC+2)L
PCH ← B, PCL ← C, SP ← SP–2
13
(SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L
PC15–11 ← 00001, PC10–0 ← fa, SP ← SP–2
*
word
JB
JR
JRE
*
JEA
CALL
*
word
CALB
CALF
*
word
01010100
Low Adrs
High Adrs
jdisp 1
jdisp
01001000
00101000
01000000
Low Adrs
01001000
00101001
01111
fa
High Adrs
27
µPD78C14(A)
RLL
JMP
Jump
Operation
B4
00111000
RRD
Call
B3
Return
Call
Instruction group
28
Instruction code
Mnemonic
B1
B3
Operation
B4
Skip
condition
16
(SP–1) ← (PC+1)H, (SP– 2) ← (PC+1)L, PCL
← (128+2ta), PCH ← (129+2ta), SP ← SP–2
SOFT1
01110010
16
(SP–1) ← PSW, (SP–2) ← (PC+1)H, (SP–3)
← (PC+1)L, PC ← 0060H, SP ← SP–3
RET
10111000
10
PCL ← (SP), PCH ← (SP+1)
SP ← SP+2
1001
10
PCL ← (SP), PCH ← (SP+1), SP ← SP+2
PC ← PC+n
01100010
13
PCL ← (SP), PCH ← (SP+1)
PSW← (SP+2), SP ← SP+3
10
Skip if (V.wa) bit = 1
(V.wa)
bit = 1
0 0 0 0 1 F2 F1 F0
8
Skip if f = 1
f=1
RETS
100
Unconditional
bit, wa
0 1 0 1 1 B2 B1 B0
SK
f
01001000
SKN
f
0001
8
Skip if f = 0
f=0
SKIT
irf
0 1 0 I4 I3 I2 I1 I0
8
Skip if irf = 1, then reset irf
irf = 1
SKNIT
irf
0 1 1 I4 I3 I2 I1 I0
8
Skip if irf = 0
Reset irf, if irf = 1
irf = 0
BIT
Skip
B2
ta
word
CALT
RETI
CPU operation
State
Operand
*
Offset
NOP
00000000
4
No Operation
EI
10101010
4
Enable Interrupt
DI
10111010
4
Disable Interrupt
HLT
01001000
00111011
12
Set Halt Mode
STOP
01001000
10111011
12
Set Stop Mode
Notes 1. B2 (Data) is applied for rpa2 = D + byte or H + byte.
2. B3 (Data) is applied for rpa3 = D + byte or H + byte.
3. In the "state" column, data to the right of the slash applies when rpa2 or rpa3 is D + byte, H + A, H + B, H + EA, or H + byte.
µPD78C14(A)
Remark When the instructions below are skipped, the number of idle states is as listed below and differs from the number of execution states.
3-byte instruction (with *) : 10-state
1-byte instruction : 4-state
: 11-state
3-byte
: 7-state
2-byte (with *)
: 14-state
4-byte
: 8-state
2-byte
µPD78C14(A)
4. LIST OF MODE REGISTERS
Name of mode register
Read/Write
Function
MA
MODE A
W
Specifies input/output of Port A in bit units
MB
MODE B
W
Specifies input/output of Port B in bit units
MCC
MODE CONTROL C
W
Specifies port/control mode of Port C in bit units
MC
MODE C
W
Specifies input/output of Port C set in the port mode in bit units
MM
MEMORY MAPPING
W
Specifies port/expansion mode of Ports D and F
MF
MODE F
W
Specifies input/output of Port F set in the port mode in bit units
TMM
Timer mode
R/W
Specifies operation mode of the timer
ETMM
Timer/Event
W
Specifies operation mode of the Timer Event Counter
R/W
Controls output level of CO0 and CO1
W
Specifies operation mode of the serial interface
Counter Mode
EOM
Timer/Event
Counter Output Mode
SML
Serial Mode
SMH
MKL
R/W
Interrupt Mask
R/W
Specifies interrupt request enable/disable
ANM
A/D Channel Mode
R/W
Specifies operation mode of the A/D converter
ZCM
Zero-cross Mode
W
Specifies operation mode of the zero-cross detection circuit
MKH
29
µPD78C14(A)
5. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
Parameter
Symbol
Power Supply Voltage
Input Voltage
Ratings
Unit
VDD
–0.5 to +7.0
V
AVDD
AVSS to VDD + 0.5
V
AVSS
–0.5 to +0.5
V
VI
–0.5 to VDD + 0.5
V
Output Voltage
VO
Output Current Low
IOL
Output Current High
IOH
A/D Converter
VAREF
Test Condition
–0.5 to VDD + 0.5
V
All Output Pin
4.0
mA
All Output Pin Total
100
mA
All Output Pin
–2.0
mA
All Output Pin Total
–50
mA
–0.5 to AVDD + 0.3
V
TA
–40 to +85
˚C
Tstg
–65 to +150
˚C
Reference Input Voltage
Operating Ambient
Temperature
Storage Temperature
*
Caution
If any of the parameters exceeds the absolute maximum ratings even for a moment, this may damage
product quality. The absolute maximum ratings are values that may physically damage the product. You
must use the product within the specified ratings.
30
µPD78C14(A)
Oscillation Characteristics (TA = –40 to +85 ˚C, VDD = AVDD = +5.0 V ± 10 %, VSS = AVSS = 0 V,
VDD – 0.8 V ≤ AVDD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD)
Resonator
Recommended Circuits
Ceramic
Parameter
Test Conditions
Oscillation Frequency (fxx) A/D Converter
Resonator
MIN.
MAX.
UNIT
4
15
MHz
5.8
15
MHz
4
15
MHz
5.8
15
MHz
0
20
ns
20
250
ns
Not used
or
X1
X2
Crystal
ResonatorNote
A/D Converter
C1
Used
C2
External
X1 Input Frequency
A/D Converter
Clock
(fx)
Not used
X1
X2
A/D Converter
Used
X1 Input
Rise, Fall Time (tr, tf)
HCMOS
Inverter
X1 Input High, Low
Level Width (tøH, tøL)
Cautions
1. Oscillator circuit should be in the nearest area from X1 and X2 pins.
2. Do not place other signal lines within the area enclosed with broken lines.
Note For a crystal resonator, the following external capacitances are recommended: C1 = C2 = 10 pF
CAPACITANCE (TA = 25 ˚C, VDD = VSS = 0 V)
Parameter
Symbol
Test Condition
MIN.
TYP.
MAX.
UNIT
Input Capacitance
CI
fC = 1 MHz
10
pF
Output Capacitance
CO
Unmeasured pins returned to 0 V
20
pF
I/O Capacitance
CIO
20
pF
31
µPD78C14(A)
DC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = AVDD = +5.0 V ± 10 %, VSS = AVSS = 0 V)
Parameter
Symbol
Test Condition
MIN.
Input Low Voltage
VIL1
All except RESET, STOP, NMI, SCK, INT1,
0
TYP.
MAX.
UNIT
0.8
V
TI, AN7 to AN4
Input High Voltage
VIL2
RESET, STOP, NMI, SCK, INT1, TI, AN7 to AN4 0
0.2VDD
V
VIH1
All except RESET, STOP, NMI, SCK, INT1,
2.2
VDD
V
0.8VDD
VDD
V
0.45
V
TI, AN7 to AN4, X1, X2
VIH2
RESET, STOP, NMI, SCK, INT1, TI, AN7 to
AN4, X1, X2
Output Low Voltage
VOL
Output High Voltage VOH
IOL = 2.0 mA
IOH = –1.0 mA
VDD – 1.0
V
IOH = –100 µA
VDD – 0.5
V
Input Current
II
INT1
±200
µA
Input Leakage
ILI
All except INT1, TI (PC3), AN7 to AN0; 0 V ≤ VI ≤ VDD
±10
µA
Note 1
, TI (PC3)
; 0 V ≤ VI ≤ VDD
Note 2
AN7 to AN0; 0 V ≤ VI ≤ VDD
±1
µA
ILO
0 V ≤ VO ≤ VDD
±10
µA
AIDD1
Operation Mode fxx = 15 MHz
0.5
1.3
mA
Current
AIDD2
STOP Mode
10
20
µA
VDD Supply Current
IDD1
Operation mode fxx = 15 MHz
16
30
mA
IDD2
HALT Mode fxx = 15 MHz
8
15
mA
VDDDR
Hardware/Software STOP Mode
IDDDR
Hardware/Software Note 3
VDDDR = 2.5 V
1
15
µA
STOP Mode
VDDDR = 5 V ± 10 %
10
50
µA
Current
Output Leakage
Current
AVDD Supply
Data Retention
2.5
V
Voltage
Data Retention
Current
Notes 1.
32
When self-bias is generated by ZCM register.
2.
When set in the control mode by MCC register and self-bias is generated by ZCM register.
3.
When self-bias is not generated.
µPD78C14(A)
AC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = AVDD = +5.0 V ± 10 %, VSS = AVSS = 0 V)
READ/WRITE OPERATION:
Parameter
Symbol
X1 Input Cycle Time
tCYC
Address Setup Time to ALE
tAL
Test Condition
fxx = 15 MHz, CL = 150 pF
MIN.
MAX.
UNIT
66
250
ns
30
ns
Address Hold Time after ALE ↓
tLA
35
ns
Address → RD ↓ Delay Time
tAR
100
ns
RD ↓ → Address Floating Time
tAFR
CL = 150 pF
20
ns
Address → Data Input Time
tAD
fxx = 15 MHz, CL = 150 pF
250
ns
ALE ↓ → Data Input Time
tLDR
135
ns
RD ↓ → Data Input Time
tRD
120
ns
ALE ↓ → RD ↓ Delay Time
tLR
15
ns
Data Hold Time after RD ↑
tRDH
CL = 150 pF
0
ns
RD ↑ → ALE ↑ Delay Time
tRL
fxx = 15 MHz, CL = 150 pF
80
ns
RD Width Low
tRR
Data Read
215
ns
415
ns
90
ns
fxx = 15 MHz, CL = 150 pF
OP code Fetch
fxx = 15 MHz, CL = 150 pF
ALE Width High
tLL
fxx = 15 MHz, CL = 150 pF
M1 Setup Time to ALE ↓
tML
fxx = 15 MHz
30
ns
M1 Hold Time after ALE ↓
tLM
35
ns
IO/M Setup Time to ALE ↓
tIL
30
ns
IO/M Hold Time after ALE ↓
tLI
35
ns
Address → WR ↓ Delay Time
tAW
ALE ↓ → Data Output Time
tLDW
WR ↓ → Data Output Time
tWD
CL = 150 pF
ALE ↓ → WR ↓ Delay Time
tLW
fxx = 15 MHz, CL = 150 pF
Data Setup Time to WR ↑
Data Hold Time after WR ↑
fxx = 15 MHz, CL = 150 pF
100
ns
180
ns
100
ns
15
ns
tDW
165
ns
tWDH
60
ns
WR ↑ → ALE ↑ Delay Time
tWL
80
ns
WR Width Low
tWW
215
ns
33
µPD78C14(A)
SERIAL OPERATION:
Parameter
Symbol
Test Condition
SCK Cycle Time
tCYK
SCK Input
MIN.
SCK Input
tKKL
800
ns
Note 2
400
ns
1.6
µs
Note 1
335
ns
Note 2
160
ns
700
ns
Note 1
335
ns
Note 2
160
ns
SCK Output
SCK Width High
SCK Input
tKKH
UNIT
Note 1
SCK Output
SCK Width Low
MAX.
SCK Output
700
ns
RxD Setup Time to SCK ↑
tRXK
Note 1
80
ns
RxD Hold Time After SCK ↑
tKRX
Note 1
80
SCK ↓ → TxD Delay Time
tKTX
Note 1
Notes 1.
2.
ns
210
ns
In case of x1 clock rate in asynchronous mode, synchronous mode, or I/O interface mode.
In case of x16 or x64 clock rate in asynchronous mode.
Remark The numeric values in the table apply when fXX = 15 MHz, CL = 150 pF.
ZERO-CROSS CHARACTERISTICS:
Parameter
Symbol
Test Condition
MIN.
MAX.
UNIT
Zero-Cross Detection Input
VZX
AC Coupled
1
1.8
VACP–P
Zero-Cross Accuracy
AZX
60-Hz Sine Wave
±135
mV
Zero-Cross Detection Input Frequency
fZX
1
kHz
0.05
OTHER OPERATION:
Parameter
Symbol
Test Condition
MIN.
MAX.
UNIT
TI Width High, Low
tTIH, tTIL
6
tCYC
CI Width High, Low
tCI1H, tCI1L
Event Counter Mode
6
tCYC
tCI2H, tCI2L
Pulse Width Measurement Mode
48
tCYC
NMI Width High, Low
tNIH, tNIL
10
µs
INT1 Width High, Low
tI1H, tI1L
36
tCYC
INT2 Width High, Low
tI2H, tI2L
36
tCYC
AN7-4 Width High, Low
tANH, tANL
36
tCYC
RESET Width High, Low
tRSH, tRSL
10
µs
34
µPD78C14(A)
A/D CONVERTER CHARACTERISTICS: (TA = –40 to +85 ˚C, VDD = +5.0 V ± 10 %, VSS = AVSS = 0 V,
VDD – 0.5 V ≤ AVDD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD)
Parameter
Symbol
Test Condition
MIN.
Resolution
TYP.
MAX.
8
Absolute Accuracy
Note
UNIT
Bits
3.4 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns
±0.8 %
FSR
4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns
±0.6 %
FSR
TA = –10 to +70 ˚C,
±0.4 %
FSR
4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns
Conversion time
Sampling Time
Analog Input Voltage
tCONV
tSAMP
VIAN
66 ns ≤ tCYC ≤ 110 ns
576
tCYC
110 ns ≤ tCYC ≤ 170 ns
432
tCYC
66 ns ≤ tCYC ≤ 110 ns
96
tCYC
110 ns ≤ tCYC ≤ 170 ns
72
tCYC
AN7-0 (include unused pins)
0
Analog Input Impedance RAN
Reference Voltage
VAREF
VAREF Current
IAREF1
Operation mode
IAREF2
AIDD1
AIDD2
AVDD Supply Current
VAREF
50
3.4
V
MΩ
AVDD
V
1.5
3.0
mA
STOP mode
0.7
1.5
mA
Operation mode, fxx = 15 MHz
0.5
1.3
mA
STOP mode
10
20
µA
Note Except quantization error (i.e. ±1/2 LSB).
AC TIMING TEST POINTS
VDD – 1.0 V
0.45 V
2.2 V
0.8 V
Test points
2.2 V
0.8 V
35
*
µPD78C14(A)
AC CHARACTERISTIC CALCULATING EXPRESSION depending on tCYC
Symbol
Calculating Expression
MIN./MAX.
UNIT
tAL
2T – 100
MIN.
ns
tLA
T – 30
MIN.
ns
tAR
3T – 100
MIN.
ns
tAD
7T – 220
MAX.
ns
tLDR
5T – 200
MAX.
ns
tRD
4T – 150
MAX.
ns
tLR
T – 50
MIN.
ns
tRL
2T – 50
MIN.
ns
tRR
4T – 50 (Data Read)
MIN.
ns
7T – 50 (OP Code Fetch)
tLL
2T – 40
MIN.
ns
tML
2T – 100
MIN.
ns
tLM
T – 30
MIN.
ns
tIL
2T – 100
MIN.
ns
tLI
T – 30
MIN.
ns
tAW
3T – 100
MIN.
ns
tLDW
T + 110
MAX.
ns
tLW
T – 50
MIN.
ns
tDW
4T – 100
MIN.
ns
tWDH
2T – 70
MIN.
ns
tWL
2T – 50
MIN.
ns
tWW
4T – 50
MIN.
ns
MIN.
ns
MIN.
ns
MIN.
ns
6T (SCK Input)
tCYK
Note 1
/12T (SCK Input)
Note 2
24T (SCK Output)
2.5T + 5 (SCK Input) Note 1 /5T + 5 (SCK Input) Note 2
tKKL
12T – 100 (SCK Output)
2.5T + 5 (SCK Input) Note 1 /5T + 5 (SCK Input) Note 2
tKKH
12T – 100 (SCK Output)
Notes 1.
2.
Remarks
36
In case of x16 or x64 clock rate in asynchronous mode.
In case of x1 clock rate in asynchronous mode, synchronous mode, or I/O interface mode.
1.
T = tCYC = 1/fxx
2.
Symbols that cannot be found in this table do not depend on the oscillation frequency (fxx).
µPD78C14(A)
Timing Waveform
Read Operation
tCYC
X1
address (high-order)
PF7-0
tAD
PD7-0
address (low-order)
tLL
read data
tLDR
tLA
tRDH
tRL
tAFR
ALE
tAL
tRD
tRR
RD
tLR
tAR
MODE1
Note 1
(M1)
tML
tLM
tIL
tLI
MODE0
(IO/M) Note 2
Write Operation
X1
PF7-0
address (high-order)
tLDW
PD7-0
write data
address (low-order)
tLL
tDW
tLA
tWDH
tWD
ALE
tWW
tAL
tWL
WR
tLW
tAW
tIL
tLI
MODE0
(IO/M) Note 3
Notes 1. M1 signal is output to MODE1 pin at first OP code fetch cycle if MODE1 pin is pulled up.
2. IO/M signal is output to MODE0 pin at sr to sr2 register read cycle if MODE0 pin is pulled up.
3. IO/M signal is output to MODE0 pin at sr to sr2 register write cycle if MODE0 pin is pulled up.
37
µPD78C14(A)
Serial Operation
tCYK
tKKL
tKKH
SCK
tKTX
TXD
RXD
tRXK
tKRX
Timer Input Timing
tTIH
tTIL
TI
Timer/Event Counter Input Timing
Event Counter Mode
tCI1H
tCI1L
tCI2H
tCI2L
CI
Pulse Width Measurement Mode
CI
38
µPD78C14(A)
Interrupt Input Timing
tNIH
tNIL
tI1L
tI1H
tI2H
tI2L
NMI
INT1
INT2
RESET Input Timing
tRSH
tRSL
0.8VDD
RESET
0.2VDD
External Clock Timing
tφH
0.8VDD
X1
0.8 V
tf
tr
tφL
tCYC
39
µPD78C14(A)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85 ˚C)
Parameter
*
Symbol
Data retention power supply voltage
VDDDR
Data retention power supply current
IDDDR
VDD rise, fall time
tRVD, tFVD
Test Condition
MIN.
TYP.
2.5
VDDDR = 2.5 V
VDDDR = 5 V ± 10 %
MAX.
UNIT
5.5
V
1
15
µA
10
50
µA
µs
200
STOP setup time to VDD
tSSTVD
12T
+ 0.5
µs
STOP hold time to VDD
tHVDST
12TNote + 0.5
µs
Note
Note T = tCYC = 1/fxx
Data Retention Timing
90 %
VDD
10 %
tFVD
tSSTVD
VDDDR
tRVD
tHVDST
VIH2
STOP
VIL2
40
µPD78C14(A)
6. CHARACTERISTIC CURVES (reference value)
IDD1, IDD2 vs VDD
(TA = 25 ˚C, f XX = 15 MHz)
30
25
VDD Supply Current IDD1 , IDD2 [mA]
IDD1 (TYP.)
20
15
10
IDD2 (TYP.)
5
0
0
5.0
5.5
Supply Voltage VDD [V]
6.0
IDD1, IDD2 vs fXX
(TA = 25 ˚C, VDD = 5 V)
30
VDD Supply Current IDD1, IDD2 [mA]
4.5
IDD1(TYP.)
20
10
IDD2(TYP.)
0
0
5
10
Oscillation Frequency fXX [MHz]
15
41
µPD78C14(A)
IOL vs VOL
(TA = 25 ˚C, VDD = 5 V)
Output Low Current IOL [mA]
2.5
TYP.
2.0
1.5
1.0
0.5
0
0
0.1
0.2
0.3
Output Low Voltage VOL [V]
0.4
0.5
IOH vs VOH
(TA = 25 ˚C, VDD = 5 V)
Output High Current IOH [mA]
– 1.5
TYP.
– 1.0
– 0.5
0
0
42
0.5
0.1
0.2
0.3
0.4
Supply Voltage – Output High Voltage VDD – V OH [V]
µPD78C14(A)
IDDDR vs VDDDR
(TA = 25 ˚C)
Data Retention Supply Current IDDDR [ µ A]
10
8
TYP.
6
4
2
0
0
2
3
4
5
Data Retention Supply Voltage VDDDR [V]
6
43
µPD78C14(A)
7. PACKAGE DRAWINGS
64 PIN PLASTIC QUIP
A
33
1
32
C
64
W
P
S
X
M
H
I
M
J
N
K
P64GQ-100-36
NOTE
Each lead centerline is located within 0.25 mm
(0.010 inch) of its true position (T.P.) at maximum material condition.
44
ITEM
MILLIMETERS
A
41.5
+0.3
–0.2
INCHES
C
16.5
0.650
H
–
0.50 +0.10
0.020 +0.004
–0.005
I
0.25
0.010
J
2.54 (T.P.)
0.100 (T.P.)
1.634+0.012
–0.008
K
1.27 (T.P.)
0.050 (T.P.)
M
1.1 +0.25
–0.15
0.043+0.011
–0.006
N
+0.10
0.25 –0.05
0.010 +0.004
–0.003
P
4.0 –
S
3.6 –
0.142 –0.005
W
–
24.13 +1.05
0.950 –
X
–
19.05 +1.05
0.750 –
+0.3
+0.1
0.157+0.013
–0.012
+0.004
+0.042
+0.042
µPD78C14(A)
64 PIN PLASTIC QFP (14×20)
A
B
33
32
64
1
20
19
detail of lead end
F
Q
5°±5°
D
C
S
51
52
G
H
I M
J
M
P
K
N
L
P64GF-100-3B8,3BE,3BR-1
NOTE
Each lead centerline is located within 0.20
mm (0.008 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
23.6 ± 0.4
0.929 ± 0.016
B
20.0 ± 0.2
0.795+0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
1.0
0.039
H
0.40 ± 0.10
0.016 +0.004
–0.005
I
0.20
0.008
J
1.0 (T.P.)
0.039 (T.P.)
K
1.8 ± 0.2
0.071–0.009
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.12
0.005
P
2.7
0.106
Q
0.1 ± 0.1
0.004 ± 0.004
S
3.0 MAX.
0.119 MAX.
+0.008
45
µPD78C14(A)
68 PIN PLASTIC QFJ (
950 mil)
A
B
C
D
F
E
H
G
U
J
68
1
I
T
Q
K
M
N
M
P
P68L-50A1-2
NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
46
ITEM
MILLIMETERS
INCHES
A
25.2 ± 0.2
0.992 ± 0.008
B
24.20
0.953
C
24.20
0.953
D
25.2 ± 0.2
0.992 ± 0.008
E
1.94 ± 0.15
0.076+0.007
–0.006
F
0.6
0.024
G
4.4 ± 0.2
0.173+0.009
–0.008
H
2.8 ± 0.2
0.110+0.009
–0.008
I
0.9 MIN.
0.035 MIN.
J
3.4
0.134
K
1.27 (T.P.)
0.050 (T.P.)
M
0.40 ± 1.0
0.016+0.004
–0.005
N
0.12
0.005
P
23.12 ± 0.20
0.910+0.009
–0.008
Q
0.15
0.006
T
R 0.8
R 0.031
U
0.20 +0.10
–0.05
0.008+0.004
–0.002
µPD78C14(A)
*
8. RECOMMENDED SOLDERING CONDITIONS
Solder the µPD78C14(A) under the recommended conditions listed below.
For details of the recommended conditions for soldering, please refer to Semiconductor Device Mounting Technology
Manual (IEI-1207).
Consult an NEC sales representative about soldering methods and soldering conditions other than listed below.
Table 8-1. Soldering Conditions for Surface Mount Type
(1) µPD78C14GF(A)-xxx-3BE: 64-pin plastic QFP (14 x 20 mm)
Soldering Method Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235 ˚C, Time: Within 30 s (at 210 ˚C or higher),
IR35-00-2
Count: Twice or less
<Attention>
(1) Perform the second reflow when the device temperature has come down
to the room temperature from the heating from the first reflow.
(2) Do not wash the soldered portion with the flux following the first reflow.
VPS
Package peak temperature: 215 ˚C, Time: Within 40 s (at 200 ˚C or higher),
VP15-00-2
Count: Twice or less
<Attention>
(1) Perform the second reflow when the device temperature has come down
to the room temperature from the heating from the first reflow.
(2) Do not wash the soldered portion with the flux following the first reflow.
Wave soldering
Soldering bath temperature: 260 ˚C or less, Time: Within 10 s,
WS60-00-1
Count: Once, Preheating temperature: 120 ˚C MAX.
(package surface temperature)
Partial heating
Pin temperature: 300 ˚C or less, Time: Within 3 s (per pin row)
—
Caution Do not use several soldering methods together (except partial heating).
(2) µPD78C14L (A)-xxx: 68-pin plastic QFJ (950 x 950 mil)
Soldering Method Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 230 ˚C, Time: Within 30 s (at 210 ˚C or higher),
Count: Once, Maximum number of days: Seven
Note
IR30-107-1
(after seven days,
prebaking at 125 ˚C is required for 10 hours)
VPS
Package peak temperature: 215 ˚C, Time: Within 40 s (at 200 ˚C or higher),
VP15-107-1
Count: Once, Maximum number of days: Seven Note (after seven days,
prebaking at 125 ˚C is required for 10 hours)
Partial heating
Note
Pin temperature: 300 ˚C or less, Time: Within 3 s (per pin row)
—
Number of storage days under the storage conditions of 25 ˚C and 65 % RH or less after the dry pack is opened.
Caution Do not use several soldering methods together (except partial heating).
47
µPD78C14(A)
Table 8-2. Soldering Conditions for Hole-Through Type
µPD78C14G(A)-xxx-36: 64-pin plastic QUIP
Soldering Method
Soldering Conditions
Wave Soldering (pin part only)
Soldering bath temperature: 260 ˚C or less, Time: Within 10 s
Partial heating
Pin temperature: 300 ˚C or less, Time: Within 3 s (per pin row)
Caution Apply wave soldering only to pins and be careful not to bring solder directly in contact with the package.
48
µPD78C14(A)
*
APPENDIX DEVELOPMENT TOOLS
The following development tools are provided for system development using the µPD78C14(A):
Language processor
87AD series
This relocatable assembler is a program which converts a program written in mnemonics
relocatable assembler
into object code that can be executed by microcontroller.
(RA87)
In addition, it contains the automatic function of symbol table generation and branch
instruction optimization processing.
Host machine
PC-9800 series
IBM PC/ATTM
Ordering code
OS
Distribution media
(product name)
MS-DOSTM
3.5-inch 2HD
µS5A13RA87
(Ver. 2.11 to Ver. 5.00A Note)
5-inch 2HD
µS5A10RA87
PC DOSTM
3.5-inch 2HC
µS7B13RA87
(Ver. 3.1)
5-inch 2HC
µS7B10RA87
PROM write tools
Hard-
PG-1500
ware
PG-1500 is a PROM programmer which enables you to program single chip microcontrollers
containing PROM by stand-alone or host machine operation by connecting an attached
board and optional programmer adapter to PG-1500. It also enables you to program typical
PROM devices of 256 Kbits to 4 Mbits.
PA-78CP14GQ
PROM programmer adapter for the µPD78CP14(A) and connected to PG-1500 for use.
Soft-
PG-1500
PG-1500 and a host machine are connected by a serial or parallel interface and PG-1500 is
ware
controller
controlled on the host machine.
Host machine
Ordering code
OS
PC-9800 series
IBM PC/AT
Distribution media
(product name)
MS-DOS
3.5-inch 2HD
µS5A13PG1500
(Ver. 2.11 to Ver. 5.00A Note)
5-inch 2HD
µS5A10PG1500
PC DOS
3.5-inch 2HD
µS7B13PG1500
(Ver. 3.1)
5-inch 2HC
µS7B10PG1500
Note Ver. 5.00/500A have task swap function. However, this function is not supported by this software.
Remark
Operations of the assembler and PG-1500 controller are guaranteed only on the host machines under the
operating systems listed above.
49
µPD78C14(A)
Debugging tools
In-circuit emulator (IE-78C11-M) is provided for µPD78C14(A) program debugging tools. The system configuration is
listed below:
Hard-
IE-78C11-M
ware
IE-78C11-M is an in-circuit emulator for the 87AD series.
IE-78C11-M can be connected to a host machine efficient debugging.
Soft-
IE-78C11-M
IE-78C11-M and a host machine are connected by RS-232-C and IE-78C11-M is controlled
ware
control program
on the host machine.
(IE controller)
Host machine
PC-9800 series
IBM PC/AT
Ordering code
OS
Distribution media
(product name)
MS-DOS
3.5-inch 2HD
µS5A13IE78C11
(Ver. 2.11 to Ver. 3.30D)
5-inch 2HD
µS5A10IE78C11
PC DOS
5-inch 2HC
µS7B10IE78C11
(Ver. 3.1)
Remark
50
Operation of IE controller is guaranteed only on the host machine under the operating systems listed above.
µPD78C14(A)
NOTES FOR CMOS DEVICES
(1)
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate
oxide and ultimately degrade the device operation. Steps must be taken to stop generation
of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Environmental control must be adequate. When it is dry, humidifier should be used. It is
recommended to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static shielding bag or
conductive material. All test and measurement tools including work bench and floor
should be grounded. The operator should be grounded using wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions need to be taken for PW
boards with semiconductor devices on it.
(2)
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is
provided to the input pins, it is possible that an internal input level may be generated due
to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or
NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up
or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor,
if it is considered to have a possibility of being an output pin. All handling related to the
unused pins must be judged device by device and related specifications governing the
devices.
(3)
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of
MOS does not define the initial operation status of the device. Immediately after the power
source is turned ON, the devices with reset function have not yet been initialized. Hence,
power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device
is not initialized until the reset signal is received. Reset operation must be executed
immediately after power-on for devices having reset function.
MS-DOS is a trademark of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
51
µPD78C14(A)
The export of this product from Japan is regulated by the Japanese government. To export this product may be
prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country.
Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
52