µPSD3200 FAMILY Flash Programmable System Device with 8032 Microcontroller Core DATA BRIEFING FEATURES SUMMARY ■ The µPSD3200 Family combines a Flash PSD architecture with an 8032 microcontroller core ■ ■ Figure 1. Packages The µPSD3200 Family of Flash PSDs features dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via USB, I2C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and one External Interrupt. As with other Flash PSD families, the µPSD3200 Family is also in-system programmable (ISP) via a JTAG ISP interface. Large 8 KByte SRAM with battery back-up option Dual bank Flash memories – 128 KByte or 256 KByte main Flash memory TQFP52 (T) – 32 KByte secondary Flash memory ■ Content Security – Block access to Flash memory ■ Programmable Decode PLD for flexible address mapping of all memories. ■ High-speed clock standard 8032 core (12-cycle) ■ USB Interface (µPSD3234A-40U6 only) ■ I2C interface for peripheral connections ■ Five Pulse Width Modulator (PWM) channels ■ Standalone Display Data Channel (DDC) ■ Six I/O ports with up to 50 I/O pins ■ 3000 gate PLD with 16 macrocells ■ Supervisor functions ■ In-System Programming (ISP) via JTAG ■ Zero-Power Technology ■ Single Supply Voltage TQFP80 (U) – 4.5 to 5.5 V – 3.0 to 3.6 V June 2002 Complete data available on Data-on-Disc CD-ROM or at www.st.com . 1/8 µPSD3200 FAMILY SUMMARY DESCRIPTION ■ Dual bank Flash memories – Concurrent operation, read from memory one while erasing and writing the other. In-Application Programming (IAP) for remote updates – One 16-bit PWM unit ■ – For use in monitor, projector, and TV applications – Large 128 KByte or 256 KByte main Flash memory for application code, operating systems, or bit maps for graphic user interfaces – Large 32 KByte secondary Flash memory divided in small sectors. Eliminate external EEPROM with software EEPROM emulation – Secondary Flash memory is large enough for sophisticated communication protocol (USB) during IAP while continuing critical system tasks ■ – Compliant with VESA standards DDC1 and DDC2B – Eliminate external DDC PROM ■ – Eliminates need for external latches and logic ■ – Eliminate external PALs, PLDs, and 74HCxx – Simple PSDsoft Express software ...Free ■ – Generates reset upon low voltage or watchdog time-out. Eliminate external supervisor device – Built-in page register breaks restrictive 8032 limit of 64 KByte address space – Reset In pin ■ – Allows efficient manufacturing, easy product testing, and Just-In-Time inventory High-speed clock standard 8032 core (12-cycle) – Two UARTs with independent baud rate, three 16-bit Timer/Counters and two External Interrupts – Eliminate sockets and pre-programmed parts – Program with FlashLINKTM cable and any PC ■ ■ I2C interface for peripheral connections – Capable of master or slave operation ■ Five Pulse Width Modulator (PWM) channels – Four 8-bit PWM units 2/8 Zero-Power Technology – Memories and PLD automatically reach standby current between input changes – Control endpoint 0 and interrupt endpoints 1 and 2 ■ Content Security – Programmable Security Bit blocks access of device programmers and readers USB Interface (µPSD3234A-40U6 only) – Supports USB 1.1 Slow Mode (1.5 Mbit/s) In-System Programming (ISP) via JTAG – Program entire chip in 10 - 25 seconds with no involvement of 8032 – 40 MHz operation at 5 V, 24 MHz at 3.3 V ■ Supervisor functions – Place individual Flash and SRAM sectors on any address boundary – Special register swaps Flash memory segments between 8032 “program” space and “data” space for efficient In-Application Programming ■ 3000 gate PLD with 16 macrocells – Create glue logic, state machines, delays, etc. Large SRAM with battery back-up option Programmable Decode PLD for flexible address mapping of all memories Six I/O ports with up to 50 I/O pins – Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, supervisor, and JTAG – 8 KByte SRAM for RTOS, high-level languages, communication buffers, and stacks ■ Standalone Display Data Channel (DDC) ■ Packages – 52-pin TQFP – 80-pin TQFP: allows access to 8032 address/ data/control signals for connecting to external peripherals µPSD3200 FAMILY Figure 2. µPSD3200 Family Functional Modules Port 3, UART, Intr, Timers,I2C Port 4 PWM and DDC Port 1, Timers and 2nd UART and ADC Port 3 Dedicated USB Pins Port 1 I2C 8051 Core 2 UARTS Interrupt 3 Timer / Counters 256 Byte SRAM 4 Channel ADC USB DDC PWM Reset Logic w/ 256 Byte & 5 Channels LVD & WDT SRAM Transceiver MCU MODULE Port 0, 2 Ext. Bus 8032 Internal Bus A0-A15 RD,PSEN WR,ALE D0-D7 Reset PSD MODULE Page Register Decode PLD 1Mb or 2Mb Main Flash 256Kb Secondary Flash 64Kb SRAM Bus Interface PSD Internal Bus JTAG ISP Port C, JTAG, PLD I/O and GPIO CPLD - 16 MACROCELLS Port A & B, PLD I/O and GPIO Port D GPIO VCC, GND, XTAL Dedicated Pins AI06619 3/8 µPSD3200 FAMILY Table 1. 80-Pin Package Pin Description Function Signal Name In/Out Basic Alternate AD7-AD0 I/O Multiplexed Address/Data bus A11-A8 I/O External Address Bus RxD2-RxD1 I/O UART Receive TxD2-TxD1 I/O UART Transmit INT1-INT0 I/O Interrupt inputs / timer gate controls T2-T0 I/O Counter inputs SDA1-SDA2 I/O I2C Bus serial data I/O / DDC interface General I/O port pins SCL1-SCL2 I/O I2C Bus clock I/O VSYNC I/O VSYNC input for DDC interface T2EX I/O Timer 2 Trigger input ADC3-ADC0 I/O ADC Channels input PWM4-PWM0 I/O 8-bit Pulse Width Modulation outputs USB-, USB+ I/O USB I/O AVREF O Reference Voltage input for ADC RD_ O Read signal, external bus WR_ O Write signal, external bus PSEN_ O PSEN signal, external bus ALE O Address Latch signal, external bus RESET_ I Active low reset input XTAL1 I Oscillator input pin for system clock XTAL2 O Oscillator output pin for system clock PA7-PA0 I/O General I/O port pins 1. 2. 3. 4. PB7-PB0 I/O General I/O port pins 1. PLD Macro-cell outputs 2. PLD inputs 3. Latched Address Out (A0-A7) PC7-PC0 I/O General I/O port pins 1. PLD Macro-cell outputs 2. PLD inputs 3. SRAM stand by voltage input (VSTBY) 4. JTAG Interface (TDI, TDO, TMS, TCK, TSTAT, TERR) 5. SRAM battery-on indicator (PC4) PD2-PD1 I/O General I/O port pin 1. PLD I/O 2. Clock input to PLD and APD 3. Chip select to PSD Module Note: PSD Port A and MCU Address/Data bus are added for 80-pin device 4/8 PLD Macro-cell outputs PLD inputs Latched Address Out (A0-A7) Peripheral I/O mode µPSD3200 FAMILY 40 ADC2 41 ADC3 42 PB7 43 PB6 44 RST-IN 45 GND 46 VREF 47 PB5 48 PB4 49 PB3 50 PB2 51 PB1 52 PB0 Figure 3. TQFP52 Connections PD1 1 39 P1.5 / ADC1 PC7 2 38 P1.4 / ADC0 PC6 3 37 P1.3 / TXD1 PC5 4 36 P1.2 / RXD1 PU 5 35 P1.1 / T2X PC4 6 34 P1.0 / T2 NC 7 33 VCC P3.3 / EXINT1 26 P3.2 / EXINT0 25 P3.1 / TXD 24 P3.0 / RXD 23 P4.0 / DDC SDA 22 P4.1 / DDC SCL 21 GND 19 27 P3.4 / T0 P4.2 / DDC VSYNC 20 28 P3.5 / T1 PC0 13 P4.3 / PWM0 18 29 P3.6 / SDA1 PC1 12 P4.4 / PWM1 17 30 P3.7 / SCL1 PC2 11 P4.5 / PWM2 16 31 XTAL1 PC3 10 P4.6 / PWM3 15 32 XTAL2 GND 9 P4.7 / PWM4 14 VCC 8 AI05790B Note: NC = Not Connected PU = Pull-up resistor required (2kΩ for 3V devices, 7.5kΩ for 5V devices) 5/8 µPSD3200 FAMILY 61 P1.6 / ADC2 62 WR, CNTL0 63 PSEN, CNTL2 64 P1.7 / ADC3 65 RD, CNTL1 66 PB7 67 PB6 68 RESET-IN 69 GND 70 VREF 71 NC 72 PB5 73 PB4 74 PB3 75 P3.0 / RXD 76 PB2 77 P3.1 / TXD 78 PB1 79 P3.2 / EXINT0 80 PB0 Figure 4. TQFP80 Connections PD2 1 60 P1.5 / ADC1 P3.3 /EXINT1 2 59 P1.4 / ADC0 PD1 3 58 P1.3 / TXD1 PD0, ALE 4 57 P2.3, A11 PC7 5 56 P1.2 / RXD1 PC6 6 55 P2.2, A10 PC5 7 54 P1.1 / T2X USB- 8 53 P2.1, A9 PC4 9 52 P1.0 / T2 USB+ 10 51 P2.0, A8 NC 11 50 VCC V CC 12 49 XTAL2 GND 13 48 XTAL1 PC3 14 47 P0.7, AD7 PC2 15 46 P3.7 / SCL1 PC1 16 45 P0.6, AD6 NC 17 44 P3.6 / SDA1 P4.7 / PWM4 18 43 P0.5, AD5 P4.6 / PWM3 19 42 P3.5 / T1 Note: 1. NC = Not Connected 2. USB- needs a pull-up resistor (see the description of the USB function) 6/8 P3.4 / T0 40 AD3, P0.3 39 AD2, P0.2 38 AD1, P0.1 37 AD0, P0.0 36 PA0 35 PA1 34 P4.0 / DDC SDA 33 PA2 32 P4.1 / DDC SCL 31 P4.2 / DCC VSYNC 30 GND 29 PA3 28 P4.3 / PWM0 27 PA4 26 P4.4 / PWM1 25 PA5 24 P4.5 / PWM2 23 PA6 22 41 P0.4, AD4 PA7 21 PC0 20 AI05791 µPSD3200 FAMILY PART NUMBERING Table 2. Ordering Information Scheme Example: uPSD 3 2 3 4 B V – 24 U 6 T Device Type uPSD = Microcontroller PSD Family 3 = 8032 core PLD Size 2 = 16 Macrocells 3 = 32 Macrocells SRAM Size 1 = 16 Kbit 3 = 64 Kbit 5 = 256 Kbit Main Flash Memory Size 3 = 1 Mbit 4 = 2 Mbit 5 = 4 Mbit IP Mix A = USB, I2C, PWM, DDC, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) B = I2C, PWM, DDC, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) Operating Voltage blank = V CC = 4.5 to 5.5V V = VCC = 3.0 to 3.6V Speed 24 = 24 MHz 40 = 40 MHz Package T = 52-pin TQFP U = 80-pin TQFP Temperature Range 1 = 0 to 70 °C (commercial) 6 = –40 to 85 °C (industrial) Optio n T = Tape & Reel Packing For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 7/8 µPSD3200 FAMILY Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. 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