MOSEL VITELIC V436632R24V(L) 3.3 VOLT 32M x 64 LOW PROFILE UNBUFFERED SDRAM MODULE PRELIMINARY Features Description ■ 168 Pin Unbuffered 33,554,432 x 64 bit Oganization SDRAM DIMM ■ Utilizes High Performance 256 Mbit, 16M x 16 SDRAM in TSOPII-54 Packages ■ Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification ■ Single +3.3V (± 0.3V) Power Supply ■ Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) ■ Auto Refresh (CBR) and Self Refresh ■ All Inputs, Outputs are LVTTL Compatible ■ 8192 Refresh Cycles every 64 ms ■ Serial Present Detect (SPD) ■ SDRAM Performance The V436632R24V(L) memory module is organized 33,554,432 x 64 bits in a 168 pin dual in line memory module (DIMM). The 32M x 64 memory module uses 8 Mosel-Vitelic 16M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. V436632R24V(L) Rev. 1.0 October 2001 Part Number V436632R24VXTG-75L 1 Speed Grade -75, CL=3 (133 MHz) Configuration 32M x 64 V436632R24VXTG-75PCL -75PC, CL=2,3 (133 MHz) 32M x 64 V436632R24VXTG-10PCL -10PC, CL=2,3 (100 MHz) 32M x 64 MOSEL VITELIC V436632R24V(L) Pin Configurations (Front Side/Back Side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 DQM1 CS0 DU VSS A0 A2 A4 A6 A8 A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC Notes: * These pins are not used in this module. Pin Names A0–A12 Address Inputs I/O1–I/O64 Data Inputs/Outputs RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input BA0, BA1 Bank Selects CKE0, CKE1 Clock Enable CS0–CS3 Chip Select CLK0–CLK3 Clock Input DQM0–DQM7 Data Mask VCC Power (+3.3 Volts) VSS Ground SCL Clock for Presence Detect V436632R24V(L) Rev. 1.0 October 2001 2 SDA Serial Data OUT for Presence Detect SA0–A2 Serial Data IN for Presence Detect CB0–CB7 Check Bits (x72 Organization) NC No Connection DU Don’t Use MOSEL VITELIC V436632R24V(L) Part Number Information V 4 3 66 32 R 2 4 V X T G - XX MOSEL VITELIC MANUFACTURED SDRAM SPEED 75PC = PC133 CL2,3 75 = PC133 CL3 10PC = PC100 CL2 Low Profile Module LEAD FINISH G = GOLD 3.3V COMPONENT PACKAGE, T=TSOP WIDTH DEPTH COMPONENT REV LEVEL 168-pins unbuffered DIMM X16 COMPONENT LVTTL REFRESH RATE 8K 4 BANKS Block Diagram CS1 CS0 DQM0 • DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS U0 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U4 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U2 CS U6 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 • DQM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS • • • A0 ~ An, BA0 & 1 • DQM4 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS3 CS2 DQM2 • • CS U1 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS U5 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SDRAM U0 ~ U7 CAS SDRAM U0 ~ U7 WE SDRAM U0 ~ U7 CKE0 SDRAM U0 ~ U3 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U3 CS U7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Serial PD SDRAM U0 ~ U7 RAS CS VDD SCL • A1 A2 SA0 SA1 SA2 10KΩ CKE1 SDA A0 • WP 47KΩ SDRAM U4 ~ U7 10Ω DQn Every DQpin of SDRAM 10Ω CLK0/1/2/3 VDD Vss • • • • V436632R24V(L) Rev.1.0 October 2001 Two 0.1uF Capacitors per each SDRAM 15pF To all SDRAMs 3 • • (L) U0/U4/U2/U6 U1/U5/U3/U7 MOSEL VITELIC V436632R24V(L) Serial Presence Detect Information written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus) A serial presence detect storage device - is assembled onto the module. Information about the module configuration, speed, etc. is E2PROM SPD Table Byte Number Hex Value Function Described SPD Entry Value -75PC -75 -10PC 0 Number of SPD bytes 128 80 80 80 1 Total bytes in Serial PD 256 08 08 08 2 Memory Type SDRAM 04 04 04 3 Number of Row Addresses (without BS bits) 13 0D 0D 0D 4 Number of Column Addresses (for x16 SDRAM) 9 09 09 09 5 Number of DIMM Banks 2 02 02 02 6 Module Data Width 64 40 40 40 7 Module Data Width (continued) 0 00 00 00 8 Module Interface Levels LVTTL 01 01 01 9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 75 75 A0 10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns 54 54 60 11 Dimm Config (Error Det/Corr.) none 00 00 00 12 Refresh Rate/Type Self-Refresh, 7.8µs 82 82 82 13 SDRAM width, Primary x16 10 10 10 14 Error Checking SDRAM Data Width n/a / x8 00 00 00 15 Minimum Clock Delay from Back to Back Random Column Address tccd = 1 CLK 01 01 01 16 Burst Length Supported 1, 2, 4, 8 0F 0F 0F 17 Number of SDRAM Banks 4 04 04 04 18 Supported CAS Latencies CL = 3, 2 06 06 06 19 CS Latencies CS Latency = 0 01 01 01 20 WE Latencies WL = 0 01 01 01 21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00 22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E 23 Minimum Clock Cycle Time at CAS Latency = 2 7.5 ns/10.0 ns 75 A0 A0 24 Maximum Data Access Time from Clock for CL = 2 5.4 ns/6.0 ns 54 60 60 25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 00 00 26 Maximum Data Access Time from Clock at CL =1 Not Supported 00 00 00 27 Minimum Row Precharge Time 15 ns/20 ns 0F 14 14 V436632R24V(L) Rev. 1.0 October 2001 4 MOSEL VITELIC V436632R24V(L) SPD (Continued)Table Byte Number Hex Value Function Described SPD Entry Value -75PC -75 -10PC 14 ns/15 ns/16 ns 0E 0F 10 28 Minimum Row Active to Row Active Delay tRRD 29 Minimum RAS to CAS Delay tRCD 15 ns/20 ns 0F 14 14 30 Minimum RAS Pulse Width tRAS 42 ns/45 ns 2A 2D 2D 31 Module Bank Density (Per Bank) 128 MByte 20 20 20 32 SDRAM Input Setup Time 1.5 ns/2.0 ns 15 15 20 33 SDRAM Input Hold Time 0.8 ns/1.0 ns 08 08 10 34 SDRAM Data Input Setup Time 1.5 ns/2.0 ns 15 15 20 35 SDRAM Data Input Hold Time 0.8 ns/1.0 ns 08 08 10 00 00 00 02 02 12 E5 2A 98 40 40 40 00 00 00 Reserved 00 00 00 126 Intel Specification for Frequency 64 64 64 127 Supported frequency 128+ Unused Storage Location 00 00 00 62-61 Superset Information (May be used in Future) 62 SPD Revision 63 Checksum for Bytes 0 - 62 64 Manufacturer’s JEDEC ID Code 65-71 72 Manufacturing Location Module Part Number (ASCII) 91-92 PCB Identification Code 93 Assembly Manufacturing Date (Year) 94 Assembly Manufacturing Date (Week) 99-125 Mosel Vitelic Manufacturer’s JEDEC ID Code (cont.) 73-90 95-98 Revision 2/1.2 V436632R24V(L) Assembly Serial Number DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V Limit Values Symbol Parameter Min. Max. Unit VIH Input High Voltage 2.0 VCC +0.3 V V IL Input Low Voltage –0.5 0.8 V V OH Output High Voltage (IOUT = –2.0 mA) 2.4 — V V OL Output Low Voltage (IOUT = 2.0 mA) — 0.4 V V436632R24V(L) Rev.1.0 October 2001 5 MOSEL VITELIC V436632R24V(L) Limit Values Symbol Parameter Min. Max. Unit II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –40 40 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT < VCC) –40 40 µA Capacitance TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz Limit Values Symbol Parameter Max. 32M x 64 Unit CI1 Input Capacitance (A0 to A11, RAS, CAS, WE) 60 pF CI2 Input Capacitance (CS0-CS3) 30 pF CICL Input Capacitance (CLK0-CLK3) 22 pF CI3 Input Capacitance (CKE0, CKE1) 50 pF CI4 Input Capacitance (DQM0-DQM7) 15 pF CIO Input/Output Capacitance (I/O1-I/064) 15 pF CSC Input Capacitance (SCL, SA0-2) 8 pF CSD Input/Output Capacitance (SA0-SA2) 10 pF Absolute Maximum Ratings Parameter Max. Units Voltage on VDD Supply Relative to VSS -1 to 4.6 V Voltage on Input Relative to VSS -1 to 4.6 V Operating Temperature 0 to +70 °C -55 to 125 °C 6.6 W Storage Temperature Power Dissipation V436632R24V(L) Rev. 1.0 October 2001 6 MOSEL VITELIC V436632R24V(L) Operating Currents TA = 0°C to 70°C, VCC = 3.3V ± 0.3V (Recommended operating conditions otherwise noted) Max. Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3N ICC3P Parameter & Test Condition -75PC /-75 -10PC Unit Note Operating Current tRC = tRCMIN., tCK= tCKMIN. Active-precharge command cycling, without Burst Operation 1 bank operation 920 840 mA 7 Precharge Standby Current in Power Down Mode CS =VIH , CKE≤ VIL(max) tCK = min. 16 16 mA 7 tCK = Infinity 8 8 mA 7 Precharge Standby Current in Non-Power Down Mode CS =VIH , CKE≥ VIL(max) tCK = min. 180 140 mA tCK = Infinity 20 20 mA No Operating Current tCK = min, CS = VIH(min) bank ; active state ( 4 banks) CKE>= VIH(MIN.) 220 180 mA CKE <= VIL(MAX.) (Power down mode) 80 80 mA 600 480 mA 7,8 7 ICC4 Burst Operating Current tCK = min Read/Write command cycling ICC5 Auto Refresh Current tCK = min Auto Refresh command cycling 1920 1760 mA ICC6 Self Refresh Current Self Refresh Mode, CKE=<0.2V 24 24 mA 13.6 13.6 mA L-version Notes: 1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC . Input signals are changed one time during tCK. 2. These parameter depend on output loading. Specified values are obtained with output open. V436632R24V(L) Rev.1.0 October 2001 7 MOSEL VITELIC V436632R24V(L) AC Characteristics 3,4 TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns Limit Values -75PC # Symbol Parameter Min. -75 Max. Min. -10PC Max. Min. Max. Unit Note Clock and Clock Enable 1 2 3 tCK fCK tAC Clock Cycle Time CAS Latency = 3 CAS Latency = 2 7.5 7.5 System frequency CAS Latency = 3 CAS Latency = 2 – – 133 133 – – 133 100 – – 100 100 MHz MHz Clock Access Time CAS Latency = 3 CAS Latency = 2 – – 5.4 6 – – 5.4 6 – – 6 6 ns ns 7.5 10 10 10 ns ns 4,5 4 tCH Clock High Pulse Width 2.5 – 2.5 – 3 – ns 6 5 tCL Clock Low Pulse Width 2.5 – 2.5 – 3 – ns 6 6 tCS Input Setup time 1.5 – 1.5 – 2 – ns 7 7 tCH Input Hold Time 0.8 – 0.8 – 1 – ns 7 8 tCKSP CKE Setup Time (Power down mode) 2 – 2 – 2 – ns 8 9 tCKSR CKE Setup Time (Self Refresh Exit) 8 – 8 – 8 – ns 9 10 tT Transition time (rise and fall) 1 – 1 – 1 – ns RAS to CAS delay 15 – 20 – 20 – ns Common Parameters 11 tRCD 12 tRC Cycle Time 70 120k 70 120k 70 120k ns 13 tRAS Active Command Period 42 – 45 – 45 – ns 14 tRP Precharge Time 15 – 20 – 20 – ns 15 tRRD Bank to Bank Delay Time 14 – 15 – 20 – ns 16 tCCD CAS to CAS delay time (same bank) 1 – 1 – 1 – CLK Refresh Cycle 17 tSREX Self Refresh Exit Time 10 – 10 – 10 – ns 9 18 tREF Refresh Period (8192 cycles) 64 – 64 – 64 – ms 8 4 Read Cycle 19 tOH Data Out Hold Time 3 – 3 – 3 – ns 20 tLZ Data Out to Low Impedance Time 0 – 0 – 0 – ns 21 tHZ Data Out to High Impedance Time 3 7.5 3 7.5 3 8 ns 22 tDQZ DQM Data Out Disable Latency 2 – 2 – 2 – CLK 10 Write Cycle 23 tDPL Data input to Precharge (write recovery) 1 – 1 – 1 – CLK 24 tDAL Data In to Active/refresh 5 – 5 – 5 – CLK 25 tDQW DQM Write Mask Latency 0 – 0 – 0 – CLK V436632R24V(L) Rev. 1.0 October 2001 8 11 MOSEL VITELIC V436632R24V(L) Notes: 1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. + 1.4 V tCH 2.4V CLOCK 50 Ohm 0.4V tCL tSETUP Z=50 Ohm tT I/O tHOLD 50 pF 1.4V INPUT tAC tAC tLZ I/O tOH 50 pF 1.4V OUTPUT Measurement conditions for tac and toh tHZ 5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to tDPL + tRP. V436632R24V(L) Rev.1.0 October 2001 9 MOSEL VITELIC V436632R24V(L) Package Diagram SDRAM DIMM LOW-PROFILE Module Package Units : Inches (Millimeters) 5.250 (133.350) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) B A .118DIA ± 0.004 (3.000DIA ± 0.100) 0.250 (6.350) 0.350 (8.890) .450 (11.430) 0.100 Min (2.540 Min) 0.700 (17.780) 0.118 (3.000) 1.000 (25.40) 0.089 (2.26) 5.014 (127.350) 0.118 (3.000) C 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.150 Max (3.81 Max) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.123 ± .005 (3.125 ± .125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A 0.039 ± 0.002 (1.000 ± 0.050) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B Tolerances: + 0.005(.13) unless otherwise specified. V436632R24V(L) Rev. 1.0 October 2001 (2.540 Min) 0.050 ± 0.0039 (1.270 ± 0.10) 10 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Detail C MOSEL VITELIC V436632R24V(L) L abel Information Module Dens ity P art Number C riteria of P C 100 or P C 133 (refer to MV I datas heet) DIMM manufacture date code 256MBC LCLX VV436632R24VXXX-XX(L) 436616R 24XXX-XX 128MB X P C 133U-XXX-542-A XXXX-XXXXXX A s s embly in T aiwan C AS Latency 2 = C L2 3 = C L3 P C 133 U - XXX - 54 2 - A UNB UF F E R E D DIMM G erber file C L = 3 or 2 (C LK ) tR C D = 3 or 2 (C LK ) tR P = 3 or 2 (C LK ) V436632R24V(L) Rev. 1.0 October 2001 ® 16B ased P C 100 x 16 J E DE C S P D R evis ion 2 tAC = 5.4 ns 11 MOSEL VITELIC WORLDWIDE OFFICES V436632R24V(L) U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 JAPAN SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 © Copyright , MOSEL VITELIC Inc. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC CENTRAL, NORTHEASTERN & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029 Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. 3910 N. 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