MOSEL V54C3128

MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
128Mbit SDRAM
3.3 VOLT, BGA PACKAGE
8M X 16
16M X 8
32M X 4
PRELIMINARY
6
7PC
7
8PC
System Frequency (fCK)
166 MHz
143 MHz
143 MHz
125 MHz
Clock Cycle Time (tCK3)
6 ns
7 ns
7 ns
8 ns
Clock Access Time (tAC3) CAS Latency = 3
5.4 ns
5.4 ns
5.4 ns
6 ns
Clock Access Time (tAC2) CAS Latency = 2
5.4 ns
5.4 ns
6 ns
6 ns
Features
Description
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The V54C3128(16/80/40)4V(BGA) is a four bank
Synchronous DRAM organized as 4 banks x 2Mbit
x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3128(16/80/40)4V(BGA) achieves high
speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
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4 banks x 2Mbit x 16 organization
4 banks x 4Mbit x 8 organization
4 banks x 8Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 60 Pin WBGA
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Device Usage Chart
Operating
Temperature
Range
Package Outline
B
6
7PC
7
8PC
Std.
L
Temperature
Mark
0°C to 70°C
•
•
•
•
•
•
•
Blank
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
Access Time (ns)
1
Power
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
V 54
C
3
128404
B
V
MOSEL-VITELIC
MANUFACTURED
SPEED
8Mbit x 16: 128164
16Mbit x 8: 128804
32Mbit x 4: 128404
SYCHRONOUS
DRAM FAMILY
6 ns
7 ns
8 ns
PKG.
C = CMOS PROCESS
B = WBGA
3.3V, LVTTL, INTERFACE
Description
WBGA
Pkg.
Pin Count
B
60
SPECIAL FEATURE
DEVICE
NUMBER
COMPONENT REV. LEVEL
V = LVTTL
60 Pin WBGA PIN CONFIGURATION
Top View
9 8 7
3 2 1
8
7
x16
VCCQ
DQ0
VCC
A
DQ1
VSSQ
DQ2
B
DQ3
VCCQ
DQ4
C
DQ5
VSSQ
DQ6
D
A
9
B
C
D
E
F
3
2
1
VSS
DQ15
VSSQ
DQ13
VCCQ
DQ14
DQ11
VSSQ
DQ12
DQ9
VCCQ
DQ10
DQ7
NC
NC
E
NC
NC
DQ8
NC
VCC
LDQM
F
UDQM
VSS
Vref
G
CAS
WE
G
NC
CLK
H
CS
RAS
H
CKE
A12
J
BA0
BA1
J
A9
A11
K
A10/AP
A0
K
A7
A8
L
A1
A2
L
A5
A6
M
A3
VCC
M
VSS
A4
9
8
7
x8
3
2
1
9
VCCQ
DQ1
VCC
A
VSS
DQ7
VSSQ
x4
8
7
VCCQ
NC
VCC
A
NC
VSSQ
DQ0
B
3
2
1
VSS
NC
VSSQ
DQ3
VCCQ
NC
NC
VSSQ
DQ1
B
DQ6
VCCQ
NC
NC
VCCQ
DQ2
C
DQ5
VSSQ
NC
NC
VCCQ
NC
C
NC
VSSQ
NC
VSSQ
DQ1
D
DQ2
VCCQ
NC
NC
VSSQ
DQ3
D
DQ4
VCCQ
NC
NC
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
E
NC
NC
NC
Vref
NC
VCC
NC
F
DQM
VSS
Vref
NC
VCC
NC
F
DQM
VSS
CAS
WE
G
NC
CLK
CAS
WE
G
NC
CLK
CS
RAS
H
CKE
A12
CS
RAS
H
CKE
A12
BA0
BA1
J
A9
A11
BA0
BA1
J
A9
A11
A0
K
A7
A8
A10/AP
A0
K
A7
A8
A10/AP
A1
A2
L
A5
A6
A1
A2
L
A5
A6
A4
A3
VCC
M
VSS
A4
A3
VCC
M
VSS
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
2
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Capacitance*
Absolute Maximum Ratings*
TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ..............................................1 W
Data out current (short circuit).......................50 mA
Max. Unit
Symbol
Parameter
C I1
Input Capacitance (A0 to A11)
3.8
pF
C I2
Input Capacitance
RAS, CAS, WE, CS, CLK, CKE, DQM
3.8
pF
C IO
Output Capacitance (I/O)
6
pF
C CLK
Input Capacitance (CLK)
3.5
pF
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
*Note:Capacitance is sampled and not 100% tested.
Block Diagram
x16 Configuration
Row Addresses
Column Addresses
A0 - A8, AP, BA0, BA1
Row address
buffer
Column address
buffer
Refresh Counter
Row decoder
Row decoder
Memory array
Memory array
Memory array
Memory array
Bank 0
4096 x 512
x 16 bit
Bank 1
4096 x 512
x16 bit
Input buffer
Column decoder
Sense amplifier & I(O) bus
Row decoder
Column decoder
Sense amplifier & I(O) bus
Row decoder
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column address
counter
A0 - A11, BA0, BA1
Bank 2
4096 x 512
x 16 bit
Output buffer
Bank 3
4096 x 512
x 16 bit
Control logic & timing generator
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
3
UDQM
LDQM
WE
CAS
RAS
CS
CKE
CLK
I/O1-I/O16
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Block Diagram
x8 Configuration
Row Addresses
Column Addresses
A0 - A9, AP, BA0, BA1
Row address
buffer
Column address
buffer
Refresh Counter
Row decoder
Row decoder
Memory array
Memory array
Memory array
Memory array
Bank 0
4096 x 1024
x 8 bit
Bank 1
4096 x 1024
x 8 bit
Input buffer
Column decoder
Sense amplifier & I(O) bus
Row decoder
Column decoder
Sense amplifier & I(O) bus
Row decoder
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column address
counter
A0 - A11, BA0, BA1
Bank 2
4096 x 1024
x 8 bit
Output buffer
Bank 3
4096 x 1024
x 8 bit
Control logic & timing generator
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
4
DQM
WE
CAS
RAS
CS
CKE
CLK
I/O1-I/O8
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Block Diagram
x4 Configuration
Row Addresses
Column Addresses
A0 - A9, A11, AP, BA0, BA1
Row address
buffer
Column address
buffer
Refresh Counter
Row decoder
Row decoder
Memory array
Memory array
Memory array
Memory array
Bank 0
4096 x 2048
x 4 bit
Bank 1
4096 x 2048
x 4 bit
Input buffer
Column decoder
Sense amplifier & I(O) bus
Row decoder
Column decoder
Sense amplifier & I(O) bus
Row decoder
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column address
counter
A0 - A11, BA0, BA1
Bank 2
4096 x 2048
x 4 bit
Output buffer
Bank 3
4096 x 2048
x 4 bit
Control logic & timing generator
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
5
DQM
WE
CAS
RAS
CS
CKE
CLK
I/O1-I/O4
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Signal Pin Description
Pin
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
CS
Input
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0 - A11
Input
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
• 32M x 4 SDRAM CA0–CA9, CA11.
• 16M x 8 SDRAM CA0–CA9.
• 8M x 16 SDRAM CA0–CA8.
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
BA0,
BA1
Input
Level
—
Selects which bank is to be active.
DQx
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
LDQM
UDQM
Input
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
VCC, VSS Supply
VCCQ
VSSQ
Supply
Power and ground for the input buffers and the core logic.
—
—
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
6
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Device
State
CKE
n-1
CKE
n
CS
RAS
CAS
WE
DQM
A0-9,
A11
A10
BS0
BS1
Idle3
H
X
L
L
H
H
X
V
V
V
Active3
H
X
L
H
L
H
X
V
L
V
Active
3
H
X
L
H
L
H
X
V
H
V
Write
Active
3
H
X
L
H
L
L
X
V
L
V
Write with Autoprecharge
Active3
H
X
L
H
L
L
X
V
H
V
Row Precharge
Any
H
X
L
L
H
L
X
X
L
V
Precharge All
Any
H
X
L
L
H
L
X
X
H
X
Mode Register Set
Idle
H
X
L
L
L
L
X
V
V
V
No Operation
Any
H
X
L
H
H
H
X
X
X
X
Device Deselect
Any
H
X
H
X
X
X
X
X
X
X
Auto Refresh
Idle
H
H
L
L
L
H
X
X
X
X
Self Refresh Entry
Idle
H
L
L
L
L
H
X
X
X
X
Idle
(Self Refr.)
H
X
X
X
L
H
L
H
H
X
X
X
X
X
Idle
Active4
H
X
X
X
H
L
L
H
H
X
X
X
X
X
Any
(Power
Down)
H
X
X
X
L
H
L
H
H
L
X
X
X
X
Data Write/Output Enable
Active
H
X
X
X
X
X
L
X
X
X
Data Write/Output Disable
Active
H
X
X
X
X
X
H
X
X
X
Operation
Row Activate
Read
Read w/Autoprecharge
Self Refresh Exit
Power Down Entry
Power Down Exit
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Power Down Mode can not entry in the burst cycle.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
7
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
operation must be done before any activate command after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in precharged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table.
Power On and Initialization
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200 µs is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.
Read and Write Operation
When RAS is low and both CAS and WE are high
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, tRCD, from the
RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation,
i.e., one of 1, 2, 4, 8. Column addresses are segmented by the burst length and serial data accesses
are done within this boundary. The first column address to be accessed is supplied at the CAS timing
and the subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with
interleave sequence, if the first address is ‘2’, then
the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and
5.
Programming the Mode Register
The Mode register designates the operation
mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
8
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Address Input for Mode Set (Mode Register Operation)
BA1 BA0 A11 A10 A9
A8
Operation Mode
A7
A6
A5
A4
A3
A2
A1
CAS Latency
BT
Burst Length
Address Bus (Ax)
A0
Mode Register
Burst Type
Operation Mode
BA1 BA0 A11 A10 A9 A8 A7
Mode
A3
Type
0
Sequential
1
Interleave
0
0
0
0
0
0
0
Burst Read/Burst
Write
0
0
0
0
1
0
0
Burst Read/Single
Write
Burst Length
CAS Latency
A6
0
0
A5
0
0
A4
0
1
Length
Latency
A2
A1
A0
Reserve
Sequential
Interleave
0
0
0
1
1
2
0
0
1
2
2
4
Reserve
0
1
0
0
1
1
3
0
1
0
4
1
0
0
Reserve
0
1
1
8
8
1
0
1
Reserve
1
0
0
Reserve
Reserve
1
1
0
Reserve
1
0
1
Reserve
Reserve
1
1
1
Reserve
1
1
0
Reserve
Reserve
1
1
1
Reserve
Reserve
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two or more
banks are activated
sequentially, interleaved bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle
latches the sense amplifiers. The maximum tRAS or
the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining addresses are overridden by the new address with the
full burst length. An interrupt which accompanies
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
9
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Burst Length and Sequence:
Burst Starting Address
Length
(A2 A1 A0)
2
xx0
xx1
4
x00
x01
x10
x11
8
000
001
010
011
100
101
110
111
Sequential Burst Addressing
(decimal)
Interleave Burst Addressing
(decimal)
0, 1
1, 0
0,
1,
2,
3,
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
0, 1
1, 0
1,
2,
3,
0,
2,
3,
0,
1,
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
0,
1,
2,
3,
3
0
1
2
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
Refresh Mode
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
2,
3,
0,
1,
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
3
2
1
0
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
SDRAM has two refresh modes, Auto Refresh
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any refresh mode. An on-chip address counter increments
the word and the bank addresses and no bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay
is required prior to any access command.
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh operations, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by taking CKE “high”. One clock delay is required for
mode entry and exit.
Auto Precharge
Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command
is issued, the Read with Auto-Precharge function
is initiated. The SDRAM automatically enters the
precharge operation one clock before the last data
out for CAS latencies 2, two clocks for CAS latencies 3 and three clocks for CAS latencies 4. If CA10
is high when a Write Command is issued, the Write
DQM Function
DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency tDQZ ). It also provides
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
0
1
2
3
4
5
6
7
1,
0,
3,
2,
10
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery time)
after the last data in.
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These
methods include using another Read or Write Command to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Command to terminate the existing burst operation but
leave the bank open for future Read or Write Commands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O contention. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10
are used to define banks as shown in the following
list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2,
two clocks before the last data out for CAS latency
= 3. Writes require a time delay twr from the last
data out to apply the precharge command.
Bank Selection by Address Bits:
A10
BA0 BA1
0
0
0
Bank 0
0
0
1
Bank 1
0
1
0
Bank 2
0
1
1
Bank 3
1
X
X
all Banks
Recommended Operation and Characteristics for LV-TTL
TA = 0 to 70 °C; VSS = 0 V; VCC,VCCQ = 3.3 V ± 0.3 V
Limit Values
Parameter
Symbol
min.
max.
Unit
Notes
Input high voltage
VIH
2.0
Vcc+0.3
V
1, 2
Input low voltage
VIL
– 0.3
0.8
V
1, 2
Output high voltage (IOUT = – 4.0 mA)
VOH
2.4
–
V
Output low voltage (IOUT = 4.0 mA)
VOL
–
0.4
V
Input leakage current, any input
(0 V < V IN < 3.6 V, all other inputs = 0 V)
II(L)
–5
5
µA
Output leakage current
(DQ is disabled, 0 V < VOUT < VCC )
IO(L)
–5
5
µA
Note:
1. All voltages are referenced to VSS.
2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with
3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
11
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Operating Currents (TA = 0 to 70°C, VCC = 3.3V ± 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Max.
Symbol
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3N
ICC3P
Parameter & Test Condition
-6
-7 / -7PC
-8PC
Unit
Note
Operating Current
tRC = tRCMIN., tRC = tCKMIN .
Active-precharge command cycling,
without Burst Operation
1 bank operation
190
170
150
mA
7
Precharge Standby Current
in Power Down Mode
CS =VIH, CKE≤ VIL(max)
tCK = min.
1.5
1.5
1.5
mA
7
1
1
1
mA
7
Precharge Standby Current
in Non-Power Down Mode
CS =VIH, CKE≥ VIL(max)
tCK = min.
55
45
35
mA
5
5
5
mA
No Operating Current
tCK = min, CS = VIH(min)
bank ; active state ( 4 banks)
CKE ≥ VIH(MIN.)
65
55
45
mA
CKE ≤VIL(MAX.)
(Power down mode)
10
10
10
mA
tCK = Infinity
tCK = Infinity
ICC4
Burst Operating Current
tCK = min
Read/Write command cycling
130
110
90
mA
7,8
ICC5
Auto Refresh Current
tCK = min
Auto Refresh command cycling
270
250
210
mA
7
ICC6
Self Refresh Current
Self Refresh Mode, CKE≤0.2V
1.5
1.5
1.5
mA
800
800
800
µA
L-version
Notes:
7. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and
tRC. Input signals are changed one time during tCK.
8. These parameter depend on output loading. Specified values are obtained with output open.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
12
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
AC Characteristics 1,2, 3
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Limit Values
-6
#
Symbol
Parameter
-7PC
-8PC
-7
Min. Max. Min. Max. Min. Max. Min. Max. Unit Note
Clock and Clock Enable
1
2
3
tCK
tCK
tAC
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
6
7.5
–
–
7
7.5
–
–
7
10
–
–
8
10
–
–
s
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
–
166
133
–
–
143
133
–
–
143
100
–
–
125
100
MHz
MHz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
–
_
5.4
5.4
–
_
5.4
5.4
–
_
5.4
6
–
_
6
6
ns
ns
2, 4
4
tCH
Clock High Pulse Width
2.5
–
2.5
–
2.5
–
3
–
ns
5
tCL
Clock Low Pulse Width
2.5
–
2.5
–
2.5
–
3
–
ns
6
tT
Transition Tim
0.3
1.2
0.3
1.2
0.3
1.2
0.5
10
ns
Setup and Hold Times
7
tIS
Input Setup Time
1.5
–
1.5
–
1.5
–
2
–
ns
5
8
tIH
Input Hold Time
0.8
–
0.8
–
0.8
–
1
–
ns
5
9
tCKS
Input Setup Time
1.5
–
1.5
–
1.5
–
2
–
ns
5
10
tCKH
CKE Hold Time
0.8
–
0.8
–
0.8
–
1
–
ns
5
11
tRSC
Mode Register Set-up Time
12
–
14
–
14
–
16
–
ns
12
tSB
Power Down Mode Entry Time
0
6
0
7
0
7
0
8
ns
Row to Column Delay Time
12
–
15
–
15
–
20
–
ns
6
Common Parameters
13
tRCD
14
tRP
Row Precharge Time
15
–
15
–
15
–
20
–
ns
6
15
tRAS
Row Active Time
40
100K
42
100K
42
100K
45
100k
ns
6
16
tRC
Row Cycle Time
60
–
60
–
60
–
60
–
ns
6
17
tRRD
Activate(a) to Activate(b) Command Period
12
–
14
–
14
–
16
–
ns
6
18
tCCD
CAS(a) to CAS(b) Command Period
1
–
1
–
1
–
1
–
CLK
Refresh Period (4096 cycles)
—
64
—
64
—
64
—
64
ms
Self Refresh Exit Time
1
—
1
—
1
—
1
—
CLK
Refresh Cycle
19
tREF
20
tSREX
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
13
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
AC Characteristics (Cont’d)
Limit Values
-6
#
Symbol
Parameter
-7PC
-8PC
-7
Min. Max. Min. Max. Min. Max. Min. Max. Unit Note
Read Cycle
21
tOH
Data Out Hold Time
3
–
3
–
3
–
3
–
ns
22
tLZ
Data Out to Low Impedance Time
1
–
1
–
1
–
0
–
ns
23
tHZ
Data Out to High Impedance Time
3
6
3
7
3
7
3
8
ns
24
tDQZ
DQM Data Out Disable Latency
–
2
–
2
–
2
–
2
CLK
Write Recovery Time
2
–
2
–
2
–
2
–
CLK
DQM Write Mask Latency
0
–
0
–
0
–
0
–
CLK
2
7
Write Cycle
25
tWR
26
tDQW
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests have VIL = 0.8V and V IH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1ns with the AC output load circuit shown
in Figure 1.
tCK
VIH
CLK
VIL
+ 1.4 V
tT
tCS
tCH
50 Ohm
1.4V
COMMAND
Z=50 Ohm
tLZ
I/O
tAC
tAC
50 pF
tOH
1.4V
OUTPUT
tHZ
Figure 1.
4. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
5. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
6. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
14
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. Burst Termination
8.1 Termination of a Burst Write Operation
8.2 Termination of a Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Power Down Mode
13. Self Refresh (Entry and Exit)
14. Auto Refresh (CBR)
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
15
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Timing Diagrams (Cont’d)
15. Random Column Read ( Page within same Bank)
15.1 CAS Latency = 2
15.2 CAS Latency = 3
16. Random Column Write ( Page within same Bank)
16.1 CAS Latency = 2
16.2 CAS Latency = 3
17. Random Row Read ( Interleaving Banks) with Precharge
17.1 CAS Latency = 2
17.2 CAS Latency = 3
18. Random Row Write ( Interleaving Banks) with Precharge
18.1 CAS Latency = 2
18.2 CAS Latency = 3
19. Precharge Termination of a Burst
19.1 CAS Latency = 2
19.2 CAS Latency = 3
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
16
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
1. Bank Activate Command Cycle
(CAS latency = 3)
T0
T1
T
T
T
T
T
CLK
..........
ADDRESS
Bank A
Col. Addr.
Bank A
Row Addr.
Bank A
Row Addr.
Bank B
Row Addr.
..........
tRCD
COMMAND
Bank A
Activate
tRRD
NOP
Write A
with Auto
Precharge
NOP
Bank B
Activate
..........
Bank A
Activate
NOP
: “H” or “L”
tRC
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
CAS latency = 2
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
NOP
DOUT A0
NOP
NOP
DOUT A2
DOUT A1
DOUT A0
17
DOUT A1
NOP
NOP
DOUT A3
DOUT A2
DOUT A3
NOP
NOP
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
READ A
READ B
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS latency = 2
NOP
DOUT A0
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
NOP
NOP
NOP
NOP
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
T3
T4
T5
T6
NOP
NOP
DOUT B3
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0
T1
T2
T7
T8
CLK
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
tDQW
DQM
tDQZ
COMMAND
NOP
READ A
I/O’s
NOP
NOP
NOP
WRITE B
DIN B0
DOUT A0
Must be Hi-Z before
the Write Command
: “H” or “L”
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
NOP
18
NOP
NOP
DIN B1
DIN B2
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
4.2 Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tDQW
DQM
tDQZ
1 Clk Interval
COMMAND
NOP
NOP
BANK A
ACTIVATE
NOP
READ A
WRITE A
NOP
NOP
NOP
DIN A1
DIN A2
DIN A3
Must be Hi-Z before
the Write Command
CAS latency = 2
DIN A0
tCK2, I/O’s
: “H” or “L”
4.3 Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
DIN B0
DIN B1
DIN B2
DIN B0
DIN B1
DIN B2
CLK
tDQW
DQM
tDQZ
OMMAND
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
CAS latency = 2
tCK1, I/O’s
DOUT A0
DOUT A1
Must be Hi-Z before
the Write Command
CAS latency = 3
tCK2, I/O’s
DOUT A0
: “H” or “L”
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
19
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
I/O’s
WRITE A
DIN A0
NOP
NOP
NOP
DIN A1
DIN A2
DIN A3
The first data element and the Write
are registered on the same clock edge.
NOP
NOP
NOP
NOP
don’t care
Extra data is ignored after
termination of a Burst.
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
WRITE A
WRITE B
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
1 Clk Interval
I/O’s
DIN A0
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
DIN B0
20
NOP
NOP
NOP
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
WRITE A
READ B
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
CAS latency = 2
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
DIN A0
don’t care
DIN A0
don’t care
NOP
NOP
DOUT B0
don’t care
NOP
NOP
NOP
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
NOP
DOUT B3
Input data must be removed from the I/O’s at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.
7. Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
BANK A
ACTIVE
NOP
NOP
WRITE A
Auto-Precharge
NOP
NOP
tWR
CAS latency = 2
I/O’s
DIN A0
DIN A1
NOP
tRP
*
tWR
tRP
CAS latency = 3
I/O’s
DIN A0
DIN A1
*
Begin Autoprecharge
Bank can be reactivated after trp
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
21
NOP
NOP
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
7.2 Burst Read with Auto-Precharge
Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
WRITE A
READ B
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
CAS latency = 2
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
DOUT A0
NOP
NOP
*
DOUT A1
NOP
*
NOP
NOP
tRP
DOUT A2
DOUT A0
NOP
DOUT A1
DOUT A3
tRP
DOUT A2
DOUT A3
*
Begin Autoprecharge
Bank can be reactivated after tRP
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
22
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
8.1 Termination of a Burst Read Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
CAS latency = 2
tCK2, I/O’s
NOP
NOP
Burst
Stop
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
CAS latency = 3
tCK3, I/O’s
NOP
NOP
NOP
NOP
DOUT A3
8.2 Termination of a Burst Write Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A
NOP
NOP
DIN A1
DIN A2
Burst
Stop
NOP
CAS latency = 2,3
I/O’s
DIN A0
don’t care
Input data for the Write is masked.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
23
NOP
NOP
NOP
T0
T1
T2
T3
T4
Burst Length = 4, CAS Latency = 2
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T17
T16
T18
T19
T20
CLK
tCH
tCK2
tCL
tCS
CKE
tCKS
Begin Auto Precharge
Bank A
tCH
Begin Auto Precharge
Bank B
tCKH
T21
T22
CILETIV LESOM
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
9.1 AC Parameters for Write Timing
CS
RAS
CAS
WE
24
BA
tAH
AP
RAx
RBx
RAy
RBy
RAz
RBy
tAS
Addr
RAx
CAx
RBx
CBx
RAy
RAy
DQM
tRCD
tDS
tRC
I/O
tDPL
tDH
tRP
tRRD
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Activate
Write with
Activate
Write with
Activate
Command Auto Precharge Command Auto Precharge Command
Bank A
Command
Bank B
Command
Bank A
Bank A
Bank B
Bx3
Ay0
Write
Command
Bank A
Ay1
Ay2
Ay3
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
V54C3128(16/80/40)4V(BGA)
RAz
T0
Burst Length = 2, CAS Latency = 2
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T12
T11
CLK
tCH
tCK2
tCL
tCS
CKE
Begin Auto
Precharge
Bank B
tCH
tCKS
tCKH
T13
CILETIV LESOM
\
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
9.2 AC Parameters for Read Timing
CS
RAS
CAS
25
WE
BA
tAH
AP
RAx
RBx
RAy
Addr
RAx
CAx
RBx
RBx
RAy
tRRD
tRAS
DQM
tRC
tAC2
tAC2
tRCD
I/O
tLZ
tOH
tRP
tHZ
tHZ
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Ax1
Bx0
Read with
Auto Precharge
Command
Precharge
Command
Bank A
Bx1
Activate
Command
Bank A
V54C3128(16/80/40)4V(BGA)
tAS
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
2 Clock min.
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CILETIV LESOM
\
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
10. Mode Register Set
CS
RAS
CAS
26
WE
BA
AP
Addr
Precharge
Command
All Banks
Mode Register
Set Command
Any
Command
V54C3128(16/80/40)4V(BGA)
Address Key
T0
T
T
T
T
T
T
T
T
T
T1
T
T
T
T
T
T
T
T
T
CLK
High level
is required
CKE
2 Clock min.
Minimum of 2 Refresh Cycles are required
T
T
T
CILETIV LESOM
\
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
11. Power on Sequence and Auto Refresh (CBR)
CS
RAS
CAS
WE
27
BA
AP
Addr
DQM
tRP
I/O
tRC
Hi-Z
Precharge 1st Auto Refresh
Command
Command
All Banks
Inputs must be
stable for 200µs
2nd Auto Refresh
Command
Mode Register
Set Command
Any
Command
V54C3128(16/80/40)4V(BGA)
Address Key
T0
T1
Burst Length = 4, CAS Latency = 2
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCKSP
CKE
CILETIV LESOM
\
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
12. Power Down Mode
CS
RAS
CAS
WE
28
BA
RAx
Addr
RAx
DQM
I/O
Hi-Z
Activate
Command
Bank A
Precharge
Command
Bank A
Power Down
Mode Entry
Power Down
Mode Exit
Any
Command
V54C3128(16/80/40)4V(BGA)
AP
T0
T1
T2
T3
T4
T5
T
T
T
T
T
T
T
T
CLK
t CKSR
tSREX
CKE
T
T
T
T
T
T
T
T
T
CILETIV LESOM
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
13. Self Refresh (Entry and Exit)
CS
RAS
CAS
29
WE
BA
Addr
tRC
DQM
I/O
Hi-Z
All Banks
must be idle
Self Refresh
Entry
Begin Self Refresh
Exit Command
Self Refresh Exit
Command issued
Self Refresh
Exit
V54C3128(16/80/40)4V(BGA)
AP
T0
T1
T2
Burst Length = 4, CAS Latency = 2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T17
T16
T18
T19
T20
T21
T22
CLK
tCK2
CKE
CILETIV LESOM
\
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
14. Auto Refresh (CBR)
CS
RAS
CAS
30
WE
BA
RAx
Addr
RAx
tRP
DQM
I/O
tRC
CAx
tRC
(Minimum Interval)
Hi-Z
Ax0
Precharge
Command
All Banks
Auto Refresh
Command
Auto Refresh
Command
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Ax3
V54C3128(16/80/40)4V(BGA)
AP
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
Burst Length = 4, CAS Latency = 2
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK2
CKE
CILETIV LESOM
\)
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
15.1 Random Column Read (Page within same Bank) (1 of 2)
CS
RAS
CAS
31
WE
BA
RAw
Addr
RAw
RAz
CAw
CAx
CAy
RAz
CAz
DQM
I/O
Hi-Z
Aw0
Activate
Command
Bank A
Read
Command
Bank A
Aw1
Aw2
Read
Command
Bank A
Aw3
Ax0
Read
Command
Bank A
Ax1
Ay0
Ay1
Ay2
Precharge
Command
Bank A
Ay3
Az0
Activate
Command
Bank A
Read
Command
Bank A
Az1
Az2
Az3
V54C3128(16/80/40)4V(BGA)
AP
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCK3
CKE
T22
CILETIV LESOM
\)
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
15.2 Random Column Read (Page within same Bank) (2 of 2)
CS
RAS
CAS
32
WE
BA
RAw
Addr
RAw
RAz
CAw
CAx
CAy
RAz
CAz
Activate
Command
Bank A
Read
Command
Bank A
DQM
I/O
Hi-Z
Aw0
Activate
Command
Bank A
Read
Command
Bank A
Aw1
Read
Command
Bank A
Aw2
Aw3
Read
Command
Bank A
Ax0
Ax1
Ay0
Ay1
Ay2
Precharge
Command
Bank A
Ay3
V54C3128(16/80/40)4V(BGA)
AP
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
Burst Length = 4, CAS Latency = 2
T11
T12
T13
T14
T15
T17
T16
T18
T19
T20
CLK
tCK2
CKE
T21
T22
CILETIV LESOM
\)
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
16.1 Random Column Write (Page within same Bank) (1 of 2)
CS
RAS
CAS
33
WE
BA
RBz
Addr
RBz
RAw
RBz
CBz
CBx
CBy
RAw
RBz
CAx
CBz
DQM
I/O
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
DBz0 DBz1 DBz2 DBz3
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
V54C3128(16/80/40)4V(BGA)
AP
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK3
CKE
CILETIV LESOM
\)
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
16.2 Random Column Write (Page within same Bank) (2 of 2)
CS
RAS
CAS
34
WE
BA
RBz
Addr
RBz
RBz
CBz
CBx
CBy
RBz
CBz
DQM
I/O
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
DBz0 DBz1
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
V54C3128(16/80/40)4V(BGA)
AP
T0
T1
T2
T3
T4
T5
T6
T7
T8
Burst Length = 8, CAS Latency = 2
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCK2
CKE
High
T22
CILETIV LESOM
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
17.1 Random Row Read (Interleaving Banks) (1 of 2)
CS
RAS
CAS
WE
35
A11(BS)
RBx
A0 - A9
RBx
CAx
tRP
Bx0
Read
Command
Bank B
CBy
RBy
tAC2
Hi-Z
Activate
Command
Bank B
RBy
RAx
CBx
tRCD
DQM
I/O
RAx
Bx1
Bx2
Bx3
Bx4
Activate
Command
Bank A
Bx5
Bx6
Bx7
Precharge
Command
Bank B
Read
Command
Bank A
Ax0
Ax1
Activate
Command
Bank B
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
Read
Command
Bank B
By0
By1
V54C3128(16/80/40)4V(BGA)
A10
T0
T1
T2
T3
T4
T5
T6
T7
T8
Burst Length = 8, CAS Latency = 3
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCK3
CKE
High
T22
CILETIV LESOM
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
17. 2 Random Row Read (Interleaving Banks) (2 of 2)
CS
RAS
CAS
36
WE
A11(BS)
RBx
A0 - A9
RBx
CAx
tRP
Bx0
Read
Command
Bank B
CBy
RBy
tAC3
Hi-Z
Activate
Command
Bank B
RBy
RAx
CBx
tRCD
DQM
I/O
RAx
Bx1
Bx2
Activate
Command
Bank A
Bx3
Bx4
Bx5
Read
Command
Bank A
Bx6
Bx7
Precharge
Command
Bank B
Ax0
Ax1
Ax2
Activate
Command
Bank B
Ax3
Ax4
Ax5
Ax6
Read
Command
Bank B
Ax7
By0
Precharge
Command
Bank A
V54C3128(16/80/40)4V(BGA)
A10
T0
T1
T2
T3
T4
T5
T6
T7
T8
Burst Length = 8, CAS Latency = 2
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK2
CKE
High
CILETIV LESOM
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
18.1 Random Row Write (Interleaving Banks) (1 of 2)
CS
RAS
CAS
37
WE
A11(BS)
RAx
A0 - A9
RAx
CAy
CAX
RBx
tRCD
Hi-Z
Activate
Command
Bank A
CBx
RAy
tDPL
DQM
I/O
RAy
RBx
CAy
tDPL
tRP
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
V54C3128(16/80/40)4V(BGA)
A10
T0
T1
T2
T3
T4
T5
T6
T7
T8
Burst Length = 8, CAS Latency = 3
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK3
CKE
High
CILETIV LESOM
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
18.2 Random Row Write (Interleaving Banks) (2 of 2)
CS
RAS
CAS
38
WE
A11(BS)
RAx
A0 - A9
RAx
RAy
RBx
CAX
RBx
tRCD
RAy
CBx
tDPL
tRP
CAy
tDPL
DQM
I/O
Hi-Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
V54C3128(16/80/40)4V(BGA)
A10
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T17
T16
T18
T19
T20
T21
CLK
tCK2
CKE
High
T22
CILETIV LESOM
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
Burst Length = 8, CAS Latency = 2
19.1 Precharge Termination of a Burst (1 of 2)
CS
RAS
CAS
WE
39
BA
RAx
Addr
RAx
RAy
RAy
CAx
RAz
RAz
CAy
CAz
tRP
tRP
tRP
DQM
I/O
Hi-Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3
Write
Precharge
Command
Command
Bank A
Bank A
Precharge Termination
of a Write Burst. Write
data is masked.
Ay0
Activate
Command
Bank A
Read
Command
Bank A
Ay1
Precharge
Command
Bank A
Ay2
Activate
Command
Bank A
Az0
Read
Command
Bank A
Az1
Precharge
Command
Bank A
Precharge Termination
of a Read Burst.
Az2
V54C3128(16/80/40)4V(BGA)
AP
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCK3
CKE
High
T22
CILETIV LESOM
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
Burst Length = 4, 8, CAS Latency = 3
19.2 Precharge Termination of a Burst (2 of 2)
CS
RAS
CAS
WE
40
BA
RAx
Addr
RAx
RAy
RAy
CAx
RAz
RAz
CAy
tRP
tRP
DQM
I/O
Hi-Z
Activate
Command
Bank A
DAx0
Write
Command
Bank A
Write Data
is masked
Ay0
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge Termination
of a Write Burst.
Read
Command
Bank A
Ay1
Precharge
Command
Bank A
Ay2
Activate
Command
Bank A
Precharge Termination
of a Read Burst.
V54C3128(16/80/40)4V(BGA)
AP
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Complete List of Operation Commands
SDRAM Function Truth Table
CURRENT
STATE1
CS
RAS
CAS
WE
BS
Addr
ACTION
H
L
L
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
L
H
H
L
L
X
H
L
X
H
L
H
L
X
X
BS
BS
BS
BS
X
Op-
X
X
X
X
RA
AP
X
Code
NOP or Power Down
NOP
ILLEGAL2
ILLEGAL2
Row (&Bank) Active; Latch Row Address
NOP4
Auto-Refresh or Self-Refresh5
Mode reg. Access5
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
L
L
H
H
L
X
X
H
L
H
L
X
X
X
BS
BS
BS
BS
X
X
X
CA,AP
CA,AP
X
AP
X
NOP
NOP
Begin Read; Latch CA; DetermineAP
Begin Write; Latch CA; DetermineAP
ILLEGAL2
Precharge
ILLEGAL
Read
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
BS
BS
BS
X
X
X
X
CA,AP
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active
Term Burst, New Read, DetermineAP3
Term Burst, Start Write, DetermineAP3
ILLEGAL2
Term Burst, Precharge
ILLEGAL
Write
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
BS
BS
BS
X
X
X
X
CA,AP
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active
Term Burst, Start Read, DetermineAP3
Term Burst, New Write, DetermineAP3
ILLEGAL2
Term Burst, Precharge3
ILLEGAL
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
X
BS
BS
X
X
X
X
X
X
X
AP
X
NOP (Continue Burst to End;> Precharge)
NOP (Continue Burst to End;> Precharge)
ILLEGAL2
ILLEGAL2
ILLEGAL
ILLEGAL2
ILLEGAL2
ILLEGAL
Idle
Row Active
Read
with
Auto
Precharge
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
41
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
SDRAM FUNCTION TRUTH TABLE(continued)
CURRENT
STATE1
CS
RAS
CAS
WE
BS
Addr
ACTION
Write
with
Auto
Precharge
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
X
BS
BS
X
X
X
X
X
X
X
AP
X
NOP (Continue Burst to End;> Precharge)
NOP (Continue Burst to End;> Precharge)
ILLEGAL2
ILLEGAL2
ILLEGAL
ILLEGAL2
ILLEGAL2
ILLEGAL
Precharging
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP;> Idle after tRP
NOP;> Idle after tRP
ILLEGAL2
ILLEGAL2
ILLEGAL2
NOP4
ILLEGAL
Row
Activating
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP;> Row Active after tRCD
NOP;> Row Active after tRCD
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL
Write
Recovering
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP
NOP
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL
Refreshing
H
L
L
L
L
L
X
H
H
H
L
L
X
H
H
L
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP;> Idle after tRC
NOP;> Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Mode
Register
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
Accessing
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
42
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Clock Enable (CKE) Truth Table:
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Addr
Self-Refresh6
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
EXIT Self-Refresh, Idle after tRC
EXIT Self-Refresh, Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self-Refresh)
Power-Down
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
EXIT Power-Down, > Idle.
EXIT Power-Down, > Idle.
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low-Power Mode)
All. Banks
Idle7
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
X
X
X
H
H
H
L
L
L
X
X
X
H
H
L
H
L
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to the function truth table
Enter Power- Down
Enter Power- Down
ILLEGAL
ILLEGAL
ILLEGAL
Enter Self-Refresh
ILLEGAL
NOP
STATE(n)
ACTION
Abbreviations:
RA = Row Address
CA = Column Address
BS = Bank Address
AP = Auto Precharge
Notes for SDRAM function truth table:
1.
2.
3.
4.
5.
6.
Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle.
Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
NOP to bank precharging or in Idle state. May precharge bank(s) indicated by BS (andAP).
Illegal if any bank is not Idle.
CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any
command other than EXIT.
7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
8. Must be legal command as defined in the SDRAM function truth table.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
43
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Package Diagram
60-Pin WBGA
0.20 M S B
8.50±0.10
1.05
1.60
0.80
0.50
A
13.0
±0.10
Ø0.45±0.05
1.00
Ø0.15
MSAB
Ø0.08 M S
1.00
0.20 M S A
B
Out of die mark area (#2)
// 0.2 9
S
0.25+0.05 (#1)
-0.10
0.12 S
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
Min 0.10 (#1)
44
Notes:
1. No bond figure exposed
2. Do not measure / / within this area
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© Copyright 2001, MOSEL VITELIC Inc.
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