V62C1802048L(L) Ultra Low Power 256K x 8 CMOS SRAM Features Functional Description • Low-power consumption - Active: 25mA at 70ns - Stand-by: 10 µA (CMOS input/output) 2 µA CMOS input/output, L version The V62C1802048L is a low power CMOS Static RAM organized as 262,144 words by 8 bits. Easy memory expansion is provided by an active LOW CE1 , an active HIGH CE2, an active LOW OE , and Tri-state I/O’s. This device has an automatic power-down mode feature when deselected. • Single + 1.8 to 2.2V Power Supply Writing to the device is accomplished by taking Chip Enable 1 (CE1 ) with Write Enable (WE ) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is performed by taking Chip Enable 1 (CE1 ) with Output Enable (OE ) LOW while Write Enable (WE ) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle. • Equal access and cycle time • 70/85/100/150 ns access time • Easy memory expansion with CE1, CE2 and OE inputs • 1.0V data retention mode The V62C1802048LL comes with a 1V data retention feature and Lower Standby Power. The V62C1802048L is available in a 32-pin 8 x 13.4 & 8 x 20 mm TSOP1 / STSOP packages. • TTL compatible, Tri-state input/output • Automatic power-down when deselected • Package available: 32-TSOP1 / STSOP Logic Block Diagram 32-Pin TSOP1 / STSOP INPUT BUFFER ROW DECODER A3 A4 A5 A6 A7 A8 A9 SENSE AMP A0 A1 A2 Cell Array I/O1 COLUMN DECODER A10 A11 I/O8 A12 A13 A14 A15 CONTROL CIRCUIT A16 A17 OE WE CE1 CE2 1 REV. 1.2 May 2001 V62C1802048L(L) A11 1 32 OE A9 2 31 A10 A8 3 30 CE1 A13 4 29 I/O8 WE 5 28 I/O7 CE2 6 27 I/O6 A15 7 26 I/O5 Vcc 8 25 I/O4 A17 9 24 GND A16 10 23 I/O3 A14 11 22 I/O2 A12 12 21 I/O1 A7 13 20 A0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 V62C1802048L(L) Absolute Maximum Ratings * Parameter Symbol Minimum Maximum Unit Voltage on Any Pin Relative to Gnd Vt -0.5 4.6 V Power Dissipation PT − 1.0 W Storage Temperature (Plastic) Tstg -55 +150 0C Temperature Under Bias Tbias -40 +85 0 C * Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth Table CE1 CE2 WE OE Data Mode H X X X High-Z Standby X L X X High-Z Standby L H H L Data Out L H H H High-Z Active, Output Disable L H L X Data In Active, Write Active, Read * Key: X = Don’t Care, L = Low, H = High Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**) Parameter Supply Voltage Input Voltage Symbol Min Typ Max Unit VCC 1.8 2.0 2.2 V Gnd 0.0 0.0 0.0 V VIH 1.6 - VCC + 0.2 V VIL -0.5* - 0.4 V * VIL min = -1.0V for pulse width less than tRC/2. ** For Industrial Temperature. 2 REV. 1.2 May 2001 V62C1802048L(L) V62C1802048L(L) DC Operating Characteristics (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Parameter Sym Test Conditions -70 -85 -100 -150 Min Max Min Max Min Max Min Max Unit Input Leakage Current IILII Vcc = Max, Vin = Gnd to Vcc - 1 - 1 - 1 - 1 µA Output Leakage Current IILOI CE1 = VIH or CE2 = VIL Vcc= Max, VOUT = Gnd to Vcc - 1 - 1 - 1 - 1 µA Operating Power Supply Current ICC CE1 = VIL , CE2 = VIH VIN = VIH or VIL , IOUT = 0 mA - 3 - 3 - 3 - 3 mA ICC1 CE1 = VIL , CE2 = VIH IOUT = 0mA, Min Cycle, 100% Duty - 20 - 20 - 15 - 15 mA ICC2 CE1 = 0.2V , CE2 =Vcc - 0.2V IOUT = 0mA, - 3 - 3 - 3 - 3 mA Average Operating Current Cycle Time=1µs, 100% Duty Standby Power Supply Current (TTL Level) ISB CE1 = VIH or CE2 = VIL - 0.3 - 0.3 - 0.3 - 0.3 mA Standby Power Supply Current (CMOS Level) ISB1 CE1 > Vcc - 0.2V or CE2 < 0.2V, f = 0 VIN < 0.2V or VIN > Vcc- 0.2V - 10 - 10 - 10 - 10 µA - 2 - 2 - 2 - 2 µA L Output Low Voltage VOL IOL = 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V Output High Voltage VOH IOH = -1 mA 1.6 - 1.6 - 1.6 - 1.6 - V Capacitance (f = 1MHz, TA = 250C) Parameter* Symbol Test Condition Max Unit Input Capacitance Cin Vin = 0V 7 pF I/O Capacitance CI/O Vin = Vout = 0V 8 pF * This parameter is guaranteed by device characterization and is not production tested. AC Test Conditions Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level 0.4V to 1.6V 5ns TTL CL* 50% of input level (VIL+VIH)/2 Output Load Condition 70ns/85 ns CL = 30pf + 1TTL Load Load 100ns/150 ns CL = 100pf + 1TTL Load Figure A. 3 REV. 1.2 May 2001 V62C1802048L(L) * Including Scope and Jig Capacitance V62C1802048L(L) Read Cycle (3,9) (Vcc = 1.8 to2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Symbol -70 -85 -100 Unit -150 Note Min Max Min Max Min Max Min Max Read Cycle Time tRC 70 - 85 - 100 - 150 - ns Address Access Time tAA - 70 - 85 - 100 - 150 ns Chip Enable Access Time tACE - 70 - 85 - 100 - 150 ns Output Enable Access Time tOE - 40 - 40 - 50 - 70 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns Chip Enable to Output in Low-Z tCLZ 10 - 10 - 10 - 10 - ns 4,5 Chip Disable to Output in High-Z tCHZ - 30 - 35 - 40 - 50 ns 4,5 Output Enable to Output in Low-Z tOLZ 5 - 5 - 5 - 5 - ns 4,5 Output Disable to Output in High-Z tOHZ - 25 - 30 - 35 - 40 ns 4,5 Power-Up Time tPU 0 - 0 - 0 - 0 - ns 5 Power-Down Time tPD - 70 - 85 - 100 - 150 ns 5 Unit Note Write Cycle (3,11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Symbol -70 -85 -100 -150 Min Max Min Max Min Max Min Max Write Cycle Time tWC 70 - 85 - 100 - 150 - ns Chip Enable to Write End tCW 60 - 70 - 80 - 120 - ns Address Setup to Write End tAW 60 - 70 - 80 - 120 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 50 - 60 - 70 - 100 - ns Write Recovering Time tWR 0 - 0 - 0 - 0 - ns Data Valid to Write End tDW 30 - 35 - 40 - 60 - ns Data Hold Time tDH 0 - 0 - 0 - 0 - ns Write Enable to Output in High-Z tWZ - 30 - 35 - 40 - 50 ns 4,5 Output Active from Write End tOW 5 - 5 - 5 - 5 - ns 4,5 4 REV. 1.2 May 2001 V62C1802048L(L) V62C1802048L(L) Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled) tRC Address tAA tOH DOUT Data Valid Timing Waveform of Read Cycle 2 (5,6,8,9) (CE1 Controlled) tRC CE1 tOE OE tOHZ tCHZ tOLZ tACE DOUT Data Valid tPD tCLZ Supply Current ICC tPU 50% 50% ISB Timing Waveform of Read Cycle 3 (3,6,8,9) (CE2 Controlled) tRC CE2 tOE OE tOLZ DOUT tOHZ tCHZ tACE Data Valid tPD tCLZ Supply Current ICC tPU 50% 50% 5 REV. 1.2 May 2001 V62C1802048L(L) ISB V62C1802048L(L) Timing Waveform of Write Cycle 1 (10,11) (WE Controlled) tAW tWC tWR Address tWP WE tAS tDW DIN tDH Data Valid tWZ tOW DOUT Timing Waveform of Write Cycle 2 (10,11) (CE1 Controlled) tWC tAW tWR Address tAS tCW CE1 tWP WE tWZ tDW DIN tDH Data Valid DOUT Timing Waveform of Write Cycle 3 (10,11) (CE2 Controlled) tWC tAW tWR Address tAS tCW CE2 tWP WE tWZ tDW DIN Data Valid DOUT REV. 1.2 May 2001 V62C1802048L(L) tDH 6 V62C1802048L(L) Data Retention Characteristics (L Version Only)(1) Parameter Symbol Test Condition VCC for Data Retention VDR CE1 > VCC - 0.2V or Data Retention Current ICCDR CE2 < + 0.2V Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or Operation Recovery Time(2) tR VIN < 0.2V Min Max Unit 1.0 - V 1 µA 0 - ns tRC - ns Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C) Data Retention Mode VCC Vcc_typ V DR > 1.0V tCDR CE Vcc_typ tR V DR V IH V IH Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. L-version includes this feature. This Parameter is samples and not 100% tested. For test conditions, see AC Test Condition, Figure A. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. This parameter is guaranteed, but is not tested. WE is HIGH for read cycle. CE1 and OE are LOW and CE2 is HIGH for read cycle. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH. All read cycle timings are referenced from the last valid address to the first transtion address. CE1 or WE must be HIGH or CE2 must be LOW during address transition. All write cycle timings are referenced from the last valid address to the first transition address. 7 REV. 1.2 May 2001 V62C1802048L(L) V62C1802048L(L) Ordering Information Device Type* Speed Package V62C1802048L-70V V62C1802048L-85V V62C1802048L-100V V62C1802048L-150V 70 ns 85 ns 100 ns 150 ns 8x13.4 mm 32-pin Plastic STSOP V62C1802048LL-70V V62C1802048LL-85V V62C1802048LL-100V V62C1802048LL-150V 70 ns 85 ns 100 ns 150 ns V62C1802048L-70T V62C1802048L-85T V62C1802048L-100T V62C1802048L-150T 70 ns 85 ns 100 ns 150 ns V62C1802048LL-70T V62C1802048LL-85T V62C1802048LL-100T V62C1802048LL-150T 70 ns 85 ns 100 ns 150 ns 8 x 20 mm 32-pin Plastic TSOP1 * For Industrial Temperature tested devices, an “I” designator will be added to the end of the Device number. 8 REV. 1.2 May 2001 V62C1802048L(L) MOSEL VITELIC V62C1802048L(L) WORLDWIDE OFFICES U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 JAPAN SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 © Copyright 2001, MOSEL VITELIC Inc. The information in this document is subject to change without notice. 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