VESD09A4A-HS4 Vishay Semiconductors 4-Line (Quad) ESD Protection Diode Array in LLP1010-6L Features • • • • • • • • • • Ultra compact LLP1010-6L package Low package height < 0.4 mm 4-line ESD protection (quad) Low leakage current < 0.1 µA Low load capacitance CD = 6 pF ESD-protection acc. IEC 61000-4-2 ± 8 kV contact discharge ± 10 kV air discharge Surge current acc. IEC 6100-4-5 IPP > 1.5 A Soldering can be checked by standard vision inspection. No X-ray necessary Pin plating NiPdAu (e4) no whisker growth Compliant to RoHS directive 2002/95/EC and in accordance to WEEE 2002/96/EC 5 4 6 1 2 3 20897 20896 Marking (example only) Dot = Pin 1 marking X = Date code Y = Type code (see table below) XY 20932 Ordering Information Ordering code Taped units per reel (8 mm tape on 7" reel) Minimum order quantity VESD09A4A-HS4-GS08 5000 5000 Device name VESD09A4A-HS4 Package Data Device name Package name VESD09A4A-HS4 LLP1010-6L Type code Weight Molding compound flammability rating Moisture sensitivity level Soldering conditions B 1.07 mg UL 94 V-0 MSL level 1 (according J-STD-020) 260 °C/10 s at terminals ** Please see document “Vishay Material Category Policy”: www.vishay.com/doc?99902 Document Number 81803 Rev. 1.4, 02-Mar-10 For technical support, please contact: [email protected] www.vishay.com 1 VESD09A4A-HS4 Vishay Semiconductors Absolute Maximum Ratings Rating Test conditions Symbol Value Unit Peak pulse current BiAs-mode: each input (pin 1, 3 to 5) to ground (pin 2 and 6); acc. IEC 61000-4-5; tp = 8/20 µs; single shot IPPM 1.5 A Peak pulse power BiAs-mode: each input (pin 1, 3 to 5) to ground (pin 2 and 6); acc. IEC 61000-4-5; tp = 8/20 µs; single shot PPP 30 W VESD ±8 kV VESD ± 10 kV TJ - 40 to + 125 °C TSTG - 55 to + 150 °C ESD immunity Contact discharge Acc. IEC61000-4-2; 10 pulses BiAs-mode: each input (pin 1, 3 to 5) to ground (pin 2 and 6) Air discharge Operating temperature Junction temperature Storage temperature BiAs-Mode (4-line Bidirectional Asymmetrical protection mode) With the VESD09A4A-HS4 up to 4 signal- or data-lines (L1 to L4) can be protected against voltage transients. With pin 2 and 6 connected to ground and pin 1, 3, 4 and 5 connected to a signal- or data-line which has to be protected. As long as the voltage level on the data- or signal-line is between 0 V (ground level) and the specified Maximum Reverse Working Voltage (VRWM) the protection diode between data line and ground offer a high isolation to the ground line. The protection device behaves like an open switch. As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The Clamping Voltage (VC) is defined by the BReakthrough Voltage (VBR) level plus the voltage drop at the series impedance (resistance and inductance) of the protection device. Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of the protection diode. The low Forward Voltage (VF) clamps the negative transient close to the ground level. Due to the different clamping levels in forward and reverse direction the VESD09A4A-HS4 clamping behaviour is Bidirectional and Asymmetrical (BiAs). L4 L3 5 4 6 1 L1 2 3 L2 20898 www.vishay.com 2 For technical support, please contact: [email protected] Document Number 81803 Rev. 1.4, 02-Mar-10 VESD09A4A-HS4 Vishay Semiconductors Electrical Characteristics Ratings at 25 °C, ambient temperature unless otherwise specified VESD09A4A-HS4 BiAs mode: each input (pin 1, 3, 4 and 5) to ground (pin 2 and/or 6) Parameter Test conditions/remarks Symbol Number of line which can be protected Nlines at IR = 0.1 µA VRWM at VR = VRWM = 9 V IR at IR = 1 mA VBR Clamping voltage at IPP = 1.5 A acc. IEC 61000-4-5 Forward clamping voltage Protection paths Reverse stand-off voltage Reverse current Reverse breakdown voltage Min. Typ. Max. Unit 4 lines 9 V < 0.01 0.1 µA 13 V VC 23 V at IF = 1.5 A acc. IEC 61000-4-5 VF 2 V at VR = 0 V; f = 1 MHz CD 6.2 10 pF at VR = 4.5 V; f = 1 MHz CD 3.2 4 pF 11.2 Capacitance If a higher surge current or peak pulse current (IPP) is needed, some protection diodes in the VESD09A4A-HS4 can also be used in parallel in order to "multiply" the performance. If two diodes are switched in parallel you get • double surge power = double peak pulse current (2 x IPPM) • half of the line inductance = reduced clamping voltage • half of the line resistance = reduced clamping voltage • double line Capacitance (2 x CD) • double Reverse leakage current (2 x IR) 5 4 6 L1 1 2 L2 3 20900 Document Number 81803 Rev. 1.4, 02-Mar-10 For technical support, please contact: [email protected] www.vishay.com 3 VESD09A4A-HS4 Vishay Semiconductors Typical Characteristics (Tamb = 25 °C, unless otherwise specified) 100 8 µs to 100 % 100 % 10 80 % 1 IF (mA) IPPM 60 % 20 µs to 50 % 0.1 40 % 0.01 20 % 0.001 0.5 0% 0 10 20548 20 30 40 Figure 1. 8/20 µs Peak Pulse Current Wave Form acc. IEC 61000-4-5 0.7 0.8 0.9 1 VF (V) Figure 4. Typical Forward Current IF vs. Forward Voltage VF 120 % 14 Rise time = 0.7 ns to 1 ns 12 100 % 10 80 % 8 VR (V) Discharge Current IESD 0.6 20936 Time (µs) 60 % 53 % 6 40 % 4 27 % 20 % 2 0% - 10 0 10 20 30 40 50 60 70 80 90 100 0.1 1 20937 Time (ns) 20557 0 0.01 Figure 2. ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 Ω/150 pF) 10 100 1000 10000 IR (µA) Figure 5. Typical Reverse Voltage VR vs. Reverse Current IR 7 25 f = 1 MHz 6 20 positive surge 15 4 VC (V) CD (pF) 5 3 Measured acc. IEC 61000-4-5 (8/20 µs - wave form) 10 VC 5 2 0 1 negative surge 0 -5 0 20935 2 4 6 8 10 VR (V) Figure 3. Typical Capacitance CD vs. Reverse Voltage VR www.vishay.com 4 0 20938 1 2 IPP (A) Figure 6. Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP For technical support, please contact: [email protected] Document Number 81803 Rev. 1.4, 02-Mar-10 VESD09A4A-HS4 Vishay Semiconductors 120 acc. IEC 61000-4-2 + 8 kV contact discharge 100 VC-ESD (V) 80 60 40 20 0 - 20 - 10 0 10 20 30 40 50 60 70 80 90 t (ns) 20939 Figure 7. Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 30 acc. IEC 61000-4-2 - 8 kV contact discharge 20 10 VC-ESD (V) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 10 0 10 20 30 40 50 60 70 80 90 t (ns) 20940 Figure 8. Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) 120 acc. IEC 61000-4-2 contact discharge 100 80 positive discharge VC-ESD (V) 60 40 20 VC-ESD 0 - 20 - 40 negative discharge - 60 - 80 0 2000 20941 4000 6000 8000 10000 VESD (kV) Figure 9. Typical Peak Clamping Voltage at ESD Contact Discharge (acc. IEC 61000-4-2) Document Number 81803 Rev. 1.4, 02-Mar-10 For technical support, please contact: [email protected] www.vishay.com 5 VESD09A4A-HS4 Vishay Semiconductors Package Dimensions in millimeters (inches): LLP1010-6L 0.125 (0.005) ref. 0.5 (0.020) exp. DAP 0 (0.000) 0.95 (0.037) 1.05 (0.041) Pin 1 marking 0.03 (0.001) 0.2 (0.008) 0.4 (0.016) 0.15 (0.006) 0.1 (0.004) 0.25 (0.010) 0.33 (0.013) 0.35 (0.014) bsc 0.7 (0.028) ref. 0.22 (0.009) exp. DAP 1.05 (0.041) 0.95 (0.037) Foot print recommendation: 0.5 (0.020) 0.05 (0.002) 0.175 (0.007) 0.35 (0.014) 0.7 (0.028) 0.35 (0.014) 0.3 (0.012) Document no.:S8-V-3906.04-004 (4) Created - Date: 17.July.2007 Rev. 4 - Date: 09. Sep. 2008 20899 Solder resist mask Solder pad Soldermask opening ± 0.03 measured middle of the package 0.22 (0.009) www.vishay.com 6 For technical support, please contact: [email protected] Document Number 81803 Rev. 1.4, 02-Mar-10 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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