VESD09A4A-HSF www.vishay.com Vishay Semiconductors 4-Line (Quad) ESD Protection Diode Array in LLP75-6L FEATURES 6 5 • Compact LLP75-6L package 4 • Low package height < 0.6 mm • 4-line ESD protection (quad) • Low leakage current < 0.1 μA 1 2 3 • Low load capacitance CD = 6 pF 21002 20453 • ESD-protection acc. IEC 61000-4-2 ± 8 kV contact discharge ± 10 kV air discharge 1 MARKING (example only) XX YY • Surge current acc. IEC 61000-4-5 IPP > 1.5 A • Soldering can be checked by standar vision inspection. No X-ray necessary 21001 • e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) Dot = pin 1 marking XX = date code YY = type code (see table below) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 ORDERING INFORMATION DEVICE NAME VESD09A4A-HSF ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VESD09A4A-HSF-GS08 3000 15 000 PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS VESD09A4A-HSF LLP75-6L 49 4.2 mg UL 94 V-0 MSL level 1 (according J-STD-020) 260 °C/10 s at terminals ABSOLUTE MAXIMUM RATINGS VESD09A4A-HSF TEST CONDITIONS SYMBOL VALUE UNIT Peak pulse current BiAs-mode: each input (pin 1, 3 - 5) to ground (pin 2 and 6); acc. IEC 61000-4-5; tp = 8/20 μs; single shot IPPM 1.5 A Peak pulse power BiAs-mode: each input (pin 1, 3 - 5) to ground (pin 2 and 6); acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 30 W Contact discharge acc. IEC 61000-4-2; 10 pulses BiAs-mode: each input (pin 1, 3 - 5) to ground (pin 2 and 6) VESD ±8 kV Air discharge acc. IEC 61000-4-2; 10 pulses BiAs-mode: each input (pin 1, 3 - 5) to ground (pin 2 and 6) VESD ± 10 kV TJ -40 to +125 °C TSTG -55 to +150 °C PARAMETER ESD immunity Operating temperature Storage temperature Rev. 1.5, 16-Jul-15 Junction temperature Document Number: 81834 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VESD09A4A-HSF www.vishay.com Vishay Semiconductors BiAs-MODE (4-line bidirectional asymmetrical protection mode) With the VESD09A4A-HSF up to 4 signal- or data-lines (L1 to L4) can be protected against voltage transients. With pin 2 connected to ground and pin 1, 3, 4 and 6 connected to a signal- or data-line which has to be protected. As long as the voltage level on the data- or signal-line is between 0 V (ground level) and the specified maximum reverse working voltage (VRWM) the protection diode between data line and ground offer a high isolation to the ground line. The protection device behaves like an open switch. As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The clamping voltage (VC) is defined by the breakthrough voltage (VBR) level plus the voltage drop at the series impedance (resistance and inductance) of the protection device. Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of the protection diode. The low forward voltage (VF) clamps the negative transient close to the ground level. Due to the different clamping levels in forward and reverse direction the VESD09A4A-HSF clamping behaviour is bidirectional and asymmetrical (BiAs). L4 L3 6 5 4 1 2 3 L2 L1 21003 ELECTRICAL CHARACTERISTICS VESD09A4A-HSF (Pin 1, 3, 4, or 5 to pin 2) (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of lines which can be protected Nchannel - - 1 lines Max. reverse working voltage VRWM - - 9 V Reverse voltage at IR = 0.1 μA VR 9 - - V Reverse current at VR = VRWM = 9 V IR - < 0.01 0.1 μA Protection paths Reverse stand-off voltage Reverse breakdown voltage at IR = 1 mA VBR 11.2 13 V Reverse clamping voltage at IPP = 1.5 A, acc. IEC 61000-4-5 VC - 23 V Forward clamping voltage at IF = 1.5 A, acc. IEC 61000-4-5 VF - 2 V at VR = 0 V; f = 1 MHz CD - 6.2 10 pF at VR = 4.5 V; f = 1 MHz CD - 3.2 4 pF Capacitance Note • BiAs mode (between pin 1 and pin 2). If a higher surge current or peak pulse current (IPP) is needed, some protection diodes in the VESD09A4A-HSF can also be used in parallel in order to "multiply" the performance. If two diodes are switched in parallel you get • double surge power = double peak pulse current (2 x IPPM) • half of the line inductance = reduced clamping voltage • half of the line resistance = reduced clamping voltage • double line capacitance (2 x CD) • double reverse leakage current (2 x IR) 6 5 4 L2 L1 1 2 3 21004 Rev. 1.5, 16-Jul-15 Document Number: 81834 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VESD09A4A-HSF www.vishay.com Vishay Semiconductors TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) 100 8 µs to 100 % 100 % 10 80 % 1 IF (mA) IPPM 60 % 20 µs to 50 % 40 % 0.1 20 % 0.01 0% 0 10 20 30 Time (µs) 20548 0.001 0.5 40 Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) 0.7 0.8 0.9 1 VF (V) Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF 14 120 % Rise time = 0.7 ns to 1 ns 12 100 % 10 80 % 8 VR (V) Discharge Current IESD 0.6 20936 60 % 53 % 6 40 % 4 27 % 20 % 2 0% -10 0 10 20 30 40 50 60 70 80 90 100 Time (ns) 20557 0 0.01 0.1 1 20937 Fig. 2 - 8/20 µs Peak Pulse Current Wave Form acc. IEC 61000-4-5 10 100 1000 10000 IR (µA) Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR 7 25 f = 1 MHz 6 20 positive surge 5 4 VC (V) CD (pF) 15 3 Measured acc. IEC 61000-4-5 (8/20 µs - wave form) 10 VC 5 2 0 1 negative surge 0 -5 0 20935 2 4 6 8 10 VR (V) Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Rev. 1.5, 16-Jul-15 0 20938 1 2 IPP (A) Fig. 6 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP Document Number: 81834 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VESD09A4A-HSF www.vishay.com Vishay Semiconductors 120 120 100 80 80 positive discharge 60 VC-ESD (V) VC-ESD (V) acc. IEC 61000-4-2 contact discharge 100 acc. IEC 61000-4-2 + 8 kV contact discharge 60 40 40 20 VC-ESD 0 - 20 20 - 40 0 - 20 - 10 0 20939 negative discharge - 60 - 80 0 10 20 30 40 50 60 70 80 90 t (ns) Fig. 7 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 20941 2000 4000 6000 8000 10000 VESD (kV) Fig. 9 - Typical Peak Clamping Voltage at ± ESD Contact Discharge (acc. IEC 61000-4-2) 30 20 10 acc. IEC 61000-4-2 - 8 kV contact discharge VC-ESD (V) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 10 0 20940 10 20 30 40 50 60 70 80 90 t (ns) Fig. 8 - Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) Rev. 1.5, 16-Jul-15 Document Number: 81834 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VESD09A4A-HSF www.vishay.com Vishay Semiconductors 0.45 (0.018) 0.55 (0.022) 0.2 (0.008) 0.3 (0.012) 0.2 (0.008) 0.3 (0.012) 1 (0.039) 0.2 (0.008) 0.3 (0.012) Heat sink 0.95 (0.037) 1.05 (0.041) PACKAGE DIMENSIONS in millimeters (Inches): LLP75-6L 0.5 (0.020) 0.6 (0.024) 0.54 (0.021) 0.60 (0.023) 0.05 (0.002) 0 (0.000) 0.15 (0.006) 0.25 (0.010) 1.65 (0.065) 1.55 (0.061) 1.55 (0.061) 1.65 (0.065) Pin 1 marking Foot print recommendation: 0.5 (0.020) 0.5 (0.020) 0.3 (0.012) 0.3 (0.012) Document no.:S8-V-3906.02-010 (4) Created - Date: 04. MAY 2005 Rev. 4 - Date: 21. March 2006 0.15 (0.006) 1 (0.039) 0.5 (0.020) 1 (0.039) 0.25 (0.010) 0.15 (0.006) Solder resist mask Solder pad 0.5 (0.020) 20454 Rev. 1.5, 16-Jul-15 Document Number: 81834 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VESD09A4A-HSF www.vishay.com Vishay Semiconductors LLP75-6x S9 F5 Pad layout - view from top / seen at bottom side S8-V-3906.02-004 (4) 10.01.2005 Rev. 1.5, 16-Jul-15 Pin 1 - location Document Number: 81834 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000