WM8143-10 10-bit/6MSPS CCD Signal Processor Production Data June 1998 Rev 3f Description Features The WM8143-10 integrates the analogue signal conditioning required by CCD sensors with a 10-bit ADC. The WM8143-10 requires minimal external circuitry and provides a cost-effective sensor to digital domain system solution. • • • • • • • • • • Each of the three analogue conditioning channels includes reset level clamp, CDS, fine offset level shifting and programmable gain amplification. The three channels are multiplexed into the ADC. The output from the ADC is fed to the output bus pins OP[9:0] via a 10/8 bit multiplexer, enabled by the OEB signal. The flexible output architecture allows ten-bit data to be accessed either on a ten-bit bus or via a time-multiplexed eight-bit bus. The WM8143-10 can be configured for pixel-by-pixel or line-by-line multiplexing operation. Reset level clamp and/or CDS features can be optionally bypassed. The device configuration is programmed either via a simple serial interface or via an eight-bit parallel interface. Reset level clamp Correlated double sampling (CDS) Fine offset level shifting Programmable gain amplification 10-bit ADC with maximum 6 MSPS Simple clocking scheme Control by serial or parallel interface Time multiplexed eight-bit data output mode 32 pin TQFP package Interface compatible with WM8144-10 and WM8144-12 Applications • • • • • Flatbed scanners Sheet feed scanners Film scanners CCD sensor interfaces Contact image sensor (CIS) interfaces The serial/parallel interfaces of the WM8143-10 are control compatible with those of the WM8144-10 and WM8144-12. Block Diagram VRLC VRU VRT VRB VMID VSMP MCLK RLC AGND DGND DVDD AVDD MUX CL RS TIMING CONTROL VS VMID OFFSET S/H RINP + PGA + S/H WM8143-10 CDS 5-BIT REG 8-BIT + SIGN DAC VMID OFFSET S/H GINP + PGA + S/H M U X OEB 10-bit ADC 10/8 MUX OP[9:0] CDS 5-BIT REG 8-BIT + SIGN DAC VMID OFFSET S/H BINP + PGA + S/H CDS 5-BIT REG 8-BIT + SIGN DAC VMID CONFIGURABLE SERIAL/PARALLEL CONTROL INTERFACE SDI / DNA SCK / RNW SEN / STB NRESET Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronic's terms and conditions. Wolfson Microelectronics Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 email: [email protected] www: http://www.wolfson.co.uk 1998 Wolfson Microelectronics Ltd. WM8143-10 Production Data SDI/DNA SEN/STB OEB RINP GINP BINP VRLC VMID 23 22 21 20 19 18 17 Ordering Information 24 Pin Configuration DEVICE 25 16 VRT RLC 26 15 VRB VSMP 27 14 VRU MCLK 28 13 AGND DGND 29 12 AVDD nc 30 11 NRESET nc 31 10 OP[9] DVDD 32 9 OP[8] 1 2 3 4 5 6 7 8 OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] PACKAGE o WM8143-10CFT/V SCK/RNW WM8143-10 TEMP. RANGE 0 - 70 C 32 Pin TQFP Absolute Maximum Ratings Analogue Supply Voltage .......... AGND - 0.3V, AGND +7V Operating Temperature Range, TA .......... 0°C to +70°C Digital Supply Voltage ...............DGND - 0.3V, DGND +7V Storage Temperature.......................... -50°C to +150°C Digital Inputs .......................... DGND - 0.3V, DVDD +0.3V Lead Temperature (soldering 10 seconds) ....... +260°C Digital Outputs ....................... DGND - 0.3V, DVDD +0.3V Reference Inputs ....................AGND - 0.3V, AVDD +0.3V RINP, GINP, BINP..................AGND - 0.3 V, AVDD +0.3V Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112-A and A113-A, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. Recommended Operating Conditions PARAMETER Supply Voltage Operating Temperature Range Input Common Mode Range SYMBOL TEST CONDITIONS AVDD, DVDD MIN 4.75 TYP MAX 5.25 TA 0 70 VCMR 0.5 4.5 Wolfson Microelectronics 2 UNIT V o C V PD Rev 3f June 98 WM8143-10 Production Data Electrical Characteristics Test Characteristics AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V … TA = 0oC to +70oC, MCLK = 12MHz, unless otherwise stated PARAMETER SYMBOL TEST CONDITIONS MIN Supply Current - Active Supply Current - Standby TYP MAX UNIT 100 140 mA 7 15 mA Digital Inputs High Level Input Voltage VIH Low Level Input Voltage VIL 0.2*DVDD V High Level Input Current IIH 1 µA Low Level Input Current IIL 1 µA 0.8*DVDD Input Capacitance V 5 pF Digital Outputs High Level Output Voltage VOH IOH = 1mA Low Level Output Voltage VOL IOL= 1mA High Impedance Output Current IOZ DVDD-0.75 V DGND+0.75 V 1 µA Input Multiplexer CDS Mode Full Scale Input Range (VVS-VRS) x denotes the channel selected Channel to Channel Gain Matching Input Video Set-up Time Input Video Hold Time Reset Video Set-up Time 2 Gx Vp-p 1 % tVSU 10 ns tVH 15 ns tRSU CDS Mode only 10 ns tRH CDS Mode only 15 ns Reference Voltage – Top VRT VRU = 5V 3.47 3.5 3.53 V Reference Voltage – Bottom VRB VRU = 5V 1.47 1.5 1.53 V DAC Reference Voltage VMID VRU = 5V 2.47 2.5 2.53 Reset Video Hold Time Reference String R.L.C. Switching Impedance Reset Level Clamp Options VRLC VRU=5V Voltage set by register configuration V Ω 500 1.46 1.5 1.54 V 2.46 2.5 2.54 V 3.46 3.5 3.54 V Impedance VRT to VRB 250 500 750 Ω Impedance VRU to AGND 1000 1500 2000 Ω 8-Bit DACs Resolution 8 Zero Code Voltage Full Scale Voltage Error VMID +20 mV 0 20 mV Wolfson Microelectronics 3 Bits VMID -20 PD.Rev 3f June 98 WM8143-10 Production Data Test Characteristics AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V … TA = 0oC to +70oC, MCLK = 12MHz, unless otherwise stated PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Differential Non Linearity DNL 0.1 0.5 LSB Integral Non Linearity INL 0.25 1 LSB 10-bit ADC performance including CDS, PGA and Offset Functions NO MISSING CODES GUARANTEED Resolution AVDD = DVDD = 5V 10 Bits Maximum Sampling Rate AVDD = DVDD = 5V 6 MSPS Zero Scale Transition Error Voltage at VINP DAC Code = 000H, AVDD = DVDD = 5V, measured relative to VRB ± 25 ±100 mV Full Scale Transition Error Voltage at VINP DAC Code = 000H, AVDD = DVDD = 5V, measured relative to VRT ± 25 ±100 mV +1 LSB Differential Non Linearity DNL AVDD = DVDD = 5V PGA Gain Monotonicity Guaranteed Red Channel Max Gain Gr Mode 1 7 7.5 Times Green Channel Max Gain Gg AVDD = DVDD = 5V 7.5 8 Times Blue Channel Max Gain Gb 7.5 8 Times MCLK Period tPER 83.3 ns MCLK High tCKH 37.5 ns MCLK Low tCKL 37.5 ns Data Set-up Time tDSU 10 ns Switching Characteristics Data Hold Time tDH Output Propagation Delay tPD Output Enable Time Output Disable Time 10 IOH=1mA, IOL=1mA ns 75 ns tPZE 50 ns tPEZ 25 ns Serial Interface SCK Period tSPER 83.3 ns SCK High tSCKH 37.5 ns SCK Low tSCKL 37.5 ns SDI Set up Time tSSU 10 ns tSH 10 ns Set up Time - SCK to SEN tSCE 20 ns Set up Time - SEN to SCK tSEC 20 ns SDI Hold Time Wolfson Microelectronics 4 PD Rev 3f June 98 WM8143-10 Production Data Test Characteristics AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V … TA = 0oC to +70oC, MCLK = 12MHz, unless otherwise stated PARAMETER SEN Pulse Width SYMBOL TEST CONDITIONS tSEW MIN TYP MAX 50 UNIT ns Parallel Interface RNW Low to OP[9:2] Tri-state tOPZ Address Setup Time to STB Low tASU 0 ns DNA Low Setup Time to STB Low tADLS 10 ns Strobe Low Time tSTB 50 ns Address Hold Time from STB High tAH 10 ns DNA Low Hold Time from STB High tADLH 10 ns Data Setup Time to STB Low tDSU 0 ns DNA High Setup Time to STB Low tADHS 10 ns Data Hold Time from STB High tDH 10 ns Data High Hold Time from STB High tADHH 10 ns tOPD 0 ns RNW High to OP[9:2] Output 20 Wolfson Microelectronics 5 ns PD.Rev 3f June 98 WM8143-10 Production Data Pin Description PIN NAME TYPE 1 OP[0] Digital OP Tri-state digital 10-bit bi-directional bus. There are four modes: DESCRIPTION 2 OP1] Digital OP Tri-state: when OEB = 1 3 OP[2] Digital IO Output ten-bit: ten bit data is output from bus 4 OP[3] Digital IO Output 8-bit multiplexed: 5 OP[4] Digital IO data output on OP[9:2] at 2 * ADC conversion rate 6 OP[5] Digital IO Input 8-bit: 7 OP[6] Digital IO control data is input on bits OP[9:2] in parallel mode when SCK/RNW = 0. 8 OP[7] Digital IO 9 OP[8] Digital IO 10 OP[9] Digital IO 11 NRESET Digital IP 12 AVDD Analogue supply 13 AGND Analogue supply 14 VRU Analogue IP 15 VRB Analogue OP 16 VRT Analogue OP ADC reference voltages. The ADC reference range is applied between VRT (full scale) and VRB (zero level). VRU can be used to derive optimal reference voltages from an external 5V reference 17 VMID Analogue OP Buffered mid-point of ADC reference string. 18 VRLC Analogue OP Selectable analogue output voltage for RLC 19 BINP Analogue IP Blue channel input video 20 GINP Analogue IP Green channel input video 21 RINP Analogue IP Red channel input video 22 OEB Digital IP Output tri-state control: all outputs enabled when OEB=0 23 SEN/STB Digital IP Serial interface: enable, active high Parallel interface: strobe, active low MSB of the output word is OP[9], LSB is OP[0] Reset input, active low. This signal forces a reset of all internal registers and selects whether serial control bus or parallel control bus is used ( see SEN/STB) Positive analogue supply (5V) Analogue ground (0V) Latched on NRESET rising edge: If low then device control is by serial interface, if high then device control is by parallel interface 24 SDI/DNA Digital IP 25 SCK/RNW Digital IP Serial interface: serial interface input data signal Parallel interface: high = data, low = address Serial interface: serial interface clock signal Parallel interface: high = OP[9:2] is output bus low = OP[9:2] is input bus 26 RLC Digital IP Selects whether reset level clamp is applied on a pixel-by-pixel basis. If RLC is required on each pixel then this pin can be tied high 27 VSMP Digital IP Video sample synchronisation pulse. This signal is applied synchronously with MLCK to specify the point in time that the input is sampled. The timing of internal multiplexing between the R, G and B channels is derived from this signal 28 MCLK Digital IP Master clock. This clock is applied at eight, six, three or two times the input pixel rate depending on the operational mode. MCLK is divided internally to define the ADC sample rate and to provide the clock source for digital logic Wolfson Microelectronics 6 PD Rev 3f June 98 WM8143-10 Production Data PIN NAME TYPE 29 DGND Digital supply 30 nc Reserved, pin must be left unconnected 31 nc Reserved, pin must be left unconnected 32 DVDD Digital supply DESCRIPTION Digital ground (0V) Positive digital supply (5V) Typical Performance o AVDD = DVDD = 5V, TA = 25 C WM8143-10 DNL 2 1.5 1 LSB's 0.5 0 -0.5 -1 -1.5 -2 0 256 512 768 1024 ADC Code PGA Gain Code PGA Gain Code vs Actual Gain 8.25 8 7.75 7.5 7.25 7 6.75 6.5 6.25 6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 3.75 3.5 3.25 3 2.75 2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 RED GREEN BLUE 0 1 2 3 4 5 6 7 8 9 Actual Gain Wolfson Microelectronics 7 PD.Rev 3f June 98 WM8143-10 Production Data System Description COLOUR CCD SENSOR BUFFERING FOR CCD RED RINP OP[9:0] PARALLEL DATA I/O WM8143-10 OEB SDI/DNA SCK/RNW SEN/STB NRESET GREEN GINP VSMP MCLK RLC BLUE CONTROL/SERIAL DATA IN ANALOGUE INTERFACE TIMING BINP Figure 1 System Diagram The digital interface to the WM8143-10 can be divided into three distinct sections: - The WM8143-10 signal processing IC interfaces typically via buffering and AC coupling to the output of CCD image sensors. The WM8143-10 also interfaces to CIS image sensors via DC coupling. • • • Analogue output signals from the image sensor are sampled, amplified and offset-corrected by the IC before being converted into digital form by an on-board high-speed 10-bit resolution analogue to digital converter. Figure 1 illustrates a typical system implementation where the three colour outputs from the CCD image sensor are buffered and AC coupled to the analogue inputs of the WM8143-10. Parallel Data I/O Digital Control/Serial Timing Analogue Interface Timing These sections are constructed for ease of use by the system designer and are described in detail on the following pages of this datasheet. Wolfson Microelectronics 8 PD Rev 3f June 98 WM8143-10 Production Data Table 1 illustrates the PGA Gains Register codes required for typical gains. (See Typical Performance Graphs). The typical gain may also be calculated using the following equation: Device Description S/H, Offset DACs and PGA Each analogue input (RINP, GINP, BINP) of the WM8143-10 consists of a sample and hold, a programmable gain amplifier, and a DC offset correction block. The operation of the red input stage is summarised in Figure 2. Typical Gain = 0.5+(Code∗0.25). CODE TYPICAL CODE TYPICAL 00000 GAIN 0.5 10000 GAIN 4.5 00001 0.75 10001 4.75 00010 1 10010 5 00011 1.25 10011 5.25 Figure 2 Operation of Red Input Stage 00100 1.5 10100 5.5 The sample/hold block can operate in two modes of operation, CDS (Correlated Double Sampling) or Single Ended. 00101 1.75 10101 5.75 00110 2 10110 6 In CDS operation the video signal processed is the difference between the voltage applied at the RINP input when RS occurs, and the voltage at the RINP input when VS occurs. This is summarised in Figure 3. 00111 2.25 10111 6.25 01000 2.5 11000 6.5 01001 2.75 11001 6.75 01010 3 11010 7 01011 3.25 11011 7.25 01100 3.5 11100 7.5 01101 3.75 11101 7.75 Figure 3 Video Signal Processed in CDS mode 01110 4 11110 8 When using CDS the actual DC value of the input signal is not important, as long as the signal extremes are maintained within 0.5 volts of the chip power supplies. This is because the signal processed is the difference between the two sample voltages, with the common DC voltage being rejected. 01111 4.25 11111 8.25 RINP + S/H GAIN=G VS + VADC - S/H VOFFSET VMID + VMID RS VRS VVS RS VS Table 1 Typical Gain The DC value of the gained signal can then be trimmed by the 8 bit plus sign DAC. The voltage output by this DAC is shown as VOFFSET in Figure 2. The range of the DAC is (VMID/2) or 1.5*(VMID/2) if the DAC_RANGE bit in Set-up Register 4 is set. In Single Ended operation, the VS and RS control signals occur simultaneously, and the voltage applied to the reset switch is fixed at VMID. This means that the voltage processed is the difference between the voltage applied to RINP when VS/RS occurs, and VMID. When using Single Ended operation the DC content of the video signal is not rejected. The output from the offset DAC stage is referenced to the VMID voltage. This allows the input to the ADC to maximise the dynamic range, and is shown diagrammatically in Figure 2 by the final VMID addition. The Programmable Gain Amplifier block multiplies the resulting input voltage by a value between 0.5 and 8.25 which can be programmed independently for each of the three input channels via the serial (or parallel) interface. Wolfson Microelectronics 9 PD.Rev 3f June 98 WM8143-10 Production Data For the input stage, the final analogue voltage applied to the ADC can be expressed as: VADC = G * (VVS − VRS) + [(1 − 2 * DSIGN) * DAC_CODE 255 * VMID 2 dependent on the type of sampling selected and the polarity of the input video signal. ] + VMID MCLK Where VADC is the voltage applied, to the ADC G is the programmed gain VVS is the voltage of the video sample. VRS is the voltage of the reset sample, DSIGN is the Offset DAC sign bit DAC_CODE is the offset DAC value. VMID is the WM8143-10 generated VMID voltage. VSMP VS CL 00 RS CL 01 (default) The ADC has a lower reference of VRB (typically 1.5 V) and an upper reference of VRT (typically 3.5 V). When an ADC input voltage is applied to the ADC equal to VRB the resulting code is 000(hex). When an ADC input voltage is applied to the ADC equal to VRT the resulting code is 3FF(hex). RS CL 10 RS CL 11 RS Reset Level Clamp Both CDS and Single Ended operation can be used with Reset Level Clamping. A typical input configuration is shown in Figure 4. Figure 5 Reset Sample and Clamp Timing For CDS operation it is important to match the clamp voltage to the amplitude and polarity of the video signal. This will allow the best use of the wide input common-mode range offered by the WM8143-10. If the input video is positive going it is advisable to clamp to VCL (Lower clamp voltage). If the video is negative going it is advisable to clamp to VCU (Upper clamp voltage). Regardless of where the video is clamped the offset DAC is programmed to move the ADC output corresponding to the reset level to an appropriate value to maximise the ADC dynamic range. For Single Ended operation it is recommended that the clamp voltage is set to VCM (middle clamp voltage). WM8143-10 RINP S/H + Cin Gain=G VS S/H - RS VRLC VMID Figure 4 Typical Input Configuration Using Reset VIDEO INPUT Level Clamping The position of the clamp relative to the video sample is shown diagramatically in Figure 6 and is programmable by CDSREF1-0 (see Table 6). By default, the reset sample occurs on the fourth MCLK rising edge after VSMP. The relative timing between the reset sample (and CL) and video sample can be altered as shown in Figure 5. When the clamp pulse is active the voltage on the WM8143-10 side of Cin, i.e. RINP, will be forced to be equal to the VRLC clamp voltage. The VRLC clamp voltage is programmable to three different levels via the serial interface. The voltage to which the clamp voltage should be programmed is CLAMP PULSE Figure 6 Position of Clamp Relative to Video Input A reset level clamp is activated if the RLC pin is high on an MCLK rising edge (Figure 7). By default this initiates an internal clamp pulse three MCLK pulses later (shown as CL in Figure 5). The relationship between CL and RS is fixed. Therefore altering the RS position also alters the CL position (Figure 5). Table 6 shows the three possible voltages to which the reset level can be clamped. Wolfson Microelectronics 10 PD Rev 3f June 98 WM8143-10 Production Data to 4 MSPS. This is achieved by altering the MCLK:VSMP ratio to 3:1. In this mode, the timing of RS and CL must be fixed (refer to Table 3). The sampled video data will pass through the internal pipeline and emerge on the OP[9:0] bus. MCLK VSMP RLC Input video 1 X X 0 r,g,b X r,g,b RLC on this pixel X 0 X Max. Speed Monochrome Mode (Mode 4) r,g,b No RLC on this pixel Figure 12 summarises the timing relationships. This mode allows the maximum sample rate to be increased to 6 MSPS. This is achieved by altering the MCLK:VSMP ratio to 2:1. The latency through the device is identical to modes 1 and 2. CDS is not available in this mode. Figure 7 RLC Timing Video Sampling Options The WM8143-10 can interface to CCD sensors using six basic modes of operation (summarised in Table 3). Mode configurations are controlled by a combination of control bits and timing applied to MCLK and VMSP pins. The default operational mode is mode 1: colour with CDS enabled. Slow Colour Mode (Mode 5) Figure 13 summarises the timing relationships. This mode is identical to Mode 1 except that the MCLK to VSMP ratio is 8 : 1 and the maximum sample rate is 1.5 MSPS. To obtain a ratio of 4:4 between the video sample position and the reset sample position, Setup Register 3 CDSREF1-0 control bits b[5:4] should be set to 10. The first three of the four output words are valid. Colour Mode Definitions (Mode 1) Figure 9 summarises the timing relationships. MCLK is applied at twice the required ADC conversion rate. Synchronisation of sampling and channel multiplexing to the incoming video signal is performed by the VSMP pulse (active high). The three input channels (R,G,B) are sampled in parallel on the rising edge of MCLK following a VSMP pulse. The sampled data is multiplexed into a single data stream at three times the VSMP rate, passes through the internal pipeline and emerges on the OP[9:0] bus. Both Correlated Double Sampling (CDS) and Single Ended Sampling modes of operation are available. Slow Monochrome Mode (Mode 6) Figure 14 summarises the timing relationships. This mode is identical to mode 2 except that the MCLK to VSMP ratio is 8 : 1 and the maximum sample rate is 1.5 MSPS. To obtain a ratio of 4:4 between the video sample position and the reset sample position, Setup Register 3 CDSREF 1-0 control bits b[5:4] should be set to 10. The first of the four output words is the only valid output. Monochrome Mode Definitions Input Impedance One input channel is continuously sampled on the rising edge of MCLK following a VSMP pulse. The user can specify which input channel (R,G,B) is to be sampled by writing to the WM8143-10 internal control registers. There are four separate monochrome modes with different maximum sample rates and CDS availability. The input impedance of the WM8143-10 is dependent upon the sampling frequency of the input signal and the gain that the PGA is set to. This is due to the effective capacitance of the ‘sample and hold’ circuits (Figure 8). S/H Monochrome Mode (Mode 2) RINP/VMID PGA C Figure 10 summarises the timing relationships. The timing in this mode is identical to mode 1 except that one input channel is sampled three times (due to the multiplexer being held in one position) and passes through the device as three separate samples. The last two samples can be ignored at the output OP[9:0]. VMID VS/RS Figure 8 Input Impedance S/H Circuit When the VS/RS control is activated the switch closes and the effective impedance of the input is 1/CF where the value of C changes from 0.3pF for minimum gain to Fast Monochrome Mode (Mode 3) Figure 11 summarises the timing relationships. This mode allows the maximum sample rate to be increased Wolfson Microelectronics 11 PD.Rev 3f June 98 WM8143-10 Production Data 9.6pF for maximum gain and F is the sample frequency in Hz. Table 2 illustrates the maximum and minimum input impedance at different frequencies. SAMPLING FREQUENCY (MHz) IMPEDANCE (MΩ Ω ) MIN. GAIN IMPEDANCE (KΩ Ω ) MAX. GAIN 0.5 6.6 208 1 3.3 104 2 1.6 52 4 0.8 26 6 0.5 17 Table 2 Effects of Frequency on Input Impedance Calibration To achieve optimum performance of the WM8143-10, a calibration procedure must be implemented. This is achieved by using a combination of the gain and offset functions to amplify and shift the input signal so that it lies within and maximises the input ADC range. Wolfson Microelectronics 12 PD Rev 3f June 98 WM8143-10 Production Data MODE DESCRIPTION CDS AVAILABLE MAX. SAMPLE RATE SENSOR INTERFACE DESCRIPTION TIMING REQUIREMENTS REGISTER CONTENTS WITH CDS REGISTER CONTENTS WITHOUT CDS* 1 Colour Yes 2MSPS Three input channels (R, G, B) are sampled in parallel at max. 2MSPS. The sampled data is multiplexed into a single data stream before the internal ADC, giving an internal serial rate of max. 6MSPS MCLK max. 12MHz. MCLK: VSMP ratio is 6:1 Setup Reg. 1: 03(H) Setup Reg. 1: 01(H) 2 Monochrome Yes 2MSPS One input channel is continuously sampled. The internal multiplexer is held in one position under control of the user. Identical to Mode 1 Setup Reg. 1: 07(H) Setup Reg. 3: bits b[7-6] define which channel is sampled Setup Reg. 1:05(H) Setup Reg. 3: bits b[7-6] define which channel is sampled 3 Fast Monochrome Yes 4MSPS Identical to Mode 2 except that max. sample rate is 4MSPS MCLK max. 12MHz. MCLK: VSMP ratio is 3:1 Identical to Mode 2 plus Setup Reg. 3: bits b[5-4] must be set to 00(H) Identical to Mode 2 4 Max. Speed Monochrome No 6MSPS Identical to Mode 2 except that max. sample rate is 6MSPS MCLK max. 12MHz. MCLK: VSMP ratio is 2:1 Not applicable Setup Reg. 1:45(H) Setup Reg. 3: bits b[7-6] define which channel is sampled 5 Slow Colour Yes 1.5MSPS Identical to Mode 1 except that max. sample rate is 1.5MSPS MCLK max. 12MHz. MCLK: VSMP ratio is 8:1 Identical to Mode 1 Identical to Mode 1 6 Slow Monochrome Yes 1.5MSPS Identical to Mode 2 except that max. sample rate is 1.5MSPS MCLK max. 12MHz. MCLK: Identical to Mode 2 Identical to Mode 2 VSMP ratio is 8:1 * Only indicates relevant register bits Table 3 WM8143-10 Mode Summary Wolfson Microelectronics 13 PD.Rev 3f June 98 WM8143-10 INPUT Production Data MCLK SIGNALS VSMP Input r1,g1,b1 video r2,g2,b2 3 2 INTERNALRS SIGNALS r4,g4,b4 r3,g3,b3 1 r5,g5,b5 4 5 3 2 5 4 VS b0 ADC input g1 r1 b1 r2 g2 b2 r3 g3 b3 r4 g4 b4 ADC sample 16.5 MCLK periods OUTPUT OP[9:0] SIGNALS g1 r1 b1 Figure 9 Default Timing in CDS Colour Mode (Mode 1) MCLK INPUT SIGNALS VSMP Input r1,g1,b1 video r2,g2,b2 r4,g4,b4 r3,g3,b3 2 3 r5,g5,b5 4 5 RS INTERNAL SIGNALS 1 3 2 5 4 VS ADC input X X r1 X X X X X X X ADC sample 16.5 MCLK periods OUTPUT OP[9:0] * X X X X X X r1 X X X SIGNALS * This example shows function when Red channel selected. 'X' indicates don't care Figure 10 Default Timing in CDS Monochrome Mode (Mode 2) Wolfson Microelectronics 14 PD Rev 3f June 98 WM8143-10 Production Data MCLK INPUT SIGNALS VSMP Input video n n+1 RS INTERNAL SIGNALS VS n ADC input ADC sample 23.5 MCLK periods OUTPUT SIGNALS n OP[9:0] * This example shows function when Red channel selected. Figure 11 Default Timing in Fast CDS Monochrome Mode (Mode 3) MCLK INPUT SIGNALS VSMP Input video INTERNAL SIGNALS VS ADC input n 1 n ADC sample 16.5 MCLK periods OUTPUT n OP[9:0] SIGNALS * This example shows function when Red channel selected. Figure 12 Default Timing in Max. Speed non-CDS Monochrome Mode (Mode 4) Wolfson Microelectronics 15 PD.Rev 3f June 98 WM8143-10 Production Data MCLK INPUT SIGNALS VSMP Input r1,g1,b1 video r2,g2,b2 r4,g4,b4 r3,g3,b3 3 2 r5,g5,b5 4 5 RS INTERNAL SIGNALS 1 3 2 4 5 VS ADC input b0 r1 g1 b1 X r2 g2 b2 X r3 g3 b3 X r4 g4 b4 X ADC sample 16.5 MCLK periods OUTPUT OP[9:0] SIGNALS r1 g1 b1 X 'X' indicates an invalid output Figure 13 Default Timing in Slow CDS Colour Mode (Mode 5) INPUT MCLK SIGNALS VSMP Input r1,g1,b1 video r2,g2,b2 3 2 INTERNAL RS SIGNALS r4,g4,b4 r3,g3,b3 1 r5,g5,b5 5 4 5 4 3 2 VS ADC input b0 r1 X X X r2 X X X r3 X X X r4 X X X ADC sample 16.5 MCLK periods OUTPUT OP[9:0] SIGNALS r1 X X X This example shows function when Red channel selected. 'X' indicated invalid output. Figure 14 Default timing in Slow Monochrome Mode (Mode 6) Wolfson Microelectronics 16 PD Rev 3f June 98 WM8143-10 Production Data It is expected that this would be achieved on system power-up by attaching a simple RC network to the NRESET pin. The RC network should delay the set-up on the NRESET pin until the other conditions have been established. This feature is only activated on a hardware reset (using the NRESET pin). The software reset does not sample SEN/STB. Applications Recommendations Output Data Interface By default, data is output from the device as a ten-bit wide word on OP[9:0]. Optionally, data can be output in an eight-bit word format. Figure 15 shows this function. Data is presented on pins OP[9:2] at twice pixel rate. Controlling the WM8143-10 In mode 3, the output is spread over three MCLK periods. The first two periods contain byte A data and the third period has byte B data. Either of the two byte A data periods are valid. The WM8143-10 can be configured through a serial interface or a parallel interface. Selection of the interface type is by the SEN/STB pin which must be tied high (parallel) or low (serial) as shown in Table 4. Serial Interface MCLK OP[9:2] A The serial interface consists of three pins (refer to Figure 16). A six-bit address is clocked in MSB first followed by an eight-bit data word, also MSB first. Each bit is latched on the rising edge of SCK. Once the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. B Figure 15 Eight-bit Multiplexed Bus Output • A =d9,d8,d7,d6,d5,d4,d3,d2 - First byte • B =d1,d0,X,X,PNS,CC1,CC0,ORNG - Second byte • PNS : This bit shows if the device is configured in parallel or serial mode. 1 = Parallel, 0 = Serial. • CC1/CC0 : These bits show which channel the current output was taken from. 00 = RED, 01 = GREEN, 10 = BLUE. • ORNG : This bit indicates if the current output pixel has exceeded the maximum or minimum range during processing. 1 = out of range, 0 = within range. • Parallel Interface The parallel interface uses bits [9:2] of the OP bus as well as the STB, DNA and RNW pins (refer to Figure 17). Pin RNW must be low during a write operation. The DNA pin defines whether the data byte is address (low) or data (high). The data bus OP[9:2] is latched in during the low period of STB. Internal Register Definition Table 5 summarises the internal register content. The first 5 addresses in the table are used to program setup registers and to provide a software reset feature (00H is reserved). The remaining 3 entries in the table define the address location of internal data registers. In each case, a further three sub-addresses are defined for the red, green and blue register. Selection between the red, green and blue registers is performed by address bits a1 and a0, as defined in the table. Setting both a1 and a0 equal to 1 forces all three registers to be updated to the same data value. Blank entries in Table 5 should be programmed to zero. X: This is an invalid output. Control Interface Selection WM8143-10 can be controlled via a serial or parallel interface. The decision on which interface is to be used is made on the sense of the SEN/STB pin on the rising edge of the NRESET signal. SEN/STB CONDITION MODE 0 NRESET rising edge Serial Interface 1 NRESET rising edge Parallel Interface Table 4 WM8143-10 Interface Set-up SCK SDI a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 SEN Address b3 b2 b1 b0 Data Word Figure 16 Serial Interface Timing Wolfson Microelectronics 17 PD.Rev 3f June 98 WM8143-10 Production Data Figure 17 Parallel Interface Timing STB Address OP[9:2] Data DNA RNW ADDRESS <a5:a0> DESCRIPTION 000000 Reserved 000001 Setup DEFAULT (HEX) BIT b7 03 b6 b5 b4 VSMP6M b3 b2 b1 b0 MONO CDS ENADC Register 1 000010 Setup 00 INVOP MUXOP Register 2 000011 Setup 11 CHAN[1] CHAN[0] CDSREF[1] CDSREF[0] RLC[1] RLC[0] Register 3 000100 Software Reset 00 000101 Setup Register 4 00 1000a1a0 DAC Values 00 1001a1a0 DAC Signs 00 1010a1a0 PGA Gains 00 DACRNG DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] DSIGN PGA[4] ADDRESS LSB DECODE a1 a0 Red Register 0 0 Green Register 0 1 Blue Register 1 0 Red, Green and Blue 1 1 PGA[3] PGA[2] PGA[1] PGA[0] Table 5 Register Map Contents Wolfson Microelectronics 18 PD Rev 3f June 98 WM8143-10 Production Data REGISTER BIT NO BIT NAMES(S) DEFAULT DESCRIPTION Setup Register 1 0 ENADC 1 ADC Standby Control: 0 = Standby, 1 = Active Address ,<a5:a0> 000001 1 CDS 1 Correlated Double Sampling Mode: 0 = Single Ended Mode, 1 = CDS Mode 2 MONO 0 Mono/Colour Select: 0 = Colour, 1 = Monochrome Operation 6 VSMP6M 0 Required when operating in Mode 4: 0 = Other Modes, 1 = Mode 4 Setup Register 2 Address ,<a5:a0> 000010 0 MUXOP 0 Eight Bit Output Mode: 0 = 10-bit, 1 = 8-bit Multiplexed 2 INVOP 0 Inverts ADC Output: 0 = Non-inverting, 1 = Inverting Setup Register 3 Address ,<a5:a0> 000011 1-0 RLC1-0 01 Reset Level Clamp Voltage: 00 = 1.5V 01 = 2.5V 10 = 3.5V 11 = Reserved 5-4 CDSREF1-0 01 CDS Mode Reset Timing Adjust: 00 = Advance 1 MCLK Period 01 = Normal 10 = Retard 1 MCLK Period 11 = Retard 2 MCLK Periods 7-6 CHAN1-0 00 Monochrome Mode Channel Select: 00 = Red channel 01 = Green channel 10 = Blue channel 11 = Reserved Setup Register 4 Address ,<a5:a0> 000101 1 DACRNG 0 Offset DAC Output Range: 0 = DAC Output Range = Vmid/2 = +/-1.25V 1 = DAC Output Range = 1.5 ∗(Vmid/2) = +/-1.875V Table 6 Control Bit Descriptions Wolfson Microelectronics 19 PD.Rev 3f June 98 WM8143-10 Production Data Detailed Timing Diagrams MCLK tDSU tDSU tDH tDH VSMP, RLC tVSU tVH tVSU tVH tVSU tVH tVSU tVH tVSU tVH R,G,B Video Inputs (Default Mode) tVSU tVH tVSU tVH R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0) tRSU R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=1) tVSU tRH tVH tRSU R,G,B Video Inputs (CDSREF[1]=1,CDSREF[0]=0) tVSU tVH tRH tRSU R,G,B Video Inputs (CDSREF[1]=1,CDSREF[0]=1) tRH tRSU tRH Figure 18 Detailed Video Input Timing - Modes 1 and 2 MCLK tDSU tDH tDH tDSU VSMP, RLC tVSU tVSU tVH tVH R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0) tRSU tRH Figure 19 Detailed Video Input Timing - Mode 3 MCLK tDSU tDH VSMP, RLC tVSU R,G,B Video Inputs RESET tVH tVSU tVH VIDEO Figure 20 Detailed Video Input Timing - Mode 4 Wolfson Microelectronics 20 PD Rev 3f June 98 WM8143-10 Production Data MCLK tDSU tDSU tDH tDH VSMP, RLC R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0) tVSU tVH tVSU tVH tRSU R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0) tVSU tRH tVH R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0) tRSU tVSU R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0) tRH tVH tRSU tRH tRSU tVSU tVH tVSU tVH tVSU tVH tVSU tVH tRH Figure 21 Detailed Video Timing - Modes 5 and 6 tCKH tCKL tPER MCLK tDH tDSU VSMP, RLC tPD OP[9:0] RED GREEN BLUE Figure 22 Detailed Digital Timing - Modes 1 and 2 tCKH tCKL tPER MCLK tDSU VSMP, RLC tDH tDSU tDH tPD t PD OP[9:0] Figure 23 Detailed Digital Timing – Mode 3 Wolfson Microelectronics 21 PD.Rev 3f June 98 WM8143-10 Production Data tCKH tCKL tPER MCLK tD H tDS U VSMP, RLC tD H tDS U tPD t PD OP[9:0] Figure 24 Detailed Digital Timing – Mode 4 tCKH tCKL tPER MCLK tDSU tDH VSMP, RLC tPD OP[9:0] X RED X BLUE GREEN 'X' Indicates Invalid Output Figure 25 Detailed Digital Timing – Modes 5 and 6 tSCKH tSPER tSCKL SCK tSH tSSU SDI tSCE tSEW tSEC SEN Figure 26 Detailed Timing Diagram for Serial Interface tSTB STB OP[9:2] tASU Data Out Z tSTB tAH Address In tADLS tDH tDSU Z Data In tADLH tADHS Data Out tADHH DNA RNW tOPZ tOPD Figure 27 Detailed Timing Diagram for Parallel Interface Wolfson Microelectronics 22 PD Rev 3f June 98 WM8143-10 Production Data SEN/STB OEB RINP GINP BINP VRLC 23 22 21 20 19 VMID SDI/DNA 24 Applications Diagram SCK/RNW 25 16 RLC 26 15 VSMP 27 MCLK 28 DGND 14 WM8143-10 VRU AGND AVDD 7 8 OP[6] OP[7] 1 6 OP[8] OP[5] 9 5 32 OP[4] OP[9] 4 10 OP[3] NRESET 31 3 30 nc OP[2] nc 11 OP[1] OP[0] + 10µF DGND AVDD 12 DVDD 100nF 13 Note: AGND and DGND should be starpointed as close as possible to the AGND pins 100nF VRB 29 2 DVDD + 10µ F 17 18 + 22µ F 100nF VRT + 10µF + 10µ F + 10µF 100nF 100nF 100nF + 10µF 100nF AGND Wolfson Microelectronics 23 PD.Rev 3f June 98 WM8143-10 Production Data Package Dimensions 0.45 0.30 0.80 BSC 0.20 M 17 24 25 16 32 9 0.20 0.09 1 8 7.00 BSC Gauge Plane 9.00 BSC 0.25 1.45 1.35 0.15 0.05 0o - 7o 0.75 0.45 Seating Plane 0.10 1.60MAX DM002.a 32-pin TQFP Notes: A. All linear dimensions are in milimeters B The drawing is subject to change without notice C Falls within JEDEC MS-026. Refer to this specification for further details. Last page of WM8143-10 Datasheet Wolfson Microelectronics 24 PD Rev 3f June 98