X20C04 X20C04 4K 512 x 8 Bit Nonvolatile Static RAM FEATURES DESCRIPTION • The Xicor X20C04 is a 512 x 8 NOVRAM featuring a static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E2PROM). The X20C04 is fabricated with advanced CMOS floating gate technology to achieve low power and wide power-supply margin. The X20C04 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs, ROMs, EPROMs, and E2PROMs. • • • • • High Reliability —Endurance: 1,000,000 Nonvolatile Store Operations —Retention: 100 Years Minimum Power-on Recall —E2PROM Data Automatically Recalled Into SRAM Upon Power-up Lock Out Inadvertent Store Operations Low Power CMOS —Standby: 250µA Infinite E2PROM Array Recall, and RAM Read and Write Cycles Compatible with X2004 The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 5ms or less and the recall operation is completed in 5µs or less. Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years. PIN CONFIGURATION NE NC 4 3 2 1 32 31 30 NC NC WE A7 VCC LCC PLCC PLASTIC CERDIP NE 1 28 NC 2 27 VCC WE A7 A6 3 26 NC 4 25 A8 NC A6 5 29 A8 A5 6 28 NC 7 27 NC 26 NC 25 OE A5 A4 5 6 23 NC A4 A3 A2 7 OE A3 8 8 22 X20C04 21 NC A2 9 A1 A0 9 20 CE A1 10 24 NC I/O7 I/O6 A0 11 23 CE NC 12 22 I/O7 I/O6 I/O1 12 17 I/O2 VSS 13 16 14 15 I/O0 I/O5 I/O4 I/O3 3825 FHD F03 3825 FHD F02 ©Xicor, Inc. 1992, 1995, 1996 Patents Pending 3825-2.8 7/31/97 T4/C0/D0 SH 13 21 14 15 16 17 18 19 20 I/O5 18 I/O4 11 I/O3 I/O0 NC 19 I/O2 VSS 10 X20C04 (TOP VIEW) I/O1 24 1 Characteristics subject to change without notice X20C04 PIN DESCRIPTIONS Write Enable (WE) Addresses (A0–A8) The Write Enable input controls the writing of data to both the static RAM and stores to the E2PROM. The Address inputs select an 8-bit memory location during a read or write operation. Nonvolatile Enable (NE) Chip Enable (CE) The Nonvolatile Enable input controls all accesses to the E2PROM array (store and recall functions). The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. PIN NAMES Symbol A0–A8 I/O0–I/O7 WE CE OE NE VCC VSS NC Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE, or NE. Data In/Data Out (I/O0–I/O7) Data is written to or read from the X20C04 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW. Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable Nonvolatile Enable +5V Ground No Connect 3825 PGM T01 FUNCTIONAL DIAGRAM VCC SENSE ST O R 512 x 8 SRAM ARRAY E ROW SELECT A3–A6 R EC AL L EEPROM ARRAY CE OE WE CONTROL LOGIC NE COLUMN SELECT & I/OS A0–A2 A7–A8 I/O0–I/O7 2 3825 FHD F01 X20C04 DEVICE OPERATION Power-Up Recall The CE, OE, WE and NE inputs control the X20C04 operation. The X20C04 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH, or when NE is LOW. Upon power-up (VCC), the X20C04 performs an automatic array recall. When VCC minimum is reached, the recall is initiated, regardless of the state of CE, OE, WE and NE. Write Protection The X20C04 has five write protect features that are employed to protect the contents of both the nonvolatile memory and the RAM. RAM Operations RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW with WE and NE HIGH. A write operation requires CE and WE to be LOW with NE HIGH. There is no limit to the number of read or write operations performed to the RAM portion of the X20C04. • VCC Sense—All functions are inhibited when VCC is ≤ 3.5V. • A RAM write is required before a Store Cycle is initiated. • Write Inhibit—Holding either OE LOW, WE HIGH, CE HIGH, or NE HIGH during power-up and powerdown will prevent an inadvertent store operation. • Noise Protection—A combined WE, NE, OE and CE pulse of less than 20ns will not initiate a Store Cycle. • Noise Protection—A combined WE, NE, OE and CE pulse of less than 20ns will not initiate a recall cycle. Nonvolatile Operations With NE LOW, recall operation is performed in the same manner as RAM read operation. A recall operation causes the entire contents of the E2PROM to be written into the RAM array. The time required for the operation to complete is 5µs or less. A store operation causes the entire contents of the RAM array to be stored in the nonvolatile E2PROM. The time for the operation to complete is 5ms or less. SYMBOL TABLE WAVEFORM 3 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X20C04 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS ....................................... –1V to +7V D.C. Output Current ........................................... 10mA Lead Temperature (Soldering, 10 seconds) ..... 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial Industrial Military 0°C –40°C –55°C +70°C +85°C +125°C Supply Voltage Limits X20C04 5V ±10% 3825 PGM T02.1 3825 PGM T03 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units lCC1 VCC Current (Active) 100 mA ICC2 VCC Current During Store 10 mA ISB1 VCC Standby Current (TTL Input) VCC Standby Current (CMOS Input) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage 10 mA 250 µA 10 10 0.8 VCC + 0.5 0.4 µA µA V V V V ISB2 ILI ILO VIL(1) VIH(1) VOL VOH –1 2 2.4 Test Conditions NE = WE = VIH, CE = OE = VIL Address Inputs = 0.4V/2.4V levels @ f = 5MHz. All I/Os = Open All Inputs = VIH All I/Os = Open CE = VIH All Other Inputs = VIH, All I/Os = Open All Inputs = VCC – 0.3V All I/Os = Open VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH IOL = 2.1mA IOH = –400µA 3825 PGM T04.3 POWER-UP TIMING Symbol (2) tPUR tPUW(2) Parameter Power-Up to RAM Operation Power-Up to Nonvolatile Operation Max. Units 100 5 µs ms 3825 PGM T05 CAPACITANCE TA = +25°C, F = 1MHz, VCC = 5V. Symbol Test Max. Units Conditions CI/O(2) CIN(2) Input/Output Capacitance Input Capacitance 10 6 pF pF VI/O = 0V VIN = 0V 3825 PGM T06.1 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 4 X20C04 ENDURANCE AND DATA RETENTION Parameter Min. Units Endurance Store Cycles Data Retention 100,000 1,000,000 100 Data Changes Per Bit Store Cycles Years 3825 PGM T07.1 MODE SELECTION CE WE NE OE Mode I/O Power H L L L L L L L L X H L L H L H L H X H H H L L H L L X L H H L H H L H Not Selected Read RAM Write “1” RAM Write “0” RAM Array Recall Nonvolatile Storing Output Disabled Not Allowed No Operation Output High Z Output Data Input Data High Input Data Low Output High Z Output High Z Output High Z Output High Z Output High Z Standby Active Active Active Active Active Active Active Active 3825 PGM T09.1 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 5V 1.92KΩ OUTPUT 0V to 3V 10ns 1.5V 3825 PGM T08.2 1.37KΩ 100pF 3825 FHD F04.1 5 X20C04 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Read Cycle Limits X20C04-15 Symbol Parameter tRC tCE tAA tOE tLZ(3) tOLZ(3) tHZ(3) tOHZ(3) tOH Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold From Address Change X20C04-20 X20C04-25 X20C04 Min. Max. Min. Max. Min. Max. Min. Max. Units 150 200 150 150 50 0 0 250 200 200 70 0 0 80 80 0 300 250 250 100 0 0 100 100 0 300 300 150 0 0 100 100 0 100 100 0 ns ns ns ns ns ns ns ns ns 3825 PGM T10 Read Cycle tRC ADDRESS tCE CE tOE OE VIH WE tOLZ tOHZ tLZ DATA I/O tOH DATA VALID tHZ DATA VALID tAA 3825 FHD F05 Note: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven. 6 X20C04 Write Cycle Limits X20C04-15 Symbol tWC tCW tAS tWP tWR tDW tDH tWZ(4) tOW(4) tOZ(4) Parameter X20C04-20 Min. Max. Min. Write Cycle Time Chip Enable to End of Write Input Address Setup Time Write Pulse Width Write Recovery Time Data Setup to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write Output Enable to Output in High Z 150 150 0 100 0 100 0 250 250 0 150 0 150 0 100 5 5 80 X20C04 Max. Min. Max. Min. Max. Units 200 200 0 120 0 120 0 80 X20C04-25 300 300 0 200 0 200 0 100 5 100 5 100 100 100 ns ns ns ns ns ns ns ns ns ns 3825 PGM T11 WE Controlled Write Cycle tWC ADDRESS OE tCW CE tWP tAS tWR WE tOZ tOW DATA OUT tDW tDH DATA VALID DATA IN 3825 FHD F06 Note: (4) tWZ, tOW, and tOZ are periodically sampled and not 100% tested. 7 X20C04 CE Controlled Write Cycle tWC ADDRESS OE VIH tCW CE tAS tWP tWR WE tWZ tOW DATA OUT tDW DATA IN tDH DATA VALID 3825 FHD F07.1 8 X20C04 STORE CYCLE LIMITS Symbol tSTC tSP tNHZ tOEST tSOE tNS Parameter Store Cycle Time Store Pulse Width Nonvolatile Enable to Output in High Z Output Enable From End of Store OE Disable to Store Function NE Setup Time from WE X20C04-15 X20C04-20 X20C04-25 Min. Min. Min. Max. 5 Max. 5 100 120 80 Max. X20C04 Min. 5 150 100 Max. Units 5 ms ns ns 200 100 100 10 10 10 10 ns 20 20 20 20 ns 0 0 0 0 ns 3825 PGM T09 Store Timing tSTC tSP NE tOEST tSOE OE WE tNS CE tNHZ DATA I/O VCC MIN (5) VCC 3825 FHD F15.1 Note: (5) X20C04 VCC min. = 4.5V The Store Pulse Width (tSP) is a minimum time that NE, WE and CE must be LOW simultaneously. 9 X20C04 ARRAY RECALL CYCLE LIMITS Symbol tRCC tRCP(6) tRWE Parameter Array Recall Cycle Time Recall Pulse Width to InitiateRecall WE Setup Time to NE X20C04-15 X20C04-20 X20C04-25 Min. Max. Min. Max. Min. Max. Min. Max. Units 0.1 5 1 0.12 5 1 0.15 5 1 0.2 5 1 µs µs 0 0 0 X20C04 0 ns 3825 PGM T13.1 Array Recall Cycle tRCC ADDRESS tRCP NE OE tRWE WE CE DATA I/O 3825 FHD F10 Note: (6) The Recall Pulse Width (tRCP) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity, NE and CE. 10 X20C04 PACKAGING INFORMATION 28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D 1.490 (37.85) MAX. 0.610 (15.49) 0.500 (12.70) PIN 1 0.005 (0.127) MIN. 0.100 (2.54) MAX. SEATING PLANE 0.232 (5.90) MAX. 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN. 0.200 (5.08) 0.125 (3.18) 0.065 (1.65) 0.038 (0.97) TYP. 0.055 (1.40) 0.110 (2.79) 0.090 (2.29) TYP. 0.100 (2.54) 0.023 (0.58) 0.014 (0.36) TYP. 0.018 (0.46) 0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60) 0° 15° 0.015 (0.38) 0.008 (0.20) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F08 11 X20C04 PACKAGING INFORMATION 28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.470 (37.34) 1.400 (35.56) 0.557 (14.15) 0.510 (12.95) PIN 1 INDEX PIN 1 0.085 (2.16) 0.040 (1.02) 1.300 (33.02) REF. 0.160 (4.06) 0.125 (3.17) SEATING PLANE 0.030 (0.76) 0.015 (0.38) 0.160 (4.06) 0.120 (3.05) 0.110 (2.79) 0.090 (2.29) 0.065 (1.65) 0.040 (1.02) 0.022 (0.56) 0.014 (0.36) 0.625 (15.88) 0.590 (14.99) 0° 15° TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F04 12 X20C04 PACKAGING INFORMATION 32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E 0.300 (7.62) BSC 0.150 (3.81) BSC 0.015 (0.38) 0.003 (0.08) 0.020 (0.51) x 45° REF. 0.095 (2.41) 0.075 (1.91) PIN 1 0.022 (0.56) DIA. 0.006 (0.15) 0.200 (5.08) BSC 0.015 (0.38) MIN. 0.028 (0.71) 0.022 (0.56) (32) PLCS. 0.050 (1.27) BSC 0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS. 0.040 (1.02) x 45° REF. TYP. (3) PLCS. 0.458 (11.63) 0.442 (11.22) 0.120 (3.05) 0.060 (1.52) 0.458 (11.63) –– 0.560 (14.22) 0.540 (13.71) 0.558 (14.17) –– 0.088 (2.24) 0.050 (1.27) 0.400 (10.16) BSC PIN 1 INDEX CORNER NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NLT ±0.005 (0.127) 3926 FHD F14 13 X20C04 32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J 0.050" TYPICAL 0.420 (10.67) 0.030" TYPICAL 32 PLACES 0.050" TYPICAL 0.510" TYPICAL 0.400" 0.050 (1.27) TYP. 0.300" REF 0.410" FOOTPRINT 0.045 (1.14) x 45° 0.021 (0.53) 0.013 (0.33) TYP. 0.017 (0.43) 0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.300 (7.62) REF. SEATING PLANE ±0.004 LEAD CO – PLANARITY — 0.015 (0.38) 0.095 (2.41) 0.060 (1.52) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07) PIN 1 0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.400 (10.16)REF. 3° TYP. NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 3926 FHD F13 14 X20C04 ORDERING INFORMATION X20C04 X X -X Access Time –15 = 150ns –20 = 200ns –25 = 250ns Blank = 300ns Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C MB = MIL-STD-833 Package D = 28-Lead Cerdip P = 28 Lead Plastic DIP E = 32-Pad Ceramic LCC J = 32-Lead PLCC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. 15