ETC X24256BI-2.5

X24256
256K
32K x 8 Bit
400kHz 2-Wire Serial EEPROM
FEATURES
DESCRIPTION
• 400kHz 2-wire serial interface
—Schmitt trigger input noise suppression
—Output slope control for ground bounce noise
elimination
• Longer battery life with lower power
—Active read current less than 1mA
—Active write current less than 3mA
—Standby current less than 1µA
• 2.5V to 5.5V power supply
• 64-byte page write mode
—Minimizes total write time per word
• Internally organized 32K x 8
• Bidirectional data transfer protocol
• Self-timed write cycle
—Typical write cycle time of 5ms
• High reliability
—Endurance: 100,000 cycles
—Data retention: 100 years
• 8-lead XBGA
• 8-lead SOIC
• 14-lead TSSOP
The X24256 is a CMOS Serial EEPROM, internally
organized 32K x 8. The device features a serial interface and software protocol allowing operation on a
simple two wire bus.
Two device select inputs (S0–S1) allow up to 4 devices
to share a common two wire bus.
These pins have internal pull downs, so they are read
as LOW if not connected.
A WP pin, when pulled HIGH prevents any nonvolatile
writes to the array. When not connected WP is pulled
LOW, so the device is not normally protected.
Xicor EEPROMs are designed and tested for applications requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
Data Register
Y Decode Logic
Serial EEPROM Data
and Address (SDA)
SCL
Command
Decode
and
Control
Logic
Page
Decode
Logic
Write Protect
Control Logic
S1
S0
Serial EEPROM
Array
32K x 8
Device
Select
Logic
Write Voltage
Control
WP
REV 1.1.3 10/23/00
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Characteristics subject to change without notice.
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X24256
PIN DESCRIPTIONS
PIN NAMES
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data
sheet.
Symbol
Description
S0, S1
Device Select Inputs
SDA
Serial Data
SCL
Serial Clock
WP
Write Protect
VSS
Ground
VCC
Supply Voltage
NC
No Connect
PIN CONFIGURATION
8-Lead XBGA: Top View
Device Select (S0, S1)
The device select inputs (S0, S1) are used to set bits in
the slave address. This allows up to four devices to
share a common bus. These inputs can be static or
actively driven. If used statically they must be tied to
VSS or VCC as appropriate. If actively driven, they must
be driven with CMOS levels (driven to VCC or VSS) and
they must be constant between each start and stop
issued on the SDA bus. These pins have an active pull
down internally and will be sensed as low if the pin is
left unconnected.
Write Protect (WP)
WP must be constant between each start and stop
issued on the SDA bus and is always active (not
gated). The WP pin has an active pull down to disable
the write protection when the input is left floating. The
Write Protect input controls the Hardware Write Protect
feature. When held LOW, Protection is disabled and
the device operates normally. When this input is held
HIGH, the device is protected, preventing changes to
any and all locations in the EEPROM array.
REV 1.1.3 10/23/00
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WP
1
8
S1
VCC
2
7
S0
SDA
3
6
VSS
SCL
4
5
NC
14-Lead TSSOP
S0
S1
1
2
NC
NC
3
4
NC
5
6
S2
VSS
14
13
12
X24256
7
11
VCC
WP
NC
NC
NC
10
9
SCL
8
SDA
8-Lead SOIC
S0
S1
1
2
S2
VSS
3
4
X24256
8
7
VCC
WP
6
5
SCL
SDA
Characteristics subject to change without notice.
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X24256
DEVICE OPERATION
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and provide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 2. Definition of Start and Stop
SCL
SDA
Start Bit
Stop Bit
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
REV 1.1.3 10/23/00
The device will respond with an acknowledge after recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data transmissions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
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Characteristics subject to change without notice.
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X24256
Figure 3. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
DEVICE ADDRESSING
Figure 4. Device Addressing
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next bit is a “0”. The
following 2 bits are the device select bits ‘0’, S1 and S0.
This allows up to 4 devices to share a single bus.
These bits are compared to the S0 and S1 device
select input pins. The last bit of the Slave Address Byte
defines the operation to be performed. When the R/W
bit is a one, then a read operation is selected. When it is
zero then a write operation is selected. Refer to Figure 4.
After loading the Slave Address Byte from the SDA bus,
the device compares the device type bits with the value
“1010” and the device select bits with the status of the
device select input pins. If the compare is not successful, no acknowledge is output during the ninth clock
cycle and the device returns to the standby mode.
On power up the internal address is undefined, so the
first read or write operation must supply an address.
Device Type
Identifier
1
0
REV 1.1.3 10/23/00
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0
0
S1
S0
R/W
Slave Address Byte
High Order Word Address
0
A14 A13 A12
A11 A10
A9
A8
X24256 Word Address Byte 1
Low Order Word Address
A7
A6
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in Figure 4.
The internal organization of the E2 array is 512 pages
by 64-bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 6 of the Word Address Byte 0. The byte
address is contained in bits 5 through 0 of the Word
Address Byte 0. See Figure 4.
1
Device
Select
A5
A4
A3
A2
A1
A0
D1
D0
Word Address Byte 0
D7
D6
D5
D4
D3
D2
Data Byte
Characteristics subject to change without notice.
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X24256
WRITE OPERATIONS
Byte Write
For a write operation, the device follows “3 byte” protocol, consisting of one Slave Address Byte, one Word
Address Byte 1, and the Word Address Byte 0, which
gives the master access to any one of the words in the
array. Upon receipt of the Word Address Byte 0, the
device responds with an acknowledge, and waits for
the first eight bits of data. After receiving the 8 bits of
the data byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress
the device inputs are disabled and the device will not
respond to any requests from the master. The SDA pin
is at high impedance. See Figure 5.
Page Write
The device is capable of a 64 byte page write operation.
It is initiated in the same manner as the byte write
operation; but instead of terminating the write operation
after the first data word is transferred, the master can
transmit up to sixty-three more words. The device will
respond with an acknowledge after the receipt of each
word, and then the byte address is internally incremented by one. The page address remains constant.
When the counter reaches the end of the page, it “rolls
over” and goes back to the first byte of the current
page. This means that the master can write 64-bytes to
the page beginning at any byte. If the master begins
writing at byte 32, and loads 64-bytes, then the first
32-bytes are written to bytes 32 through 63, and the
last 16 words are written to bytes 0 through 31. Afterwards, the address counter would point to byte 32. If the
master writes more than 64-bytes, then the previously
loaded data is overwritten by the new data, one byte at
a time.
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. Refer to Figure 6 for the address, acknowledge, and data transfer sequence.
Figure 5. Byte Write Sequence
Signals from
the Master
SDA Bus
S
T
A
R
T
Word Address
Byte 1
Slave
Address
Word Address
Byte 0
S
T
O
P
Data
S 1 0 1 0 0 S1 S0 0
P
A
C
K
Signals from
the Slave
A
C
K
A
C
K
A
C
K
Figure 6. Page Write Sequence
(0 ≤ n ≤ 64)
Signals from
the Master
SDA Bus
Signals from
the Slave
REV 1.1.3 10/23/00
S
T
A
R
T
Word Address
Byte 1
Slave
Address
Data
(0)
Word Address
Byte 0
S
T
O
P
Data
(n)
S 1 0 1 0 0 S1 S0 0
P
A
C
K
A
C
K
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A
C
K
A
C
K
A
C
K
Characteristics subject to change without notice.
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X24256
Stop and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Figure 7. Acknowledge Polling Sequence
Acknowledge Polling
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the internal write cycle, then no ACK will be returned. If the
device has completed the internal write operation, an
ACK will be returned and the host can then proceed
with the read or write operation. Refer to Figure 7.
Byte Load Completed
By Issuing Stop
Enter ACK Polling
Issue
Start
Issue Slave
Address Byte
(Read or Write)
ACK
Returned?
Issue Stop
No
Yes
High
Voltage
Cycle Complete.
Continue
Sequence?
No
Yes
Continue Normal
Read or Write
Command Sequence
Issue Stop
Proceed
REV 1.1.3 10/23/00
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Characteristics subject to change without notice.
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X24256
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Random Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last word read or written
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address on the same page.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 8 for the
address, acknowledge, and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 8. Current Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
REV 1.1.3 10/23/00
S
T
A
R
T
Slave
Address
S
T
O
P
S 1 0 1 0 0 S1 S0 1
P
A
C
K
Data
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues the Word Address Byte 1,
receives another acknowledge, then issues the Word
Address Byte 0. After the device acknowledges receipt
of the Word Address Byte 0, the master issues another
start condition and the Slave Address Byte with the R/W
bit set to one. This is followed by an acknowledge and
then eight bits of data from the device. The master terminates the read operation by not responding with an
acknowledge and then issuing a stop condition. Refer
to Figure 9 for the address, acknowledge, and data
transfer sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the
second start shown in Figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this operation is that the new address is loaded into the address
counter, but no data is output by the device.
The next Current Address Read operation will read
from the newly loaded address.
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first Data Byte is
transmitted as with the other modes; however, the
master now responds with an acknowledge, indicating
it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all byte addresses, allowing the entire memory
contents to be read during one operation. At the end of
the address space the counter “rolls over” to address
0000h and the device continues to output data for each
acknowledge received. Refer to Figure 10 for the
acknowledge and data transfer sequence.
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Characteristics subject to change without notice.
7 of 17
X24256
Figure 9. Random Read Sequence
Signals from
the Master
SDA Bus
S
T
A
R
T
Slave
Address
S
T
A
R
T
Word Address
Byte 0
Word Address
Byte 1
S 1 0 1 0 0 S1 S0 0
S
T
O
P
1
S
A
C
K
Signals from
the Slave
Slave
Address
A
C
K
P
A
C
K
A
C
K
Data
Figure 10. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
Address
S
A
C
K
A
C
K
S
T
O
P
A
C
K
P
0 S1 S0 1
A
C
K
Data
(1)
Data
(2)
Data
(n–1)
Data
(n)
(n is any integer greater than 1)
REV 1.1.3 10/23/00
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Characteristics subject to change without notice.
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X24256
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias X24256 ...... –65°C to +135°C
Storage Temperature........................ –65°C to +150°C
Voltage on any pin with
respect to VSS .........................................–1V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indicated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
X24256–2.5
2.5V to 5.5V
Commercial
0°C
+70°C
Industrial
–40°C
+85°C
D.C. OPERATING CHARACTERISTICS VCC equals the range indicated for each device type, unless otherwise stated.
VCC = 2.5 to 5.5V
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
VIL = VCC X 0.1, VIH = VCC X 0.9,
fSCL = 400kHz, SDA = Open
ICC1
Active Supply Current
(Read)
1
mA
ICC2
Active Supply Current
(Write)
3
mA
Standby Current AC
1
mA
ISB1(2)
VSB
(2)
Standby Voltage (Test)
VCC – 0.2
VIL = VCC X 0.1, VIH = VCC X 0.9,
fSCL = 400kHz, SDA = Open
V
Standby Current DC
1
mA
VSDA = VSCL = VSB, Others =
GND or VSB
ILI
Input Leakage Current
10
mA
VIN = GND to VCC
ILO
Output Leakage Current
10
mA
VSDA = GND to VCC, Device is in
Standby(2)
ISB2
VlL(3)
Input LOW Voltage
–0.5
VCC x 0.3
V
VIH
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VHYS
Schmitt Trigger Input
Hysteresis Fixed input level
(3)
VCC related level
VOL
Output LOW Voltage
REV 1.1.3 10/23/00
0.2
V
VCC x 0.05
V
0.4
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V
IOL = 3mA
Characteristics subject to change without notice.
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X24256
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
(3)
(3)
CI/O
CIN
Parameter
Max.
Unit
Test Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (S0, S1, SCL, WP)
6
pF
VIN = 0V
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing levels
VCC X 0.5
Output load
Standard output load
5V
for VOL = 0.4V
IOL = 3mA
1.53KΩ
Output
100pF
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise stated.
Read & Write Cycle Limits
VCC = 2.5V
Symbol
Min.
Max.
Unit
SCL clock frequency
0
400
kHz
tIN
Pulse width suppression time at inputs
50
tAA
SCL LOW to SDA data out valid
0.1
tBUF
Time the bus must be free before a new transmission can start
1.3
µs
tLOW
Clock LOW period
1.3
µs
tHIGH
Clock HIGH period
0.6
µs
tSU:STA
Start condition setup time
0.6
µs
tHD:STA
Start condition hold time
0.6
µs
tSU:DAT
Data in setup time
100
ns
tHD:DAT
Data in hold time
0
µs
tSU:STO
Stop condition setup time
0.6
µs
Data output hold time
50
ns
tR
SDA and SCL rise time
.1Cb(3)
tF
SDA and SCL fall time
fSCL
tDH
Parameter
20 +
tSU:S0, S1, WP
S0, S1, and WP Setup Time
0.6
tHD:S0, S1, WP
S0, S1, and WP Hold Time
0
Cb
Capacitive load for each bus line
REV 1.1.3 10/23/00
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ns
0.9
µs
300
ns
300
ns
ns
ns
400
Characteristics subject to change without notice.
pF
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X24256
POWER-UP TIMING(4)
Symbol
Parameter
Max.
Unit
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
5
ms
Notes: (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
(5) Typical values are for TA = 25°C and nominal supply voltage (5V), Cb = total capacitance of one bus line in pF.
Bus Timing
tF
tHIGH
tHD:STA
tHD:DAT
tLOW
tR
SCL
tSU:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
S0, S1, and WP Pin Timing
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
tSU: S0, S1, WP
tHD: S0, S1, WP
S0, S1, and WP
Write Cycle Limits
Symbol
(6)
TWC
Note:
Parameter
Min.
Typ.
Max.
Unit
Write Cycle Time
—
5
10
ms
(6) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X24256 bus interface circuits are disabled, SDA is allowed to remain HIGH, and
the device does not respond to its slave address.
REV 1.1.3 10/23/00
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Characteristics subject to change without notice.
11 of 17
X24256
Write Cycle Timing
SCL
8th Bit
SDA
ACK
Word n
tWC
Stop
Condition
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
Start
Condition
SYMBOL TABLE
WAVEFORM
Resistance (KΩ)
120
V
RMIN = CC MAX
IOL MIN
100
tR
CBUS
80
RMAX =
60
Max.
Resistance
40
20
Min.
Resistance
0
0
20
40
60
80 100 120
Bus Capacitance (pF)
REV 1.1.3 10/23/00
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INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
Characteristics subject to change without notice.
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X24256
PACKAGING INFORMATION
8-Lead Plastic, 0.200” Wide Small Outline
Gullwing Package Typ “A” (EIAJ SOIC)
0.020 (.508)
0.012 (.305)
.213 (5.41)
.205 (5.21)
.330 (8.38)
.300 (7.62)
Pin 1 ID
.050 (1.27) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.013 (.330)
.004 (.102)
.010 (.254)
.007 (.178)
0°–8° Ref.
.035 (.889)
.020 (.508)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
REV 1.1.3 10/23/00
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Characteristics subject to change without notice.
13 of 17
X24256
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"Typical
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.3 10/23/00
www.xicor.com
Characteristics subject to change without notice.
14 of 17
X24256
PACKAGING INFORMATION
8-Lead XBGA
8-Lead XBGA
Complete Part Number
Top Mark
X24256B-2.5
X24256BI-2.5
XAAI
XAAU
X24256: Bottom View
A1
WP
S1
8-Lead XBGA: Top View
PIN 1
VCC
S0
.079”
WP
1
8
S1
VCC
2
7
S0
SDA
3
6
VSS
SCL
4
5
NC
C
VSS
SDA
NC
SCL
.137”
e
E
F
DWG Symbol
8L XBGA
A
Contact Factory
A1
Contact Factory
C
Contact Factory
D
Contact Factory
E
Contact Factory
e
Contact Factory
F
Contact Factory
D
D
A1
A
C
ALL DIMENSIONS IN µM (to convert to inches, 1µm = 3.94 x 10-5 inch)
ALL DIMENSIONS ARE TYPICAL VALUES
REV 1.1.3 10/23/00
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Characteristics subject to change without notice.
15 of 17
X24256
PACKAGINING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.3 10/23/00
www.xicor.com
Characteristics subject to change without notice.
16 of 17
X24256
Ordering Information
X24256
X
X
-X
VCC Range
2.5 = 2.5V to 5.5V
Device
Temperature Range
Blank = 0°C to +70°C
I = –40°C to +85°C
Package
X24256
V14 = 14-Lead TSSOP
S8 = 8-Lead SOIC, 150 mil wide, JEDEC
A8 = 8-Lead SOIC, 200 mil wide, EIAJ
B = 8-Lead XBGA
Part Mark Conventions
XBGA PACKAGE
Complete Part Number Top Mark
X24256B - 2.5
X24256BI - 2.5
XAAI
XAAU
TSSOP/SOIC
X24256
X
X
V14 = 14-Lead TSSOP
S8 = 8-Lead SOIC (JEDEC)
A8 = 8-Lead SOIC (EIAJ)
AE = 2.5V to 5.5V, 0°C to +70°C
K = 2.5V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
©Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.1.3 10/23/00
www.xicor.com
Characteristics subject to change without notice.
17 of 17