APPLICATION NOTE A V A I L A B L E AN83 • Development Tools XK76C Password Access Security Supervisor X76F041 4K 4 x 128 x 8 Bit PASSTM SecureFlash FEATURES DESCRIPTION • 64-Bit Password Security • Three Password Modes —Secure Read Access —Secure Write Access —Secure Configuration Access • Programmable Configuration —Read, Write and Configuration Access Passwords —Multiple Array Access/Functionality —Retry Register/Counter • 8 Byte Sector Write • (4) 1K Memory Arrays • ISO Response to Reset • Low Power CMOS —50µ A Standby Current —3mA Active Current • 1.8V to 3.6V or 5V “Univolt” Read and Program Power Supply Versions • High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years —ESD Protection: 2000V on All Pins The X76F041 is a password access security supervisor device, containing four 128 x 8 bit SecureFlash arrays. Access can be controlled by three 64-bit programmable passwords, one for read operations, one for write operations and one for device configuration. The X76F041 features a serial interface and software protocol allowing operation on a simple two wire bus. The bus signals are a clock input (SCL) and a bidirectional data input and output (SDA). Access to the device is controlled through a chip select input (CS), allowing any number of devices to share the same bus. The X76F041 also features a synchronous response to reset; providing an automatic output of a pre-configured 32-bit data stream conforming to the ISO standard for memory cards. The X76F041 utilizes Xicor’s proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years. FUNCTIONAL DIAGRAM CHIP ENABLE CS 000–07F DATA TRANSFER RETRY COUNTER SCL SDA INTERFACE LOGIC RST ARRAY ACCESS ENABLE 080–0FF PASSWORD ARRAY AND PASSWORD VERIFICATION LOGIC 100–17F ISO RESET RESPONSE DATA REGISTER 180–1FF CONFIGURATION REGISTER (4) 16 x 64 SECUREFLASH ARRAYS 7002 ILL F01 ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 7002-2.2 4/30/97 T3/C0/D0 SH 1 Characteristics subject to change without notice X76F041 PIN CONFIGURATION PIN DESCRIPTION Serial Data Input/Output (SDA) SDA is a true three state serial data input/output pin. During a read cycle, data is shifted out on this pin. During a write cycle, data is shifted in on this pin. In all other cases this pin is in a high impedance state. DIP/SOIC Serial Clock (SCL) The Serial Clock controls the serial bus timing for data input and output. Chip Select (CS) When CS is HIGH, the X76F041 is deselected and the SDA pin is at high impedance and unless an internal write operation is underway the X76F041 will be in the standby power mode. CS LOW enables the X76F041, placing it in the active power mode. VCC 1 8 VSS RST 2 7 CS SCL 3 6 SDA NC 4 5 NC X76F041 7002 ILL F02 Symbol CS Reset (RST) RST is a device reset pin. When RST is pulsed HIGH while CS is LOW the X76F041 will output 32 bits of fixed data which conforms to the ISO standard for “synchronous response to reset”. CS must remain LOW and the part must not be in a write cycle for the response to reset to occur. If at any time during the response to reset CS goes HIGH, the response to reset will be aborted and the part will return to the standby mode. Description Chip Select Input SDA Serial Data Input/Output RST Reset Input SCL Serial Clock Input VSS Ground VCC Supply Voltage NC No Connect 7002 FRM T01 2 X76F041 Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device. DEVICE OPERATION There are three primary modes of operation for the X76F041; READ, WRITE and CONFIGURATION. The READ and WRITE modes may be performed with or without an 8-byte password. The CONFIGURATION mode always requires an 8-byte password. If the X76F041 is in a nonvolatile write cycle a “no ACK” (SDA HIGH) response will be issued in response to loading of the command + high order address byte. If a stop condition is issued prior to the nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. The basic method of communication is established by first enabling the device (CS LOW), generating a start condition and then transmitting a command and address field followed by the correct password (if configured to require a password). All parts will be shipped from the factory in the non-password mode. The user must perform an ACK Polling routine to determine the validity of the password and start the data transfer (see Acknowledge Polling). Only after the correct password is accepted and an ACK Polling has been performed can the data transfer occur. The basic sequence is illustrated in Figure 1. After each transaction is completed, the X76F041 will reset and enter into a standby mode. This will also be the response if an attempt is made to access any limited array. Password Registers The three passwords, Read, Write and Configuration are stored in three 64 bit Write Only registers as illustrated in figure 2. To ensure correct communication, RST must remain LOW under all conditions except when initiating a “Response to Reset sequence”. Figure 2. Password Registers Figure 1. X76F041 Device Operation 63 0 64 BIT WRITE PASSWORD LOAD COMMAND+HIGH ORDER ADDRESS BYTE 64 BIT READ PASSWORD LOAD LOW ORDER ADDRESS / CONFIGURATION INSTRUCTION BYTE 64 BIT CONFIGURATION PASSWORD 7002 ILL F04 LOAD 8–BYTE PASSWORD (IF APPLICABLE) Device Configuration Five 8-Bit configuration registers are used to configure the X76F041. These are shown in figure 3. VERIFY PASSWORD ACCEPTANCE BY USE OF ACK POLLING (IF APPLICABLE) Figure 3. Configuration Registers READ / WRITE DATA BYTES 63 0 ACR1 ACR2 CR RR RC RES RES RES 7002 ILL F03 RESERVED RETRY COUNTER RETRY REGISTER CONFIGURATION REGISTER ARRAY CONTROL REGISTER 2 ARRAY CONTROL REGISTER 1 7002 ILL F04B 3 X76F041 Array Control Access Bits The four 1K arrays, are each programmable to different levels of access and functionality. Each array can be programmed to require or not require the read/write passwords. The functional options are: • Read and Write Access. • Read access with all write operations locked out. • Read access and program only (writing a “1” to a “0”). If an attempt to change a “0” to a “1” occurs the X76F041 will reset, issue a “no ACK” and enter the standby power mode. • No read or write access to the memory. Access only through use of the configuration password. X Y READ PASSWORD 0 0 NOT REQUIRED NOT REQUIRED 1 0 NOT REQUIRED REQUIRED 0 1 REQUIRED NOT REQUIRED 1 1 REQUIRED REQUIRED 7002 FRM T03 8-Bit Configuration Register MSB UA1 Array Map First ‘1k’ Addresses 000 07F (hex) Second ‘1k’ Addresses 080 0FF (hex) Third ‘1k’ Addresses 100 17F (hex) Fourth ‘1k’ Addresses 180 1FF (hex) High-order Addresses Y2 Z2 ACCESS MSB FUNCTION X1 0 RCR RCE 0 0 Access is forbidden if retry register equals the retry counter (provided that the retry counter is enabled) and no further access of any kind will be allowed. FIRST 1K T2 1 Unauthorized Access Bits (UA1, UA2): 10 8 Bit Array Control Register 1 X2 LSB UA2 RESERVED RETRY COUNTER ENABLE RETRY COUNTER RESET RESERVED RESERVED UNAUTHORIZED ACCESS BIT 2 UNAUTHORIZED ACCESS BIT 1 7002 ILL F06 7002 ILL F04A SECOND 1K WRITE PASSWORD Y1 ACCESS Z1 0 1, 0 0, 1 1 Only configuration operations are allowed if the retry register equals the retry counter (provided that the retry counter is enabled). T1 FUNCTION LSB 7002 ILL F05A Retry Counter Reset Bit (RCR): If the retry counter reset bit is a “1” then the retry counter will be reset following a correct password, provided the retry counter is enabled. 8 Bit Array Control Register 2 UPPER 1K X4 Y4 Z4 ACCESS MSB THIRD 1K T4 FUNCTION X3 Y3 ACCESS Z3 T3 If the retry counter reset bit is a “0” then the retry counter will not be reset following a correct password, provided the retry counter is enabled. FUNCTION LSB 7002 ILL F05B Retry Counter Enable Bit (RCE): If the Retry counter enable bit is a “1”, then the retry counter is enabled. An initial comparison between the retry register and retry counter determines whether the number of allowed incorrect password attempts has been reached. If not, the protocol continues and in case of a wrong password, the retry counter is incremented by one. If the password is correct then the retry counter will either be reset or unchanged, depending on the reset bit. Functional Bits Z T FUNCTIONALITY 0 0 READ AND WRITE UNLIMITED 1 0 READ ONLY, WRITE LIMITED 0 1 PROGRAM & READ ONLY, ERASE LIMITED 1 1 NO READ OR WRITE, FULLY LIMITED 7002 FRM T02 4 X76F041 DEVICE PROTOCOL The retry register must have a higher value than the retry counter for correct device operation. If the retry counter value is larger than the retry register and the retry counter is enabled, the device will wrap around allowing up to an additional 255 incorrect access attempts. The X76F041 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X76F041 will be considered a slave in all applications. If the Retry counter enable bit is a “0”, then the retry counter is disabled. Retry Register/Counter Both the retry register and retry counter are accessible in the configuration mode and may be programmed with a value of 0 to 255. Start Condition All commands except for response to reset are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X76F041 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. The difference between the retry register and the retry counter is the number of access attempts allowed, therefore the retry counter must be programmed to a smaller value than the retry register to prevent wrap around. Figure 4. Data Validity During Write SCL SDA DATA STABLE DATA CHANGE 7002 ILL F07 Figure 5. Definition of Start and Stop SCL SDA START BIT NOTE: STOP BIT 7002 ILL F08 The part requires the SCL input to be LOW during non-active periods of operation. In other words, the SCL will need to be LOW prior to any START condition and LOW after a STOP condition. This is also reflected in the timing diagram. 5 X76F041 Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. OPERATIONAL MODES THE FIRST BYTE IN THE PROTOCOL THE SECOND BYTE IN THE PROTOCOL 0 0 0XXXXA Write address Write (Sector) Write 0 0 1XXXXA Read address Read (Random / Sequential) Read 0 1 0XXXXA Write address Write (Sector) Configuration 0 1 1XXXXA Read address Read (Random / Sequential) Configuration 1 0 0XXXXX 00000000 Program write-password Write 1 0 0XXXXX 00010000 Program read-password Read 1 0 0XXXXX 00100000 Program configuration-password Configuration 1 0 0XXXXX 00110000 Reset write password (all 0’s) Configuration 1 0 0XXXXX 01000000 Reset read password (all 0’s) Configuration 1 0 0XXXXX 01010000 Program configuration registers Configuration 1 0 0XXXXX 01100000 Read configuration registers Configuration 1 0 0XXXXX 01110000 Mass program Configuration 1 0 0XXXXX 10000000 Mass erase Configuration All the rest COMMAND DESCRIPTION PASSWORD USED: Reserved 7002 FRM T04 6 X76F041 WRITE OPERATION ure 6. Eight bytes must be transferred. After the last byte to be transferred is acknowledged, a stop condition is issued, which starts the nonvolatile write cycle. If more than 8 bytes are transferred the data will wrap around and previous data will be overwritten. All data will be written to the same sector as defined by A8–A3. Sector Write The Sector Write mode requires issuing the 3-bit write command followed by the address, password if required and then the data bytes transferred as illustrated in FigFigure 6. Sector Write S T A RCMD A A A A A XXXX 8 T SDA LINE WRITE PASSWORD 0 WRITE PASSWORD 7 AAAAAAAA 7 6 5 4 3 2 1 0 WAIT tWC/ACK POLLING S A C K A C K DATA 0 A C K DATA 1 A C K A C K S T O P WAIT t S WC DATA 7 DATA 2 IF PASSWORD MATCH THEN A C K A C K A C K A C K 7 A C K 7002 ILL F10.1 X76F041 ACK Polling Once a stop condition is issued to indicate the end of the host’s write sequence, the X76F041 initiates the internal nonvolatile write cycle. In order to take advantage of the typical 5ms write cycle, ACK polling can be initiated immediately. This involves issuing the Start condition followed by the new command code of eight bits (1st byte of the protocol). If the X76F041 is still busy with the nonvolatile write operation, it will issue a “no ACK” in response. If the nonvolatile write operation has completed, an “ACK” will be returned and the host can then proceed with the rest of the protocol. Refer to the following flow: After a password sequence, there is always a nonvolatile write cycle. In order to continue the transaction, the X76F041 requires the master to perform an ACK polling with the specific code of C0h. As with regular acknowledge polling the user can either time out for 10ms, and then issue the ACK polling once, or continuously loop as described in the flow. As with regular acknowledge polling, if the user chooses to loop, then as long as the nonvolatile write cycle is active, a no ACK will be issued in response to each polling cycle. If the password that was inserted was correct, then an “ACK” will be returned once the nonvolatile write cycle is over, in response to the ACK polling cycle immediately following it. ACK Polling Sequence WRITE SEQUENCE COMPLETED ENTER ACK POLLING If the password that was inserted was incorrect, then a “no ACK” will be returned even if the nonvolatile write cycle is over. Therefore, the user cannot be certain that the password is incorrect until the 10ms write cycle time has elapsed. ISSUE A START ISSUE NEW COMMAND CODE (1ST BYTE) ACK RETURNED NO ACK (SDA HIGH) YES (SDA LOW) PROCEED 7002 ILL F12A Figure 7. Acknowledge Polling SCL SDA 8th clk. of 8th pwd. byte ‘ACK’ clk 8th clk ACK clk 8th bit ‘ACK’ START condition ACK or no ACK 7002 ILL F11 8 X76F041 READ OPERATION This is followed by the eight byte read password sequence which includes the 10ms wait time and the password acknowledge polling sequence. If the password is accepted an “ACK” will be returned followed by eight bits of “secure read setup” which is to be ignored. At this point a START is issued followed by the address and data to be read within the original 1K block. See figure 8. Once the first byte has been read, another start can be issued followed by a new 8-bit address. Random reads are allowed only within the original 1K-bit block. To access another 1K-bit block, a stop must be issued followed by a new command/block address/password sequence. Random Read with Password Random read with password operations are initiated with a START command followed by the read command and the address of the first byte of the block in which data is to be read: Block 0 = 000h Block 1 = 080h Block 2 = 100h Block 3 = 180h Figure 8. Random Read with Password FIRST BYTE BLOCK ADDRESS S T A RCMD A A A A A A A A A A A A A XXXX 8 7 6 5 4 3 2 1 0 T SDA LINE READ PASSWORD 0 READ PASSWORD 7 S A C K SECURE READ SETUP IF PASSWORD MATCH THEN A C K S T A RA A A A A A A A T7 6 5 4 3 2 1 0 A C K DATA 0 XXXXXXXXS A C K A C K S T A RA A A A A A A A T7 6 5 4 3 2 1 0 DATA 1 S A C K A C K WAIT tWC/ACK POLLIN S T O P S A C K 7002 ILL F13 9 X76F041 Random Read without Password Random read operations without a password do not require the first byte block initiation address. To perform a random read without password, a START is followed by the read command plus address location of the byte to be read. This is followed by an “ACK” and the eight bits of data to be read. Other bytes within the same 1K-bit block may be read by issuing another START followed by a new 8-bit address as shown in figure 9. Sequential Read Once past the password acceptance sequence (when required) and “secure read setup”, the host can read sequentially within the originally addressed 1K-bit array. The data output is sequential, with the data from address n followed by the data from address n+1. The address counter for read operations increments the address, allowing the 1K memory contents to be serially read during one operation. At the end of the address space (address 127), the counter “rolls over” to address space 0 within the 1K Block and the X76F041 continues to output data for each acknowledge received. Refer to figure 10 for the address, acknowledge and data transfer sequence. An acknowledge must follow each 8-bit data transfer. After the last bit has been read, a stop condition is generated without a preceding acknowledge. Figure 9. Random Read without Password S T A RCMD A A A A A XXXX 8 T AAAAAAAA 7 6 5 4 3 2 1 0 S T A RA A A A A A A A T7 6 5 4 3 2 1 0 DATA 0 S SDA LINE S T O P DATA 1 S A C K S A C K A C K 7002 ILL F13A.2 Figure 10. Sequential Read with Password FIRST BYTE S BLOCK ADDRESS T A RCMD A A A A A A A A A A A A A XXXX 8 7 6 5 4 3 2 1 0 T SDA LINE READ PASSWORD 0 READ PASSWORD 7 S A C K SECURE READ SETUP IF PASSWORD MATCH THEN A C K A C K S T A RA A A AAA A A T7 6 5 4 3 2 1 0 A C K DATA 0 DATA 1 XXXXXXXXS A C K WAIT tWC/ACK POLLING A C K DATA X S T O P S A C K A C K 7002 ILL F12.3 10 X76F041 CONFIGURATION OPERATIONS Configuration Read/Write Configuration read/write allows access to all of the nonvolatile memory arrays regardless of the contents of the configuration registers. Access includes sector writes, random and sequential reads using the same format as normal reads and writes. Configuration commands generally require the configuration password. The exception is that programming a new read/write password requires the old read/write password and not the configuration password. In most cases these operations will be performed by the equipment manufacturer or end distributor of the equipment or card. In general, the configuration read/write operation enables access to any memory location that may otherwise be limited. The configuration password, in this sense, is like a master key that can override the limits caused by the control partitioning of the arrays. Figure 11. Configuration Write S T A RCMD A A A A A XXXX 8 T SDA LINE AAAAAAAA 7 6 5 4 3 2 1 0 CONFIGURATION PASSWORD 0 CONFIGURATION PASSWORD 7 WAIT tWC/ACK POLLING S A C K A C K DATA 0 A C K DATA 1 A C K A C K S T O P WAIT t S WC DATA X DATA 2 IF PASSWORD MATCH THEN A C K A C K A C K A C K A C K 7002 ILL F14.1 Figure 12. Configuration Sequential Read FIRST BYTE S BLOCK ADDRESS T A RCMD A A A A A A A A A A A A A XXXX 8 7 6 5 4 3 2 1 0 T SDA LINE CONFIGURATION PASSWORD 0 CONFIGURATION PASSWORD 7 S A C K SECURE READ SETUP IF PASSWORD MATCH THEN A C K A C K S T A RAAAAAAAA T 7 6 5 4 3 2 1 0 A C K DATA 1 DATA 0 XXXXXXXXS A C K WAIT tWC/ACK POLLING A C K DATA X S T O P S A C K A C K 7002 ILL F15.3 11 X76F041 Program Configuration Registers This mode allows programming of the five configuration/ control registers using the configuration password. The retry counter must be programmed with a value less than the retry register. If it is programmed with a value larger than the retry register there will be a wrap around. Configuration of Passwords The sequence in figure 14 will change (program) the write, read and configuration passwords. The programming of passwords is done twice prior to the nonvolatile write cycle in order to verify that the new password is consistent. After the eight bytes are entered in the second pass, a comparison takes place. A mismatch will cause the part to reset and enter into the standby mode and a “no ACK” will be issued. Read Configuration Registers This mode allows reading of the 5 configuration/control registers with the configuration password. It may be useful for monitoring purposes. There is no way to read the Read/Write/Configuration passwords. Figure 13. Configuration Random Read FIRST BYTE S BLOCK ADDRESS T A RCMD A A A A A A A A A A A A A XXXX 8 7 6 5 4 3 2 1 0 T SDA LINE CONFIGURATION PASSWORD 0 CONFIGURATION PASSWORD 7 WAIT tWC/ACK POLLING S A C K A C K A C K S T SECURE A READ SETUP R A A A A A A A A T 7 6 5 4 3 2 1 0 IF PASSWORD MATCH THEN A C K S T A RAAAAAAAA T 7 6 5 4 3 2 1 0 DATA 0 A C K S T O P DATA 1 S XXXXXXXXS S A C K A C K A C K 7002 ILL F16.3 Figure 14. Program Passwords S T A RCMD A A A A A XXXX 8 T SDA LINE READ/WRITE/ CONFIGURATION INSTRUCTION OLD PASSWORD 0 OLD PASSWORD 7 WAIT tWC/ACK POLLING S A C K A C K NEW PASSWORD 7 A C K A C K NEW PASSWORD 0 S T O P WAIT S tWC NEW PASSWORD 0 NEW PASSWORD 7 IF PASSWORD MATCH THEN A C K A C K A C K A C K A C K A C K 7002 ILL F17.1 12 X76F041 Read Password Reset This mode allows resetting of the READ password to all “0”s in case re-programming is needed and the old password is not known. Mass Program This mode allows mass programming of the array, configuration registers and password to all “0”s using a special configuration command. All parts are shipped mass programmed. Write Password Reset This mode allows resetting of the WRITE password to all “0”s in case re-programming is needed and the old password is not known. Mass Erase This mode allows mass erase of the array, configuration register and password to all “1”s using a special configuration command. Figure 15. Program Configuration Registers S T A RCMD A A A A A XXXX 8 T SDA LINE CONFIGURATION CONFIGURATION INSTRUCTION PASSWORD 7 CONFIGURATION PASSWORD 0 WAIT tWC/ACK POLLING S A C K A C K BCR 1 BYTE A C K BCR 2 BYTE A C K CR BYTE A C K S T O P WAIT S tWC RC BYTE RR BYTE IF PASSWORD MATCH THEN A C K A C K A C K A C K A C K A C K 7002 ILL F18.1 Figure 16. Read Configuration Registers S T A RCMD A A A A A XXXX 8 T SDA LINE CONFIGURATION CONFIGURATION INSTRUCTION PASSWORD 7 CONFIGURATION PASSWORD 0 WAIT tWC/ACK POLLING S A C K A C K BCR 1 BYTE A C K BCR 2 BYTE A C K CR BYTE RR BYTE A C K RC BYTE IF PASSWORD MATCH THEN S T O P S A C K A C K A C K A C K 13 A C K 7002 ILL F19.1 X76F041 Figure 17. Read/Write Password Reset WAIT tWC/ACK POLLING S T A RCMD A A A A A XXXX 8 T SDA LINE CONFIGURATION CONFIGURATION INSTRUCTION PASSWORD 7 S T O P CONFIGURATION PASSWORD 0 S A C K A C K A C K A C K A C K WAIT S t WC 7002 ILL F20.1 Figure 18. Mass Program/Erase S T A RCMD A A A A A XXXX 8 T SDA LINE WAIT tWC/ACK POLLING CONFIGURATION CONFIGURATION INSTRUCTION PASSWORD 7 S T O P CONFIGURATION PASSWORD 0 S A C K A C K A C K A C K A C K WAIT S t WC 7002 ILL F20A.1 SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature under Bias ..................... –65°C to +135°C Storage Temperature .......................... –65°C to +150°C Voltage on any Pin with Respect to VSS ..................................... –1V to +7V D.C. Output Current ................................................. 5mA Lead Temperature (Soldering, 10 seconds) .................................300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 14 X76F041 RECOMMENDED OPERATING CONDITIONS Temp Commercial Extended Min. Max. Supply Voltage Limits 0°C +70°C X76F041 4.5V to 5.5V –20°C +85°C X76F041 – 3 3V to 3.6V 7002 FRM T05 7002 FRM T06.1 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Limits Min. Max. Parameter Units Test Conditions ICC1 VCC Supply Current (Read) 2 mA fSCL = VCC x 0.1/VCC x 0.9 Levels @ 1MHz, SDA = Open RST = CS = VSS ICC2(3) VCC Supply Current (Write) 3 mA fSCL = VCC x 0.1/VCC x 0.9 Levels @ 1MHz, SDA = Open RST = CS = VSS ISB1(1) VCC Supply Current (Standby) 100 µA SCL = VSS, CS = VCC – 0.3V SDA = Open, RST = VCC = 5.5V ISB2(1) VCC Supply Current (Standby) 50 µA SCL = VSS, CS = VCC – 0.3V SDA = Open, RST = VSS, VCC = 3V ILI Input Leakage Current 10 µA VIN = VSS to VCC ILO Output Leakage Current 10 µA VOUT = VSS to VCC VIL1(2) Input LOW Voltage VCC x 0.3 V VCC = 5.5V VIH1(2) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VCC = 5.5V VCC x 0.1 V VCC = 3.0V VCC x 0.9 VCC + 0.5 V VCC = 3.0V V IOL = 2mA V IOH = –1mA (2) Input LOW Voltage (2) VIH2 Input HIGH Voltage VOL Output LOW Voltage VOH Output HIGH Voltage VIL2 –0.5 –0.5 0.4 VCC – 0.8 7002 FRM T07.1 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Test (3) COUT (3) CIN Max. Units Conditions Output Capacitance (SDA) 10 pF VI/O = 0V Input Capacitance (RST, SCL, CS) 10 pF VIN = 0V 7002 FRM T08 NOTES: (1) Must perform a stop command after a read command prior to measurement (2) VIL min. and VIH max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS Input Pulse Levels 3V 5V Input Rise and Fall Times 1.3KΩ 2.3KΩ Input and Output Timing Level OUTPUT OUTPUT 100pF Output Load 100pF VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 100pF 7002 FRM T09 7002 ILL F21.1 15 X76F041 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Read & Write Cycle Limits Symbol Parameter Min. Max. Units 1 MHz Noise Suppression Time Constant at SCL & SDA Inputs 20 ns SCL HIGH to SDA Data Valid 450 ns fSCL SCL Clock Frequency TI tDV tLOW Clock LOW Period 500 ns tHIGH Clock HIGH Period 500 ns tSTAS1 Start Condition Setup Time to Rising Edge of SCL 150 ns tSTAS2 Start Condition Setup Time to Falling Edge of SCL 150 ns tSTAH1 Start Condition Hold Time to Rising Edge of SCL 50 ns tSTAH2 Start Condition Hold Time to Falling Edge of SCL 50 ns tSTPS1 Stop Condition Setup Time to Rising Edge of SCL 150 ns tSTPS2 Stop Condition Setup Time to Falling Edge of SCL 150 ns tSTPH1 Stop Condition Hold Time to Rising Edge of SCL 50 ns tSTPH2 Stop Condition Hold Time to Falling Edge of SCL 50 ns tHD:DAT Data in Hold Time 10 ns tSU:DAT Data in Setup Time 150 ns (4) SCL Rise Time 90 ns (4) tRSCL tFSCL SCL Fall Time 90 ns (4) SDA, CS, RST Rise Time 90 ns (4) tF SDA, CS, RST Fall Time 90 ns tDH Data Out Hold Time tHZ1 SCL LOW to High Impedance tLZ SCL HIGH to Output Active 0 ns 5 ms ns tR 0 ns 150 ns tVCCS VCC to CS Setup Time tSU:CS CS Setup Time 200 tHD:CS CS Hold Time 100 tHZ2 CS Deselect Time tSU:SCL SCL Setup Time to CS LOW after Power Up 200 ns tRST RST HIGH Time 1500 ns tSU:RST RST Setup Time 500 ns fSCL:RST SCL Frequency During Response to Reset tLOW:RST SCL LOW Time During Response to Reset 500 ns tHIGH:RST SCL HIGH Time During Response to Reset 500 ns tPD SCL LOW to SDA Valid During Response to Reset tNOL RST to SCL Non-Overlap tWC Nonvolatile Write Cycle ns 150 1 450 500 ns MHz ns ns 10 ms 7002 FRM T10 NOTES: (4) This parameter is periodically sampled and not 100% tested. 16 X76F041 Bus Timing(1) — SDA Driven by the Bus Master tFSCL tRSCL tLOW tHIGH SCL tF tR tSU:DAT tHD:DAT SDA (IN) from master Start bit 7002 ILL F22 Bus Timing(2) — SDA Driven by the Slave 1st clock pulse of sequence SCL last clock pulse of sequence tDV tDH tLZ tHZ1 SDA (OUT) from slave 7002 ILL F23 START Condition Timing SCL tSTAS1 tSTAH1 tSTAS2 tSTAH2 SDA (IN) from master Start Bit 7002 ILL F24 NOTES: (1) The master may issue a STOP condition at any given time in which it is driving the SDA line. In other words, when the part is sending ACK or data the master may NOT issue a STOP condition. The part will not respond to any such attempt which also causes bus contention. At any other time, a STOP condition will cause the part to reset and stop (enter a stand-by mode). Write operations will terminate prior to entering the stand-by mode. (2) When the part drives the SDA line, it will tri-state the bus only after the last bit of the sequence. In other words, after the 8th bit of a byte that is read or after ACK between incoming bytes. In all other cases when the part drives the bus (between successive bits) it will continue to drive the bus also during the clock LOW periods. 17 X76F041 STOP Condition Timing SCL tSTPS1 tSTPH1 tSTPH2 tSTPS2 SDA (IN) from master Stop Bit 7002 ILL F25 Acknowledge Response from Slave (Same Timing as Data Out) SCL tDV SDA (OUT) from slave (acknowledge) tDH tLZ tHZ1 7002 ILL F26 Acknowledge Response from Master SCL tSU:DAT tHD:DAT SDA (OUT) from master (acknowledge) 7002 ILL F27 CS Timing Diagram (Selecting/Deselecting the Part) SCL tHD:CS tSU:CS CS from master 7002 ILL F28 18 X76F041 VCC to CS Setup Timing Diagram VCC VCCMIN tVCCS CS tSU:SCL tSU:CS SCL 7002 ILL F29 CS Deselect CS tHZ2 SDA (OUT) from slave 7002 ILL F29A RST Timing Diagram — Response to a Synchronous Reset (ISO) RST tRST SCL tNOL tHIGH_RST 1st clk. pulse 2nd clk. pulse tPD SDA CS tSU:RST fSCL_RST tLOW_RST 3rd clk. pulse tPD 1st DATA BIT 2nd DATA BIT (low) 7002 ILL F30 NOTES: (1) The reset operation results in an answer from the part containing a header transmitted from the part to the master. The header has a fixed length of 32 bits and begins with two mandatory fields of eight bits : H1 and H2. (2) The chronological order of transmission of the information bits shall correspond to bit identification b1 to b32 with the LEAST significant bit transmitted first. (3) The current values are: H1 : 19 h H2 : 55 h H3 : AA h H4 : 55 h 19 X76F041 PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 8-LEAD PLASTIC, 0.200” WIDE SMALL OUTLINE GULLWING PACKAGE TYP “A” (EIAJ SOIC) 0.020 (.508) 0.012 (.305) 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) .213 (5.41) .205 (5.21) PIN 1 INDEX .330 (8.38) .300 (7.62) PIN 1 PIN 1 ID 0.300 (7.62) REF. HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL .050 (1.27) BSC 0.145 (3.68) 0.128 (3.25) SEATING PLANE .212 (5.38) .203 (5.16) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.150 (3.81) 0.125 (3.18) .080 (2.03) .070 (1.78) 0.060 (1.52) 0.020 (0.51) 0.020 (0.51) 0.016 (0.41) 0.110 (2.79) 0.090 (2.29) .013 (.330) .004 (.102) 0 REF 8 0.015 (0.38) MAX. .010 (.254) .007 (.178) .035 (.889) .020 (.508) TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.325 (8.25) 0.300 (7.62) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 ILL F33.1 3926 FHD F01 20 X76F041 ORDERING INFORMATION X76F041 X X –X Device VCC Limits Blank = 5V ±10% 3 = 3V to 3.6V Temperature Range Blank = Commercial = 0°C to +70°C E = Extended = –20°C to +85°C Package P = 8-Lead Plastic DIP A = 8-Lead SOIC (EIAJ) H = Die in Waffle Packs W = Die in Wafer Form LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 21