X9251
®
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet
September 14, 2005
Quad Digitally-Controlled (XDCP™)
Potentiometer
FN8166.2
DESCRIPTION
The X9251 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
FEATURES
• Four potentiometers in one package
• 256 resistor taps–0.4% resolution
• SPI Serial Interface for write, read, and transfer
operations of the potentiometer
• Wiper resistance: 100Ω typical @ VCC = 5V
• 4 Non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper positions
• Standby current < 5µA max
• VCC: 2.7V to 5.5V Operation
• 50kΩ, 100kΩ versions of total resistance
• 100 yr. data retention
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per
register
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-free plus anneal available (RoHS compliant)
The digitally controlled potentiometers are implemented with a combination of resistor elements and
CMOS switches. The position of the wipers are
controlled by the user through the SPI bus interface.
Each potentiometer has associated with it a volatile
Wiper Counter Register (WCR) and four non-volatile
Data Registers that can be directly written to and read
by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls
the content of the default Data Registers of each DCP
(DR00, DR10, DR20, and DR30) to the corresponding
WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
HOLD
A1
SPI
Interface
A0
SO
RH1
RH0
VCC
WCR0
DR00
DR01
DR02
DR03
POWER UP,
INTERFACE
CONTROL
AND
STATUS
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
RH3
RH2
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
SI
SCK
CS
VSS
WP
1
RW0
RL0
RW1
RL1
RW2
RL2
RW3
RL3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9251
Ordering Information
PART NUMBER
PART MARKING
VCC LIMITS (V)
5 ±10%
POTENTIOMENTER TEMP RANGE
ORGANIZATION (kΩ)
(°C)
X9251UP24I
X9251UP I
X9251US24*
X9251US
0 to 70
24 Ld SOIC (300MIL)
X9251US24Z* (Note)
X9251US Z
0 to 70
24 Ld SOIC (300MIL) (Pb-Free)
X9251US24I*
X9251US I
-40 to +85
24 Ld SOIC (300MIL)
X9251US24IZ* (Note)
X9251US Z I
-40 to +85
24 Ld SOIC (300MIL) (Pb-Free)
X9251UV24
X9251UV
0 to 70
24 Ld TSSOP (4.4mm)
X9251UV24Z (Note)
X9251UV Z
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free)
X9251UV24I
X9251UV I
-40 to +85
24 Ld TSSOP (4.4mm)
X9251UV24IZ (Note)
X9251UV Z I
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-free)
-40 to +85
24 Ld PDIP
X9251TP24I
50
100
-40 to +85
PACKAGE
24 Ld PDIP
X9251TS24*
X9251TS
0 to 70
24 Ld SOIC (300MIL)
X9251TS24Z* (Note)
X9251TS Z
0 to 70
24 Ld SOIC (300MIL) (Pb-Free)
X9251TS24I*
X9251TS I
-40 to +85
24 Ld SOIC (300MIL)
X9251TS24IZ* (Note)
X9251TS Z I
-40 to +85
24 Ld SOIC (300MIL) (Pb-Free)
X9251TV24
X9251TV
0 to 70
24 Ld TSSOP (4.4mm)
X9251TV24Z (Note)
X9251TV Z
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free)
X9251TV24I
X9251TV I
-40 to +85
24 Ld TSSOP (4.4mm)
X9251TV24IZ (Note)
X9251TV Z I
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-free)
X9251US24-2.7*
X9251US F
X9251US24Z-2.7* (Note)
X9251US Z F
X9251US24I-2.7*
X9251US G
-40 to +85
24 Ld SOIC (300MIL)
X9251US24IZ-2.7* (Note)
X9251US Z G
-40 to +85
24 Ld SOIC (300MIL) (Pb-Free)
X9251UV24-2.7
X9251UV F
0 to 70
24 Ld TSSOP (4.4mm)
X9251UV24Z-2.7 (Note)
X9251UV Z F
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free)
X9251UV24I-2.7
X9251UV G
-40 to +85
24 Ld TSSOP (4.4mm)
X9251UV24IZ-2.7 (Note)
X9251UV Z G
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-free)
X9251TS24-2.7*
X9251TS F
X9251TS24Z-2.7* (Note)
X9251TS Z F
X9251TS24I-2.7*
X9251TS G
-40 to +85
24 Ld SOIC (300MIL)
X9251TS24IZ-2.7* (Note)
X9251TS Z G
-40 to +85
24 Ld SOIC (300MIL) (Pb-Free)
X9251TV24-2.7
X9251TV F
0 to 70
24 Ld TSSOP (4.4mm)
X9251TV24Z-2.7 (Note)
X9251TV Z F
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free)
X9251TV24I-2.7
X9251TV G
-40 to +85
24 Ld TSSOP (4.4mm)
X9251TV24IZ-2.7 (Note)
X9251TV Z G
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-free)
2.7 to 5.5
50
100
0 to 70
24 Ld SOIC (300MIL)
0 to 70
24 Ld SOIC (300MIL) (Pb-Free)
0 to 70
24 Ld SOIC (300MIL)
0 to 70
24 Ld SOIC (300MIL) (Pb-Free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8166.2
September 14, 2005
X9251
CIRCUIT LEVEL APPLICATIONS
PIN CONFIGURATION
• Vary the gain of a voltage amplifier
SOIC/TSSOP
• Provide programmable dc reference voltages for
comparators and detectors
SO
1
24
HOLD
A0
2
23
SCK
RW3
3
22
RL2
RH3
4
21
RH2
RL3
5
20
RW2
NC
6
19
NC
• Trim the resistance in Wheatstone bridge circuits
VCC
7
18
VSS
• Control the gain, characteristic frequency and
Q-factor in filter circuits
RL0
8
17
RW1
RH0
9
16
RH1
RW0
10
15
RL1
CS
11
14
A1
WP
12
13
SI
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
X9251
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
PIN ASSIGNMENTS
Pin
(SOIC)
Symbol
1
SO
Serial Data Output for SPI bus
Device Address for SPI bus. (See Note 1)
Function
• Adjust the contrast in LCD displays
2
A0
• Control the power level of LED transmitters in
communication systems
3
RW3
Wiper Terminal of DCP3
4
RH3
High Terminal of DCP3
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
5
RL3
Low Terminal of DCP3
7
VCC
System Supply Voltage
• Control the gain in audio and home entertainment
systems
8
RL0
Low Terminal of DCP0
9
RH0
High Terminal of DCP0
• Provide the variable DC bias for tuners in RF wireless systems
10
RW0
Wiper Terminal of DCP0
11
CS
SPI bus. Chip Select active low input
• Set the operating points in temperature control
systems
12
WP
Hardware Write Protect - active low
13
SI
Serial Data Input for SPI bus
• Control the operating point for sensors in industrial
systems
14
A1
Device Address for SPI bus. (See Note 1)
15
RL1
Low Terminal of DCP1
• Trim offset and gain errors in artificial intelligent
systems
16
RH1
High Terminal of DCP1
17
RW1
Wiper Terminal of DCP1
18
VSS
System Ground
20
RW2
Wiper Terminal of DCP2
21
RH2
High Terminal of DCP2
22
RL2
Low Terminal of DCP2
23
SCK
Serial Clock for SPI bus
24
HOLD
6, 19
NC
Device select. Pauses the SPI serial bus.
No Connect
Note 1: A0 - A1 device address pins must be tied to a logic level.
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FN8166.2
September 14, 2005
X9251
PIN DESCRIPTIONS
Potentiometer Pins
Bus Interface Pins
RH, RL
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer. Since
there are 4 potentiometers, there are 4 sets of RH and
RL such that RH0 and RL0 are the terminals of DCP0
and so on.
SERIAL INPUT (SI)
RW
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the device
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 4 sets of RW such that RW0
is the terminals of DCP0 and so on.
SERIAL CLOCK (SCK)
Supply Pins
SERIAL OUTPUT (SO)
The SCK input is used to clock data into and out of the
X9251.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
DEVICE ADDRESS (A1 - A0)
The address inputs are used to set the two least
significant bits of the slave address. A match in the
slave address serial data stream must be made with
the address input in order to initiate communication
with the X9251. Device pins A1 - A0 must be tie to a
logic level which specify the internal address of the
device, see Figures 2, 3, 4, 5 and 6.
CHIP SELECT (CS)
When CS is HIGH, the X9251 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device is in the standby
state. CS LOW enables the X9251, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
4
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS
pin is the system ground.
Other Pins
NO CONNECT
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents non-volatile writes to
the Data Registers.
PRINCIPLES OF OPERATION
The X9251 is an integrated circuit incorporating four
DCPs and their associated registers and counters,
and a serial interface providing direct communication
between a host and the potentiometers.
DCP Description
Each DCP is implemented with a combination of
resistor elements and CMOS switches. The physical
ends of each DCP are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL pins). The
RW pin is an intermediate node, equivalent to the
wiper terminal of a mechanical potentiometer.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
FN8166.2
September 14, 2005
X9251
Figure 1. Detailed Potentiometer Block Diagram
One of Four Potentiometers
RH
#: 0, 1, 2, or 3
SERIAL
BUS
INPUT
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#1
DR#0
8
DR#2
IF WCR = 00[H] then RW is closet to RL
IF WCR = FF[H] then RW is closet to RH
8
WIPER
COUNTER
REGISTER
(WCR#)
DR#3
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers,
one for each potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 wiper positions along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR#0) upon power-up. (See Figure 1.)
The wiper counter register is a volatile register; that is,
its contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the
value in DR#0 upon power-up, this may be different
5
COUNTER
--DECODE
DCP
CORE
RW
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
Power Up and Down Recommendations.
There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to
the potentiometer pins provided that VCC is always
more positive than or equal to VH, VL, and VW, i.e.,
VCC ≥ VH, VL, VW. The VCC ramp rate specification is
always in effect.
PARALLEL
BUS
INPUT
UP/DN
CLK
RL
from the value present at power-down. Power-up
guidelines are recommended to ensure proper
loadings of the DR#0 value into the WCR#.
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a non-volatile operation and takes a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).
Status Register (SR)
This 1-bit Status Register is used to store the system
status.
WIP: Write In Progress status bit, read only.
– When WIP=1, indicates that high-voltage write cycle
is in progress.
– When WIP=0, indicates that no high-voltage write
cycle is in progress.
FN8166.2
September 14, 2005
X9251
Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile).
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
(MSB)
WCR0
(LSB)
Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Non-volatile).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSB)
Bit 0
(LSB)
SERIAL INTERFACE
The X9251 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in, on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
IDENTIFICATION BYTE
The first byte sent to the X9251 from the host,
following a CS going HIGH to LOW, is called the
Identification Byte. The most significant four bits of the
Identification Byte are a Device Type Identifier, ID[3:0].
For the X9251, this is fixed as 0101 (refer to Table 3).
The least significant four bits of the Identification Byte
are the Slave Address bits, AD[3:0]. For the X9251, A3
is 0, A2 is 0, A1 is the logic value at the input pin A1,
and A0 is the logic value at the input pin A0. Only the
device which Slave Address matches the incoming
bits sent by the master executes the instruction. The
A1 and A0 inputs can be actively driven by CMOS
input signals or tied to VCC or VSS.
INSTRUCTION BYTE
The next byte sent to the X9251 contains the instruction
and register pointer information. The four most significant
bits are used provide the instruction opcode (I[3:0]). The
RB and RA bits point to one of the four Data Registers of
each associated XDCP. The least two significant bits
point to one of four Wiper Counter Registers or
DCPs.The format is shown below in Table 4.
Table 3. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
ID2
ID1
ID0
A3
A2
A1
A0
0
1
0
1
0
0
Pin A1
Logic Value
Pin A0
Logic Value
(MSB)
(LSB)
Table 4. Instruction Byte Format
Register
Selection
Instruction
Opcode
I3
I2
I1
(MSB)
I0
RB
DCP Selection
(WCR Selection)
RA
P1
P0
(LSB)
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FN8166.2
September 14, 2005
X9251
Data Register Selection
Register
RB
RA
DR#0
0
0
DR#1
0
1
DR#2
1
0
DR#3
1
1
#: 0, 1, 2, or 3
Table 5. Instruction Set
I3
1
I2
0
Instruction Set
I1
I0 RB RA
0
1
0
0
1
0
1
0
0
0
1/0
1/0
1
0
1
1
1/0
1/0
1/0
1/0
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0
XFR Data Register to
Wiper Counter Register
1
1
0
1
1/0
1/0
1/0
1/0
XFR Wiper Counter
Register to Data Register
1
1
1
0
1/0
1/0
1/0
1/0
Global XFR Data Registers
to Wiper Counter Registers
0
0
0
1
1/0
1/0
0
0
Global XFR Wiper Counter
Registers to Data Register
1
0
0
0
1/0
1/0
0
0
Increment/Decrement
Wiper Counter Register
0
0
1
0
0
0
1/0
1/0
Instruction
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
Note:
P1
P0
Operation
1/0
1/0
Read the contents of the Wiper Counter
Register pointed to by P1 - P0
Write new value to the Wiper Counter
Register pointed to by P1 - P0
Read the contents of the Data Register
pointed to by P1 - P0 and RB - RA
Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
Transfer the contents of the Data Register
pointed to by P1 - P0 and RB - RA to its
associated Wiper Counter Register
Transfer the contents of the Wiper Counter
Register pointed to by P1 - P0 to the Data
Register pointed to by RB - RA
Transfer the contents of the Data Registers
pointed to by RB - RA of all four pots to their
respective Wiper Counter Registers
Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by RB - RA of all four pots
Enable Increment/decrement of the Control
Latch pointed to by P1 - P0
1/0 = data is one or zero
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FN8166.2
September 14, 2005
X9251
Instructions
Four of the nine instructions are three bytes in length.
These instructions are:
– Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
– Write Wiper Counter Register – change current
wiper position of the selected potentiometer,
– Read Data Register – read the contents of the
selected Data Register,
– Write Data Register – write a new value to the
selected Data Register,
– Read Status – this command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action is delayed by tWRL. A transfer from
the WCR (current wiper position), to a Data Register is
a write to non-volatile memory and takes a minimum of
tWR to complete. The transfer can occur between one
of the four potentiometer’s WCR, and one of its
associated registers, DRs; or it may occur globally,
where the transfer occurs between all potentiometers
and one associated register. The Read Status
Register instruction is the only unique format (See
Figure 5).
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data Registers to the associated Wiper Counter
Registers.
– Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (See
Figures 6 and 7). The Increment/Decrement command
is different from the other commands. Once the
command is issued and the X9251 has responded
with an Acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCK clock pulse (tHIGH) while SI is HIGH,
the selected wiper moves one wiper position towards
the RH terminal. Similarly, for each SCK clock pulse
while SI is LOW, the selected wiper moves one wiper
position towards the RL terminal. A detailed illustration
of the sequence and timing for this operation are
shown. See Instruction format for more details.
Four instructions require a two-byte sequence to
complete. These instructions transfer data between
the host and the X9251; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:
8
FN8166.2
September 14, 2005
X9251
Figure 2. Two-Byte Instruction Sequence
CS
SCK
SI
1
0
0
ID3 ID2 ID1 ID0
0
0
0
1
0
A1
A0
Internal
Address
Device ID
I3
I2
I1
RB RA P1
I0
Instruction
Opcode
P0
Register DCP/WCR
Address Address
Figure 3. Three-Byte Instruction Sequence SPI Interface; Write Case
CS
SCK
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
A1 A0
I3 I2
I0
Instruction
Opcode
Internal
Address
Device ID
I1
RB RA P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
Data for WCR[7:0] or DR[7:0]
Register DCP/WCR
Address Address
Figure 4. Three-Byte Instruction Sequence SPI Interface, Read Case
CS
SCK
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
X
A1 A0
Internal
Address
Device ID
I3
I2
I1
I0
Instruction
Opcode
RB RA P1 P0
X
X
X
X
X
X
X
Don’t Care
Register DCP/WCR
Address Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register Bit [7:0]
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FN8166.2
September 14, 2005
X9251
Figure 5. Three-Byte Instruction Sequence (Read Status Register
CS
SCK
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
1
A1 A0
I3
Internal
Address
Device ID
0
I2
1
1
I1 I0
Instruction
Opcode
0
0
0
0
0
0
RB RA P1 P0
0
WIP
Register Pot/WCR
Address Address
Status
Bit
Figure 6. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
Device ID
A1 A0
I2
Internal
Address
I3
I1
I0
Instruction
Opcode
RB RA P1 P0
Register Pot/WCR
Address Address
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Figure 7. Increment/Decrement Timing Spec
tWRID
SCK
SI
VOLTAGE OUT
RW
INC/DEC CMD ISSUED
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X9251
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
Opcode
0 0 A1 A0 1
0
0
1
WCR
Addresses
0
0
0
Wiper Position
(Sent by X9251 on SO)
W
C
0
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
CS
W Rising
C Edge
R
0
W
C
R
1
Write Wiper Counter Register (WCR)
Device Type
Identifier
CS
Falling
Edge 0
1
0
1
Device
Addresses
Instruction
Opcode
0 0 A1 A0 1
0
1
0
WCR
Addresses
0
0
0
W
C
0
R
7
Data Byte
(Sent by Host on SI)
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
Read Data Register (DR)
Device Type
Device
Instruction
DR and WCR
Data Byte
CS
CS
Identifier
Addresses
Opcode
Addresses
(Sent by X9271 on SO)
Falling
Rising
Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA P1 P0 D D D D D D D D Edge
7 6 5 4 3 2 1 0
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
CS
Falling
Rising
Edge 0 1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D D D D D D D D Edge
7 6 5 4 3 2 1 0
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
CS
Identifier
Falling
Edge 0 1 0 1
Notes: (1)
(2)
(2)
(3)
Device
Addresses
0
Instruction
Opcode
DR
Addresses
CS
Rising
0 A1 A0 0 0 0 1 RB RA 0 0 Edge
“A1 ~ A0”: stands for the device addresses sent by the master.
WPx refers to wiper position data in the Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
“D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
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X9251
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Device
Instruction
DR
CS
CS
Identifier
Addresses
Opcode
Addresses
Falling
Rising
Edge 0 1 0 1 0 0 A1 A0 1 0 0 0 RB RA 0 0 Edge
HIGH-VOLTAGE
WRITE CYCLE
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Device
Instruction
DR and WCR
CS
Identifier
Addresses
Opcode
Addresses
Falling
Edge 0 1 0 1 0 0 A1 A0 1 1 1 0 RB RA 0 0
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Device
Instruction
DR and WCR
CS
Identifier
Addresses
Opcode
Addresses
Falling
Edge 0 1 0 1 0 0 A1 A0 1 1 0 1 RB RA 0 0
CS
Rising
Edge
Increment/Decrement Wiper Counter Register (WCR)
Device Type
Device
Instruction
WCR
Increment/Decrement
CS
CS
Identifier
Addresses
Opcode
Addresses
(Sent by Master on SI)
Falling
Rising
Edge 0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D Edge
Read Status Register (SR)
Device Type
Device
Instruction
WCR
Data Byte
CS
Identifier
Addresses
Opcode
Addresses
(Sent by X9251 on SO)
Falling
Edge 0 1 0 1 0 0 A1 A0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 WIP
Notes: (1)
(2)
(2)
(3)
CS
Rising
Edge
“A1 ~ A0”: stands for the device addresses sent by the master.
WPx refers to wiper position data in the Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
“D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
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X9251
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK, any address input, VCC
with respect to VSS ................................. -1V to +7V
∆V = | (VH - VL) |................................................... 5.5V
Lead temperature (soldering, 10s) .................... 300°C
IW (10s) ..............................................................±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Supply Voltage (VCC) Limits(4)
5V ± 10%
2.7V to 5.5V
Device
X9251
X9251-2.7
ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.)
Parameter
Symbol
Limits
Min.
Typ.
Max.
Units
Test Conditions
RTOTAL
End to End Resistance
100
kΩ
T version
RTOTAL
End to End Resistance
50
kΩ
U version
End to End Resistance Tolerance
±20
%
Power Rating
50
mW
IW
Wiper Current
±3
mA
RW
Wiper Resistance
300
Ω
150
Ω
VCC
V
VTERM
Voltage on any RH or RL Pin
VSS
Noise
0.4
V(VCC)
@ VCC = 3V
RTOTAL
IW =
V(VCC)
@ VCC = 5V
RTOTAL
VSS = 0V
%
Absolute Linearity (1)
-1
+1
MI(3)
Rw(n)(actual) - Rw(n)(expected)(5)
Relative Linearity (2)
-0.6
+0.6
MI(3)
Rw(n + 1) - [Rw(n) + MI](5)
±300
Temperature Coefficient of RTOTAL
Ratiometric Temp. Coefficient
CH/CL/CW
IW =
dBV/√Hz Ref: 1V
-120
Resolution
25°C, each pot
Potentiometer Capacitances
-20
ppm/°C
+20
10/10/25
ppm/°C
pF
See Macro model
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (RH - RL) / 255, single pot
(4) During power up VCC > VH, VL, and VW.
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.
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X9251
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
400
µA
fSCK = 2.5 MHz, SO = Open, VCC = 6V
Other Inputs = VSS
5
mA
fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ICC1
VCC supply current
(active)
ICC2
VCC supply current
(non-volatile write)
ISB
VCC current (standby)
3
µA
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 6V
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW voltage
-1
VCC x 0.3
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
VOH
Output HIGH voltage
VCC - 0.8
V
IOH = -1mA, VCC ≥ +3V
VOH
Output HIGH voltage
VCC - 0.4
V
IOH = -0.4mA, VCC ≤ +3V
1
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
CAPACITANCE
Symbol
CIN/OUT
(6
)
Test
Input / Output capacitance (SI)
Max.
Units
8
pF
Test Conditions
VOUT = 0V
COUT(6)
Output capacitance (SO)
8
pF
VOUT = 0V
CIN(6)
Input capacitance (A0, A1, CS, WP, HOLD, and SCK)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tr VCC
(6)
tPUR(7)
tPUW(7)
Parameter
VCC Power-up rate
Min.
Max.
Units
0.2
50
V/ms
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
50
ms
A.C. TEST CONDITIONS
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.
These parameters are periodically sampled and not 100% tested.
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X9251
EQUIVALENT A.C. LOAD CIRCUIT
VCC
SPICE Macromodel
2kΩ
RTOTAL
RL
RH
SO pin
CW
CL
2kΩ
10pF
CL
10pF
25pF
10pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Units
2
MHz
fSCK
SPI clock frequency
tCYC
SPI clock cycle rime
500
ns
tWH
SPI clock high rime
200
ns
tWL
SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
2
µs
tFI
SI, SCK, HOLD and CS input fall time
2
µs
tDIS
SO output disable time
250
ns
tV
SO output valid time
200
ns
tHO
SO output hold time
tRO
SO output rise time
tFO
SO output fall time
tHOLD
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
10
ns
tCS
CS deselect time
tWPASU
WP, A0 setup time
0
ns
tWPAH
WP, A0 hold time
0
ns
15
0
0
2
ns
100
ns
100
ns
µs
FN8166.2
September 14, 2005
X9251
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
tWR
High-voltage write cycle time (store instructions)
Typ.
Max.
Units
5
10
ms
XDCP TIMING
Symbol
Parameter
Min.
Max. Units
tWRPO
Wiper response time after the third (last) power supply is stable
5
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
5
10
µs
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
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FN8166.2
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X9251
TIMING DIAGRAMS
Input Timing
tCS
CS
SCK
tSU
tH
...
tWH
tWL
...
MSB
SI
tLAG
tCYC
tLEAD
tRI
tFI
LSB
High Impedance
SO
Output Timing
CS
SCK
...
tV
tDIS
...
MSB
SO
SI
tHO
LSB
ADDR
Hold Timing
CS
tHSU
SCK
tHH
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
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FN8166.2
September 14, 2005
X9251
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
SI
...
MSB
LSB
VWx
SO
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
tWPAH
WP
A0
A1
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FN8166.2
September 14, 2005
X9251
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
VO
100kΩ
–
VO
+
}
}
TL072
R1
R2
10kΩ
10kΩ
+12V
10kΩ
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
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FN8166.2
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X9251
Application Circuits (continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
V O = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
V O = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
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FN8166.2
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X9251
PACKAGING INFORMATION
24-Lead Plastic, TSSOP, Package Code V24
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
0° - 8°
(4.16) (7.72)
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
Detail A (20X)
(0.42)
(0.65)
.031 (.80)
.041 (1.05)
ALL MEASUREMENTS ARE TYPICAL
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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FN8166.2
September 14, 2005
X9251
PACKAGING INFORMATION
24-Lead Plastic, SOIC, Package Code S24
0.290 (7.37) 0.393 (10.00)
0.299 (7.60) 0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
Typical
0° - 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" Typical
24 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
22
FN8166.2
September 14, 2005