X9279
®
Single Supply/Low Power/256-Tap/2-Wire Bus
Data Sheet
September 27, 2005
Single Digitally-Controlled (XDCP™)
Potentiometer
FN8175.2
DESCRIPTION
The X9279 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
FEATURES
• 256 Resistor Taps
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer
• Wiper Resistance, 100Ω Typical @ 5V
• 16 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position
on Power-up.
• Standby Current < 5µA Max
• VCC: 2.7V to 5.5V Operation
• 50kΩ, 100kΩ Versions of End to End Resistance
• Endurance: 100,000 Data Changes per Bit per
Register
• 100 yr. Data Retention
• 14 Ld TSSOP
• Low Power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. The potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default data register (DR0)
to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
2-Wire
Bus
Interface
Address
Data
Status
RH
Write
Read
Transfer
Inc/Dec
Control
1
wiper
Wiper Counter
Register (WCR)
Bus
Interface
and Control
VSS
Power-on Recall
50kΩ and 100kΩ
256-taps
POT
Data Registers
16 Bytes
RW
RL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9279
Ordering Information
PART NUMBER
PART MARKING
X9279TV14*
X9279TV
X9279TV14I*
X9279TV I
X9279UV14*
X9279UV
X9279UV14Z (Note)
X9279UV14I*
VCC LIMITS (V)
POTENTIOMETER
ORGANIZATION (kΩ) TEMP RANGE (°C)
5 ±10%
100
0 to 70
14 Ld TSSOP (4.4mm)
-40 to 85
14 Ld TSSOP (4.4mm)
0 to 70
14 Ld TSSOP (4.4mm)
X9279UV Z
0 to 70
14 Ld TSSOP (4.4mm) (Pb-free)
X9279UV I
-40 to 85
14 Ld TSSOP (4.4mm)
-40 to 85
14 Ld TSSOP (4.4mm) (Pb-free)
50
X9279UV14IZ* (Note)
X9279TV14-2.7*
X9279TV F
X9279TV14I-2.7*
X9279TV G
X9279UV14-2.7*
X9279UV F
2.7 to 5.5
100
0 to 70
14 Ld TSSOP (4.4mm)
-40 to 85
14 Ld TSSOP (4.4mm)
0 to 70
14 Ld TSSOP (4.4mm)
0 to 70
14 Ld TSSOP (4.4mm) (Pb-free)
50
X9279UV14Z-2.7 (Note)
X9279UV14I-2.7*
PACKAGE
X9279UV G
X9279UV14IZ-2.7* (Note)
-40 to 85
14 Ld TSSOP (4.4mm)
-40 to 85
14 Ld TSSOP (4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
DETAILED FUNCTIONAL DIAGRAM
VCC
Bank 0
DR0 DR1
SCL
SDA
A2
A1
DR2 DR3
INTERFACE
AND
CONTROL
CIRCUITRY
A0
Power-on Recall
RH
WIPER
50kΩ and 100kΩ
256-taps
COUNTER
REGISTER
(WCR)
RL
RW
DATA
WP
Bank 1
Bank 2
Bank 3
DR0 DR1
DR0 DR1
DR0 DR1
DR2 DR3
DR2 DR3
DR2 DR3
Control
12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits
VSS
2
FN8175.2
September 27, 2005
X9279
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Trim out the offset voltage error in a voltage
amplifier circuit
• Control the gain in audio and home entertainment
systems
• Set the output voltage of a voltage regulator
• Provide the variable DC bias for tuners in RF
wireless systems
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the operating points in temperature control
systems
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Control the operating point for sensors in industrial
systems
• Vary the frequency and duty cycle of timer ICs
• Trim offset and gain errors in artificial intelligent
systems
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
PIN CONFIGURATION
TSSOP
NC
A0
NC
A2
SCL
SDA
VSS
14
1
X9279
13
2
3
12
4
11
5
10
6
9
8
7
VCC
RL
RH
RW
A3
A1
WP
PIN ASSIGNMENTS
Pin
TSSOP
Symbol
1
NC
No Connect
2
A0
Device Address for 2-Wire bus.
3
NC
No Connect
4
A2
Device Address for 2-Wire bus.
5
SCL
Serial Clock for 2-Wire bus.
6
SDA
Serial Data Input/Output for 2-Wire bus.
7
VSS
System Ground.
8
WP
Hardware Write Protect
9
A1
Device Address for 2-Wire bus.
10
A3
Device Address for 2 wire-bus.
11
RW
Wiper Terminal of the Potentiometer.
12
RH
High Terminal of the Potentiometer.
13
RL
Low Terminal of the Potentiometer.
14
VCC
Function
System Supply Voltage.
3
FN8175.2
September 27, 2005
X9279
PIN DESCRIPTIONS
Potentiometer Pins
Bus Interface Pins
RH, RL
SERIAL DATA INPUT/OUTPUT (SDA)
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of
the serial clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.
SERIAL CLOCK (SCL)
RW
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS
pin is the system ground.
Other Pins
NO CONNECT
This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9279.
DEVICE ADDRESS (A2 - A0)
The Address inputs are used to set the least
significant 3 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9279. A maximum of 8
devices may occupy the 2-Wire serial bus.
4
No connect pins should be left open. This pins are used
for Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
FN8175.2
September 27, 2005
X9279
PRINCIPLES OF OPERATION
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time.
The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
– Resistor Array Description.
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
– Serial Interface Description.
– Instruction and Register Description.
Array Description
The X9279 is comprised of a resistor array (See Figure
1). The array contains, in effect, 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL inputs).
Power-up and Down Recommendations.
There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to
the potentiometer pins provided that VCC is always
more positive than or equal to VH, VL, and VW, i.e.,
VCC ≥ VH, VL, VW. The VCC ramp rate specification is
always in effect.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL
BUS
INPUT
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 1
(DR1)
8
8
BANK_0 Only
REGISTER 2
(DR2)
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
REGISTER 3
(DR3)
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
RH
C
O
U
N
T
E
R
D
E
C
O
D
E
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
RL
RW
5
FN8175.2
September 27, 2005
X9279
SERIAL INTERFACE DESCRIPTION
Serial Interface
The X9279 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9279 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.
Start Condition
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9279 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9279 will respond with a final acknowledge.
See Figure 2.
Figure 2. Acknowledge Response from Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
6
ACKNOWLEDGE
FN8175.2
September 27, 2005
X9279
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9279
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9279 is still busy with the write operation no ACK
will be returned. If the X9279 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
FLOW 1: ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Issue STOP
No
INSTRUCTION AND REGISTER DESCRIPTION
Device Addressing: Identification Byte ( ID and A)
The first byte sent to the X9279 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device ID for the X9279; this is fixed as
0101[B] (refer to Table 1).
The A[2:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A2 - A0 input pins. The slave address
is externally specified by the user. The X9279
compares the serial data stream with the address
input state; a successful compare of both address bits
is required for the X9279 to successfully continue the
command sequence. Only the device which slave
address matches the incoming device address sent by
the master executes the instruction. The A2 - A0
inputs can be actively driven by CMOS input signals or
tied to VCC or VSS.
Instruction Byte (I)
The next byte sent to the X9279 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [2:0]. The RB and RA bits point to one of the
four Data Registers. P0 is the POT selection; since the
X9279 is single POT, the P0 = 0. The format is shown
in Table 2.
Yes
Further
Operation?
Register Bank Selection (RB, RA, P1, P0)
There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for Data Register to Wiper Counter
Register operations.
No
Yes
Issue
Instruction
Issue STOP
Proceed
Proceed
7
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for 2-Wire write and read
operations. The Data Registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
between the Wiper Counter Register.
FN8175.2
September 27, 2005
X9279
Register Selection (R0 to R3) Table
Register Bank Selection (Bank 0 to Bank 3) Table
Register
RB
0
Bank
RA Selection
Operations
0
0
Data Register Read and Write;
Wiper Counter Register
Operations
1
1
Data Register Read and Write;
Wiper Counter Register
Operations
0
2
Data Register Read and Write;
Wiper Counter Register
Operations
1
3
Data Register Read and Write;
Wiper Counter Register
Operations
0
1
1
P1
0
P0
0
0
1
1
0
1
1
Selection
Operations
0
Data Register Read and Write;
Wiper Counter Register
Operations
1
Data Register Read and
Write Only
2
Data Register Read and
Write Only
3
Data Register Read and
Write Only
Table 1. Identification Byte Format
Device Type
Identifier
Set to 0
for proper operation
ID3
ID2
ID1
ID0
0
1
0
1
0
A2
Internal Slave
Address
A1
(MSB)
A0
(LSB)
Table 2. Instruction Byte Format
P1 and P0 are used also for register Bank Selection
for 2-Wire Register Write and Read operations
Register
Selection
Instruction Opcode
Register Selection
Register Selected
I3
I2
I1
I0
(MSB)
RB
RA
P1
RB
RA
P0
DR0
0
0
(LSB)
DR1
0
1
DR2
1
0
DR3
1
1
Pot Selection (Bank Selection)
Set to P0 = 0 for potentiometer operations
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FN8175.2
September 27, 2005
X9279
Table 3. Instruction Set
I3
1
I2
0
Instruction Set
I1 I0 RB RA
0
1
0
0
1
0
1
0
0
1
0
1
1
Write Data Register
1
1
0
XFR Data Register to
Wiper Counter Register
1
1
XFR Wiper Counter
Register to Data Register
Increment/Decrement
Wiper Counter Register
1
0
Instruction
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
Note:
P1
0
P0
0
0
0
0
1/0
1/0
1/0
1/0
0
1/0
1/0
1/0
1/0
0
1
1/0
1/0
0
0
1
1
0
1/0
1/0
0
0
0
1
0
0
0
0
0
Operation
Read the contents of the Wiper Counter
Register
Write new value to the Wiper Counter
Register
Read the contents of the Data Register pointed to
by P1 - P0 and RB - RA
Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
Transfer the contents of the Data Register
pointed to by RB - RA (Bank 0 only) to the Wiper
Counter Register
Transfer the contents of the Wiper Counter Register
to the Register pointed to by RB-RA (Bank 0 only)
Enable Increment/decrement of the Wiper Counter
Register
1/0 = data is one or zero
DEVICE DESCRIPTION
Wiper Counter Register (WCR)
The X9279 contains contains a Wiper Counter
Register, for the DCP potentiometer. The Wiper
Counter Register can be envisioned as a 8-bit parallel
and serial load counter with its outputs decoded to
select one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
Data Registers (DR)
The potentiometer has four 8-bit nonvolatile Data
Registers (DR3-DR0). These can be read or written
directly by the host. Data can also be transferred
between any of the four Data Registers and the
associated Wiper Counter Register. All operations
changing data in one of the Data Registers is a
nonvolatile operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bit [7:0] are used to store one of the 256 wiper
positions (0~255).
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9279 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR. The
DR0 value of Bank 0 is the default value.
9
FN8175.2
September 27, 2005
X9279
Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
(MSB)
(LSB)
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
NV
V
NV
NV
NV
NV
NV
Bit 0
NV
MSB
NV
LSB
Two instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9279; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
Instructions
Four of the seven instructions are three bytes in
length. These instructions are:
– Read Wiper Counter Register – read the current
wiper position of the potentiometer,
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the Wiper Counter Register.
– Write Wiper Counter Register – change current
wiper position of the potentiometer,
– Read Data Register – read the contents of the
selected Data Register;
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the Wiper Counter
Register to the specified Data Register.
– Write Data Register – write a new value to the
selected Data Register.
The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the X9279 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH,
the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the RL terminal.
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between the potentiometer and one of its four
associated registers (Bank 0).
See Instruction format for more details.
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
0
1
0
1
S ID3 ID2 ID1 ID0 0 A2 A1 A0
T
A
Internal
R
Device ID
T
Address
0
A
C
K
I3
I2 I1 I0
Instruction
Opcode
0
RB RA P1 P0 A
C
K
Register
Pot/Bank
Address
Address
S
T
O
P
These commands only valid when P1 = P0 = 0
10
FN8175.2
September 27, 2005
X9279
Figure 4. Three-Byte Instruction Sequence
SCL
0
1
0
S ID3 ID2 ID1 ID0
T
A
R
Device ID
T
0
SDA
1
0
A2 A1 A0
External
Address
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0 A S
I0 RB RA P1 P0 A
C
C T
K
K O
Pot/Bank
WCR[7:0]
valid
only
when
P1=P0=0;
Instruction
P
Register
Address
or
Opcode
Address
Data Register D[7:0] for all values of P1 and P0
I3 I2
I1
Figure 5. Increment/Decrement Instruction Squence
SCL
0
SDA
S
T
A
R
T
1
0
1
0
ID3 ID2 ID1 ID0 0 A2
A1 A0
External
Address
Device ID
A
C
K
I3
I2
I1 I0
Instruction
Opcode
RB RA P1 P0
A
C
Register Pot/Bank K
Address
Address
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
tWRID
SCL
SDA
Voltage Out
VW/RW
11
FN8175.2
September 27, 2005
X9279
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
DR/Bank
S
Opcode
Addresses
A
C
0 A2 A1 A0 K 1 0 0 1 0 0 0 0
S
A
C
K
Wiper Position
(Sent by X9279 on SDA) M
W W W W W W W W A
C C C C C C C C C
R R R R R R R R K
7 6 5 4 3 2 1 0
S
T
O
P
S
A
C
K
Wiper Position
(Sent by Master on SDA) S
W W W W W W W W A
C C C C C C C C C
R R R R R R R R K
7 6 5 4 3 2 1 0
S
T
O
P
Write Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
DR/Bank
S
Opcode
Addresses
A
C
0 A2 A1 A0 K 1 0 1 0 0 0 0 0
Read Data Register (DR)
S
T
A
R
T
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
DR/Bank
S
Opcode
Addresses
A
C
0 A 2 A 1 A 0 K 1 0 1 1 RB RA P1 P0
S
A
C
K
Wiper Position
(Sent by X9279 on SDA) M
W W W W W W W W A
C C C C C C C C C
R R R R R R R R K
7 6 5 4 3 2 1 0
S
A
C
K
Wiper Position
(Sent by Master on SDA) S
W W W W W W W W A
C C C C C C C C C
R R R R R R R R K
7 6 5 4 3 2 1 0
S
T
O
P
S
T
A
R
T
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
DR/Bank
S
Opcode
Addresses
A
C
0 A2 A1 A0
1 1 0 0 RB RA P1 P0
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
DR/Bank
S
S
Opcode
Addresses
A
A
C
C
0 A2 A1 A0
1 1 1 0 RB RA 0 0
K
K
12
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
FN8175.2
September 27, 2005
X9279
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S Device Type
T
Identifier
A
R 0 1 0 1
T
Device
Addresses
Instruction
DR/Bank
S
S
Opcode
Addresses
A
A
C
C
0 A 2 A 1 A 0 K 1 1 0 1 RB RA 0 0 K
S
T
O
P
Increment/Decrement Wiper Counter Register (WCR)
S Device Type
T
Identifier
A
R 0 1 0 1
T
Notes: (1)
(2)
(3)
(4)
(5)
Device
Addresses
Instruction
DR/Bank
S
Opcode
Addresses
A
C
0 A2 A1 A0 K 0 0 1 0 0 0 0 0
Increment/Decrement
S
(Sent by Master on SDA)
A
C
K I/D I/D . . . . I/D I/D
S
T
O
P
“MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
“A3 ~ A0”: stands for the device addresses sent by the master.
“X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
“I”: stands for the increment operation, SDA held high during active SCL phase (high).
“D”: stands for the decrement operation, SDA held low during active SCL phase (high).
13
FN8175.2
September 27, 2005
X9279
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCL, SDA any address input
with respect to VSS ................................. -1V to +7V
∆V = | (VH - VL) |................................................... 5.5V
Lead temperature (soldering, 10s) .................... 300°C
IW (10s) ..............................................................±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Supply Voltage (VCC)(4) Limits
5V ± 10%
2.7V to 5.5V
Device
X9279
X9279-2.7
ANALOG CHARACTERISTICS (Over recommended industrial (2.7V) operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min.
Typ.
RTOTAL
End to End Resistance
100
RTOTAL
End to End Resistance
50
Max.
Units
Test Conditions
kΩ
T version
kΩ
U version
End to End Resistance Tolerance
±20
%
Power Rating
50
mW
25°C, each pot
IW
Wiper Current
±3
mA
RW
Wiper Resistance
300
Ω
IW = ± 3mA @ VCC = 3V
RW
Wiper Resistance
150
Ω
IW = ± 3mA @ VCC = 5V
VTERM
Voltage on any RH or RL Pin
VCC
V
VSS = 0V
Noise
VSS
Resolution
0.4
Ref: 1V
%
Absolute Linearity (1)
±1
MI(3)
Rw(n)(actual) - Rw(n)(expected)(5)
Relative Linearity (2)
±0.2
MI(3)
Rw(n + 1) - [Rw(n) + MI](5)
Temperature Coefficient of
RTOTAL
±300
Ratiometric Temp. Coefficient
CH/CL/CW
dBV/√Hz
-120
Potentiometer Capacitances
ppm/°C
20
10/10/25
ppm/°C
pF
See Macro model
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (RH - RL) / 255, single pot
(4) During power-up VCC > VH, VL, and VW.
(5) n = 0, 1, 2, ....,255; m =0, 1, 2, ...., 254.
14
FN8175.2
September 27, 2005
X9279
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
VCC supply current
(active)
3
mA
fSCL = 400kHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active, Read
and Volatile Write States only)
ICC2
VCC supply current
(nonvolatile write)
5
mA
fSCL = 400kHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)
ISB
VCC current (standby)
5
µA
ILI
Input leakage current
10
µA
VCC = +6V; VIN = VSS or VCC;
SDA = VCC; (for 2-Wire, Standby
State only)
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW voltage
-1
VCC x 0.3
V
VOL
Output LOW voltage
0.4
V
VOH
Output HIGH voltage
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
CAPACITANCE
Symbol
CIN/OUT
(6)
CIN(6)
Test
Max.
Units
Test Conditions
Input / Output capacitance (SDA)
8
pF
VOUT = 0V
Input capacitance (SCL, WP, A2, A1 and A0)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tr VCC
(6)
tPUR(7)
tPUW(7)
Parameter
VCC Power-up rate
Min.
Max.
Units
0.2
50
V/ms
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
50
ms
A.C. TEST CONDITIONS
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.
These parameters are periodically sampled and not 100% tested.
15
FN8175.2
September 27, 2005
X9279
EQUIVALENT A.C. LOAD CIRCUIT
5V
SPICE Macromodel
3V
1533Ω
RTOTAL
867Ω
SDA pin
RH
SDA pin
RL
CW
CL
100pF
100pF
CL
10pF
25pF
10pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Units
400
kHz
fSCL
Clock Frequency
tCYC
Clock Cycle Time
2500
ns
tHIGH
Clock High Time
600
ns
tLOW
Clock Low Time
1300
ns
tSU:STA
Start Setup Time
600
ns
tHD:STA
Start Hold Time
600
ns
tSU:STO
Stop Setup Time
600
ns
tSU:DAT
SDA Data Input Setup Time
100
ns
tHD:DAT
SDA Data Input Hold Time
30
ns
tR
SCL and SDA Rise Time
300
ns
tF
SCL and SDA Fall Time
300
ns
tAA
SCL Low to SDA Data Output Valid Time
0.9
µs
tDH
SDA Data Output Hold Time
0
ns
TI
Noise Suppression Time Constant at SCL and SDA inputs
50
ns
tBUF
Bus Free Time (Prior to Any Transmission)
1200
ns
tSU:WPA
A0, A1 Setup Time
0
ns
tHD:WPA
A0, A1 Hold Time
0
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
16
Typ.
Max.
Units
5
10
ms
FN8175.2
September 27, 2005
X9279
XDCP TIMING
Symbol
Parameter
Min.
Max.
Units
tWRPO
Wiper response time after the third (last) power supply is stable
5
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
5
10
µs
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
.
17
FN8175.2
September 27, 2005
X9279
TIMING DIAGRAMS
Start and Stop Timing
(START)
(STOP)
tR
tF
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tAA
18
tDH
FN8175.2
September 27, 2005
X9279
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
VWx
Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
19
FN8175.2
September 27, 2005
X9279
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
VO
100kΩ
–
VO
+
}
}
TL072
R1
R2
10kΩ
10kΩ
+12V
10kΩ
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
20
FN8175.2
September 27, 2005
X9279
Application Circuits (continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
V O = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
V O = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
21
FN8175.2
September 27, 2005
X9279
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
DetailA(20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
22
FN8175.2
September 27, 2005