TOREX XC610101A216ER

XC6101~XC6107, XC6111~XC6117 Series
ETR0207_010
Voltage Detector (VDF=1.6V~5.0V)
■GENERAL DESCRIPTION
The XC6101~XC6107, XC6111~XC6117 series are groups of high-precision, low current consumption voltage detectors with
manual reset input and watchdog functions incorporating CMOS process technology. The series consist of a reference
voltage source, delay circuit, comparator, and output driver. With the built-in delay circuit, the XC6101 ~ XC6107, XC6111 ~
XC6117 series do not require any external components to output signals with release delay time. Moreover, with the manual
reset function, reset can be asserted at any time. The ICs produce two types of output; VDFL (low when detected) and VDFH
(high when detected). With the XC6101 ~ XC6105, XC6111 ~ XC6115 series, the WD pin can be left open if the watchdog
function is not used. Whenever the watchdog pin is opened, the internal counter clears before the watchdog timeout occurs.
Since the manual reset pin is internally pulled up to the VIN pin voltage level, the ICs can be used by leaving the manual reset
pin unconnected if the pin is unused. The detect voltages are internally fixed 1.6V ~ 5.0V in increments of 100mV, using laser
trimming technology. Six watchdog timeout periods are available in a range from 6.25ms to 1.6s. Seven release delay times
are available in a range from 3.13ms to 1.6s.
■APPLICATIONS
■FEATURES
●Microprocessor reset circuits
●Memory battery backup circuits
●System power-on reset circuits
●Power failure detection
Detect Voltage Range
: 1.6V ~ 5.0V, +2%
(100mV increments)
Hysteresis Width
: VDF x 5%, TYP.
(XC6101~XC6107)
VDF x 0.1%, TYP.
(XC6111~XC6117)
Operating Voltage Range : 1.0V ~ 6.0V
Detect Voltage Temperature: +100ppm/OC (TYP.)
Coefficient
Output Configuration
: N-channel open drain,
CMOS
Reset Output Options
: VDFL (Low when detected)
VDFH (High when detected)
Watchdog Function
: Watchdog input WD;
If it remains ether high or low for
the duration of the watchdog
timeout period, a reset is
asserted.
Manual Reset Function
: Manual Reset Input MRB;
When it changes from high to
low, a reset is asserted.
Release Delay Time
: 1.6s, 400ms, 200ms, 100ms,
50ms, 25ms, 3.13ms (TYP.)
Watchdog Timeout Period : 1.6s, 400ms, 200ms, 100ms,
50ms, 6.25ms (TYP.)
: SOT-25, USP-6C
Packages
■TYPICAL APPLICATION CIRCUIT
■TYPICAL PERFORMANCE
CHARACTERISTICS
●Supply Current vs. Input Voltage
μP
V IN
XC61X1~XC61X5 (2.7V)
30
V IN
Rpull ＊
V IN
RESETB
WD
MRB
V SS
RESETB
INPUT
I/O
VS S
Supply Current: ISS (μA)
XC6101/XC6102
25
20
Ta=25℃
15
Ta=85℃
10
Ta=-40℃
5
0
* Not necessary with CMOS output products.
0
1
2
3
4
5
Input Voltage: VIN (V)
6
* ‘x’ represents both ‘0’ and ‘1’. (ex. XC61x1⇒XC6101 and XC6111)
1/27
XC6101~XC6107, XC6111~XC6117 Series
■PIN CONFIGURATION
●SOT-25
XC6101, XC6102 Series
XC6111, XC6112 Series
XC6103 & XC6113 Series
XC6104, XC6105 Series
XC6114, XC6115 Series
XC6106, XC6107 Series
XC6116, XC6117 Series
VIN
WD
VIN
WD
VIN
WD
VIN
MRB
5
4
5
4
5
4
5
4
1
RESETB
2
VSS
1
3
2
RESET
MRB
SOT-25 (TOP VIEW)
VSS
3
1
MRB
RESETB
2
1
3
RESETB
VSS RESET
2
3
VSS RESET
SOT-25 (TOP VIEW)
SOT-25 (TOP VIEW)
SOT-25 (TOP VIEW)
XC6103 & XC6113 Series
XC6104, XC6105 Series
XC6114, XC6115 Series
XC6106, XC6107 Series
XC6116, XC6117 Series
●USP-6C
XC6101, XC6102 Series
XC6111, XC6112 Series
VIN 6
1 WD
VIN 6
1 WD
V IN 6
1 WD
V IN 6
1 MRB
VSS 5
2 MRB
VSS 5
2 MRB
V SS 5
2 RESET
V SS 5
2 RESET
3 NC
RESETB 4
3 NC
RESET 4
USP-6C (BOTTOM VIEW)
3 NC
RESETB 4
USP-6C (BOTTOM VIEW)
USP-6C (BOTTOM VIEW)
RESETB 4
3 NC
USP-6C (BOTTOM VIEW)
* The dissipation pad for the USP-6C package should be
solder-plated in recommended mount pattern and metal
masking so as to enhance mounting strength and heat
release. If the pad needs to be connected to other pins, it
should be connected to the VSS (No.5) pin.
■PIN ASSIGNMENT
PIN NUMBER
XC6101, XC6102
XC6103
XC6104, XC6105 XC6106, XC6107
PIN NAME
XC6111, XC6112
XC6113
XC6114, XC6115 XC6116, XC6117
SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C
2/27
FUNCTION
1
4
-
-
1
4
1
4
RESETB
Reset Output
(VDFL: Low Level When Detected)
2
5
2
5
2
5
2
5
VSS
Ground
3
2
3
2
-
-
4
1
MRB
Manual Reset
4
1
4
1
4
1
-
-
WD
Watchdog
5
6
5
6
5
6
5
6
VIN
Power Input
-
-
1
4
3
2
3
2
RESET
Reset Output
(VDFH: High Level When Detected)
XC6101 ~ XC6107, XC6111~ XC6117
Series
■PRODUCT CLASSIFICATION
●Selection Guide
SERIES
WATCHDOG
MANUAL
RESET OUTPUT
RESET
VDFL (RESETB)
VDFH (RESET)
XC6101
XC6111
Available
Available
CMOS
-
XC6102
XC6112
Available
Available
N-channel open drain
-
XC6103
XC6113
Available
Available
-
CMOS
XC6104
XC6114
Available
Not Available
CMOS
CMOS
XC6105
XC6115
Available
Not Available
N-channel open drain
CMOS
XC6106
XC6116
Not Available
Available
CMOS
CMOS
XC6107
XC6117
Not Available
Available
N-channel open drain
CMOS
●Ordering Information
XC61①②③④⑤⑥⑦⑧
DESIGNATOR
DESCRIPTION
①
Hysteresis Width
②
③
Functions and
Type of Reset Output
Release Delay Time *
SYMBOL
0
: VDF x 5% (TYP.) with hysteresis
1
: VDF x 0.1% (TYP.) without hysteresis
: Watchdog and manual functions, and reset
1~7
Watchdog Timeout Period
⑤⑥
Detect Voltage
⑦
Packages
⑧
Device Orientation
output type as per Selection Guide in the above
chart
A
: 3.13ms (TYP.)
B
: 25ms (TYP.)
C
: 50ms (TYP.)
D
: 100ms (TYP.)
E
: 200ms (TYP.)
F
: 400ms (TYP.)
H
: 1.6s (TYP.)
0
④
DESCRIPTION
: No WD timeout period for
XC6106, XC6107, XC6116, XC6117 Series
1
: 6.25ms (TYP.)
2
: 50ms (TYP.)
3
: 100ms (TYP.)
4
: 200ms (TYP.)
5
: 400ms (TYP.)
6
: 1.6s (TYP.)
16 ~ 50
: Detect voltage
ex.) 4.5V: ⑤⇒4, ⑥⇒5
M
: SOT-25
E
: USP-6C
R
: Embossed tape, standard feed
L
: Embossed tape, reverse feed
* Please set the release delay time shorter than or equal to the watchdog timeout period.
ex.) XC6101D427MR or XC6101D327MR
3/27
XC6101~XC6107, XC6111~XC6117 Series
■BLOCK DIAGRAMS
●XC6101, XC6111 Series
●XC6102, XC6112 Series
●XC6103, XC6113 Series
4/27
XC6101 ~ XC6107, XC6111~ XC6117
Series
■BLOCK DIAGRAMS (Continued)
●XC6104, XC6114 Series
●XC6105, XC6115 Series
●XC6106, XC6116 Series
●XC6107, XC6117 Series
5/27
XC6101~XC6107, XC6111~XC6117 Series
■ABSOLUTE MAXIMUM RATINGS
Ta = 25OC
PARAMETER
SYMBOL
RATINGS
UNITS
VIN
VSS -0.3 ~ 7.0
V
MRB
VSS -0.3 ~ VIN +0.3
V
WD
VSS -0.3 ~ 7.0
V
IOUT
20
mA
CMOS Output
RESETB/RESET
VSS -0.3 ~ VIN +0.3
N-ch Open Drain Output
RESETB
VSS -0.3 ~ 7.0
Input Voltage
Output Current
V
Output Voltage
Power Dissipation
SOT-25
Pd
USP-6C
6/27
250
mW
100
Operational Temperature Range
Topr
-40 ~ +85
O
C
Storage Temperature Range
Tstg
-40 ~ +125
O
C
XC6101 ~ XC6107, XC6111~ XC6117
Series
■ELECTRICAL CHARACTERISTICS
●XC6101~XC6107, XC6111~XC6117 Series
PARAMETER
Detect Voltage
Hysteresis Width
XC6101~XC6107 (*1)
Hysteresis Width
XC6111~XC6117 (*2)
Supply Current
SYMBOL
VDFL
VDFH
VHYS
MIN.
VDF(T)
× 0.98
VDF
× 0.02
VHYS
0
ISS
CONDITIONS
VIN=1.0V
VIN=2.0V (VDFL(T)> 2.0V)
VIN=3.0V (VDFL(T) >3.0V)
VIN=4.0V (VDFL(T) >4.0V)
1.0
0.15
2.0
3.0
3.5
VDF
× 0.05
VDF
× 0.001
5
10
12
4
8
10
0.5
2.5
3.5
4.0
MAX.
VDF(T)
× 1.02
VDF
× 0.08
VDF
x 0.01
11
16
18
10
14
16
6.0
-
VIN=6.0V
-
- 1.1
-0.8
④
VIN=6.0V
4.4
4.9
-
③
VIN=1.0V
VIN=2.0V (VDFH(T)> 2.0V)
VIN=3.0V (VDFH(T)>3.0V)
VIN=4.0V (VDFH(T)>4.0V)
-
- 0.08
- 0.50
- 0.75
- 0.95
- 0.02
- 0.30
- 0.55
- 0.75
-
+100
-
2
13
25
60
120
240
3.13
25
50
100
200
400
5
38
75
140
280
560
960
2
13
25
60
120
240
960
1600
3.13
25
50
100
200
400
1600
2240
5
38
75
140
280
560
2240
XC61X1/XC61X2/XC61X3 VIN=VDF(T)×0.9V
XC61X4/XC61X5 (*3)
(The MRB & the WD Pin: VIN=VDF(T)×1.1V
No connection)
VIN=6.0V
XC61X6/XC61X7
(The MRB Pin:
No connection)
Operating Voltage
VDFL
Output Current
(RESETB)
IRBOUT
Temperature
Coefficient
△VDF /
△Topr・VDF
Detect Delay Time
VDFL/VDFH
CMOS Output
Leak Current
VDFL N-ch Open Drain
Output
Leak Current
N-ch.
VDS = 0.5V
CMOS,
P-ch
VDS = 0.5V
N-ch
VDS = 0.5V
IROUT
Release Delay Time
(VDF>1.9V)
VIN=VDF(T)×0.9V
VIN=VDF(T)×1.1V
VIN=6.0V
VIN
VDFH
Output Current
(RESET)
Release Delay Time
(VDF<1.8V)
(*3)
TDR
P-ch.
VDS = 0.5V
-40OC < Topr < 85 OC
Time until VIN is increased from
1.0V to 2.0V
and attains to the release time level,
and the Reset output pin inverts.
TYP.
Ta = 25 OC
UNITS CIRCUIT
VDF(T)
V
①
V
①
V
①
μA
②
V
①
③
mA
mA
④
ppm/ OC
①
ms
⑤
ms
⑤
TDR
Time until VIN is increased from
1.0V to (VDFx1.1V)
and attains to the release time level,
and the Reset output pin inverts.
TDF
Time until VIN is decreased from 6.0V to
1.0V and attains to the detect voltage
level, and the Reset output pin detects
while the WD pin left opened.
-
3
30
μs
⑤
ILEAK
VIN=6.0V, RESETB=6.0V (VDFL)
VIN=6.0V, RESET=0V (VDFH)
-
0.01
-
μA
③
ILEAK
VIN=6.0V, RESETB=6.0V
-
0.01
0.10
μA
③
NOTE:
*1: XC6101~XC6107 (with hysteresis)
*2: XC6111~XC6117 (without hysteresis)
*3: ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
*4: VDF(T): Setting detect voltage
*5: If only “VDF” is indicated, it represents both VDFL (low when detected) and VDFH (high when detected).
7/27
XC6101~XC6107, XC6111~XC6117 Series
■ELECTRICAL CHARACTERISTICS (Continued)
●XC6101~XC6105, XC6111~XC6115 Series
PARAMETER
SYMBOL
CONDITIONS
Watchdog
Timeout Period
(VDF<1.8V)
TWD
Time until VIN increases form
1.0V to 2.0V and
the Reset output pin is released to go into
the detection state. (WD=VSS)
Watchdog
Timeout Period
(VDF>1.9V)
TWD
Time until VIN increases form
1.0V to (VDFx1.1V)
and the Reset output pin is released to go
into the detection state. (WD=VSS)
Watchdog
Minimum Pulse Width
TWDIN
Watchdog
High Level Voltage
Watchdog
Low Level Voltage
Watchdog
Input Current
Watchdog
Input Resistance
MIN.
3.13
25
60
120
240
960
3.13
25
60
120
240
960
TYP.
6.25
50
100
200
400
1600
6.25
50
100
200
400
1600
MAX.
9.38
75
140
280
560
2240
9.38
75
140
280
560
2240
VIN=6.0V,
Apply pulse from 6.0V to 0V
to the WD pin.
300
-
VWDH
VIN=VDF x 1.1V ~ 6.0V
VIN x 0.7
VWDL
VIN=VDF x 1.1V ~ 6.0V
0
IWD
VIN=6.0V, VWD=6.0V (Avg. when peak )
VIN=6.0V, VWD=0V (Avg. when peak)
RWD
VIN=6.0V, VWD=0V, RWD=VIN/ |IWD|
315
ms
⑥
ms
⑥
-
ns
⑦
-
6
V
⑦
-
VIN x 0.3
V
⑦
-
12
19
- 19
-12
-
μA
⑧
500
880
kΩ
⑧
●XC6101 ~ XC6103, XC6106 ~ XC6107, XC6111 ~ XC6113, XC6116 ~ XC6117 Series
PARAMETER
MRB
High Level Voltage
MRB
Low Level Voltage
MRB
Pull-up Resistance
MRB Minimum
(*3)
Pulse Width
XC6101~XC6105
XC6111~XC6115
MRB Minimum
(*4)
Pulse Width
XC6106, XC6107
XC6116, XC6117
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
VMRH
VIN=VDFx1.1V ~ 6.0V
1.4
-
VIN
VMRL
VIN=VDFx1.1V ~ 6.0V
0
-
0.35
RMR
VIN=6.0V, MRB=0V, RMR=VIN/ |IMRB|
1.6
2.4
3.0
TMRIN
VIN=6.0V,
Apply pulse from 6.0V to 0V to
the MRB pin
2.8
-
-
TMRIN
VIN=6.0V,
Apply pulse from 6.0V to 0V to
the MRB pin
1.2
-
NOTE:
*1: VDF(T): Setting detect voltage
*2: If only “VDF” is indicated, it represents both VDFL (low when detected) and VDFH (high when detected).
*3: Watchdog function is available.
*4: Watchdog function is not available.
8/27
Ta = 25 OC
UNITS CIRCUIT
-
Ta = 25 OC
UNITS CIRCUIT
V
⑨
⑨
MΩ
⑩
μs
⑪
XC6101 ~ XC6107, XC6111~ XC6117
Series
■OPERATIONAL EXPLANATION
The XC6101~XC6107, XC6111~XC6117 series compare, using the error amplifier, the voltage of the internal voltage
reference source with the voltage divided by R1, R2 and R3 connected to the VIN pin. The resulting output signal from the
error amplifier activates the watchdog logic, manual reset logic, delay circuit and the output driver. When the VIN pin voltage
gradually falls and finally reaches the detect voltage, the RESETB pin output goes from high to low in the case of the VDFL type
ICs, and the RESET pin output goes from low to high in the case of the VDFH type ICs.
<RESETB / RESET Pin Output Signal>
* VDFL (RESETB) type - output signal: Low when detected.
The RESETB pin output goes from high to low whenever the VIN pin voltage falls below the detect voltage, or whenever the
MRB pin is driven from high to low. The RESETB pin remains low for the release delay time (TDR) after the VIN pin voltage
reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period,
the RESETB pin output remains low for the release delay time (TDR), and thereafter the RESET pin outputs high level signal.
* VDFH (RESET) type – output signal: High when detected.
The RESET pin output goes from low to high whenever the VIN pin voltage falls below the detect voltage, or whenever the
MRB pin is driven from high to low. The RESET pin remains high for the release delay time (TDR) after the VIN pin voltage
reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period,
the VOUT pin output remains high for the release delay time (TDR), and thereafter the RESET pin outputs low level signal.
<Hysteresis>
When the internal comparator output is high, the NMOS transistor connected in parallel to R3 is turned ON, activating the
hysteresis circuit. The difference between the release and detect voltages represents the hysteresis width, as shown by the
following calculations:
VDF (detect voltage) = (R1+R2+R3) x Vref(R2+R3)
VDR (release voltage) = (R1+R2) x Vref(R2)
VHYS (hysteresis width)=VDR-VDF (V)
VDR > VDF
* Detect voltage (VDF) includes conditions of both VDFL (low when detected) and VDFH (high when detected).
* Please refer to the block diagrams for R1, R2, R3 and Vref.
Hysteresis width is selectable from VDF x 0.05V (XC6101~XC6107) or VDF x 0.001V (XC6111~XC6117).
<Watchdog (WD) Pin>
The XC6101~XC6107, XC6111~XC6117 series use a watchdog timer to detect malfunction or “runaway” of the
microprocessor. If neither rising nor falling signals are applied from the microprocessor within the watchdog timeout period,
the RESETB/RESET pin output maintains the detection state for the release delay time (TDR), and thereafter the
RESET/RESETB pin output returns to the release state (Please refer to the FUNCTION CHART). The timer in the watchdog
is then restarted. Six watchdog timeout period settings are available in 1.6s, 400ms, 200ms, 100ms, 50ms, 6.25ms.
<MRB Pin>
Using the MRB pin input, the RESET/RESETB pin signal can be forced to the detection state. When the MRB pin is driven
from high to low, the RESETB pin output goes from high to low in the case of the VDFL type ICs, and the RESET pin output
goes from low to high in the case of the VDFH type. Even after the MRB pin is driven back high, the RESET/RESETB pin
output maintains the detection state for the release delay time (TDR). Since the MRB pin is internally pulled up to the VIN pin
voltage level, leave the MRB pin open if unused (Please refer to the FUNCTION CHART). A diode, which is an input
protection element, is connected between the MRB pin and VIN pin. Therefore, if the MRB pin is applied voltage that exceeds
VIN, the current will flow to VIN through the diode. Please use this IC within the stated maximum ratings (VSS -0.3 ~ VIN +0.3)
on the MRB pin.
<Release Delay Time>
Release delay time (TDR) is the time that elapses from when the VIN pin reaches the release voltage, or when the watchdog
timeout period expires with no rising signal applied to the WD pin, until the RESET/RESETB pin output is released from the
detection state. Seven release delay time (TDR) watchdog timeout period settings are available in 1.6s, 400ms, 200ms,
100ms, 50ms, 25ms, 3.13ms.
<Detect Delay Time>
Detect Delay Time (TDF) is the time that elapses from when the VIN pin voltage falls to the detect voltage until the RESET/
RESETB pin output goes into the detection state.
9/27
XC6101~XC6107, XC6111~XC6117 Series
■TIMING CHARTS
●CMOS Output
●TDF (CMOS Output)
VIN
6.0V
VIN Pin Wave Form
VDFL Level
1.0V
GND
TDF
VIN Level
VDFL Level
VIN x 0.1V
GND
10/27
RESETB Pin Wave Form (VDFL)
0.6V
XC6101 ~ XC6107, XC6111~ XC6117
Series
■NOTES ON USE
1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent
damage to the device.
2. When a resistor is connected between the VIN pin and the input, the VIN voltage drops while the IC is operating and a
malfunction may occur as a result of the IC’s through current. For the CMOS output products, the VIN voltage drops while
the IC is operating and malfunction may occur as a result of the IC’s output current. Please be careful with using the
XC6111~XC6117 series (without hysteresis).
3. In order to stabilize the IC’s operations, please ensure that the VIN pin’s input frequency’s rise and fall times are more than
1 μs/V.
4. Noise at the power supply may cause a malfunction of the watchdog operation or the circuit. In such case, please
strength the line between VIN and the GND pin and connect about 0.22μF of a capacitor between the VIN pin and the GND
pin.
5. Protecting against a malfunction while the watchdog time out period, an ignoring time (no reaction time) occurs to the rise
and fall times. Referring to the figure below, the ignoring time (no reaction time) lasts for 900μs at maximum.
6. The watchdog function can be disabled by connecting a three-state device to the WDI pin as a result of the high impedance
state of the WDI pin. This is effective when the watchdog function is not required, for example, during data loading to the
CPU. The WDI input is internally driven through a buffer (LOGIC) and series resistor (RWD) from the watchdog counter as
showed in the block diagrams of page 4 and 5. The WDI input is designed for minimizing the input current by placing the
series resistor (RWD) in the maximum resistance of 880kΩ. A voltage drop occurs in proportion to the leakage current of the
three-state device multiplied by the resistance value of the series resistor (RWD) when the three-state device is in the state
of high impedance. The voltage level must be reaching the threshold level of the WD so that a three-state device with small
leakage current should be selected.
The other series is available in the name of XC6121~XC6124 with the ON/OFF control pin for the watchdog function.
When these series is used, external parts such as the three-state device is not required.
● No Reaction Time
No reaction time
No reaction time
(MAX 900μs)
(MAX 900μs)
11/27
XC6101~XC6107, XC6111~XC6117 Series
■PIN LOGIC CONDITIONS
PIN NAME
VIN
MRB
WD
LOGIC
H
L
H
L
H
L
L → H
H → L
CONDITIONS
VIN>VDF+VHYS
VIN<VDF
MRB>1.40V
MRB<0.35V
When keeping WD>VWDH more than TWD
When keeping WD<VWDL more than TWD
VWDL → VWDH, TWDIN>300ns
VWDH →VWDH, TWDIN>300ns
NOTE:
*1: If only “VDF” is indicated, it represents both VDFL (low when
detected) and VDFH (high when detected).
*2: For the details of each parameter, please see the electrical
characteristics.
VDF: Detect Voltage
VHYS: Hysteresis Width
VWDH: WD High Level Voltage
VWDL: WD Low Level Voltage
TWDIN: WD Pulse Width
TWD: WD Timeout Period
■FUNCTION CHART
●XC6101/XC61111, XC6102/6112 Series
VIN
MRB
WD
H
H
H
L
H
or
Open
H
Open
H
L → H
H
H → L
H
L
*1
L
RESETB (*2)
Repeat detect and release (H→L→H)
H
L
●XC6103/XC61113 Series
VIN
H
H
H
H
H
H
L
MRB
H or Open
L
RESETB (*3)
WD
H
L
Open
L → H
H → L
Repeat detect and release (L→H→L)
L
*1
H
●XC6104/XC61114, XC6105/XC6115 Series
VIN
WD
RESETB (*2)
H
H
Repeat detect and release (H→L→H)
H
L
H
Open
H
H
L → H
H
H → L
H
*1
L
L
RESET (*3)
Repeat detect and release (L→H→L)
L
H
●XC6106/XC61116, XC6107/XC6117 Series
VIN
H
H
L
MRB
H or Open
RESETB (*2)
H
RESET (*3)
L
L
L
H
*1: Including all logic of WD (WD=H, L, L→H, H→L, OPEN).
*2: When the RESETB is High, the circuit is in the release state.
When the RESETB is Low, the circuit is in the detection state.
*3: When the RESET is High, the circuit is in the release state.
When the RESET is Low, the circuit is in the detection state.
*4: VIN=L and MRB=H can not be combined for the rated input voltage of the MRB pin is Vss-0.3V to VIN+0.3V.
*5: The RESET/RESETB pin becomes indefinite operation while 0.35V<MRB<1.4V.
12/27
XC6101 ~ XC6107, XC6111~ XC6117
Series
■TEST CIRCUITS
Circuit 1
Circuit 2
Circuit 3
Circuit 4
13/27
XC6101~XC6107, XC6111~XC6117 Series
■TEST CIRCUITS (Continued)
Circuit 5
Circuit 6
Circuit 7
14/27
XC6101 ~ XC6107, XC6111~ XC6117
Series
■TEST CIRCUITS (Continued)
Circuit 8
Circuit 9
100kΩ
(Not used when the CMOS
Output products selected.)
Circuit 10
Circuit 11
15/27
XC6101~XC6107, XC6111~XC6117 Series
■TYPICAL PERFORMANCE CHARACTERISTICS
(1.1) Supply Current vs. Input Voltage
XC61X1~XC61X5 (2.7V)
30
25
25
Supply Current:
Current: ISS
Supply
ISS(μA)
(μA)
Supply Current:
Current: ISS
Supply
ISS(μA)
(μA)
XC61X1~XC61X5 (1.6V)
30
20
Ta=25℃
15
Ta=85℃
10
Ta=-40℃
5
0
20
Ta=25℃
15
Ta=85℃
10
Ta=-40℃
5
0
0
1
2
3
4
5
Input Voltage: VIN
VIN(V)
(V)
Input
6
0
1
2
3
4
5
Input
VIN
Input Voltage:
Voltage: VIN(V)
(V)
6
XC61X1~XC61X5 (5.0V)
ISS
Supply Current:
Current: ISS
(μA)
Supply
(μA)
30
25
20
Ta=85℃
15
Ta=25℃
10
5
Ta=-40℃
0
0
1
2
3
4
5
Input Voltage:
Voltage: VIN
VIN(V)
(V)
Input
6
(1.2) Supply Current vs. Input Voltage
XC61X6~XC61X7 (2.7V)
30
25
25
Supply Current:
Current: ISS
Supply
ISS(μA)
(μA)
ISS(μA)
(μA)
Supply Current:
Current: ISS
XC61X6~XC61X7 (1.6V)
30
20
15
Ta=25℃
Ta=85℃
10
5
Ta=-40℃
0
20
15
Ta=25℃
Ta=85℃
10
5
Ta=-40℃
0
0
1
2
3
4
5
Input
VIN (V)
(V)
Input Voltage:
Voltage:　VIN
6
0
1
* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
16/27
2
3
4
5
Input Voltage:
Voltage: VIN
(V)
Input
VIN(V)
6
XC6101 ~ XC6107, XC6111~ XC6117
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(1.2) Supply Current vs. Input Voltage (Continued)
XC61X6~XC61X7 (5.0V)
Supply
Supply Current:
Current: ISS
ISS(μA)
(μA)
30
25
20
15
Ta=25℃
10
Ta=85℃
5
Ta=-40℃
0
0
1
2
3
4
5
Input Voltage:
Voltage: VIN
VIN(V)
(V)
Input
6
(2) Detect, Release Voltage vs. Ambient Temperature
XC61X1~XC61X7 (1.6V)
XC61X1~XC61X7 (2.7V)
2.90
Detect, Release Voltage: VDF,VDR (V)
Detect,
VDR (V)
Detect,Release
Release Voltage:
Voltage: VDF,
VDF,VDR
1.70
VDR
1.65
1.60
VDF
1.55
-50
-25
0
25
50
75
Ambient
Temperature:
Ta
(
)
℃
Ambient Temperature: Ta (℃)
2.80
VDR
2.70
VDF
2.60
100
-50
-25
0
25
50
75
Ambient Temperature:
Temperature: Ta
℃)
Ambient
Ta ((℃)
100
XC61X1~XC61X7 (5.0V)
Detect,Release
ReleaseVoltage:
Voltage:VDF,
VDF,VDR
(V)
Detect,
VDR (V)
5.30
5.20
VDR
5.10
5.00
VDF
4.90
-50
-25
0
25
50
75
℃)
Ambient Temperature:
Temperature: Ta
Ta ((℃)
100
* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
17/27
XC6101~XC6107, XC6111~XC6117 Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(3-1) Detect,
(3.1)
Output Voltage
Releasevs.
Voltage
Input Voltage
vs. Input(V
Voltage
DFL)
(VDFL)
XC6101~XC6107 (1.6V)
XC6101~XC6107 (2.7V)
Detect,
VDFL, VDR (V)
Detect, Release
Release Voltage:
Voltage:VDFL,VDR(V)
Detect, Release
Release Voltage:
Voltage:VDFL,VDR(V)
Detect,
VDFL, VDR (V)
2.0
Rpull:100kΩ
Ta=-40℃
25℃
85℃
↓： VDF
↑： VDR
1.5
1.0
0.5
0.0
0
1
Input Voltage: VIN
VIN (V)
(V)
Input
2
3.0
Rpull:100kΩ
Ta=-40℃
25℃
85℃
↓： VDF
↑： VDR
2.5
2.0
1.5
1.0
0.5
0.0
0
1
2
Input Voltage: VIN
VIN(V)
(V)
Input
3
Detect,
Voltage: VDFL, VDR (V)
Detect, Release
Release Voltage:VDFL,VDR(V)
XC6101~XC6107 (5.0V)
6.0
Rpull:100kΩ
Ta=-40℃
25℃
85℃
↓： VDF
↑： VDR
5.0
4.0
3.0
2.0
1.0
0.0
0
1
2
3
4
5
Input Voltage:
Voltage: VIN
VIN(V)
(V)
Input
6
(3.2) Detect, Release Voltage vs. Input Voltage (VDFH)
XC6103~XC6107 (2.7V)
Detect,
ReleaseVoltage:VDR,VDFH(V)
Voltage: VDR, VDFH (V)
Detect,Release
Detect,
ReleaseVoltage:VDR,VDFH(V)
Voltage: VDR, VDFH (V)
Detect,Release
XC6103~XC6107 (1.6V)
2.0
Rpull:100kΩ
Ta=-40℃
25℃
85℃
↑： VDF
↓： VDR
1.5
1.0
0.5
0.0
0
1
Input Voltage:
Voltage: VIN
VIN(V)
(V)
Input
3.0
2.0
1.5
1.0
0.5
0.0
2
* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
18/27
Rpull:100kΩ
Ta=-40℃
25℃
85℃
↑： VDF
↓： VDR
2.5
0
1
2
Input
Input Voltage:
Voltage: VIN
VIN(V)
(V)
3
XC6101 ~ XC6107, XC6111~ XC6117
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(3.2) Detect, Release Voltage vs. Input Voltage (VDFH) (Continued)
Detect, Release Voltage: VDR, VDFH (V)
Detect,Release Voltage:VDR,VDFH(V)
XC6103~XC6107 (5.0V)
6.0
Rpull:100kΩ
Ta=-40℃
25℃
85℃
↑： VDF
↓： VDR
5.0
4.0
3.0
2.0
1.0
0.0
0
1
2
3
4
5
Input Voltage:
Voltage: VIN(V)
(V)
Input
VIN
6
(4) N-ch Driver Output Current vs. VDS
XC61X1~XC61X7
XC61X1~XC61X7
6
20
Ta=25℃
VIN=2.0V
Output Current: IOUT (mA)
Output Current: IOUT (mA)
Ta=25℃
5
4
3
2
1
VIN=4.0V
16
12
VIN=3.0V
8
4
VIN=1.0V
0
0
0
1
2
3
0
VDS (V)
1
2
3
4
VDS (V)
5
6
(5) N-ch Driver Output Current vs. Input Voltage
XC61X1~XC61X7
6.0
Output Current: IOUT (mA)
VDS=0.5V
5.0
Ta=-40℃
Ta=25℃
4.0
Ta=85℃
3.0
2.0
1.0
0.0
0
1
2
3
4
5
Input Voltage: VIN (V)
6
* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
19/27
XC6101~XC6107, XC6111~XC6117 Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(6) P-ch Driver Output Current vs. Input Voltage 1
(7) P-ch Driver Output Current vs. Input Voltage 2
XC61X1, XC61X3~XC61X7
XC61X1, XC61X3~XC61X7
6.0
2.0
VDS=0.5V
Output Current: IOUT (mA)
Output Current: IOUT (mA)
Ta=25℃
5.0
VDS=2.0V
4.0
1.5V
3.0
1.0V
2.0
0.5V
1.0
0.0
1.6
Ta=-40℃
1.2
Ta=25℃
0.8
Ta=85℃
0.4
0.0
0
1
2
3
4
5
Input Voltage: VIN (V)
6
0
1
2
3
4
5
Input Voltage: VIN (V)
6
(8) Release Delay Time vs. Ambient Temperature
XC61X1~XC61X7
XC61X1~XC61X7
300
TDR=3.13msec
Release Delay Time TDR (ms)
Release Delay Time TDR （ msec ）
Release Delay Time TDR (ms)
Release Delay Time TDR （ msec ）
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-50
-25
0
25
50
75
Ambient Temperature: Ta (℃ )
100
XC61X1~XC61X7
Release Delay Time TDR (ms)
Release Delay Time TDR （ msec ）
3000
TDR=1.6sec
2500
2000
1500
1000
500
0
-50
-25
0
25
50
75 100
Ambient Temperature: Ta (℃ )
* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
20/27
TDR=100msec
250
200
150
100
50
0
-50
-25
0
25
50
75
Ambient Temperature: Ta (℃ )
100
XC6101 ~ XC6107, XC6111~ XC6117
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(9) Watchdog Timeout Period vs. Ambient Temperature
XC61X1~XC61X5
XC61X1~XC61X5
300
TW D=6.25msec
TWD=6.25ms
10
8
6
4
2
0
-50
-25
0
25
50
75
Ambient Temperature: Ta (℃ )
TW D=100msec
TWD=100ms
WD Timeout Period TWD (ms)
WD Timeout Piriod TWD （ msec ）
WD Timeout Period TWD (ms)
WD Timeout Piriod TWD （ msec ）
12
250
200
150
100
50
0
-50
100
-25
0
25
50
75
Ambient Temperature: Ta (℃ )
100
XC61X1~XC61X5
WD Timeout Period TWD (ms)
WD Timeout Piriod TWD （ msec ）
3000
TW D=1.6sec
TWD=1.6s
2500
2000
1500
1000
500
0
-50
-25
0
25
50
75
Ambient Temperature: Ta (℃ )
100
(10) Release Delay Time vs. Input Voltage
(11) Watchdog Timeout Period vs. Input Voltage
XC61x1~XC61x5
XC61x1~XC61x7
120
Ta=25℃
TDR=100msecTa=25℃ TWD=100ms
110
100
90
80
70
WD Timeout Period TWD (ms)
WD Timeout Piriod : TWD （ msec ）
Release Delay Time TDR (ms)
Release Delay Time : TDR （msec ）
120
Ta=25℃
TW D=100msecTa=25℃ TWD=100ms
110
100
60
90
80
70
60
1
2
3
4
5
6
Input Voltage: VIN (V)
7
1
2
3
4
5
6
Input Voltage: VIN (V)
7
* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
21/27
XC6101~XC6107, XC6111~XC6117 Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(12) Watchdog Low Level Voltage vs. Ambient Temperature
(13) Watchdog High Level Voltage vs. Ambient Temperature
XC61X1~XC61X5
XC61X1~XC61X5
6.0
WD HighLevel Threshold Voltage
VWDH(V)
WD LowLevel Threshold Voltage
VWDL(V)
6.0
5.0
4.0
3.0
VIN=6.0V
2.0
VIN=3.0V
1.0
VIN=1.76V
0.0
-50
-25
0
25
50
75
5.0
4.0
VIN=6.0V
3.0
VIN=3.0V
2.0
1.0
VIN=1.76V
0.0
100
-50
Ambient Temperature: Ta (℃ )
(14) MRB Low Level Voltage vs. Ambient Temperature
XC61X1~XC61X3, XC61X6~XC61X7
XC61X1~XC61X3, XC61X6~XC61X7
1.10
MRB HighLevel Threshold Voltage
VMRH(V)
MRB LowLevel Threshold Voltage
VMRL(V)
100
(15) MRB High Level Voltage vs. Ambient Temperature
1.10
1.00
0.90
VIN=3.0V
0.80
VIN=6.0V
0.70
0.60
VIN=1.76V
0.50
-50
-25
0
25
50
75
100
Ambient Temperature: Ta (℃ )
* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
22/27
-25
0
25
50
75
Ambient Temperature: Ta (℃ )
1.00
0.90
VIN=6.0V
0.80
VIN=3.0V
0.70
VIN=1.76V
0.60
0.50
-50
-25
0
25
50
75
Ambient Temperature: Ta (℃ )
100
XC6101 ~ XC6107, XC6111~ XC6117
Series
■PACKAGING INFORMATION
●SOT-25
●USP-6C
23/27
XC6101~XC6107, XC6111~XC6117 Series
■PACKAGING INFORMATION (Continued)
●USP-6C Recommended Pattern Layout
24/27
●USP-6C Recommended Metal Mask Design
XC6101 ~ XC6107, XC6111~ XC6117
Series
■MARKING RULE
●SOT-25
①
②
③ ④
SOT-25
(TOP VIEW)
① Represents product series
MARK
PRODUCT SERIES
0
XC6101xxxxxx
1
XC6102xxxxxx
2
XC6103xxxxxx
3
XC6104xxxxxx
4
XC6105xxxxxx
5
XC6106xxxxxx
6
XC6107xxxxxx
MARK
7
8
9
A
B
C
D
PRODUCT SERIES
XC6111xxxxxx
XC6112xxxxxx
XC6113xxxxxx
XC6114xxxxxx
XC6115xxxxxx
XC6116xxxxxx
XC6117xxxxxx
② Represents release delay time and watchdog timeout period
RELEASE
RELEASE
WATCH DOG
PRODUCT
WATCH DOG
MARK
MARK
DELAY
DELAY
TIMEOUT PERIOD
SERIES
TIMEOUT PERIOD
TIME
TIME
A
3.13ms XC61X6, XC61X7 series XC61xxA0xxxx
E
50ms
400ms
0
3.13ms
6.25ms
XC61xxA1xxxx
F
50ms
1.6s
1
3.13ms
50ms
XC61xxA2xxxx
D
100ms
XC61X6, XC61X7 series
2
3.13ms
100ms
XC61xxA3xxxx
H
100ms
100ms
3
3.13ms
200ms
XC61xxA4xxxx
K
100ms
200ms
4
3.13ms
400ms
XC61xxA5xxxx
L
100ms
400ms
5
3.13ms
1.6s
XC61xxA6xxxx
M
100ms
1.6s
B
25ms
XC61X6, XC61X7 series XC61xxB0xxxx
E
200ms
XC61X6, XC61X7 series
6
25ms
50ms
XC61xxB2xxxx
P
200ms
200ms
7
25ms
100ms
XC61xxB3xxxx
R
200ms
400ms
8
25ms
200ms
XC61xxB4xxxx
S
200ms
1.6s
9
25ms
400ms
XC61xxB5xxxx
F
400ms
XC61X6, XC61X7 series
A
25ms
1.6s
XC61xxB6xxxx
T
400ms
400ms
C
50ms
XC61X6, XC61X7 series XC61xxC0xxxx
U
400ms
1.6s
B
50ms
50ms
XC61xxC2xxxx
H
1.6s
XC61X6, XC61X7 series
C
50ms
100ms
XC61xxC3xxxx
V
1.6s
1.6s
D
50ms
200ms
XC61xxC4xxxx
③ Represents detect voltage
MARK
DETECT VOLTAGE
F
1.6
H
1.7
K
1.8
L
1.9
M
2.0
N
2.1
P
2.2
R
2.3
S
2.4
T
2.5
U
2.6
V
2.7
X
2.8
Y
2.9
Z
3.0
0
3.1
1
3.2
2
3.3
PRODUCT SERIES
XC61Xxxx16xx
XC61Xxxx17xx
XC61Xxxx18xx
XC61Xxxx19xx
XC61Xxxx20xx
XC61Xxxx21xx
XC61Xxxx22xx
XC61Xxxx23xx
XC61Xxxx24xx
XC61Xxxx25xx
XC61Xxxx26xx
XC61Xxxx27xx
XC61Xxxx28xx
XC61Xxxx29xx
XC61Xxxx30xx
XC61Xxxx31xx
XC61Xxxx32xx
XC61Xxxx33xx
MARK
3
4
5
6
7
8
9
A
B
C
D
E
F
H
K
L
M
DETECT VOLTAGE
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
PRODUCT
SERIES
XC61xxC5xxxx
XC61xxC6xxxx
XC61xxD0xxxx
XC61xxD3xxxx
XC61xxD4xxxx
XC61xxD5xxxx
XC61xxD6xxxx
XC61xxE0xxxx
XC61xxE4xxxx
XC61xxE5xxxx
XC61xxE6xxxx
XC61xxF0xxxx
XC61xxF5xxxx
XC61xxF6xxxx
XC61xxH0xxxx
XC61xxH6xxxx
PRODUCT SERIES
XC61Xxxx34xx
XC61Xxxx35xx
XC61Xxxx36xx
XC61Xxxx37xx
XC61Xxxx38xx
XC61Xxxx39xx
XC61Xxxx40xx
XC61Xxxx41xx
XC61Xxxx42xx
XC61Xxxx43xx
XC61Xxxx44xx
XC61Xxxx45xx
XC61Xxxx46xx
XC61Xxxx47xx
XC61Xxxx48xx
XC61Xxxx49xx
XC61Xxxx50xx
④ Represents production lot number
0 to 9 and A to Z and inverted 0 to 9 and A to Z repeated. (G, I, J, O, Q, W expected.)
* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
25/27
XC6101~XC6107, XC6111~XC6117 Series
■MARKING RULE (Continued)
●USP-6C
USP-6C
(TOP VIEW)
① Represents product series
MARK
PRODUCT SERIES
3
XC6101xxxxxx
4
XC6102xxxxxx
5
XC6103xxxxxx
6
XC6104xxxxxx
7
XC6105xxxxxx
3
XC6106xxxxxx
4
XC6107xxxxxx
MARK
8
9
A
B
C
8
9
PRODUCT SERIES
XC6111xxxxxx
XC6112xxxxxx
XC6113xxxxxx
XC6114xxxxxx
XC6115xxxxxx
XC6116xxxxxx
XC6117xxxxxx
② Represents release delay time
MARK
RELEASE DELAY TIME
A
3.13ms
B
25ms
C
50ms
D
100ms
E
200ms
F
400ms
H
1.6s
PRODUCT SERIES
XC61XxAxxxxx
XC61XxBxxxxx
XC61XxCxxxxx
XC61XxDxxxxx
XC61XxExxxxx
XC61XxFxxxxx
XC61XxHxxxxx
③ Represents watchdog timeout period
MARK
WATCHDOG TIMEOUT PERIOD
0
XC61X6, XC61X7 series
1
6.25ms
2
50ms
3
100ms
4
200ms
5
400ms
6
1.6s
④⑤ Represents detect voltage
MARK
DETECT VOLTAGE (V)
④
⑤
3
3
3.3
5
0
5.0
PRODUCT SERIES
XC61Xxx0xxxx
XC61Xxx1xxxx
XC61Xxx2xxxx
XC61Xxx3xxxx
XC61Xxx4xxxx
XC61Xxx5xxxx
XC61Xxx6xxxx
PRODUCT SERIES
XC61Xxxx33xx
XC61Xxxx50xx
⑥ Represents production lot number
0 to 9 and A to Z repeated. (G, I, J, O, Q, W excepted.)
* No character inversion used.
** ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
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XC6101 ~ XC6107, XC6111~ XC6117
Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics.
Consult us, or our representatives
before use, to confirm that the information in this catalog is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this catalog.
3. Please ensure suitable shipping controls (including fail-safe designs and aging
protection) are in force for equipment employing products listed in this catalog.
4. The products in this catalog are not developed, designed, or approved for use with such
equipment whose failure of malfunction can be reasonably expected to directly
endanger the life of, or cause significant injury to, the user.
(e.g. Atomic energy; aerospace; transport; combustion and associated safety
equipment thereof.)
5. Please use the products listed in this catalog within the specified ranges.
Should you wish to use the products under conditions exceeding the specifications,
please consult us or our representatives.
6. We assume no responsibility for damage or loss due to abnormal use.
7. All rights reserved. No part of this catalog may be copied or reproduced without the
prior permission of Torex Semiconductor Ltd.
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