Z86160 CP96TEL1700 P R E L I M I N A R Y PRELIMINARY CUSTOMERPRODUCTSPECIFICATION Z86160 SET-TOPCONTROLLER FEATURES Part ROM RAM* Kbytes Bytes Z86160 32 Package Speed Information 768 16 n 0°C to +70°C Temperature Range n 512 Bytes Battery Backed-Up (BBU) Secure RAM n Keypad Buffer 100-Pin QFP *General-Purpose n 3.0- to 5.5-Volt Operating Range n LED Controller n Low-Power Consumption n Two Comparators n Custom Input/Output Lines n Two On-Chip Counter/Timers GENERAL DESCRIPTION The Z86160 is a member of the Z8 ® single-chip microcontroller family offering a unique architecture that is characterized by Zilog's 8-bit microcontroller core. This CMOS microcontroller features fast execution, efficient use of memory, sophisticated interrupts, input/ output bit manipulation capabilities, and easy hardware/ software system expansion along with low-cost and low-power consumption. For applications demanding powerful I/O capabilities, the Z86160 fulfills this with custom I/O, specifically tailored to meet the needs of set-top requirements. Four basic address spaces, the Program Memory, Data Memory, 236 General-Purpose Registers, and 512 bytes of protected RAM, support a wide range of memory configurations. The protected RAM is mapped into data memory. CP96TEL1700 (3/96) To unburden the program from coping with real-time problems such as counting/timing, and serial data communications, the Z86160 offers two on-chip counter/timers with a large number of user selectable modes, and an asynchronous receiver/transmitter (UART) (see Block Diagram). Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS 1 Z86160 CP96TEL1700 P R E L I M I N A R Y GENERAL DESCRIPTION Output Input Vcc GND Machine Timing and Instruction Control Port 3 UART ALU Counter/ Timers (2) FLAGS Interrupt Control XTAL /AS /DS R//W /RESET Prg. Memory 32,768 x 8-Bit Register Pointer Register File 256 x 8-Bit Program Counter Custom Logic I/O Port 0 Port 2 4 I/O (Bit Programmable) Port 1 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) Figure 1. Z86160 Functional Block Diagram 2 Secure RAM 512 Bytes Z86160 CP96TEL1700 P R E L I M I N A R Y PIN DESCRIPTION 80 51 81 50 Z86160 QFP 100 1 31 30 Figure 2. Z86160 100-Pin QFP Package 3 Z86160 CP96TEL1700 P R E L I M I N A R Y PIN DESCRIPTION (Continued) Z86160 100-Pin QFP Pin Identification Pin # Symbol Pin # 1 2 3 4 5 EXADR14 EXR/W EXADR07 EXADR12 GND 26 27 28 29 30 6 7 8 9 10 EXADR13 EXADR08 EXADR06 EXADR09 VCC 11 12 13 14 15 Pin # Symbol Pin # Symbol VCC D5 D1 D4 D2 51 52 53 54 55 S4 S5 S6 K1 S7 76 77 78 79 80 M7 ON/OFF GND N1 N2 31 32 33 34 35 D3 S0 S1 GND0 GND1 56 57 58 59 60 T0 T1 T2 T3 T4 81 82 83 84 85 VCC K5 N3 K6 K7 EXADR05 EXADR11 EXADR04 /EXDS GND 36 37 38 39 40 GND2 GND3 S2 GND I0 61 62 63 64 65 T5 GND T6 T7 M0 86 87 88 89 90 L0 L1 L3 B0 B1 16 17 18 19 20 EXADR03 EXADR10 EXADR02 /EXRAMCS EXADR01 41 42 43 44 45 I1 I2 I3 I4 I5 66 67 68 69 70 M1 M2 VCC M3 K2 91 92 93 94 95 GND XTAL1 XTAL2 GND B2 21 22 23 24 25 D7 EXADR00 D6 D0 GND 46 47 48 49 50 I6 I7 K0 VCC S3 71 72 73 74 75 M4 K3 M5 K4 M6 96 97 98 99 100 B3 L4 N4 N5 L5 4 Symbol Z86160 CP96TEL1700 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Symbol Description Min Max Units VCC TSTG TA Supply Voltage* –0.3 Storage Temp –65 Oper Ambient Temp 0° +7.0 +150 70° V C C Notes: * Voltages on all pins with respect to GND. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load). From Output Under Test I 15 pF Figure 3. Test Load Diagram 5 Z86160 CP96TEL1700 P R E L I M I N A R Y DC ELECTRICAL CHARACTERISTICS Z86160 Sym Parameter TA = 0°C to +70°C Min Max Conditions V V V IIN<250 µA DrivenbyExternalClockGenerator DrivenbyExternalClockGenerator VCC+0.3 0.2VCC V V V IOH= –2.0 mA [3] VCC–100mV 0.75 0.3 0.3 V V V V IOH=–100µA IOL = +7.0 mA [3] IOL = +2.0 mA [3] IOL = +1.0 mA [2] –2 –2 2 2 µA µA VIN =0V,VCC VIN =0V,VCC mA mA µA µA [1]@16MHz [1]HALTModeVIN =0V,VCC@16MHz [1]@0MHzVIN =0V,VCC=3V –14 44 18.75 5 14 MaxInputVoltage ClockInputHighVoltage ClockInputLowVoltage 0.85VCC VSS– 0.3 VIH VIL VOH InputHighVoltage InputLowVoltage OutputHighVoltage 2 VSS– 0.3 4 VOH VOL VOL VOL OutputHighVoltage OutputLowVoltage OutputLowVoltage OutputLowVoltage IIL IOL InputLeakage OutputLeakage ICC ICC1 ICC2 IALL SupplyCurrent(StandardMode) StandbyCurrent(StandardMode) StandbyCurrent AutoLatchLowCurrent 6 Units VCC+0.3 VCC+0.3 0.8 VCH VCL Notes: [1] All inputs driven to either 0V or VCC, outputs floating. [2] VCC = 3.0V to 3.6V [3] VCC = 4.5V to 5.5V Data Retention @ 2.0V – BBU Typical at 25°C 30 5.75 5 Z86160 CP96TEL1700 P R E L I M I N A R Y AC CHARACTERISTICS Additional Timing Diagram 1 3 Clock 2 2 3 Additional Timing AC CHARACTERISTICS Additional Timing Table Z86160 No Symbol Parameter TA = 0°C to +70°C 16 MHz Min Max 1 2 3 TpC TrC,TfC TwC Input Clock Period Clock Input Rise & Fall Times Input Clock Width TBD TBD TBD Units ns ns ns Notes [1] [1] [1] Notes: [1] Clock timing references use 0.85VCC for a logic 1 and 0.8V for a logic 0. 7 P R E L I M I N A R Y Z86160 CP96TEL1700 LIMITATIONS Be advised that AC Electrical Characteristics and Timing Diagram information was unavailable at the time of this publication, they will be supplied at a later date. Development Projects: Customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems and delays. No production release is authorized or committed until the Customer and Zilog have agreed upon a Customer Procurement Specification for this project. Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship. Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or nonconformance with some aspects of the CPS may be found, © 1996 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. 8 either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http//:www.zilog.com