Z86C95 DSP CPS DC-4067-13 CUSTOMER PROCUREMENT SPECIFICATION Z86C95 CMOS Z8® DIGITAL SIGNAL PROCESSOR (DSP) GENERAL DESCRIPTION The Z86C95 MCU (Microcontroller Unit ) introduces a new level of sophistication to Superintegration™ ICs. The Z86C95 is a member of the Z8® single-chip microcontroller family incorporating a CMOS ROMless Z8 microcontroller with an embedded DSP processor for digital servo control. The DSP slave processor can perform 16-bit x 16-bit multiplicates and accumulates in one clock cycle. Additionally, the Z86C95 is further enhanced with a hardwired 16-bitx16-bit multiplier and a 32-bit/16-bit divider, three 16-bit counter timers with capture and compare registers, a half flash 8-channel 8-bit A/D converter with a 2 µsec conversion time, an 8-bit DAC with 1/4 programmable gain stage, UART, serial peripheral interface, and a PWM output channel (Functional Block Diagram). It is fabricated using CMOS technology and offered in an 80-pin QFP, 84pin PLCC, or 100-pin VQFP package. The Z86C95 provides up to 16 output address lines thus permitting an address space of up to 64 Kbytes of data and program memory each. Eight address outputs (AD7-AD0) are provided by a multiplexed, 8-bit, Address/Data bus. The remaining 8 bits are provided via output address bits A15-A8. There are 256 registers located on chip and organized as 236 general-purpose registers, 16 control and status registers, and four I/O port registers. The register file can be divided into sixteen groups of 16 working registers each. Configuration of the registers in this manner allows the use of short format instructions; in addition, any of the individual registers can be accessed directly. Also, the Z86C95 contains 512 bytes of DSP Program RAM and 128 words of DSP data RAM. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS OPERATING ERRATA This notice only applies to devices top marked "Z86C9524 ASC/FSC/VSC" with a date code of 9237 or later. The following operating errata only applies to devices topmarked with "Z86C95 ASC/FSC/VSC." 1. A DSP load to the DAC Register fails below approximately VCC = 4.7V. 1. ICC1 at HALT Mode will show a current of 17-18 mA, then will jump to 40-70 mA, and will settle between 1724 mA. Settling time is about 10-15 seconds. 2. Clipping occurs in the linearity of the DAC with a 100K load at about 3.3V output (VDHI = 3.5V). 3. ICC1 at HALT Mode will show a current of 17-18 mA, then will jump to 40-70 mA, and will settle between 1724 mA. Settling time is about 10-15 seconds. 4. ICC2 at STOP Mode and DSP Pause will show a current of 1-2 mA, then will jump to 5-7 mA, and will settle at 34 mA. Settling time is about 10-15 seconds. DC-4067-13 (5-17-94) 2. ICC2 at STOP Mode and DSP Pause will show a current of 1-2 mA, then will jump to 5-7 mA, and will settle at 3-4 mA. Settling time is about 10-15 seconds. The following operating errata only applies to devices topmarked with "Z86C9540 ASC/FSC/VSC or SL 1636." 1. ICC1 at HALT Mode will show a current of 17-18 mA, then will jump to 40-70 mA, and will settle between 1724 mA. Settling time is about 10-15 seconds. 1 Z86C95 DSP CPS DC-4067-13 GENERAL DESCRIPTION (Continued) 3. The zero error for the ADC at 25°C is about 180 mV. 2. ICC2 at STOP Mode and DSP Pause will show a current of 1-2 mA, then will jump to 5-7 mA, and will settle at 3-4 mA. Settling time is about 10-15 seconds. Output Input Vcc XTAL /AS /DS R//W /RESET /WAIT GND Machine Timing and Instruction Control Port 3 SPI UART Three 16-Bit Counter/ Timers 32 ÷ 16 Divider 16 x 16 Multiplier ALU Flags Program Counter Register Pointer Register File 256 x 8-Bit Interrupt Control Port 2 I/O (Bit Programmable) Digital Signal Processor Address A15-A0* AD7-AD0 * In multiplexed mode, A7-A0 reflects the DSP address bus for emulation. 8 Address/Data DSP RAM Bank 1 DSP RAM Bank 2 Program RAM ADC DAC PWM Analog Out PWM 8 Channel Analog In Functional Block Diagram 2 Z86C95 DSP CPS DC-4067-13 P2(0) 64 65 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VDD VSS DO DI SK SLAVESEL DSP_RW DSP_SYNC C02 C01 DSP_SSN /WAIT PIN DESCRIPTION 41 40 A3 P2(1) A2 P2(2) A1 P2(3) A0 P2(4) AD0 P2(5) VSS P2(6) AD1 P2(7) AD2 Z86C95 80-Lead QFP VSS AD3 ANGND AD4 AVCC AD5 VAHI AD6 VALO AD7 ANA(0) R/W ANA(1) /DS 25 24 IACK SYNC SCLK /RESET PWM XTAL2 P3(0) XTAL1 P3(1) P3(2) P3(3) P3(5) P3(6) P3(7) VDD VDHI DAC VDLO ANA(7) ANA(6) ANA(5) ANA(4) 1 /AS P3(4) 80 ANA(3) ANA(2) 80-Lead QFP Pin Assignments 3 Z86C95 DSP CPS DC-4067-13 1 84 DSP_SSN N/C /WAIT P20 P21 P22 P23 P24 P25 P26 VSS 11 ANA4 P27 ANGND VAHI AVCC VALO ANA0 ANA1 ANA2 ANA3 N/C PIN DESCRIPTION (Continued) 75 74 12 C02 ANA6 DSP_SYNC ANA7 DSP_RW VDLO SLAVESEL DAC SK VDHI D1 VDD D0 P37 VDD P36 VSS Z86C95 84-Lead PLCC P35 A15 P33 A14 P32 A13 P31 A12 P30 A11 XTAL1 A10 XTAL2 A9 PWM A8 /RESET A7 SCLK A6 54 53 84-Lead PLCC Pin Assignments DSP-A8 A3 A2 A1 A0 AD0 VSS AD1 AD2 AD3 AD5 AD6 AD7 R//W /DS /AS P34 42 43 IACK N/C 33 A4 32 AD4 SYNC 4 C01 ANA5 A5 Z86C95 DSP CPS DC-4067-13 45 50 40 35 30 25 55 20 60 15 Z86C95 100-Lead VQFP 65 10 70 5 80 85 90 95 1 NC SYNC SCLK NC RESET PWM XTAL2 XTAL1 P30 P31 P32 P33 P35 P36 P37 VDD VDHI DAC VDLO ANA7 ANA6 ANA5 ANA4 NC NC AVCC AVHI AVLO ANA0 ANA1 ANA2 ANA3 NC NC NC 75 NC NC P20 P21 P22 P23 P24 P25 P26 P27 VSS NC NC NC ANGND A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS VDD NC D0 D1 SK SLAVESEL DSP_RW DSP_SYNC C02 C01 DSP_SSN /WAIT A3 A2 A1 A0 AD0 VSS AD1 AD2 AD3 AD4 AD5 AD6 AD7 R//W /DS /AS P34 IACK NC NC NC NC NC NC DSP_A8 PIN DESCRIPTION (Continued) 100-Pin VQFP Pin Assignments 5 Z86C95 DSP CPS DC-4067-13 A7-A0 (DSP Emulator Support) ANVCC Z86C95 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Analog Inputs To A/D VDLO VDHI D/A Ref Voltage DAC PWM DAC Output PWM Output C01 C02 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 SLAVESEL SK DI DO Port 3 VAHI P37 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P23 P24 P22 P21 P20 /WAIT Port 2 (Bit Programmable I/O) 6 ANGND Analog Power R//W /RESET /AS Timing and Control /DS DSP_SYNC A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DSP Sync DSP_RW /SYNC DSP-A8 SCLK IACK XTAL1 Emulation Pins DSP Read Write VALO Address A15-A0 XTAL2 +5V GND Clock DSP Single Step DSP_SSN PIN FUNCTIONS A/D Ref Voltage Compare Outputs SPI Slave Select SPI Clock SPI Data Asynchronous WAIT States Z86C95 DSP CPS DC-4067-13 ABSOLUTE MAXIMUM RATINGS Symbol VDD TSTG TA Description Min Max Unit Supply Voltage* Storage Temp Oper Ambient Temp –0.3 –65 † +7.0 +150 † V C C Notes: * Voltages on all pins with respect to GND. † See Ordering Information Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS I OL The characteristics listed below apply for standard test conditions as noted (Test Load Diagram). DUT Device Under Test V Commutation 50 pf I OH Test Load Diagram 7 Z86C95 DSP CPS DC-4067-13 DC ELECTRICAL CHARACTERISTICS VCC = 3.3V ± 10% Sym Parameter VCH VCL VIH VIL Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage VOH VOH VOL VRH VRl Output High Voltge Output High Voltge Output Low Voltage Reset Input High Voltage Reset Input Low Voltage IIL IOL IIR ICC Input Leakage Output Leakage Reset Input Current Supply Current ICC1 ICC2 IALL HALT STOP and Pause Mode Auto Latch Low Current TA = 0°C to +70°C Min Max 0.8 VCC –0.03 0.6xVCC –0.3 0.8xVCC –0.03 –2 –2 –10 Units Conditions 7 VCC 0.1xVCC VCC 0.2xVCC V V V V V IIN 250 µA Driven by External Clock Generator Driven by External Clock Generator 0.4 VCC 0.2xVCC V V V V V IOH = –1.0 mA IOH = –100 µA IOL = +1.0 mA 2 2 –180 50 40 µA µA µA mA Test at 0V, VCC Test at 0V, VCC VRL = 0V @ 24 MHz [1] 15 20 10 10 6 5 mA µA µA HALT Mode VIN=OV, VCC @ 24 MHz [1] STOP Mode VIN=OV, VCC [1] 2.0 VCC – 100 mV Note: [1] All inputs driven to 0V, VCC and outputs floating. 8 Typical at 25°C Z86C95 DSP CPS DC-4067-13 DC ELECTRICAL CHARACTERISTICS VCC = 5.0V ± 10% Sym Parameter VCH VCL VIH VIL Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage VOH VOH VOL VRH VRl Output High Voltge Output High Voltge Output Low Voltage Reset Input High Voltage Reset Input Low Voltage IIL IOL IIR ICC Input Leakage Output Leakage Reset Input Current Supply Current ICC1 HALT ICC2 IALL STOP and Pause Mode Auto Latch Low Current TA = 0°C to +70°C Min Max 3.8 –0.03 2.0 –0.3 Typical at 25°C –2 –2 –20 Conditions 7 VCC 0.8 VCC 0.8 V V V V V IIN 250 µA Driven by External Clock Generator Driven by External Clock Generator 0.4 VCC 0.8 V V V V V IOH = –2.0 mA IOH = –100 µA IOH = +2.0 mA 2 2 –180 82 120 150 50 70 85 µA µA µA mA mA mA Test at 0V, VCC Test at 0V, VCC VRL = 0V @ 24 MHz [1] @ 33 MHz [1] @ 40 MHz [1], [2] 20 30 45 13 20 30 mA mA mA HALT Mode VIN=OV, VCC @ 24 MHz [1] HALT Mode VIN=OV, VCC @ 33 MHz [1] HALT Mode VIN=OV, VCC @ 40 MHz [1], [2] 20 20 6 5 µA µA STOP Mode VIN=OV, VCC [1] 2.4 VCC – 100mV 3.8 –0.03 Units Note: [1] All inputs driven to 0V, VCC and outputs floating. [2] Preliminary values, to be characterized. 9 Z86C95 DSP CPS DC-4067-13 AC CHARACTERISTICS External I/O or Memory Read/Write Timing Diagram R/W, /DM 19 20 12 13 Port 0 A8 - A15 21 16 Port 1 D0 - D7 IN A0 - A7 A0 - A7 9 2 3 10 /AS 8 11 4 5 /DS (Read) Port1 1 6 17 D0 - D7 OUT A0 - A7 14 15 7 /DS (Write) External I/O or Memory Read/Write Timing 10 A0-A7 Z86C95 DSP CPS DC-4067-13 AC CHARACTERISTICS External I/O or Memory Read and Write; DSR/DSW; WAIT Timing Table 40 MHz** Min Max TA = 0°C to +70°C 33 MHz Min Max Sym Parameter 1 2 3 4 TdA(AS) TdAS(A) TdAS(DI) TwAS Address Valid To /AS Rise Delay /AS Rise To Address Hold Time /AS Rise Data In Req’d Valid Delay /AS Low Width 8 15 10 15 28 5 6 7 8 TdAZ(DSR) TwDSR TwDSW TdDSR(DI) Address Float To /DS Fall (Read) /DS (Read) Low Width /DS (Write) Low Width /DS Fall (Read) To Data Req'd Valid Delay 0 60 35 0 65 40 0 100 65 9 10 11 12 ThDSR(DI) TdDS(A) TdDS(AS) TdR/W(AS) /DS Rise (Read) to Data In Hold Time /DS Rise To Address Active Delay /DS Rise To /AS Delay R/W To Valid /AS Rise Delay 0 20 16 10 0 25 16 12 0 40 30 26 ns ns ns ns 13 14 15 16 TdDS(R/W) TdDO(DSW) ThDSW(DO) TdA(DI) /DS Rise To R/W Not Valid Delay Data Out To /DS Fall (Write) Delay /DS Rise (Write) To Data Out Hold Time Address Valid To Data Req’d Valid Delay 12 12 12 12 12 12 30 34 34 ns ns ns ns 17 19 20 TdAS(DSR) TdDM(AS) TdDS(DM) /AS Rise To /DS Fall (Read) Delay /DM Valid To /AS Rise Delay /DS Rise To /DM Valid Delay 20 10 15 21 22 23 24 ThDS(A) TdXT(SCR) TdXT(SCF) TdXT(DSRF) /DS Rise To Address Valid Hold Time XTAL Falling to SCLK Rising XTAL Falling to SCLK Falling XTAL Falling to/DS Read Falling 15 25 26 27 28 29 30 TdXT(DSRR) TdXT(DSWF) TdXT(DSWF) TsW(XT) ThW(XT) TwW XTAL Falling to /DS Read Rising XTAL Falling to /DS Write Falling XTAL Falling to /DS Write Rising Wait Set-up Time Wait Hold Time Wait Width (One Wait Time) 15 20 75 22 25 96 40 130 45 90 5 15 20 Min 24 MHz Max No 80 115 20 10 15 160 40 22 35 15 30 35 35 45 40 40 50 30 40 30 35 45 35 45 50 45 5 15 25 ns ns ns ns ns ns ns ns ns ns ns 30 30 40 5 15 20 Units ns ns ns ns ns ns ns ns ns ns Notes: When using extended memory timing add 2 TpC. Timing numbers given are for minimum TpC. ** Preliminary values, to be characterized. 11 Z86C95 DSP CPS DC-4067-13 AC CHARACTERISTICS (Continued) Timing Diagrams XTAL1 (External Clock Drive) 22 23 SCLK 25 24 /DS (Read) 27 26 /DS (Write) XTAL/SCLK To DSR and DSW Timing T1 T2 TW TW TW XTAL1 SCLK /AS /DS 30 /WAIT 28 29 XTAL/SCLK To WAIT Timing 12 T3 T1 Z86C95 DSP CPS DC-4067-13 3 1 Clock 2 7 2 3 7 T IN 4 5 6 IRQ N 8 9 Additional Timing AC CHARACTERISTICS Additional Timing Table No Symbol Parameter 1 2 3 4 TpC TrC,TfC TwC TwTinL Input Clock Period Clock Imput Rise & Fall Times Input Clock Width Timer Input Low Width 5 6 7 8a TwTinH TpTin TrTin,TfTin TwIL 8b 9 TwIL TwIH 40 MHz Min Max 25 1000 5 TA = 0°C to +70°C 24 MHz 33 MHz Min Max Min Max 42 1000 10 30 8 75 11 75 10 75 Timer Input High Width Timer Input Period Timer Input Rise & Fall Times Interrupt Request Input Low Times 3 TpC 8 TpC 3 TpC 8 TpC 3 TpC 8 TpC 70 70 70 Interrupt Request Input Low Times Interrupt Request Input High Times 5 TpC 3 TpC 5 TpC 3 TpC 5 TpC 3 TpC 100 100 1000 5 100 Units Notes ns ns ns ns [1] [1] [1] [2] ns ns [2] [2] [2] [2,4] [2,5] [2,3] Notes: [1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request via Port 3. [4] Interrupt request via Port 3 (P33-P31). [5] Interrupt request via Port 30. 13 Z86C95 DSP CPS DC-4067-13 AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid 1 Next Data In Valid 3 2 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Valid Data Out Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed Output Handshake Timing 14 RDY Z86C95 DSP CPS DC-4067-13 AC CHARACTERISTICS Handshake Timing Table No Symbol Parameter 1 2 3 4 TsDI(DAV) ThDI(DAV) TwDAV TdDAVIf(RDYf) Data In Setup Time to /DAV RDY to Data In Hold Time /DAV Width /DAV to RDY Delay 5 6 7 8 TdDAVIr(RDYr) TdRDYOr(DAVIf) TdD0(DAV) TdDAV0f(RDYIf) DAV Rise to RDY Wait Time RDY Rise to DAV Delay Data Out to DAV Delay /DAV to RDY Delay 9 10 11 TdRDYIf(DAVOr) TwRDY TdRDYIr(DAVOf) RDY to /DAV Rise Delay RDY Width RDY Rise to DAV Wait Time TA = 0°C to +70°C Min Max Units Data Direction ns ns ns ns In In In In 40 ns ns ns ns In In Out Out 70 ns ns ns Out Out Out 0 0 40 70 0 TpC 0 40 40 15 Z86C95 DSP CPS DC-4067-13 AC CHARACTERISTICS (Continued) A/D Converter Electrical Characteristics VCC = 3.3V ± 10% Parameter Minimum Resolution Integral non-linearity Differential non-linearity Zero Error at 25°C Typical 8 0.5 0.5 2.7 3.0 20 Maximum Units 1 1 5.0 Bits LSB LSB mV Volts mW MHz Volts Supply Range Power dissapation, no load Clock frequency Input voltage range VALO 3.3 40 24 VAHI Conversion time Input capacitance on ANA VAHI range VALO range VAHI -–VALO 25 VALO +2.5 ANGND 2.5 2 40 AVCC AVCC–2.5 AVCC µsec pF Volts Volts Volts Typical Maximum Units 8 0.25 0.25 1.5 10 1 0.5 3.0 20 Bits LSB LSB µsec mV Notes: Voltage 2.7V – 3.3V Temp 0-70°C D/A Converter Electrical Characteristics VCC = 3.3V ± 10% Parameter Minimum Resolution Integral non-linearity Differential non-linearity Setting time, 1/2 LSB Zero Error at 25°C Full Scale error at 25°C Supply Range Power dissapation, no load Ref Input resistance Output noise voltage VDHI range at 3 volts VDLO range at 3 volts VDHI–VDLO, at 3 volts Capacitive output load, CL Resistive output load, RL Output slew rate Notes: Voltage 2.7V – 3.3V Temp 0-70°C 16 1.5 0.25 3.0 10 4K 50 1.8 0.2 1.3 0.5 1.6 50K 1.0 3.0 2.7 2K 0.5 3.3 10K 2.1 0.8 1.9 20 LSB Volts mW Ohms µVp-p Volts Volts Volts pF Ohms V/µsec Z86C95 DSP CPS DC-4067-13 A/D Converter Electrical Characteristics VCC = 5.0V ± 10% Parameter Minimum Resolution Integral non-linearity Differential non-linearity Zero Error at 25°C Typical 8 0.5 0.5 4.5 5.0 50 Maximum Units 1 1 45 Bits LSB LSB mV Volts mW MHz Volts Supply Range Power dissapation, no load Clock frequency Input voltage range VALO 5.5 85 33 VAHI Conversion time Input capacitance on ANA VAHI range VALO range VAHI -–VALO 25 VALO +2.5 ANGND 2.5 2 40 AVCC AVCC–2.5 AVCC µsec pF Volts Volts Volts Typical Maximum Units 8 0.25 0.25 1.5 10 1 0.5 3.0 20 Bits LSB LSB µsec mV Notes: Voltage 4.5V –5.5V Temp 0-70°C D/A Converter Electrical Characteristics VCC = 5.0V ± 10% Parameter Minimum Resolution Integral non-linearity Differential non-linearity Setting time, 1/2 LSB Zero Error at 25°C Full Scale error at 25°C Supply Range Power dissapation, no load Ref Input resistance Output noise voltage VDHI range at 3 volts VDLO range at 5V volts VDHI–VDLO, at 5V volts Capacitive output load, CL Resistive output load, RL Output slew rate 4.5 2K 1 5.0 50 4K 50 2 5.5 85 10K 2.6 3.5 0.8 0.9 1.7 2.7 30 20K* 1.0 3.0 % FSR Volts mW Ohms µVp-p Volts Volts Volts pF Ohms V/µsec Notes: Voltage 4.5V - 5.5V Temp 0-70°C * 100K for 24 MHz device. 17 Z86C95 DSP CPS DC-4067-13 © 1994 by Zilog, Inc. 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