ZILOG Z86E73

PRELIMINARY PRODUCT SPECIFICATION
1
Z86E72/73
1
OTP IR MICROCONTROLLERS
FEATURES
Part
ROM
(KB)
RAM*
(Bytes)
I/O
Voltage
Range
Z86E73
Z86E72
32
16
256
768
31
31
3.0V to 5.5V
3.0V to 5.5V
■
Five Priority Interrupts
– Three External
– Two Assigned to Counter/Timers
■
Two Independent Comparators with Programmable
Interrupt Polarity
■
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC (mask option), or External Clock
Drive
■
Software Selectable 200 kOhms Pull-Ups on Ports 0 and
Port 2
– All Eight Port 2 Bits at One Time or Not Pull-Ups
Automatically Disabled Upon Selecting Individual
Pins as Outputs.
■
Software Mouse/Trackball Interface on P00 Through
P03
Note: *General-Purpose
■
Low Power Consumption - 60 mW (Typical)
■
Two Standby Modes (Typical)
– STOP - 2 µA
– HALT - 0.8 mA
■
Special Architecture to Automate Both Generation and
Reception of Complex Pulses or Signals:
– One Programmable 8-Bit Counter/Timer with Two
Capture Registers
– One Programmable 16-Bit Counter/Timer with
One Capture Register
– Programmable Input Glitch Filter for Pulse
Reception
GENERAL DESCRIPTION
The Z86E7X family of IR (Infrared) CCP™ (Consumer Controller Processor) are OTP-based members of the Z8® single-chip microcontroller family with 256 or 768 bytes of
general-purpose RAM. The only differentiating factor between the E72/73 versions is the availability of RAM and
ROM. This EPROM Microcontroller family of OTP IR controllers also offer the use of external memory which enables this Z8 microcontroller to be used where code flexibility is required. Zilog's CMOS microcontrollers offer fast
execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated
pulse generation/reception, and easy hardware/software
system expansion along with cost-effective and low power
consumption.
DS96LVO1100
The Z86E7X architecture is based on Zilog's 8-bit microcontroller core with an Expanded Register File to allow access to register mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The CCP offers a flexible I/O
scheme, an efficient register and address space structure,
and a number of ancillary features that are useful in many
consumer, automotive, computer peripheral, and battery
operated hand-held applications.
CCP™ applications demand powerful I/O capabilities. The
Z86L7X family fulfills this with five package options in
which the E72/73/L74 versions provide 31 pins of dedicated input and output. These lines are grouped into four
ports. Each port consists of eight lines (Port 3 has seven
lines of I/O and one Pref comparator input) and is config-
PRELIMINARY
1-1
Z86E72/E73
OTP IR Microcontrollers
GENERAL DESCRIPTION (Continued)
urable under software control to provide timing, status signals, parallel I/O with or without handshake, and an address/data bus for interfacing external memory.
There are five basic address spaces available to support a
wide range of configurations: Program Memory, Register
FIle, Expanded Register File, Extended Data RAM and External Memory. The register file is composed of 256 bytes
of RAM. It includes four I/O port registers, 16 control and
status registers and the rest are General Purpose registers. The Extended Data RAM adds 512 (E72) of usable
general-purpose registers. The Expanded Register File
consists of two additional register groups (F and D).
family offers a new intelligent counter/timer architecture
with 8-bit and 16-bit counter/timers (Figure 1). Also included are a large number of user-selectable modes, and two
on-board comparators to process analog signals with separate reference voltages (Figure 2).
Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is
active Low, only).
Power connections follow conventional descriptions below:
To unburden the program from coping with such real-time
problems as generating complex waveforms or receiving
and demodulating complex waveform/pulses, the Z86E7X
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
HI16
LO16
8
8
16-Bit
T16
1 2 4 8
16
8
SCLK
Clock
Divider
8
TC16H
TC16L
HI8
Glitch
Filter
And/Or
Logic
Timer 8/16
LO8
8
8
Input
Timer 16
Edge
Detect
Circuit
8-Bit
T8
Timer 8
8
8
TC8H
TC8L
Figure 1. Z86E7X Counter/Timer Block Diagram
1-2
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
P00
P01
P02
P03
Register File
256 or 768 x 8-Bit
4
P31
P32
P33
Port 0
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
I/O Bit
Programmable
P20
P21
P22
P23
P24
P25
P26
P27
Port 3
Register Bus
Internal
Address Bus
4
ROM
16K/32K x 8
1
P34
P35
P36
P37
Z8 Core
Internal Data Bus
8
Port 1
Expanded
Register
File
Expanded
Register Bus
Machine
Timing
&
Instruction
Control
Power
Port 2
XTAL
/AS
/DS
R/W
/RESET
VDD
VSS
Counter/Timer 16
16-Bit
Counter/Timer 8
8-Bit
Figure 2. Z86E7X Functional Block Diagram
PIN DESCRIPTION
R//W
P25
P26
P27
P04
P05
P06
P14
P15
P07
VDD
P16
P17
XTAL2
XTAL1
P31
P32
P33
P34
/AS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Z86E72/73
DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
/DS
P24
P23
P22
P21
P20
P03
P13
P12
VSS
P02
P11
P10
P01
P00
Pref1
P36
P37
P35
/RESET
Figure 3. 40-Pin DIP Pin Assignments (Standard Mode)
DS96LVO1100
PRELIMINARY
1-3
Z86E72/E73
OTP IR Microcontrollers
PIN DESCRIPTION (Continued)
NC
A13
A14
/PGM
A4
A5
A6
D4
D5
A7
VDD
D6
D7
NC
NC
/OE
EPM
VPP
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Z86E72/73
DIP
NC
A12
A11
A10
A9
A8
A3
D3
D2
VSS
A2
D1
D0
A1
A0
/CE
NC
NC
NC
NC
P20
P03
P13
P12
VSS
VSS
P02
P11
P10
P01
P00
Figure 4. 40-Pin DIP Pin Assignments (EPROM Mode)
6
7
8
9
10
11
12
13
14
15
16
17
18
4
42
1
Z86E72/73
PLCC
20
22
24
26
40
39
38
37
36
35
34
33
32
31
30
29
28
Pref1
P36
P37
P35
/RESET
VSS
/AS
P34
P33
P32
P31
P05
P06
P14
P15
P07
VDD
VDD
P16
P17
XTAL2
XTAL1
P21
P22
P23
P24
/DS
R//RL
R//W
P25
P26
P27
P04
Figure 5. 44-Pin PLCC Pin Assignments (Standard Mode)
1-4
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
A8
A3
D3
D2
VSS
VSS
A2
D1
D0
A2
A0
1
6
7
8
9
10
11
12
13
14
15
16
17
18
4
42
1
Z86E72/73
PLCC
20
22
24
26
40
39
38
37
36
35
34
33
32
31
30
29
28
/CE
NC
NC
NC
NC
SCC
NC
NC
VPP
EPM
/OE
P05
P06
P14
P15
P07
VDD
VDD
P16
P17
XTAL2
XTAL1
A9
A10
A11
A12
NC
NC
NC
A13
A14
/PGM
A4
P20
P03
P13
P12
VSS
VSS
P02
P11
P10
P01
P00
Figure 6. 44-Pin PLCC Pin Assignments (EPROM Mode)
33
34
35
36
37
38
39
40
41
42
43
44
1
31
29
27
25
Z86E72/73
QFP
3
5
7
9
23
22
21
20
19
18
17
16
15
14
13
12
11
Pref1
P36
P37
P35
/RESET
VSS
/AS
P34
P33
P32
P31
P05
P06
P14
P15
P07
VDD
VDD
P16
P17
XTAL2
XTAL1
P21
P22
P23
P24
/DS
R//RL
R//W
P25
P26
P27
P04
Figure 7. 44-Pin QFP Pin Assignments (Standard Mode)
DS96LVO1100
PRELIMINARY
1-5
Z86E72/E73
OTP IR Microcontrollers
A8
A3
D3
D2
VSS
VSS
A2
D1
D0
A1
A0
PIN DESCRIPTION (Continued)
33
34
35
36
37
38
39
40
41
42
43
44
1
29
31
27
25
Z86E72/73
QFP
3
5
7
9
23
22
21
20
19
18
17
16
15
14
13
12
11
/CE
N/C
N/C
N/C
N/C
VSS
N/C
N/C
VPP
EPM
/OE
A5
A6
D4
D5
A7
VDD
VDD
D6
D7
XTAL2
XTAL1
A9
A10
A11
A12
N/C
N/C
N/C
A13
A14
/PGM
A4
Figure 8. 44-Pin QFP Pin Assignments (EPROM Mode)
Table 1. Pin Identification (Standard Mode)
1-6
40-Pin
DIP #
44-Pin
PLCC #
44-Pin
QFP #
Symbol
26
27
40
41
23
24
P00
P01
Input/Output
Input/Output
30
34
5
6
7
10
28
29
44
5
17
18
19
22
42
43
27
32
44
1
2
5
25
26
P02
P03
P04
P05
P06
P07
P10
P11
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
32
33
8
9
12
13
3
4
20
21
25
26
30
31
3
4
8
9
P12
P13
P14
P15
P16
P17
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Direction
PRELIMINARY
Description
Port 0 is Nibble Programmable.
Port 0 can be configured as A15-A8
external program
ROM Address Bus.
Port 0 can be configured as a
mouse/trackball input.
Port 1 is byte programmable.
Port 1 can be configured as multiplexed
A7-A0/D7-D0 external program ROM
Address/Data Bus
.
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Table 1. Pin Identification (Standard Mode)
1-7
40-Pin
DIP #
44-Pin
PLCC #
44-Pin
QFP #
Symbol
35
6
33
P20
Input/Output
36
37
38
39
2
3
4
16
17
18
19
22
24
23
20
40
1
21
15
14
11
7
8
9
10
14
15
16
29
30
31
32
36
38
37
33
11
13
35
28
27
23, 24
34
35
36
37
41
42
43
12
13
14
15
19
21
20
16
38
40
18
11
10
6, 7
P21
P22
P23
P24
P25
P26
P27
P31
P32
P33
P34
P35
P36
P37
/AS
/DS
R//W
/RESET
XTAL1
XTAL2
VDD
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
31
1, 2, 34
17, 28, 29
VSS
25
NC
39
12
22
39
Pref1
R//RL
Direction
Description
Port 2 pins are individually configurable
as input or output
IRQ2/Modulator input
IRQ0
IRQ1
T8 output
T16 output
T8/T16 output
Address Strobe
Data Strobe
Read/Write
Reset
Crystal, Oscillator Clock
Crystal, Oscillator Clock
Power Supply
Ground
Input
Input
PRELIMINARY
Comparator 1 Reference
ROM//ROMless
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
PIN DESCRIPTION (Continued)
Table 2. Z86E72/73 40-Pin DIP Identification (EPROM Mode)
1-8
40-Pin #
Symbol
Function
Direction
1
2-3
4
5-7
8-9
10
11
N/C
A13-14
/PGM
A4-A6
D4-D5
A7
VDD
Not Connected
Address 13,14
Program Mode
Address 4,5,6
Data 4,5
Address 7
Power Supply
Input
Input
Input
Input/Output
Input
12-13
14-15
16
17
18
D6-D7
N/C
/OE
EPM
VPP
Data 6,7
Not Connected
Output Enable
EPROM Prog.Mode
Prog. Voltage
19-24
25
26-27
28-29
30
31
N/C
/CE
A0-A1
D0-D1
A2
VSS
Not Connected
Chip Enable
Address 0,1
Data 0, 1
Address 2
Ground
32-33
34
35-39
40
D2-D3
A3
A8-A12
N/C
Data 2,3
Address 3
Address 8,9,10,11,12
Not Connected
PRELIMINARY
Input/Output
Input
Input
Input
Input
Input
Input/Output
Input
Input/Output
Input
Input
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Table 3. Z86E72/73 44-Pin QFP/PLCC Pin Identification(EPROM Mode)
44-Pin
QFP
44-Pin
PLCC
Symbol
Function
Direction
1-2
3-4
5
6-7
18-19
20-21
22
23-24
A5-A6
D4-D5
A7
VDD
Address 5,6
Data 4,5
Address 7
Power Supply
Input
Input/Output
Input
8-9
10
11
12
13
14
25-26
27
28
29
30
31
D6-D7
XTAL2
XTAL1
/OE
EPM
VPP
Data 6,7
Crystal Oscillator Clock
Crystal Oscillator Clock
Output Enable
EPROM Prog. Mode
Prog. Voltage
Input/Output
15-16
17
32-33
34
N/C
VSS
Not Connected
Ground
18-21
22
23-24
25-26
27
28-29
35-38
39
40-41
42-43
44
1-2
N/C
/CE
A0-A1
D0-D1
A2
VSS
Not Connected
Chip Select
Address 0,1
Data 0,1
Address 2
Ground
30-31
32
33-37
38-40
41-42
43
44
3-4
5
6-10
11-13
14-15
16
17
D2-D3
A3
A8-A12
N/C
A13-A14
/PGM
A4
Data 2, 3
Address 3
Address 8,9,10,11,12
Not Connected
Address 13,14
Prog. Mode
Address 4
DS96LVO1100
PRELIMINARY
1
Input
Input
Input
Input
Input
Input/Output
Input
Input/Output
Input
Input
Input
Input
Input
1-9
Z86E72/E73
OTP IR Microcontrollers
ABSOLUTE MAXIMUM RATINGS
Symbol
Description
Min
Max
Units
VCC
Supply Voltage (*)
–0.3
+7.0
V
TSTG
Storage Temp.
–65°
+150°
C
†
C
TA
Oper. Ambient Temp.
Notes:
* Voltage on all pins with respect to GND.
† See Ordering Information.
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period
may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 13).
From Output
Under Test
I
150 pF
Figure 9. Test Load Diagram
CAPACITANCE
TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
1-10
Parameter
Max
Input capacitance
Output capacitance
I/O capacitance
12 pF
12 pF
12 pF
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
DC CHARACTERISTICS
Preliminary
Sym.
Parameter
VCC
TA = 0°C to +70°C
Min
Max
1
Typical
@ 25°C
Units
Conditions
7
7
V
V
IIN 250 µA
IIN 250 µA
Max Input Voltage
3.0V
5.5V
VCH
Clock Input
High Voltage
3.0V
5.5V
0.9 VCC
0.9 VCC
VCC + 0.3
VCC + 0.3
V
V
Driven by External
Clock Generator
VCL
Clock Input
Low Voltage
3.0V
5.5V
VSS –0.3
VSS –0.3
0.2 VCC
0.2 VCC
V
V
Driven by External
Clock Generator
VIH
Input High Voltage
3.0V
5.5V
0.7 VCC
0.7 VCC
VCC + 0.3
VCC + 0.3
0.5 VCC
0.5 VCC
V
V
VIL
Input Low Voltage
3.0V
5.5V
VSS –0.3
VSS –0.3
0.2 VCC
0.2 VCC
0.5 VCC
0.5 VCC
V
V
VOH1 Output High Voltage
3.0V
5.5V
VCC –0.4
VCC –0.4
2.9
5.4
V
V
IOH = –0.5 mA
IOH = –0.5 mA
VOH2 Output High Voltage
(P00,P01,P36, P37)
3.0V
5.5V
VCC 0.7
VCC 0.7
V
V
IOH = –7 mA
IOH = –7 mA
VOL1 Output Low Voltage
3.0V
5.5V
0.4
0.4
0.1
0.2
V
V
IOL = 1.0 mA
IOL = 4.0 mA
VOL2* Output Low Voltage
3.0V
5.5V
0.8
0.8
0.5
0.3
V
V
IOL = 5.0 mA
IOL = 7.0 mA
VOL2 Output Low Voltage
(P00, P01, P36,P37)
3.0V
5.5V
0.8
0.8
0.3
0.2
V
V
IOL = 10 mA
IOL = 10 mA
VRH
Reset Input
High Voltage
3.0V
5.5V
0.8 VCC
0.8 VCC
VCC
VCC
1.5
2.5
V
V
VRl
Reset Input
Low Voltage
3.0V
5.5V
VSS –0.3
VSS –0.3
0.2 VCC
0.2 VCC
0.9
1.8
3.0V
5.5V
3.0V
5.5V
–1
–1
25
25
1
1
10
10
<1
<1
mV
mV
µA
µA
VIN = 0V, VCC
VIN = 0V, VCC
–1
–1
1
1
<1
<1
µA
µA
VIN = 0V, VCC
VIN = 0V, VCC
–230
–400
10
15
–50
–80
4
10
µA
µA
mA
mA
@ 8.0 MHz
@ 8.0 MHz
VOFFSET Comparator Input
Offset Voltage
IIL
Input Leakage
IOL
Output Leakage
3.0V
5.5V
IIR
Reset Input Current
ICC
Supply Current
(WDT off)
3.0V
5.5V
3.0V
5.5V
DS96LVO1100
PRELIMINARY
1-11
Z86E72/E73
OTP IR Microcontrollers
DC CHARACTERISTICS (Continued)
TA = 0°C to +70°C
Sym.
Parameter
ICC1
Standby Current
(WDT Off)
ICC2
TPOR
Standby Current
Power-On Reset
Vram
Static RAM Data
Retention Voltage
VLV
VCC Low Voltage
(Vbo) Protection
Notes: ICC1
Crystal/Resonator
External Clock Drive
VCC
Max
@ 25°C
3.0V
3
1
mA
5.5V
5
4
mA
3.0V
2
0.8
mA
5.5V
4
2.5
mA
3.0V
8
2
µA
5.5V
10
3
µA
3.0V
5.5V
500
800
310
600
µA
µA
75
20
18
7
0.5
ms
ms
V
2.15
1.7
V
3.0V
5.5V
Vram
Min
Typical
12
5
0.8
Typ
3.0 mA
Max
5
Unit
mA
Frequency
8.0 MHz
0.3 mA
5
mA
8.0 MHz
Units Conditions
Notes
HALT Mode
VIN = 0V, VCC @ 8.0
MHz
HALT Mode
VIN = 0V, VCC
@ 8.0 MHz
Clock Divide-by-16 @
8.0 MHz
Clock Divide-by-16 @
8.0 MHz
STOP Mode
VIN = OV, VCC
WDT is not Running
STOP Mode
VIN = 0V, VCC
WDT is not Running
STOP Mode
VIN = 0V, VCC
WDT is Running
1,2
1,2
1,2
1,2
3,5
3,5
3,5
6
8 MHz max
Ext. CLK Freq.
4
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF
3. Same as note [4] except inputs at VCC.
4. The VLV increases as the temperature decreases.
5. Oscillator stopped.
6. Oscillator stops when VCC falls below Vlv limit
7. 32 kHz clock driver input.
* All Outputs excluding P00, P01, P36, and P37.
1-12
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing
1
R//W
13
12
19
Port 0, /DM
16
18
Port 1
20
3
A7 - A0
1
D7 - D0 IN
2
9
/AS
8
11
4
5
/DS
(Read)
6
17
10
Port 1
A7 - A0
D7 - D0
OUT
14
15
7
/DS
(Write)
Figure 10. External I/O or Memory Read/Write Timing
DS96LVO1100
PRELIMINARY
1-13
Z86E72/E73
OTP IR Microcontrollers
AC CHARACTERISTICS
Preliminary
External I/O or Memory Read and Write Timing Table
No. Symbol
Parameter
VCC
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
1
TdA(AS)
2
TdAS(A)
Address Valid to
/AS Rising Delay
/AS Rising to Address Float Delay
3
TdAS(DR)
/AS Rising to Read Data Required Valid
4
TwAS
/AS Low Width
5
Td
6
TwDSR
Address Float to
/DS Falling
/DS (Read) Low Width
7
TwDSW
/DS (Write) Low Width
8
TdDSR(DR)
/DS Falling to Read Data Required Valid
9
ThDR(DS)
10
TdDS(A)
Read Data to
/DS Rising Hold Time
/DS Rising to Address Active Delay
11
TdDS(AS)
12
13
14
15
16
17
18
19
20
/DS Rising to /AS
Falling Delay
TdR/W(AS) R//W Valid to /AS
Rising Delay
TdDS(R/W) /DS Rising to
R//W Not Valid
TdDW(DSW) Write Data Valid to /DS Falling (Write)
Delay
TdDS(DW)
/DS Rising to Write
Data Not Valid Delay
TdA(DR)
Address Valid to Read Data Required
Valid
TdAS(DS)
/AS Rising to
/DS Falling Delay
TdDM(AS)
/DM Valid to /AS
Falling Delay
TdDS(DM)
/DS Rise to
/DM Valid Delay
ThDS(A)
/DS Rise to Address Valid Hold Time
TA = 0°C to +70°C
16 MHz
Min.
Max.
55
55
70
70
400
400
80
80
0
0
300
300
165
165
260
260
0
0
85
95
60
70
70
70
70
70
80
80
70
80
475
475
100
100
55
55
70
70
70
70
Units
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
1,2
1,2
2
2
1,2
1,2
1,2
2
2
2
2
2
2
1,2
2
2
2
Notes:
1. When using extended memory timing add 2 TpC.
2. Timing numbers given are for minimum TpC.
Standard Test Load
All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
1-14
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
AC CHARACTERISTICS
Additional Timing Diagram
1
3
1
Clock
2
7
T
2
3
7
IN
4
5
6
IRQ
N
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 11. Additional Timing
DS96LVO1100
PRELIMINARY
1-15
Z86E72/E73
OTP IR Microcontrollers
AC CHARACTERISTICS
Preliminary
Additional Timing Table
TA = 0°C to +70°C
Parameter
VCC
Min
Max
Units
Notes
Input Clock Period
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
4.5V
5.5V
4.5V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
121
121
DC
DC
25
25
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
No
Symbol
1
TpC
2
TrC,TfC
3
TwC
4
TwTinL
Timer Input Low Width
5
TwTinH
Timer Input High Width
6
TpTi
7
Clock Input Rise and Fall Times
Input Clock Width
Timer Input Period
TrTin,TfTi Timer Input Rise and Fall Timers
8A
TwIL
Interrupt Request Low Time
8B
TwIL
Int. Request Low Time
9
TwIH
Interrupt Request Input High Time
10
Twsm
Stop-Mode Recovery Width Spec
11
Tost
Oscillator Start-up Time
12
Twdt
Watch-Dog Timer Delay Time
(5 ms)
(10 ms)
(20 ms)
(80 ms)
37
37
100
70
3TpC
3TpC
8TpC
8TpC
100
70
100
70
3TpC
5TpC
5TpC
5TpC
12
12
5TpC
5TpC
12
5
25
10
50
20
225
80
1
1
1
ns
ns
ns
ns
ns
ns
5TpC
5TpC
75
20
150
40
300
80
1200
320
1
1
1,2
1,2
1,3
1,3
1,2
1,2
7
7
6
6
4
ms
ms
ms
ms
ms
ms
ms
ms
Notes:
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. Interrupt request through Port 3 (P30).
4. SMR – D5 = 0
5. Reg. WDTMR
6. Reg. SMR – D5 = 0
7. Reg. SMR – D5 = 1
1-16
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
AC CHARACTERISTICS
Handshake Timing Diagrams
1
Data In
Data In Valid
Next Data In Valid
2
1
3
/DAV
(Input)
Delayed DAV
5
4
RDY
(Output)
6
Delayed RDY
Figure 12. Input Handshake Timing
Data Out
Next Data Out Valid
Data Out Valid
7
/DAV
(Output)
Delayed DAV
8
9
11
10
RDY
(Input)
Delayed
RDY
Figure 13. Output Handshake Timing
DS96LVO1100
PRELIMINARY
1-17
Z86E72/E73
OTP IR Microcontrollers
AC CHARACTERISTICS
Preliminary
Handshake Timing Table
Symbol
Parameter
VCC
1
TsDI(DAV)
Data In Setup Time
2
ThDI(DAV)
Data In Hold Time
3
TwDAV
Data Available Width
4
TdDAVI(RDY)
5
TdDAVId(RDY)
6
TdRDYO(DAV)
7
TdDO(DAV)
8
TdDAV0(RDY)
9
TdRDY0(DAV)
10
TwRDY
DAV Falling to RDY
Falling Delay
DAV Rising to RDY
Falling Delay
RDY Rising to DAV
Falling Delay
Data Out to DAV
Falling Delay
DAV Falling to RDY
Falling Delay
RDY Falling to DAV
Rising Delay
RDY Width
11
TdRDY0d(DAV)
4.0V
5.5V
4.0V
5.5V
4.0V
5.5V
4.0V
5.5V
4.0V
5.5V
4.0V
5.5V
4.0V
5.5V
4.0V
5.5V
4.0V
5.5V
4.0V
5.5V
4.0V
5.5V
No
1-18
RDY Rising to DAV
Falling Delay
PRELIMINARY
TA = 0°C to +70°C
16 MHz
Min
Max
0
0
0
155
110
160
115
120
80
0
0
63
63
0
0
160
115
110
80
110
80
Data
Direction
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
PIN FUNCTIONS
/DS (Output, active Low). Data Strobe is activated once for
each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of /DS. For
WRITE operations, the falling edge of /DS indicates that
output data is valid.
/AS (Output, active Low). Address Strobe is pulsed once
at the beginning of each machine cycle. Address output is
through Port 0/Port 1 for all external programs. Memory
address transfers are valid at the trailing edge of /AS. Under program control, /AS is placed in the high-impedance
state along with Ports 0 and 1, Data Strobe, and
Read/Write.
XTAL1 Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, or RC
network or an external single-phase clock to the on-chip
oscillator input.
XTAL2 Crystal 2 (time-based output). This pin connects a
parallel-resonant, crystal, ceramic resonant, LC, or RC
network to the on-chip oscillator output.
R//W Read/Write (output, write Low). The R//W signal is
Low when the CCP is writing to the external program or
data memory.
R//RL (input). This pin, when connected to GND, disables
the internal ROM and forces the device to function as a
ROMless Z8. (Note that, when left unconnected or pulled
high to VCC, the part functions normally as a Z8 ROM version.)
Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS
compatible port. These eight I/O lines are configured under software control as a nibble I/O port, or as an address
port for interfacing external memory. The output drivers
are push-pull. Port 0 is placed under handshake control. In
this configuration, Port 3, lines P32 and P35 are used as
the handshake control /DAV0 and RDY0. Handshake signal direction is dictated by the I/O direction to Port 0 of the
upper nibble P07-P04. The lower nibble must have the
same direction as the upper nibble.
For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If
the address range requires 12 bits or less, the upper nibble
of Port 0 can be programmed independently as I/O while
the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured
by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port.
Port 0 is set in the high-impedance mode if selected as an
address output state along with Port 1 and the control signals /AS, /DS, and R//W (Figure 8).
A software option is available to program 0.4 VDD CMOS
trip inputs on P00-P03. This allows direct interface to
mouse/trackball IR sensors.
An optional 200 kOhm pull-up is available as a software
option of all Port 0 bits with nibble select.
These pull-ups are disabled when configured (bit by bit) as
an output.
DS96LVO1100
PRELIMINARY
1-19
1
Z86E72/E73
OTP IR Microcontrollers
PIN FUNCTIONS (Continued)
4
Port 0 (I/O or A15 - A8)
Z86LXX
MCU
4
Optional
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
Mask
Option
OEN
200 kΩ
PAD
Out
In
In
0.4 VDD
Trip Point Buffer
* Note: On P00 and P07 only.
** POIM, DI, DO Mask Selectable.
*** Refer to the Z86C17 specification for
application information in utilizing these
inputs in a mouse or trackball application.
Figure 14. Port 0 Configuration
1-20
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Port 1 (P17-P10). Port 1 is a multiplexed Address (A7-A0)
and Data (D7-D0), CMOS compatible port. Port 1 is dedicated to the Zilog ZBus®-compatible memory interface.
The operations of Port 1 are supported by the Address
Strobe (/AS) and Data Strobe (/DS) lines, and by the
Read/Write (R//W) and Data Memory (/DM) control lines.
Data memory read/write operations are done through this
port (Figure 20). If more than 256 external locations are required, Port 0 outputs the additional lines.
Port 1 can be placed in the high-impedance state along
with Port 0, /AS, /DS, and R//W, allowing the Z86L7X to
share common resources in multiprocessor and DMA applications. Port1 can also be configured for standard port
output mode.
Port 1
(I/O or AD7 - AD0)
8
Z86LXX
MCU
Optional
Handshake Controls
/DAV1 and RDY1
(P33 and P34)
OEN
PAD
Out
In
Auto Latch
R ≈ 500 KΩ
Figure 15. Port 1 Configuration
DS96LVO1100
PRELIMINARY
1-21
1
Z86E72/E73
OTP IR Microcontrollers
PIN FUNCTIONS (Continued)
Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS
compatible I/O port. These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A software option is available to connect eight 200 kOhms
(±50%) pull-up resistors on this port. Bits programmed as
outputs are globally programmed as either push-pull or
open-drain. Port 2 may be placed under handshake control. In this configuration, Port 3 lines, P31 and P36 are
used as the handshake controls lines /DAV2 and RDY2.
The handshake signal assignment for Port 3, lines P31
and P36 is dictated by the direction (input or output) assigned to Bit 7, Port 2 (Figure 10).
The CCP wakes up with the eight bits of Port 2 configured
as inputs with open-drain outputs.
Port 2 also has an 8-bit input OR and an AND gate which
can be used to wake up the part. P20 can be programmed
to access the edge selection circuitry (Figure 21).
Port 2 (I/O)
Z86LXX
MCU
Optional
Handshake Controls
/DAV2 and RDY2
(P31 and P36)
(L72/E72 Only)
VCC
Open-Drain
200 kΩ
OEN
Mask
Option
PAD
Out
In
Figure 16. Port 2 Configuration
1-22
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Port 3 (P37-P31). Port 3 is a 7-bit, CMOS compatible three
fixed input and four fixed output port. Port 3 consists of
three fixed input (P33-P31) and four fixed output (P37P34), and can be configured under software control for Input/Output, Interrupt, Port handshake, Data Memory functions and output from the counter/timers. P31, P32, and
P33 are standard CMOS inputs; outputs are push-pull.
ter bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the Counter Timer edge detection circuit is through P31 or P20 (see CTR1
description).
Port 3 provides the following control functions: handshake
for Ports 0, 1, and 2 (/DAV and RDY); three external interrupt request signals (IRQ2-IRQ0); Data Memory Select
(/DM) (Table 8).
Two on-board comparators process analog signals on P31
and P32 with reference to the voltage on Pref1 and P33.
The analog function is enabled by programming the Port 3
Mode Register (bit 1). P31 and P32 are programmable as
rising, falling, or both edge triggered interrupts (IRQ regis-
Port 3 also provides output for each of the counter/timers
and the AND/OR Logic. Control is performed by programming bits D5-D4 of CTRI, bit 0 of CTR0 and bit 0 of CTR2.
P34
Counter/Timer
PAD
T8
P34 OUT
P34 OUT
P31
+
-
COMP1
CTR0
PREF1
D0
0 Normal Control
1 8-bit Timer output active
P37
PAD
P37 OUT
P32
+
-
COMP2
P33 (PREF2)
PCON
D0
0 = P34, P37 Standard Output *
1 = P34, P37 Comparator Output
*
Reset condition.
Figure 17. Port 3 Configuration
DS96LVO1100
PRELIMINARY
1-23
1
Z86E72/E73
OTP IR Microcontrollers
PIN FUNCTIONS (Continued)
Table 4. Pin Assignments
Pin
Pref1
P31
P32
P33
P34
P35
P36
P37
P20
I/O
IN
IN
IN
IN
OUT
OUT
OUT
OUT
I/O
C/T
IN
T8
T16
T8/16
Comp.
RF1
AN1
AN2
RF2
A01
Int.
P0 HS
IRQ2
IRQ0
IRQ1
D/R
P1 HS
P2 HS
Ext
D/R
D/R
R/D
D/M
R/D
R/D
A02
IN
Notes:
HS = Handshake Signals
D = /DAV
R = RDY
Comparator Inputs. In Analog Mode, Port 3 (P31 and
P32) have a comparator front end. The comparator reference is supplied to P33 and Pref1. In this mode, the P33
internal data latch and its corresponding IRQ1 is diverted
to the SMR sources (excluding P31, P32, and P33) as
shown in Figure 37. In digital mode, P33 is used as D3 of
the Port 3 input register which then generates IRQ1 as
shown in Figure 23.
Notes: Comparators are disabled/powered down by entering STOP mode. For P31-P33 to be used as a Stop-Mode
recovery source, these inputs must be placed into digital
mode.
/RESET (Input, active Low). Initializes the MCU. Reset is
accomplished either through Power-On, Watch-Dog Timer, Stop-Mode Recovery, Low Voltage detection, or external reset. During Power-On Reset and Watch-Dog Timer
Reset, the internally generated reset drives the reset pin
Low for the POR time. Any devices driving the reset line
should be open-drain in order to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. There is no condition internal to the L7X that will
not allow an external reset to occur.
Comparator Outputs. These may be programmed to be
outputted on P34 and P37 through the PCON register (Figure 22).
1-24
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
After the POR time, /RESET is a Schmitt-triggered input.
To avoid asynchronous and noisy reset problems, the
Z86L7X is equipped with a reset filter of four external
clocks (4TpC). If the external reset signal is less than 4TpC
in duration, no reset occurs. On the fifth clock after the reset is detected, an internal RST signal is latched and held
for an internal register count of 18 external clocks, or for
the duration of the external reset, whichever is longer.
During the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC/2. Program execution begins at location 000CH, 5-10 TpC cycles after the RST is released. For
Power-On Reset, the typical reset output time is 5 ms. The
Z86E7X devices do not have internal pull resistors on
Port 3 inputs.
Pref1
200 KΩ
P31
P32
P33
Z86LXX
MCU
Mask
Option
Port 3
(I/O or Handshake)
P34
P35
Note:
P31, 32, 33 have a 200 KΩ
mask option called Mask
option 3 similar to Mask
options 1 and 2.
P36
P37
R247 = P3M
D1
1 = Analog
0 = Digital
DIG.
P31 (AN1)
IRQ2, P31 Data Latch
+
PREF1
COMP1
AN.
-
P32 (AN2)
IRQ0, P32 Data Latch
+
COMP2
P33 (REF2)
-
IRQ1, P33 Data Latch
From Stop-Mode
Recovery Source
Figure 18. Port 3 Configuration
DS96LVO1100
PRELIMINARY
1-25
1
Z86E72/E73
OTP IR Microcontrollers
PIN FUNCTIONS (Continued)
CTR0, D0
Out 34
T8_Out
VDD
MUX
Pad
P34
CTR2, D0
VDD
Out 35
MUX
Pad
T16_Out
P35
CTR1, D6
VDD
Out 36
T8/16_Out
MUX
Pad
P36
Figure 19. Port 3 Configuration
1-26
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
FUNCTIONAL DESCRIPTION
The Z8® CCP incorporates special functions to enhance
the Z8's functionality in consumer and battery operated applications.
Note: The Extended Data RAM cannot be used as
STACK or instruction/code memory. Accessing the
Extended Data RAM has the following condition: P01M
register bits D4-D3 cannot be set to 11.
Reset. The device is reset in one of the following conditions:
65535
External ROM
1. Power-On Reset
16384
Location of
First Byte of
Instruction
Executed
After RESET
12
2. Watch-Dog Timer
3. Stop-Mode Recovery Source
4. Low Voltage Detection
RAM. The Z86E72 has a 768-byte RAM, 256 bytes make
up the Register file. The remaining 512 bytes make up the
Extended Data RAM. The Z86E73 has just the 256 bytes
of the Register file.
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
Extended Data RAM. The Extended Data RAM of the
Z86E72 occupies the address range FE00H-FFFFH (512
bytes). This range of addresses FD00H-FFFFH cannot be
used to directly read from or write to external memory. Accessing the Extended Data RAM is accomplished by using
LDE, LDEI, LDC, or LDCI instructions. Port 1 and Port 0
are free to be set as I/O or ADDR/DATA modes; except
high-impedance when accessing Extended Data RAM. In
addition, if the External Memory uses the same address
range of the Extended Data RAM it can be used as the External Stack only.
DS96LVO1100
PRELIMINARY
Reset Start Address
11
Reserved
10
Reserved
9
IRQ4
8
IRQ4
7
IRQ3
6
IRQ3
5
IRQ2
4
IRQ2
3
IRQ1
2
IRQ1
1
IRQ0
0
IRQ0
5. External Reset
Program Memory. The Z86E72/73 addresses up to
16K/32 Kbytes of internal program memory, with the remainder being external memory (Figure 26). The first 12
bytes of program memory are reserved for the interrupt
vectors. These locations contain five 16-bit vectors that
correspond to the five available interrupts. Addresses of
16K/32K consist of on-chip OTP. At addresses 16K or 32K
and greater, the E72/73 executes external program memory fetches (refer to external memory timing specifications).
On-Chip
ROM
Figure 20. Program Memory Map
1-27
1
Z86E72/E73
OTP IR Microcontrollers
FUNCTIONAL DESCRIPTION (Continued)
Bits 7-4 of register RP select the working register group.
Bits 3-0 of register RP select the expanded register file
bank. Note that expanded register bank is also referred
to as expanded register group (Figure 24).
65535
The upper nibble of the register pointer (Figure 24) selects
which working register group of 16 bytes in the register file,
out of the possible 256, will be accessed. The lower nibble
selects the expanded register file bank and, in the case of
the Z86LXX family, banks 0, F, and D are implemented. A
0h in the lower nibble will allow the normal register file
(bank 0) to be addressed, but any other value from 1h to
Fh will exchange the lower 16 registers to an expanded
register bank.
External
Data
Memory
32,768
For example:
Z86E73: (See Figure 23)
R253 RP = 00H
R0 = Port0
R1 = Port1
R2 = Port2
R3 = Port3
Not Addressable
But if:
R253 RP = 0DH
R0 = CTRL0
R1 = CTRL1
R2 = CTRL2
R3 = Reserved
0
Figure 21. External Memory Map
External Memory. The Z86E72/73 addresses up to 32
Kbytes (minus FD00H-FFFFH) of External Memory beginning at address 8000H (32K+1), (Figure 27). External data
memory is included with, or separated from, the external
program memory space. /DM, an optional I/O function that
is programmed to appear on P34, is used to distinguish between data and program memory space. The state of the
/DM signal is controlled by the type of instruction being executed. An LDC opcode references PROGRAM (/DM inactive) memory, and an LDE instruction references data
(/DM active Low) memory.
Expanded Register File. The register file has been expanded to allow for additional system control registers,
and for mapping of additional peripheral devices into the
register address area. The Z8 register address space R0
through R15 has been implemented as 16 banks of 16 registers per bank. These register groups are known as the
ERF (Expanded Register File).
1-28
The counter/timers are mapped into ERF group D. Access
is easily done using the following example:
LD
RP,#0DH
LD
LD
LD
R0,#xx
1,#xx
RP,#7DH
LD
R1,2
PRELIMINARY
Select ERF D for access and
register Bank 0 as the working
register group.
access CTRL0
access CTRL1
Select expanded register group
(ERF) group D for access and
register Bank 7 as the working
register bank.
CTRL2 → register 71H
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Z8® STANDARD CONTROL REGISTERS
RESET CONDITION
1
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER**
REGISTER POINTER
7
6
5
4
3
2
1
0
Expanded Register
Bank/Group Pointer
Working Register
Group Pointer
*
*
Z8 Register File**
FF
SPL
U
U
U
U
U
U
U
U
FE
SPH
U
U
U
U
U
U
U
U
FD
RP
0
0
0
0
0
0
0
0
FC
FLAGS
U
U
U
U
U
U
U
U
FB
IMR
0
U
U
U
U
U
U
U
FA
IRQ
0
0
0
0
0
0
0
0
F9
IPR
U
U
U
U
U
U
U
U
F8
P01M
0
1
0
0
1
1
0
1
F7
P3M
0
0
0
0
0
0
0
0
F6
P2M
1
1
1
1
1
1
1
1
F5
Reserved
U
U
U
U
U
U
U
U
F4
Reserved
U
U
U
U
U
U
U
U
F3
Reserved
U
U
U
U
U
U
U
U
F2
Reserved
U
U
U
U
U
U
U
U
F1
Reserved
0
0
0
0
0
0
0
0
F0
Reserved
0
U
U
0
0
0
0
0
FF
FO
EXPANDED REG. BANK/GROUP (F)
REGISTER**
RESET CONDITION
(F) 0F
WDTMR
U
U
U
0
1
1
0
(F) 0E
OPT
0
0
0
0
0
0
0
0
(F) 0D
SMR2
U
0
U
0
0
0
U
U
0
0
1
0
0
0
U
0
U
U
U
U
U
U
U
0
*
7F
Reserved
†
Reserved
0F
00
*
(F) 0C
Reserved
(F) 0B
SMR
(F) 0A
Reserved
(F) 09
Reserved
(F) 08
Reserved
(F) 07
Reserved
(F) 06
Reserved
(F) 05
Reserved
(F) 04
Reserved
(F) 03
Reserved
(F) 02
Reserved
(F) 01
Reserved
(F) 00
PCON
1
EXPANDED REG. BANK/GROUP (D)
REGISTER**
EXPANDED REG. GROUP (0)
REGISTER**
*
*
Reserved
(D) 0B
HI8
U
U
U
U
U
U
U
U
U
(D) 0A
L08
U
U
U
U
U
U
U
U
U
U
(D) 09
HI16
U
U
U
U
U
U
U
U
U
U
(D) 08
L016
U
U
U
U
U
U
U
U
U
U
(D) 07
TC16H
U
U
U
U
U
U
U
U
(D) 06
TC16L
U
U
U
U
U
U
U
U
(D) 05
TC8H
U
U
U
U
U
U
U
U
(D) 04
TC8L
U
U
U
U
U
U
U
U
(D) 03
Reserved
RESET CONDITION
(0) 03
P3
0
0
0
0
U
U
U
(0) 02
P2
U
U
U
U
U
U
(0) 01
P1
U
U
U
U
U
U
(0) 00
P0
U
U
U
U
U
U
U = Unknown
RESET CONDITION
(D) 0C
* Will not be reset with a Stop-Mode Recovery
** All addresses are in Hexadecimal
† Will not be reset with a Stop-Mode Recovery, except Bit 0.
(D) 02
CTR2
0
U
U
U
U
U
U
(D) 01
CTR1
0
0
U
U
U
U
U
U
(D) 00
CTR0
0
U
U
U
U
U
U
0
Figure 22. Expanded Register File Architecture
DS96LVO1100
PRELIMINARY
1-29
Z86E72/E73
OTP IR Microcontrollers
FUNCTIONAL DESCRIPTION (Continued)
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
r7 r 6 r5 r 4
r3 r 2 r1 r 0
R253
Expanded Register File Pointer
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group
Working Register Pointer
Default Setting After Reset = 0000 0000
Figure 23. Register Pointer
FF
Register File. The register file (bank 0) consists of four I/O
port registers, 236 general-purpose registers, and 16 control and status registers (R0-R3, R4-R239, and R240R255, respectively), Plus two expanded registers groups
(Banks D and F). Instructions can access registers directly
or indirectly through an 8-bit address field. This allows a
short, 4-bit register address using the Register Pointer
(Figure 23). In the 4-bit mode, the register file is divided
into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group.
Note: Working register group E0-EF of Bank 0 are only
accessed through working registers and indirect addressing modes.
Stack. The Z86E7X external data memory or the internal
register file is used for the stack. An 8-bit Stack Pointer
(R255) is used for the internal stack that resides in the general-purpose registers (R4-R239). SPH is used as a general-purpose register only when using internal stacks.
Note: When SPH is used as a general-purpose register
and Port 0 is in address mode, the contents of SPH will be
loaded into Port 0 whenever the internal stack is accessed.
1-30
PRELIMINARY
R15 to R0
F0
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register
Specified Working
Register Group
2F
20
1F
Register Group 1
R15 to R0
Register Group 0
R15 to R4
I/O Ports
R3 to R0
10
0F
00
Figure 24. Register Pointer
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION
Table 5. Expanded Register Group D
(D) %0C
(D) % 0B
(D) % 0A
(D) %09
(D) %08
(D) %07
(D) %06
(D) %05
(D) %04
(D) %03
(D) %02
(D) %01
(D) %00
L016(D)%08: Holds the captured data from the output of
the 16-bit Counter/Timer16. This register holds the LSByte of the data.
Reserved
HI8
LO8
HI16
LO16
TC16H
TC16L
TC8H
TC8L
Reserved
CTR2
CTR1
CTR0
Field
Bit Position
T16_Capture_LO 76543210
Value
Description
R/W
Captured Data
No Effect
TC16H(D)%07: Counter/Timer2 MS-Byte Hold Register.
Field
T16_Data_HI
Bit Position
Value
Description
76543210
R/W
Data
TC16L(D)%06: Counter/Timer2 LS-Byte Hold Register.
Field
Bit Position
Value
Description
76543210
R/W
Data
Register Description
T16_Data_LO
HI8(D)%0B: Holds the captured data from the output of the
8-bit Counter/Timer0. This register is typically used to hold
the number of counts when the input signal is 1.
TC8H(D)%05: Counter/Timer8 High Hold Register.
Field
Field
Bit Position
T8_Capture_HI 76543210
Value
Description
R/W
Captured Data
No Effect
L08(D)%0A: Holds the captured data from the output of
the 8-bit Counter/Timer0. This register is typically used to
hold the number of counts when the input signal is 0.
Field
Bit Position
Value
T8_Capture_L0
76543210
R/W
T8_Level_HI
Bit Position
Value
Description
76543210
R/W
Data
TC8L(D)%04: Counter/Timer8 Low Hold Register.
Field
T8_Level_LO
Bit Position
Value
Description
76543210
R/W
Data
Description
Captured Data
No Effect
HI16(D)%09: Holds the captured data from the output of
the 16-bit Counter/Timer16. This register holds the MSByte of the data.
Field
T16_Capture_HI
DS96LVO1100
Bit Position
Value
76543210
R/W
Description
Captured
Data
No Effect
PRELIMINARY
1-31
1
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
CTR0 (D)00: Counter/Timer8 Control Register.
Field
T8_Enable
Bit Position
7-------
Value
R
W
Single/Modulo
-6------
R/W
Time_Out
--5------
R
T8 _Clock
---43---
W
R/W
Capture_INT_MASK
-----2--
R/W
Counter_INT_Mask
------1-
R/W
P34_Out
-------0
R/W
0*
1
0
1
0
1
0
1
0
1
00
01
10
11
0
1
0
1
0*
1
Description
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Modulo-N
Single Pass
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
SCLK
SCLK/2
SCLK/4
SCLK/8
Disable Data Capture Int.
Enable Data Capture Int.
Disable Time-Out Int.
Enable Time-Out Int.
P34 as Port Output
T8 Output on P34
Note: *Indicates the value upon Power-On Reset
CTR0: Counter/Timer8 Control Register Description
T8 Enable. This field enables T8 when set (written) to 1.
Single/Modulo-N. When set to 0 (modulo-n), the counter
reloads the initial value when the terminal count is
reached. When set to 1 (single pass), the counter stops
when the terminal count is reached.
Time-Out. This bit is set when T8 times out (terminal count
reached). To reset this bit, a 1 should be written to this location. This is the only way to reset this status condition, therefore, care should be taken to reset this bit
prior to using/enabling the counter/timers.
T8 Clock. Defines the frequency of the input signal to T8.
Capture_INT_Mask. Set this bit to allow interrupt when
data is captured into either LO8 or HI8 upon a positive or
negative edge detection in demodulation mode.
Counter_INT_Mask. Set this bit to allow interrupt when T8
has a time out.
P34_Out. This bit defines whether P34 is used as a normal
output pin or the T8 output
Note: Care must be taken when utilizing the OR or AND
commands to manipulate CTR0, bit 5 and CTR1, bits 0
and 1 (Demodulation Mode). These instructions use a
Read-Modify-Write sequence in which the current status
from the CTR0 and CTR1 registers will be ORed or ANDed
with the designated value and then written back into the
registers. Example: When the status of bit 5 is 1, a reset
condition will occur.
1-32
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
CTR1(D)%01: Controls the functions in common with the T8 and T16.
Field
Bit Position
Value
Mode
7-------
R/W
P36_Out/
Demodulator_Input
-6------
R/W
0*
1
0*
1
0
1
T8/T16_Logic/
Edge _Detect
--54----
R/W
00
01
10
11
00
01
10
11
Transmit_Submode/
Glitch_Filter
----32--
R/W
00
01
10
11
00
01
10
11
Initial_T8_Out/
Rising_Edge
------1R/W
0
1
R
0
1
0
1
W
Initial_T16_Out/
Falling _Edge
-------0
R/W
0
1
R
0
1
0
1
W
Description
1
Transmit Mode
Demodulation Mode
Transmit Mode
Port Output
T8/16 Output
Demodulation Mode
P31
P20
Transmit Mode
AND
OR
NOR
NAND
Demodulation Mode
Falling Edge
Rising Edge
Both Edges
Reserved
Transmit Mode
Normal Operation
Ping-Pong Mode
T16_OUT = 0
T16_OUT = 1
Demodulation Mode
No Filter
4 SCLK Cycle
8 SCLK Cycle
16 SCLK Cycle
Transmit Mode
T8_OUT is 0 Initially
T8_OUT is 1 Initially
Demodulation Mode
No Rising Edge
Rising Edge Detected
No Effect
Reset Flag to 0
Transmit Mode
T16_OUT is 0 Initially
T16_OUT is 1 Initially
Demodulation Mode
No Falling Edge
Falling Edge Detected
No Effect
Reset Flag to 0
Note: * Indicates the value upon Power-On Reset.
DS96LVO1100
PRELIMINARY
1-33
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
CTR1 Register Description
Mode. If it is 0, the Counter/Timers are in the transmit
mode, otherwise they are in the demodulation mode.
P36_Out/Demodulator_Input. In Transmit Mode, this bit
defines whether P36 is used as a normal output pin or the
combined output of T8 and T16.
In Demodulation Mode, this bit defines whether the input
signal to the Counter/Timers is from P20 or P31.
T8/T16_Logic/Edge _Detect. In Transmit Mode, this field
defines how the outputs of T8 and T16 are combined
(AND, OR, NOR, NAND).
In Demodulation Mode, this field defines which edge
should be detected by the edge detector.
Transmit_Submode/Glitch Filter. In Transmit Mode, this
field defines whether T8 and T16 are in the "Ping-Pong"
mode or in independent normal operation mode. Setting
this field to "Normal Operation Mode" terminates the "PingPong Mode" operation. When set to 10, T16 is immediately
forced to a 0. When set to 11, T16 is immediately forced
to a 1.
In Demodulation Mode, this field defines the width of the
glitch that should be filtered out.
Initial_T8_Out/Rising_Edge. In Transmit Mode, if 0, the
output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. When this bit is
set to 1 or 0, T8_OUT will be set to the opposite state of
this bit. This insures that when the clock is enabled a transition occurs to the initial state set by CTR1, D1.
In Demodulation Mode, this bit is set to 1 when a rising
edge is detected in the input signal. In order to reset it, a 1
should be written to this location.
Initial_T16 Out/Falling _Edge. In Transmit Mode, if it is 0,
the output of T16 is set to 0 when it starts to count. If it is
1, the output of T16 is set to 1 when it starts to count. This
bit is effective only in Normal or Ping-Pong Mode (CTR1,
D3, D2). When this bit is set, T16_OUT will be set to the
opposite state of this bit. This insures that when the clock
is enabled a transition occurs to the initial state set by
CTR1, D0.
In Demodulation Mode, this bit is set to 1 when a falling
edge is detected in the input signal. In order to reset it, a 1
should be written to this location.
Note: Modifying CTR1, (D1 or D0) while the counters are
enabled will cause un-predictable output from T8/T16 out.
1-34
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
CTR2 (D)%02: Counter/Timer16 Control Register.
Field
T16_Enable
Bit Position
R
7-------
W
Submode/Modulo-N
Value
Description
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Transmit Mode
Modulo-N
Single Pass
Demodulation Mode
T16 Recognizes Edge
T16 Does Not Recognize Edge
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
SCLK
SCLK/2
SCLK/4
SCLK/8
Disable Data Capture Int.
Enable Data Capture Int.
Disable Time-Out Int.
Enable Time-Out Int.
P35 as Port Output
T16 Output on P35
R/W
-6------
0
1
Time_Out
0
1
0
1
0
1
00
01
10
11
0
1
0
1
0*
1
R
--5-----
W
T16 _Clock
---43---
R/W
Capture_INT_Mask
-----2--
R/W
Counter_INT_Mask
------1-
R/W
P35_Out
-------0
R/W
Note: * Indicates the value upon Power-On Reset.
CTR2 Description
T16_Enable. This field enables T16 when set to 1.
T16_Clock. Defines the frequency of the input signal to
Counter/Timer16.
Single/Modulo-N. In Transmit Mode, when set to 0, the
counter reloads the initial value when terminal count is
reached. When set to 1, the counter stops when the terminal count is reached.
Capture_INT_Mask. Set this bit to allow interrupt when
data is captured into LO16 and HI16.
In Demodulation Mode, when set to 0 , T16 captures and
reloads on detection of all the edges; when set to 1, T16
captures and detects on the first edge, but ignores the subsequent edges. For details, see the description of T16 Demodulation Mode.
Counter_INT_Mask. Set this bit to allow interrupt when
T16 times out.
P35_Out. This bit defines whether P35 is used as a normal
output pin or T16 output.
Time_Out. This bit is set when T16 times out (terminal
count reached). In order to reset it, a 1 should be written to
this location.
DS96LVO1100
PRELIMINARY
1-35
1
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
SMR2(F) %0D: Stop-Mode Recovery Register 2.
Field
Bit Position
Value
Reserved
Recovery Level
7-------6------
W
Reserved
Source
--5-------432--
W
Reserved
------10
0
0*
1
0
000*
001
010
011
100
101
110
111
00
Description
Reserved (Must be 0)
Low
High
Reserved (Must be 0)
A. POR Only
B. NAND of P23-P20
C. NAND or P27-P20
D. NOR of P33-P31
E. NAND of P33-P31
F. NOR of P33-P31, P00,P07
G. NAND of P33-P31,P00,P07
H. NAND of P33-P31,P22-P20
Reserved (Must be 0)
Note: * Indicates the value upon Power-On Reset.
Counter/Timer Functional Blocks
CTR1 D5,D4
P31
Glitch
Filter
MUX
P20
Edge
Detector
Pos Edge
Neg Edge
CTR1 D6
CTR1 D3,D2
Figure 25. Glitch Filter Circuitry
1-36
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Z8 Data Bus
CTR0 D2
1
Pos Edge
IRQ4
Neg Edge
HI8
LO8
CTR0 D4, D3
SCLK
CTR0 D1
Clock
Select
Clock
8-Bit
Counter T8
TC8H
T8_OUT
TC8L
Z8 Data Bus
Figure 26. 8-Bit Counter/Timer Circuits
Input Circuit
The edge detector monitors the input signal on P31 or P20.
Based on CTR1 D5-D4, a pulse is generated at the Pos
Edge or Neg Edge line when an edge is detected. Glitches
in the input signal which have a width less than specified
(CTR1 D3, D2) are filtered out.
T8 Transmit Mode
When T8 is enabled, the output of T8 depends on CTR1,
D1. If it is 0, T8_OUT is 1. If it is 1, T8_OUT is 0.
When T8 is enabled, the output T8_OUT switches to the
initial value (CTR1 D1). If the initial value (CTR1 D1) is 0,
TC8L is loaded, otherwise TC8H is loaded into the
counter. In Single-Pass Mode (CTR0 D6), T8 counts down
to 0 and stops, T8_OUT toggles, the time-out status bit
(CTR0 D5) is set, and a time-out interrupt can be generated if it is enabled (CTR0 D1) (Figure 33). In Modulo-N
Mode, upon reaching terminal count, T8_OUT is toggled,
but no interrupt is generated. Then T8 loads a new count
(if the T8_OUT level now is 0), TC8L is loaded; if it is 1,
TC8H is loaded. T8 counts down to 0, toggles T8_OUT,
sets the time-out status bit (CTR0 D5) and generates an
interrupt if enabled (CTR0 D1) (Figure 34). This completes
one cycle. T8 then loads from TC8H or TC8L according to
the T8_OUT level, and repeats the cycle.
DS96LVO1100
The user can modify the values in TC8H or TC8L at any
time. The new values take effect when they are loaded.
Care must be taken not to write these registers at the time
the values are to be loaded into the counter/timer, to ensure known operation. An initial count of 1 is not allowed (a
non-function will occur). An initial count of 0 will cause TC8
to count from 0 to %FF to %FE (Note, % is used for hexadecimal values). Transition from 0 to %FF is not a time-out
condition.
Note: Using the same instructions for stopping the
counter/timers and setting the status bits is not recommended. Two successive commands, first stopping
the counter/timers, then resetting the status bits is necessary. This is required because it takes one counter/timer
clock interval for the initiated event to actually occur.
PRELIMINARY
1-37
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
TC8H Counts
“Counter Enable” Command,
T8_OUT Switches To Its
Initial Value (CTR1 D1)
T8_OUT Toggles,
Time-Out Interrupt
Figure 27. T8_OUT in Single-Pass Mode
T8_OUT Toggles
T8_OUT
TC8L
“Counter Enable” Command,
T8_OUT Switches To Its
Initial Value (CTR1 D1)
TC8H
TC8L
Time-Out Interrupt
TC8H
TC8L
Time-Out Interrupt
Figure 28. T8_OUT in Modulo-N Mode
1-38
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
T8 Demodulation Mode
The user should program TC8L and TC8H to %FF. After
T8 is enabled, when the first edge (rising, falling, or both
depending on CTR1 D5, D4) is detected, it starts to count
down. When a subsequent edge (rising, falling, or both depending on CTR1 D5, D4) is detected during counting, the
current value of T8 is one's complemented and put into
one of the capture registers. If it is a positive edge, data is
put into LO8, if negative edge, HI8. One of the edge detect
status bits (CTR1 D1, D0) is set, and an interrupt can be
generated if enabled (CTR0 D2). Meanwhile, T8 is loaded
with %FF and starts counting again. Should T8 reach 0,
the time-out status bit (CTR0 D5) is set, an interrupt can be
generated if enabled (CTR0 D1), and T8 continues counting from %FF (Figure 35).
T8 (8-Bit)
Count Capture
No
T8_Enable
(Set By User)
Yes
Edge Present
No
Yes
What Kind Of Edge
Neg
Pos
T8 → HI8
T8 → L08
%FF → T8
Figure 29. Demodulation Mode Count Capture Flowchart
DS96LVO1100
PRELIMINARY
1-39
1
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
T8 (8-Bit)
Transmit Mode
No
T8_Enable Bit Set
CTR0, D7
Reset T8_Enable Bit
Yes
0
T8_OUT Value
Load TC8L
Reset T8_OUT
1
Load TC8H
Set T8_OUT
Set Time-out Status Bit
(CTR0 D5) and Generate
Timeout_Int If Enabled
Enable T8
No
T8_Timeout
Yes
Single Pass
Single Pass?
Modulo-N
1
0
T8_OUT Value
Load TC8L
Reset T8_OUT
Load TC8H
Set T8_OUT
Enable T8
Set Time-out Status Bit
(CTR0 D5) and Generate
Timeout_Int If Enabled
No
T8_Timeout
Yes
Disable T8
Figure 30. Transmit Mode Flowchart
1-40
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
T8 (8-Bit)
Demodulation Mode
1
No
T8_Enable
CTR0, D7
Yes
%FF → TC8
Edge Present
No
Yes
Disable T8
Enable TC8
T8_Enable Bit Set
Yes
No
Edge Present
Yes
Set Edge Present Status
Bit And Trigger Data
Capture Int. If Enabled
T8 Time Out
No
Yes
Set Time-out Status
Bit And Trigger Time
Out Int. If Enabled
Continue Counting
Figure 31. Demodulation Mode Flowchart
DS96LVO1100
PRELIMINARY
1-41
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
Z8 Data Bus
CTR2 D2
Pos Edge
IRQ3
Neg Edge
HI16
LO16
CTR2 D4, D3
SCLK
CTR2 D1
Clock
Select
Clock
16-Bit
Counter
T16
TC16H
T16_OUT
TC16L
Z8 Data Bus
Figure 32. 16-Bit Counter/Timer Circuits
T16 Transmit Mode
In Normal or Ping-Pong Mode, the output of T16 when not
enabled is dependent on CTR1, D0. If it is a 0, T16_OUT
is a 1; if it is a 1, T16_OUT is 0. The user can force the output of T16 to either a 0 or 1 whether it is enabled or not by
programming CTR1 D3, D2 to a 10 or 11.
When T16 is enabled, TC16H * 256 + TC16L is loaded,
and T16_OUT is switched to its initial value (CTR1 D0).
When T16 counts down to 0, T16_OUT is toggled (in Normal or Ping-Pong Mode), an interrupt is generated if enabled (CTR2 D1), and a status bit (CTR2 D5) is set. Note
that global interrupts will override this function as described in the interrupts section. If T16 is in Single-Pass
Mode, it is stopped at this point. If it is in Modulo-N Mode,
it is loaded with TC16H * 256 + TC16L and the counting
continues.
1-42
The user can modify the values in TC16H and TC16L at
any time. The new values take effect when they are loaded. Care must be taken not to load these registers at the
time the values are to be loaded into the counter/timer, to
ensure known operation. An initial count of 1 is not allowed. An initial count of 0 will cause T16 to count from 0
to %FF FF to %FFFE. Transition from 0 to %FFFF is not a
time-out condition.
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
TC16H*256+TC16L Counts
1
“Counter Enable” Command,
T16_OUT Switches To Its
Initial Value (CTR1 D0)
T16_OUT Toggles,
Time-Out Interrupt
Figure 33. T16_OUT in Single-Pass Mode
TC16H*256+TC16L
TC16H*256+TC16L
T16_OUT
“Counter Enable” Command,
T16_OUT Switches To Its
Initial Value (CTR1 D0)
TC16H*256+TC16L
T16_OUT Toggles,
Time-Out Interrupt
T16_OUT Toggles,
Time-Out Interrupt
Figure 34. T16_OUT in Modulo-N Mode
T16 Demodulation Mode
The user should program TC16L and TC16H to %FF. After
T16 is enabled, when the first edge (rising, falling or both
depending on CTR1, D5, D4) is detected. T16 captures
HI16 and LO16, reloads and begins counting.
If D6 of CTR2 is 0: When a subsequent edge (rising, falling, or both depending on CTR1 D5, D4) is detected during
counting, the current count in T16 is one's complemented
and put into HI16 and LO16. When data is captured, one
of the edge detect status bits (CTR1 D1, D0) is set and an
interrupt is generated if enabled (CTR2 D2). T16 is loaded
with %FFFF and starts again.
DS96LVO1100
If D6 of CTR2 is 1: T16 ignores the subsequent edges in
the input signal and continues counting down. A time out
of T8 will cause T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16
does not reload and continues counting. If D6 bit of CTR2
is toggled (by writing a 0 then a 1 to it), T16 will capture and
reload on the next edge (rising, falling, or both depending
on CTR1 D5, D4) but continue to ignore subsequent edges.
Should T16 reach 0, it continues counting from %FFFF;
meanwhile, a status bit (CTR2 D5) is set and an interrupt
time-out can be generated if enabled (CTR2 D1).
PRELIMINARY
1-43
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
Ping-Pong Mode
This operation mode is only valid in Transmit Mode. T8
and T16 need to be programmed in Single-Pass Mode
(CTR0 D6, CTR2 D6) and Ping-Pong Mode needs to be
programmed in CTR1 D3, D2. The user can begin the operation by enabling either T8 or T16 (CTR0 D7 or CTR2
D7). For example, if T8 is enabled, T8_OUT is set to this
initial value (CTR1 D1). According to T8_OUT's level,
TC8H or TC8L is loaded into T8. After the terminal count
is reached, T8 is disabled and T16 is enabled. T16_OUT
switches to its initial value (CTR1 D0), data from TC16H
and TC16L is loaded, and T16 starts to count. After T16
reaches the terminal count it stops, T8 is enabled again,
and the whole cycle repeats. Interrupts can be allowed
when T8 or T16 reaches terminal control (CTR0 D1, CTR2
D1). To stop the Ping-Pong operation, write 00 to bits D3
and D2 of CTR1.
Note: Enabling Ping-Pong operation while the
counter/timers are running may cause intermittent
counter/timer function. Disable the counter/timers, then
reset the status flags prior to instituting this operation.
Enable
TC8
Time-Out
Enable
Ping-Pong
CTR1 D3,D2
TC16
Time-Out
Figure 35. Ping-Pong Mode
To Initiate Ping-Pong Mode
First, make sure both counter/timers are not running. Then
set T8 into Single-Pass Mode (CTR0 D6), set T16 into Single-Pass Mode (CTR2 D6), and set Ping-Pong Mode
(CTR1 D2, D3). These instructions do not have to be in
any particular order. Finally, start Ping-Pong Mode by enabling either T8 (CTR0 D7) or T16 (CTR2 D7).
1-44
During Ping-Pong Mode
The enable bits of T8 and T16 (CTR0 D7, CTR2 D7) will
alternately be set and cleared by hardware. The time-out
bits (CTR0 D5, CTR2 D5) will be set every time the
counter/timers reach the terminal count.
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
P34_INTERNAL
MUX
P34_EXT
1
CTR0 D0
P36_INTERNAL
T8_OUT
T16_OUT
CTR1, D2
AND/OR/NOR/NAND
Logic
MUX
P36_EXT
MUX
CTR1 D6
CTR1 D5,D4
CTR1 D3
P35_INTERNAL
MUX
P35_EXT
CTR2 D0
Figure 36. Output Circuit
DS96LVO1100
PRELIMINARY
1-45
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
Interrupts. The Z86E7X has five different interrupts. The
interrupts are maskable and prioritized (Figure 42). The
five sources are divided as follows: three sources are
claimed by Port 3 lines P33-P31, the remaining two by the
counter/timers (Table 10). The Interrupt Mask Register
globally or individually enables or disables the five interrupt requests.
IRQ0
IRQ2
IRQ 1, 3, 4
Interrupt
Edge
Select
IRQ Register (D6, D7)
IRQ
IMR
5
Global
Interrupt
Enable
Interrupt
Request
IPR
Priority
Logic
Vector Select
Figure 37. Interrupt Block Diagram
1-46
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Table 6. Interrupt Types, Sources, and Vectors
Name
Source
Vector
Location
IRQ0
/DAV0, IRQ0
0, 1
IRQ1,
IRQ1
2, 3
IRQ2
/DAV2, IRQ2,
TIN
4,5
IRQ3
IRQ4
T16
T8
6, 7
8, 9
Comments
External
(P32), Rising
Falling Edge
Triggered
External
(P33), Falling
Edge
Triggered
External
(P31), Rising
Falling Edge
Triggered
Internal
Internal
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by
the Interrupt Priority register. An interrupt machine cycle is
activated when an interrupt request is granted. This disables all subsequent interrupts, saves the Program
Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt.
All Z86E7X interrupts are vectored through locations in the
program memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request register is polled to determine which
of the interrupt requests need service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling, or both edge triggered, and are programmable by the user. The software
can poll to identify the state of the pin.
DS96LVO1100
Programming bits for the Interrupt Edge Select are located
in the IRQ Register (R250), bits D7 and D6 . The configuration is shown in Table 11.
Table 7. IRQ Register
IRQ
D7
D6
0
0
1
1
0
1
0
1
Interrupt Edge
IRQ2 (P31)
IRQ0 (P32)
F
F
F
R/F
F
R
F
R/F
Notes:
F = Falling Edge
R = Rising Edge
In analog mode, the Stop-Mode Recovery sources selected by
the SMR register are connected to the IRQ1 input. Any of the
Stop-Mode Recovery sources for SMR (except P31, P32, and
P33) can be used to generate IRQ1 (falling edge triggered).
Clock. The Z86E7X on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a crystal, LC,
ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 1 MHz to 8 MHz maximum, with a series resistance
(RS) less than or equal to 100 Ohms. The Z86L7X on-chip
oscillator may be driven with a cost-effective RC network
or other suitable external clock source.
The crystal should be connected across XTAL1 and
XTAL2 using the recommended capacitors (capacitance
greater than or equal to 22 pF) from each pin to ground.
The RC oscillator configuration is an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to ground (Figure 44).
PRELIMINARY
1-47
1
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and
the oscillator circuit to stabilize before instruction execution begins.
1. Power Fail to Power OK status.
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
The POR time is a nominal 5 ms. Bit 5 of the Stop-Mode
Register determines whether the POR timer is bypassed
after Stop-Mode Recovery (typical for external clock, RC,
LC oscillators).
XTAL1
C1
3. WDT Time-Out.
XTAL1
XTAL1
C1
C1
XTAL2
XTAL1
C1
XTAL1
Rf
R
L
C2
2. Stop-Mode Recovery (if D5 of SMR = 1).
XTAL2
XTAL2
XTAL2
XTAL2
C2
C2
Ceramic Resonator or Crystal
C1, C2 = 47 pF TYP *
f = 8 MHz
* Preliminary value including pin parasitics
LC
C1, C2 = 22 pF
RC
@ 3V VCC (TYP)
L = 130 µH *
f = 3 MHz *
C1 = 33 pF *
R = 1K *
Rd
32 kHz XTAL
C1 = 20 pF, C = 33
pF
Rd = 56 - 470K
Rf =10 M
External Clock
Figure 38. Oscillator Configuration
1-48
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active.
The devices are recovered by interrupts, either externally
or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT.
STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current
to 10 µA (typical) or less. STOP mode is terminated only
by a reset, such as WDT time-out, POR, SMR, or external
reset. This causes the processor to restart the application
program at address 000CH. In order to enter STOP (or
HALT) mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction.
To do this, the user must execute a NOP (opcode = FFH)
immediately before the appropriate sleep instruction, i.e.,
FF
6F
FF
7F
NOP
STOP
or
NOP
HALT
; clear the pipeline
; enter STOP mode
; clear the pipeline
; enter HALT mode
Port Configuration Register (PCON). The PCON register configures the comparator output on Port 3. It is located in the expanded register file at Bank F, location 00 (Figure 44).
PCON (0F) 0H
D7 D6 D5
D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Reserved (Must be 1)
* Default Setting After Reset
Figure 39. Port Configuration Register (PCON)
(Write Only)
Comparator Output Port 3 (D0). Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port
to its standard I/O configuration.
DS96LVO1100
Stop-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 46). All bits are write only except bit 7, which is read only. Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset by
a power-on cycle. Bit 6 controls whether a low level or a
high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3, and D4, of
the SMR register, specify the source of the Stop-Mode Recovery signal. Bit D0 determines if SCLK/TCLK are divided
by 16 or not. The SMR is located in Bank F of the Expanded Register Group at address 0BH
PRELIMINARY
1-49
1
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
SMR D4 D3 D2
0 0 0
SMR2 D4 D3 D2
0 0 0
VCC
VCC
SMR D4 D3 D2
0 1 0
SMR2 D4 D3 D2
0 0 1
P20
P31
S1
P23
SMR D4 D3 D2
0 1 1
SMR2 D4 D3 D2
0 1 0
P20
P32
P27
S2
SMR D4 D3 D2
1 0 0
SMR2 D4 D3 D2
0 1 1
P31
P32
P33
P33
S3
To IRQ1
SMR2 D4 D3 D2
1 0 0
S4
SMR D4 D3 D2
1 0 1
P31
P32
P33
P27
SMR D4 D3 D2
1 1 0
P31
P32
P33
P00
P07
P20
P23
SMR D4 D3 D2
1 1 1
P31
P32
P33
P00
P07
P20
P27
SMR D6
P31
P32
P33
P20
P21
P22
To RESET and WDT
Circuitry (Active Low)
SMR2 D4 D3 D2
1 0 1
SMR2 D4 D3 D2
1 1 0
SMR2 D4 D3 D2
1 1 1
SMR2 D6
Figure 40. Stop-Mode Recovery Register
1-50
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Stop-Mode Recovery Delay Select (D5). This bit, if low,
disables the 5 ms /RESET delay after Stop-Mode Recovery. The default configuration of this bit is one. If the "fast"
wake up is selected, the Stop-Mode Recovery source
needs to be kept active for at least 5TpC.
OSC
÷2
÷ 16
Stop-Mode Recovery Edge Select (D6). A 1 in this bit position indicates that a High level on any one of the recovery
sources wakes the Z86E7X from STOP mode. A 0 indicates Low level recovery. The default is 0 on POR (Figure
36).
SCLK
SMR, D0
TCLK
Figure 41. SCLK Circuit
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR
controls a Divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT mode (where TCLK sources interrupt
logic). After Stop-Mode Recovery, this bit is set to a 0.
Stop-Mode Recovery Source (D2, D3, and D4). These
three bits of the SMR specify the wake up source of the
STOP recovery (Figure 49 and Table 12).
Table 8. Stop-Mode Recovery Source
SMR:432
D4
D3
D2
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Operation
Description of Action
POR and/or external reset recovery
Reserved
P27 transition
Logical NOR of
P20 through P23
Logical NOR of
P20 through P27
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP mode. It is a Read Only Flag bit. A 1
in D7 (warm) indicates that the device will awaken from a
SMR source or a WDT while in STOP mode. A 0 in this bit
(cold) indicates that the device will be reset by a POR or
WDT while not in STOP.
Stop-Mode Recovery Register 2 (SMR2). This register
determines the mode of STOP mode recovery for SMR2.
(Figure 49)
If SMR2 is used in conjunction with SMR, either of the
specified events will cause a Stop-Mode Recovery.
Note: Port pins configured as outputs are ignored as a
SMR or SMR2 recovery source. For example, if the NAND
of P23-P20 is selected as the recovery source and P20 is
configured as an output then the remaining SMR pins
(P23-P21) form the NAND equation.
Note: Any Port 2 bit defined as an output will drive the corresponding input to the default state to allow the remaining
inputs to control the AND/OR function. Refer to SMR2 register for other recover sources.
DS96LVO1100
PRELIMINARY
1-51
1
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR only*
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved
(Must be 0)
Recovery Level
0 Low*
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR,
either of the two specified events will
cause a Stop-Mode Recovery.
*Default Setting After Reset
Figure 42. Stop-Mode Recovery Register 2
((0F) DH: D2-D4, D6 Write Only)
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction and refreshed on
subsequent executions of the WDT instruction. The WDT
circuit is driven by an on-board RC oscillator or external
oscillator from the XTAL1 pin. The WDT instruction affects
the Zero (Z), Sign (S), and Overflow (V) flags.
This register is accessible only during the first 64 processor cycles (128 XTAL clocks) from the execution of the first
instruction after Power-On-Reset, Watch-Dog Reset, or a
Stop-Mode Recovery (Figure 40). After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read and is located in
Bank F of the Expanded Register Group at address location 0FH. It is organized as follows:
The POR clock source is selected with bit 4 of the WDT
register. Bit 0 and 1 control a tap circuit that determines the
time-out period. Bit 2 determines whether the WDT is active during HALT and Bit 3 determines WDT activity during
STOP. Bits 5 through 7 are reserved (Figure 48).
1-52
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
WDTMR (0F) FH
1
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00
01 *
10
11
INT RC OSC External Clock
5 ms
256 TpC
10 ms
512 TpC
20 ms
1024 TpC
80 ms
4096 TpC
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
* Default Setting After Reset
Figure 43. Watch-Dog Timer Mode Register
(Write Only)
WDT Time Select (D0, D1). Selects the WDT time period.
It is configured as shown in Table 13.
Table 9. WDT Time Select
D1
D0
0
0
1
1
0
1
0
1
Time-Out of
Internal RC Time-Out of
OSC
XTAL Clock
5 ms min
10 ms mi
20 ms mi
80 ms mi
256 TpC
512 TpC
1024 TpC
4096 TpC
WDTMR During STOP (D3). This bit determines whether
or not the WDT is active during STOP mode. Since the
XTAL clock is stopped during STOP mode, the on-board
RC has to be selected as the clock source to the
WDT/POR counter. A 1 indicates active during STOP. The
default is 1.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configuration of this bit is 0, which selects the RC oscillator.
Notes:
TpC = XTAL clock cycle
The default on reset is 10 ms
WDTMR During HALT (D2). This bit determines whether
or not the WDT is active during HALT mode. A 1 indicates
active during HALT. The default is 1.
DS96LVO1100
PRELIMINARY
1-53
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
/RESET
5 Clock
Filter
* /CLR 2
CLK
18 Clock RESET
Generator
RESET
Internal
RESET
Active
High
WDT TAP SELECT
CK Source
Select
(WDTMR)
XTAL
INTERNAL
RC
OSC.
VDD
VBO/VLV
2V REF.
+
-
M
U
X
POR
3
4
WDT1 2
CLK
WDT/POR Counter Chain
*CLR1
Low Operating
Voltage Det.
VCC
WDT
From Stop
Mode
Recovery
Source
12 ns Glitch Filter
Stop Delay
Select (SMR)
* /CLR1 and /CLR2 enable the WDT/POR and
18 Clock Reset timers upon a Low to High input translation.
Figure 44. Resets and WDT
1-54
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Low Voltage Protection. An on-board Voltage Comparator checks that VCC is at the required level to ensure correct operation of the device. Reset is globally driven if VCC
is below VLV (Low Voltage). The minimum operating voltage varies with the temperature and operating frequency,
while VLV varies with temperature only.
Software Selectable Options. There are four Software
Selectable Options to choose from which corresponds to
the ROM based parts mask options. Register (F0) EH OTP
byte is where these options are controlled; these options
are:
Bit Name
Reg(0F)EH
Port 0 Pull-ups (lower nibble)
Port 0 Pull-ups (upper nibble)
Port 2 Pull-ups
Mouse/Normal
On/Off
On/Off
On/Off
M/N
Note: The RC oscillator Xtal1/2 option is invoked during
OTP programming as a user-selectable item.
The Low Voltage trip voltage (VLV) is less than 3.0V under
the following conditions:
Maximum (VLV) Conditions:
TA = 0°C, +70°C Internal clock frequency equal to or less
than 8.0 MHz
Note: The internal clock frequency is one-half the external
clock frequency.
The device functions normally above 3.0V under all conditions. The minimum functionality point below 3V is to be
defined. The VLV is a function of temperature and process
parameters.
VLV
VLV
T
B
D
0
15
35
25
Temperature
45
55
Figure 45. Typical Z86E7X Low Voltage
vs Temperature at 8 MHz
DS96LVO1100
PRELIMINARY
1-55
1
Z86E72/E73
OTP IR Microcontrollers
EPROM PROGRAMMING
Table 10. Programming and Testmode
Device Pins
User/Test Mode
Device Pin #
User Modes
P33
VPP
P32
EPM
Pref1
/CE
P31
/OE
P20
/PGM
VCC
Port 1
CNFG
DATA
Test
ADDR
A0-A3
Addr
EPROM Read
VCC
VH
VIL
VIL
VIH
Addr
3.0V
Out
XX
Program
VPP
VCC
VIL
VIH
VIL
Addr
6.0V
In
XX
Program Verify
VPP
VCC
VIL
VIL
VIH
Addr
6.0V
Out
XX
RC Option
VPP
VCC
VH
VIH
VIL
XX
6.0V
XX
XX
Margin Read
VVA
VH
VIL
VH
VIH
Addr
6.0V
Out
00
1
Shadow Row Rd
VCC
VH
VIL
VIL
VIH
COL
3.0V
Out
01
1
Shadow Row Prg
VPP
VH
VIL
VIH
VIL
COL
6.0V
In
01
1
Shadow Row Ver
VPP
VH
VIL
VIL
VIH
COL
6.0V
Out
01
1
Shadow Col Rd
VCC
VH
VIL
VIL
VIH
ROW
3.0V
Out
02
1
Shadow Col Prg
VPP
VH
VIL
VIH
VIL
ROW
6.0V
In
03
1
Shadow Col Ver
VPP
VH
VIL
VIL
VIH
ROW
6.0V
Out
02
1
Page Prg 2 Byte
VPP
VH
VIL
VIH
VIL
TBD
6.0V
In
04
1
Page Prg 4 Byte
VPP
VH
VIL
VIH
VIL
TBD
6.0V
In
05
1
Page Prg 8 Byte
VPP
VH
VIL
VIH
VIL
TBD
6.0V
In
06
1
Page Prg 16 Byte
VPP
VH
VIL
VIH
VIL
TBD
6.0V
In
07
1
Note
Notes:
1. All test modes are entered by first setting up the corresponding test
address and then latching the address by bringing the /OE to VH and then
to VIL, except for the margin read which requires /OE to be kept at VH.
VVA = Variable from VCC to VPP
VPP = 12.5V ± 0.5V
VH = 12.5V ± 0. 5V
VIH = 3V
VIL = 0V
XX = Irrelevant
IPP during programming = 40 mA maximum
ICC during programming, verify, or read = 40 mA maximum.
1-56
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Table 11. Timing of Programming Waveform
Parameters
Name
Min
Max
Units
1
2
3
Address Setup Time
Data Setup Time
VPP Setup Time
2
2
2
µs
µs
µs
4
VCC Setup Time
2
µs
5
6
7
8
9
10
11
12
13
14
15
Chip Enable Setup Time
Program Pulse Width
Data Hold Time
/OE Setup Time
Data Access Time
Data Output Float Time
Overprogram Pulse Width
EPM Setup Time
/PGM Setup Time
Address to /OE Setup Time
Option Program Pulse Width
2
0.95
2
2
µs
µs
µs
µs
ns
ns
ms
µs
µs
µs
ms
DS96LVO1100
200
100
2.85
2
2
2
78
PRELIMINARY
1
1-57
Z86E72/E73
OTP IR Microcontrollers
EPROM PROGRAMMING (Continued)
VIH
Address
Address Stable
VIL
0 Min
VIH
Data
VIL
Address Stable
Invalid
Valid
Invalid
Valid
9
VH
VPP
VIL
VH
EPM
VIL
5.5V
12
VCC
4.5V
VIH
/CE
VIL
0 Min
VIH
/OE
VIL
VIH
/PGM
VIL
3
Figure 46. EPROM Read
1-58
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
VIH
Address
1
VIH
Data
1
Address Stable
VIL
Data Stable
VIL
Data Out Valid
2
9
10
VH
VPP
VIH
3
VH
EPM
VIL
6V
VCC
4.5V
VIH
4
7
/CE
VIL
5
VIH
/OE
VIL
VIH
/PGM
VIL
6
8
11
Program Cycle
Verify Cycle
Figure 47. EPROM Program and Verify
DS96LVO1100
PRELIMINARY
1-59
Z86E72/E73
OTP IR Microcontrollers
EPROM PROGRAMMING (Continued)
VIH
Address
VIL
VIH
Data
VIL
VH
VPP
VIH
3
6V
VCC
4.5V
4
VH
/CE
VIH
5
/OE
VIH
VIL
VIL
VH
EPM
VIH
VIL
VIH
VIL
12
12
12
VIH
/PGM
VIL
15
15
15
EPROM Protect
RC Oscillator
RAM Protect
Figure 48. Programming EPROM, RAM Protect and 16K Size Selection
1-60
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Start
1
Addr =
First Location
Vcc = 6.0V
Vpp = 12.5V
N=0
Program
1 ms Pulse
Increment N
Yes
N = 25 ?
No
Fail
Verify
One Byte
Verify Byte
Fail
Pass
Pass
Prog. One Pulse
3xN ms Duration
Increment
Address
No
Last Addr ?
Yes
*
Vcc = Vpp = 4.5V
Note: * To ensure proper operations during the spec.,
Zilog recommends verification over the V cc
range of the device V cc spec.
Fail
Verify All
Bytes
Pass
Vcc = Vpp = 5.5V
Verify All
Bytes
Pass
*
Device Failed
Fail
Device Passed
Figure 49. Programming Flowchart
DS96LVO1100
PRELIMINARY
1-61
Z86E72/E73
OTP IR Microcontrollers
EXPANDED REGISTER FILE CONTROL REGISTERS (0D)
CTR0 (0D) 0H
D7 D6 D5 D4 D3 D2 D1 D0
0 P34 as Port Output*
1 Timer8 Output
0 Disable T8 Time Out Interrupt
1 Enable T8 Time Out Interrupt
0 Disable T8 Data Capture Interrupt
1 Enable T8 Data Capture Interrupt
00
01
10
11
R
R
W
W
SCLK on T8
SCLK/2 on T8
SCLK/4 on T8
SCLK/8 on T8
0 No T8 Counter Time Out
1 T8 Counter Time Out Occured
0 No Effect
1 Reset Flag to 0
0 Modulo-N
1 Single Pass
* Default Setting After Reset
R
R
W
W
0
1
0
1
T8 Disabled *
T8 Enabled
Stop T8
Enable T8
Figure 50. TC8 Control Register
((0D) 0H: Read/Write Except Where Noted)
1-62
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
CTR1 (0D) 1H
D7
D6
D5
D4
D3
D2
D1
1
D0
Transmit Mode
R/W 0 T16_OUT is 0 Initially
1 T16_OUT is 1 Initially
Demodulation Mode
R
0 No Falling Edge Detection
R
1 Falling Edge Detection
W
W
0 No Effect
1 Reset Flag to 0
Transmit Mode
R/W 0 T8_OUT is 0 Initially
1 T8_OUT is 1 Initially
Demodulation Mode
0 No Rising Edge Detection
R
1 Rising Edge Detection
R
0 No Effect
W
1 Reset Flag to 0
W
Transmit Mode
0 0 Normal Operation
0 1 Ping-Pong Mode
1 0 T16_OUT = 0
1 1 T16_OUT = 1
Demodulation Mode
0 0 No Filter
0 1 4 SCLK Cycle Filter
1 0 8 SCLK Cycle Filter
1 1 16 SCLK Cycle Filter
Transmit Mode/T8/T16 Logic
0 0 AND
0 1 OR
1 0 NOR
1 1 NAND
Demodulation Mode
0 0 Falling Edge Detection
0 1 Rising Edge Detection
1 0 Both Edge Detection
1 1 Reserved
Transmit Mode
0 P36 as Port Output*
1 P36 as T8/T16_OUT
Demodulation Mode
0 P31 as Demodulator Input
1 P20 as Demodulator Input
Transmit/Demodulation Modes
0 Transmit Mode*
1 Demodulation Mode
Note: Care must be taken in differentiating
Transmit Mode from Demodulation Mode.
Depending on which of these two modes is
operating, the CTR1 bit will have different
functions.
*Note: Changing from one mode to
another cannot be done without
disabling the counter/timers.
Figure 51. T8 and T16 Common Control Functions
((0D) 1H: Read/Write)
DS96LVO1100
PRELIMINARY
1-63
Z86E72/E73
OTP IR Microcontrollers
EXPANDED REGISTER FILE CONTROL REGISTERS (0D) (Continued)
CTR2 (0D) 02H
D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
P35 is Port Output*
P35 is TC16 Output
Disable T16 Time-Out Interrupt
Enable T16 Time-Out Interrupt
0 Disable T16 Data Capture Interrupt
1 Enable T16 Data Capture Interrupt
00
01
10
11
R
R
W
W
SCLK on T16
SCLK/2 on T16
SCLK/4 on T16
SCLK/8 on T16
0
1
0
1
No T16 Time Out
T16 Time Out Occurs
No Effect
Reset Flag to 0
Transmit Mode
0 Modulo-N for T16
1 Single Pass for T16
Demodulator Mode
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
* Default Setting After Reset
R
R
W
W
0
1
0
1
T16 Disabled *
T16 Enabled
Stop T16
Enable T16
Figure 52. T16 Control Register
((0D) 2H: Read/Write Except Where Noted)
1-64
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
EXPANDED REGISTER FILE CONTROL REGISTERS (0F)
1
SMR (0F) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF **
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
0 11 P32
100 P33
101 P27
11 0 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Stop Recovery Level
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery**
* Default Setting After Reset
** Default Setting After Reset and Stop-Mode Recovery
Figure 53. Stop-Mode Recovery Register
((F) 0BH: D6-D0 = Write Only, D7 = Read Only)
DS96LVO1100
PRELIMINARY
1-65
Z86E72/E73
OTP IR Microcontrollers
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR only*
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved
(Must be 0)
Recovery Level
0 Low*
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR,
either of the two specified events will
cause a Stop-Mode Recovery.
*Default Setting After Reset
Figure 54. Stop-Mode Recovery Register 2
((0F) DH: D2-D4, D6 Write Only)
OPT (0F) EH
D7 D6 D5 D4 D3 D2 D1 D0
Port 0 (0-3) Pull-up
1 pull-up active
0 pull-up inactive
Port 0 (7-4) Pull-up
1 pull-up active
2 pull-up inactive
Port 2 pull-up option
1 pull-up active
0 pull-up inactive
Reserved (Must be 0.)
Mask option for
mouse trackball interface
P00-P03
1 For mouse trackball interface
0 Normal
Reserved (Must be 0)
Figure 55. Option Bit Register
1-66
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
EXPANDED REGISTER FILE CONTROL REGISTERS (0F) (Continued)
WDTMR (0F) FH
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00
01 *
10
11
INT RC OSC External Clock
5 ms
256 TpC
10 ms
512 TpC
20 ms
1024 TpC
80 ms
4096 TpC
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
* Default Setting After Reset
Figure 56. Watch-Dog Timer Mode Register
((F) 0FH: Write Only)
PCON (0F) 0H
D7 D6 D5
R246 P2M
D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Reserved (Must be 1)
P27-P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
*Default Setting After Reset
* Default Setting After Reset
P37 comparator output only on E72
Figure 57. Port Configuration Register (PCON)
((0F) 0H: Write Only)
1-67
PRELIMINARY
Figure 58. Port 2 Mode Register
(F6H: Write Only)
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
Z8® STANDARD CONTROL REGISTER DIAGRAMS
R247 P3M
D7 D6 D5 D4 D3 D2 D1 D0
0 Port 2 Open Drain*
1 Port 2 Push-pull
0 = P31, P32 Digital Mode
1 = P31, P32 Analog Mode
0 P32 = Input
P35 = Output *
1 P32 = /DAV0/RDY0
P35 = RDY0//DAV0
00
01
10
11
P33 = Input
P34 = Output *
P33 = Input
P34 = /DM
P33 = /DAV1/RDY1
P34 = RDY1//DAV1
0 P31 = Input (TIN)
P36 = Output (TOUT)
1 P31 = /DAV2/RDY2
P36 = RDY2//DAV2
0
1
* Default Setting After Reset
P30 = Input
P37 = Output
P30 = Serial In
P37 = Serial Out
0 Parity Off
1 Parity On
Figure 59. Port 3 Mode Register
(F7H: Write Only)
1-68
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
1
P00-P03 Mode
00 Output
01 Input*
1X A11-A8
Stack Selection
0 External
1 Internal*
P17-P10 Mode
00 Byte Output
01 Reserved
10 AD7-AD0
11 High-Impedance AD7AD0,
/AS, /DS, /R//W, A11-A8,
A15-A12, If Selected
External Memory Timing
0 Normal*
1 Extended
* Default Setting After Reset.
P07-P04 Mode
00 Output
01 Input*
1X A15-A12
Figure 60. Port 0 and 1 Mode Register
(F8H: Write Only)
DS96LVO1100
PRELIMINARY
1-69
Z86E72/E73
OTP IR Microcontrollers
Z8® STANDARD CONTROL REGISTER DIAGRAMS (Continued)
R249 IPR
R251 IMR
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Reserved (Must be 0)
1 Enables IRQ4-IRQ0
(D0 = IRQ0)
Reserved (Must be 0)
Reserved (Must be 0)
0 Master Interrupt Disable*
1 Master Interrupt Enable
* Default Setting After Reset
Figure 63. Interrupt Mask Register
((0) FBH: Read/Write)
R252 Flags
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
Figure 61. Interrupt Priority Registers
((0) F9H: Write Only)
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Tag
R250 IRQ
D7 D6
D5
D4
D3
D2
D1
Sign Flag
D0
Zero Flag
Carry Flag
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = T16
IRQ4 = T8
Figure 64. Flag Register
((0) FCH: Read/Write
Reserved (Must be 0)
Default Setting After Reset = 0000 0000
Inter Edge
P31 ↓ P32 ↓ = 00
P31 ↓ P32 ↑ = 01
P31 ↑ P32 ↓ = 10
P31 ↑↓ P32 ↑↓ = 11
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register (Bank)
Pointer
Figure 62. Interrupt Request Register
((0) FAH: Read/Write)
Default Setting After
Reset = 0000
Working Register
Pointer
Figure 65. Register Pointer
((0) FDH: Read/Write)
1-70
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
R254 SPH
R255 SPL
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Upper
Byte (SP15-SP8)
Figure 66. Stack Pointer High
((0) FEH: Read/Write)
DS96LVO1100
1
Stack Pointer Lower
Byte (SP7-SP0)
Figure 67. Stack Pointer Low
((0) FFH: Read/Write)
PRELIMINARY
1-71
Z86E72/E73
OTP IR Microcontrollers
PACKAGE INFORMATION
Figure 68. 40-Pin DIP Package Diagram
1-72
PRELIMINARY
DS96LVO1100
Z86E72/E73
OTP IR Microcontrollers
1
Figure 69. 44-Pin QFP Package Diagram
Figure 70. 44-Pin PLCC Package Diagram
DS96LVO1100
PRELIMINARY
1-73
Z86E72/E73
OTP IR Microcontrollers
ORDERING INFORMATION
40-Pin DIP
Z86E72/E73
16 MHz
44-Pin PLCC
44-Pin QFP
Z86E7216PSC
Z86E7316PSC
Z86E7216VSC
Z86E7316VSC
Z86E7216FSC
Z86E7316FSC
For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
Package
P = Plastic DIP
F = Plastic Quad Flat Pack
V = Plastic Chip Carrier
Temperature
S = 0°C to +70°C
Speed
16 = 16 MHz
Environmental
C = Plastic Standard
Example:
Z 86E73 16 P S C
is an Z86E73, 16 MHz, DIP, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
1-74
PRELIMINARY
DS96LVO1100