ETC Z86E8316SSC

PRELIMINARY PRODUCT SPECIFICATION
1
Z86C83/C84/E83
1
CMOS Z8® MCU
FEATURES
Device
ROM
(KB)
RAM*
(Bytes)
I/O
Lines
Voltage
Range
Z86C83
Z86E83
Z86C84
4
4 (OTP)
4
237
237
237
21
21
17
3.0V to 5.5V
3.5V to 5.5V
3.0V to 5.5V
■
Six Vectored, Prioritized Interrupts from Six Different
Sources
■
Two Analog Comparator Inputs with Programmable
Interrupt Polarity
■
Two Programmable 8-Bit Timers, each with a 6-Bit
Programmable Prescaler
Note: * General-Purpose
■
28-Pin DIP, SOIC, and PLCC Packages
■
Power-On Reset (POR) Timer
■
Clock Speed: 16 MHz
■
Permanent Watch-Dog Timer (WDT) Option
■
Three Expanded Register Groups
■
Software-Programmable Pull-Up Resistors (Port 2 Only)
■
8-Channel, 8-Bit A/D Converter with Track and Hold,
and Unique R-Ladder AGND Offset Control
■
On-Chip Oscillator for Crystal, Resonator or LC
■
ROM Protect
■
Z86C84 has two 8-Bit D/A Converters
Programmable Gain Stages, 3 µs Settling Time
with
GENERAL DESCRIPTION
The Z86C83/C84/E83 are full-featured members of the
Z8® MCU family offering a unique register-to-register architecture that avoids accumulator bottlenecks for higher
code efficiency than RISC processors.
The Z86C83/C84/E83 are designed to be used in a wide
variety of embedded control applications, such as appliances, process controls, keyboards, security systems, battery chargers, and automotive modules.
For applications requiring powerful I/O capabilities, the
Z86C83/C84/E83 devices can have up to 21/17 (83/84 respectively) pins dedicated to input and output. These lines
are grouped into three ports, and are configured by software to provide digital/analog I/O timing and status signals.
An on-chip, half-flash 8-bit ±1/2 Least Significant Bit (LSB)
A/D converter can multiplex up to eight analog inputs. Unused analog inputs revert to standard digital I/O use.
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Unique, programmable AGND offset control of the A/D resistor ladder compresses the converter's dynamic range
for maximum effective 9-bit A/D resolution.
The Z86C84 has two 8-bit ±1/2 LSB D/A converters. High
and low reference voltages provide precise control of the
output voltage range. Programmable gain for each D/A
converter provides a maximum effective 10-bit resolution
for many tasks.
On-chip 8-bit counter/timers with many user-selectable
modes simplify real-time tasks, such as counting, timing,
and generation of PWM signals.
The designer can prioritize six different maskable, vectored, internal or external interrupts for efficient interrupt
handling and multitasking functions.
PRELIMINARY
8-1
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
GENERAL DESCRIPTION (Continued)
By means of an expanded register file, the designer has
access to additional control registers for configuring peripheral functions including the A/D and D/A converters,
counter/timers, and I/O port functions (Figure 1).
Power connections follow conventional descriptions below:
Connection
Notes: All signals with a preceding front slash, "/", are
active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).
Device
Power
VCC
VCC
Ground
GND
VSS
Register File
Comparators
(2)
P00
P01
P02
P03†
Circuit
P31
P32
P33
Port 3
Port 0
Register Bus
P04†
P05†
P06†
VDHI **
VDL0 **
DAC1 **
DAC2 **
AC0/P20
AC1/P21
AC2/P22
AC3/P23
AC4/P24
AC5/P25
AC6/P26
AC7/P27
AVCC
AGND
P34
P35
P36
Internal
Address Bus
**Dual
8-Bit
DAC
Program
Memory
4K x 8
Z8 Core
Internal Data Bus
Expanded
Register File
Port 2
Expanded
Register Bus
Machine
Timing
and
Instruction
Control
Power
8-Channel
8-Bit A/D
Counter/Timer
8-Bit (2)
XTAL 1/2
/RESET
VCC
GND
Notes:
** Not available on Z86C83/E83
† Not available on Z86C84
Figure 1. Z86C83/C84/E83 Functional Block Diagram
8-2
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
PIN DESCRIPTION
1
P21/AC1
P22/AC2
P23/AC3
P24/AC4
P25/AC5
P26/AC6
P27/AC7
/RESET
XTAL1
XTAL2
GND
VCC
P31
P32
1
28
Z86C83/
Z86E83
DIP/ SOIC
28 - Pin
14
15
P20/AC0
AVCC
AGND
P06
P05
P04
P03
P02
P01
P00
P35
P36
P34
P33
Figure 2. Z86C83 and Standard Mode Z86E83 28-Pin DIP
and SOIC Pin Configuration*
Table 1. Z86C83 and Standard Mode Z86E83 28-Pin DIP, SOIC, PLCC Pin Identification*
No
Symbol
Function
Direction
1-7
Port 2, Bit 1-7
Analog In 1-7
Reset
Oscillator Clock
Oscillator Clock
Ground
Power
Input/Output
8
9
10
11
12
P21-P27
or AC1-AC7
/RESET
XTAL1
XTAL2
GND
VCC
13-15
16
17
18
19-25
26
P31-P33
P34
P36
P35
P00-P06
AGND
Port 3, Bits 1-3
Port 3, Bit 4
Port 3, Bit 6
Port 3, Bit 5
Port 0, Bits 0-6
Analog Ground
Input
Output
Output
Output
Input/Output
27
AVCC
Analog Power
28
P20
or AC0
Port 2, Bit 0
Analog In 0
Input
Input
Output
Input/Output
Note: * DIP and SOIC Pin Description and Configuration are identical.
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PRELIMINARY
8-3
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
PIN DESCRIPTION (Continued)
P21/AC1
P22/AC2
P23/AC3
P24/AC4
P25/AC5
P26/AC6
P27/AC7
/RESET
XTAL1
XTAL2
GND
VCC
P31
P32
1
28
Z86C84
DIP/SOIC
28 - Pin
14
15
P20/AC0
AVCC
AGND
DAC1
DAC2
VDHI
VDLO
P02
P01
P00
P35
P36
P34
P33
Figure 3. Z86C84 28-Pin DIP and SOIC Pin Configuration
Table 2. Z86C84 28-Pin DIP, SOIC, PLCC Pin Identification*
No
Symbol
Function
Direction
1-7
Port 2, Bit 1-7
Analog In 1-7
Reset
Oscillator Clock
Oscillator Clock
Ground
Power
Input/Output
8
9
10
11
12
P21-P27
or AC1-AC7
/RESET
XTAL1
XTAL2
GND
VCC
13-15
16
17
18
19-21
22
23
24-25
26
P31-P33
P34
P36
P35
P00-P02
VDLO
VDHI
DAC2-1
AGND
Port 3, Bits 1-3
Port 3, Bit 4
Port 3, Bit 6
Port 3, Bit 5
Port 0, Bits 0-3
D/A Ref. Volt.,Low
D/A Ref. Volt.,High
D/A Converter
Analog Ground
Input
Output
Output
Output
Input/Output
Input
Input
Output
27
AVCC
Analog Power
28
P20
or AC0
Port 2, Bit 0
Analog In 0
Input
Input
Output
Input/Output
Note: * DIP, PLCC and SOIC Pin Description and Configuration are identical
8-4
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
D1
D2
D3
D4
D5
D6
D7
NC
/CE
NC
GND
VCC
/OE
EPM
1
28
Z86E83
(EPROM Mode)
DIP/SOIC
28 - Pin
14
15
D0
NC
NC
NC
NC
NC
NC
/PGM
CLK
CLR
NC
NC
NC
VPP
1
Figure 4. Z86E83 EPROM Programing Mode 28-Pin DIP and SOIC Pin Configuration
Table 3. Z86E83 EPROM Programming Mode 28-Pin DIP, PLCC and SOIC Pin Identification
No
Symbol
Function
Direction
1-7
8
9
10
11
12
D1-D7
NC
/CE
NC
GND
VCC
Data 1,2,3,4,5,6,7
No Connection
Chip Enable
No Connection
Ground
Power
Input/Output
13
14
15
/OE
EPM
VPP
Output Enable
EPROM Program Mode
Program Voltage
16-18
19
20
21
22-27
28
NC
CLR
CLK
/PGM
NC
D0
No Connection
Clear CLock
Address
Program Mode
No Connection
Data 0
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PRELIMINARY
Input
Input
Input
Input
Input
Input
Input
Input/Output
8-5
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
4
P25/AC5
XXX
P26/AC6
XXX
P27/AC7
XXX
/RESET
XXX
XTAL1
XXX
XTAL2
XXX
GND
XXX
1
5
26
25
Z86C83/E83
PLCC 28 - Pin
11
12
19
18
P06
XXX
XXX
P05
XXX
P04
XXX
P03
XXX
P02
XXX
P01
XXX
P00
Figure 5. Z86C83 and Standard Mode Z86E83 28-Pin PLCC Pin Configuration
4
P25/AC5
XXX
P26/AC6
XXX
P27/AC7
XXX
/RESET
XXX
XTAL1
XXX
XTAL2
XXX
GND
XXX
1
5
26
25
Z86C84
PLCC 28 - Pin
11
12
19
18
DAC1
XXX
XXX
DAC2
XXX
VDHI
XXX
VDLO
XXX
P02
XXX
P01
XXX
P00
Figure 6. Z86C84 28-Pin PLCC Pin Configuration
8-6
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
1
4
XXX
D5
XXX
D6
XXX
D7
XXX
NC
XXX
/CE
XXX
NC
GND
XXX
1
5
26
25
Z86E83
PLCC 28 - Pin
11
12
19
18
NC
XXX
XXX
NC
XXX
NC
XXX
NC
XXX
/PGM
XXX
CLK
XXX
CLR
Figure 7. Z86E83 EPROM Programming Mode 28-Pin
PLCC Pin Configuration
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PRELIMINARY
8-7
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
ABSOLUTE MAXIMUM RATING
Parameter
Min
Max
Units
Notes
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to VSS
–40
–65
–0.6
+105
+150
+7
C
C
V
1
Voltage on VCC Pin with Respect to VSS
–0.3
+7
V
Voltage on /RESET Pin with Respect to VSS
–0.6
VCC+1
V
2
Voltage on P32, P33 and /Reset Pin with Respect to VSS
-0.6
VCC+1
V
2,5
Total Power Dissipation
Maximum Current out of VSS
770
140
mW
mA
Maximum Current into VCC
125
mA
+600
+600
25
25
µA
µA
mA
mA
Maximum Current into an Input Pin
Maximum Current into an Open-Drain Pin
Maximum Output Current Sinked by Any I/O Pin
Maximum Output Current Sourced by Any I/O Pin
–600
–600
3
4
Notes:
1. This applies to all pins except /RESET pin and where otherwise noted.
2. There is no input protection diode from pin to VCC.
3. This excludes XTAL pins.
4. Device pin is not at an output Low state.
5. For Z86E83 only
Notice:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at any condition
above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating
conditions for an extended period may affect device reliability.
Total power dissipation should not exceed 770 mW for the package.
Power dissipation is calculated as follows:
Total Power Dissipation =
VCC x [ICC – (sum of IOH)]
+ sum of [(VCC – VOH) x IOH]
+ sum of (V0L x I0L)
8-8
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Figure 8).
From Output
Under Test
1
I
150 pF
Figure 8. Test Load Diagram
VDD SPECIFICATION
VDD = 3.5V to 5.5V (Z86E83 only at 0° C to 70° C)
VDD = 3.0V to 5.5V (Z86C83/C84)
VDD = 4.5V to 5.5V (Z86E83 only at -40° C to 105° C)
CAPACITANCE
TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Input capacitance
Output capacitance
I/O capacitance
Min
Max
0
0
0
15 pF
15 pF
15 pF
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PRELIMINARY
8-9
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
DC ELECTRICAL CHARACTERISTICS
For Z86C83/C84 Only
Sym
Parameter
V
Clock Input High
Voltage
CH
V
CL
Clock Input Low
Voltage
TA = 0° C
to +70°C
Min
Max
VCC
Note 3
3.0V
0.7 V
5.5V
0.7 V
CC
CC
V
+0.3 0.7 V
V
+0.3 0.7 V
CC
CC
3.0V GND-0.3 0.2 V
5.5V GND-0.3 0.2 V
V
IH
Input High
Voltage
3.0V
0.7 V
5.5V
0.7 V
CC
CC
V
TA = –40°C
to +105°C
Min
Max
CC
CC
CC
+0.3
1.3
V
V
+0.3
2.5
V
0.7
V
1.5
V
CC
CC
GND-0.3 0.2 V
+0.3 0.7 V
V
+0.3 0.7 V
CC
CC
CC
CC
Input Low Voltage 3.0V GND-0.3 0.2 V
V
GND-0.3 0.2 V
V
IL
CC
OH1
Output High
Voltage
3.0V
V
1.3
V
V
+0.3
2.5
V
0.7
V
1.5
V
3.1
V
IOH = -2.0 mA
8
4.8
V
IOH = -2.0 mA
8
CC
CC
GND-0.3 0.2 V
-0.4
V
V
OL1
V
OL2
V
RH
Output Low
Voltage
Output Low
Voltage
Reset Input High
Voltage
Rl
Reset Input Low
Voltage
-0.4
CC
-0.4
V
-0.4
CC
3.0V
0.6
0.6
0.2
V
IOL = +4.0 mA
8
5.5V
0.4
0.4
0.1
V
IOL = +4.0 mA
8
3.0V
1.2
1.2
0.3
V
IOL = +6 mA
8
1.2
0.3
V
IOL = +10 mA
8
V
1.5
V
2.1
V
1.1
V
1.7
V
10
10
5.5V
3.0V
1.2
.8 V
V
.8 V
CC
5.5V
.8 V
CC
V
CC
V
CC
V
CC
CC
.8 V
CC
3.0V GND-0.3 0.2 V
CC
V
CC
CC
GND-0.3 0.2 V
CC
5.5V GND-0.3 0.2 V
CC
GND-0.3 0.2 V
CC
V
OFFSET
I
IL
I
Comparator Input 3.0V
Offset Voltage
5.5V
Input Leakage
3.0V
Output Leakage
OL
I
IR
I
CC
Reset Input
Current
Supply Current
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
+0.3
GND-0.3 0.2 V
CC
5.5V
CC
CC
CC
V
CC
Notes
V
CC
5.5V GND-0.3 0.2 V
Typical
[13]
@ 25°C Units Conditions
-1
25
25
1
5.5V
-1
3.0V
5.5V
CC
-1
25
25
2
10
10
<1
mV
mV
µA VIN = 0V, VCC
1
-1
2
<1
µA VIN = 0V, VCC
-1
1
-1
2
<1
µA VIN = 0V, VCC
-1
1
-1
2
<1
µA VIN = 0V, VCC
-130
-180
20
25
7
10
-25
-40
7
20
3
5
µA
µA
mA
mA
mA
mA
3.0V
5.5V
3.0V
5.5V
5.0V
5.5V
8-10
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-130
-180
20
25
7
10
PRELIMINARY
@ 16 MHz
@ 16 MHz
@ 3.58 MHz
@ 8 MHz
1,4
1,4
1,4,15
1,4,15
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
Sym
Parameter
I
Standby Current
(HALT Mode)
CC1
ICC2
Standby Current
(STOP Mode)
VICR
IALL
IALH
TA = –40°C
to +105°C
Min
Max
3.0V
4.5
4.5
2.0
5.5V
8
8
3.7
3.0V
3.4
3.4
1.5
5.5V
7.0
7.0
2.9
3.0V
8
15
1
5.5V
10
20
2
3.0V
500
600
310
5.5V
800
1000
600
Input Common
Mode
3.0
0
Voltage Range
5.5
0
Auto Latch Low
Current
3.0V
CC
1.0V
V CC
1.0V
8
5.5V
Auto Latch High
Current
VLV
TA = 0° C
to +70°C
Min
Max
VCC
Note 3
CC
1.5V
V CC
1.5V
10
15
3.0V
5.5V
VCC Low-Voltage
Protection Voltage
2.0
V
0
V
mA VIN = 0V, VCC @ 16
MHz
mA VIN = 0V, VCC @
16 MHz
mA Clock Divide-by-16
@ 16 MHz
mA Clock Divide-by-16
@ 16 MHz
µA VIN = 0V,VCC
Vcc WDT is not
Running
µA VIN = 0V, VCC
WDT is not
Running
µA VIN = 0V, VCC
WDT is Running
µA VIN = 0V, VCC
WDT is not
Running
V
Notes
4
4
4
4
1,6,11
1,6,11
1,6,11,14
1,6,11,14
10
V
10
5
µA 0V < VIN < VCC
9
20
11
µA 0V < VIN < VCC
9
-5
-7
-3
µA 0V < VIN < VCC
9
-8
-10
-6
µA 0V < VIN < VCC
9
3.5
3.0
V
7
3.3
0
Typical
[13]
@ 25°C Units Conditions
2.2
2 MHz max Int.
CLK Freq.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Combined digital VCC and Analog AVCC supply currents.
GND = 0V.
VCC voltage specification of 3.0V guarantees 3.3V ±0.3V, and VCC voltage specification of 5.5V guarantees 5.0V ±0.5V.
All outputs unloaded, I/O pins floating, inputs at rail.
CL1 = CL2 = 22 pF.
Same as note [4] except inputs at VCC.
The VLV increases as the temperature decreases.
Standard Mode (not Low EMI).
Auto Latch (mask option) selected.
For analog comparator, inputs when analog comparators are enabled.
Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
Excludes clock pins.
Typicals are at VCC = 5.0V and 3.3V.
Internal RC selected
For Z86C83 only
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PRELIMINARY
8-11
1
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
AC ELECTRICAL CHARACTERISTICS
For Z86C83/C84 Only. Low EMI Mode Only.
No
Symbol
Parameter
1
TpC
Input Clock Period
2
TrC, TfC
Clock Input Rise & Fall Times
3
TwC
Input Clock Width
4
TwTinL
Timer Input Low Width
5
TwTinH
Timer Input High Width
6
TpTin
Timer Input Period
7
TrTin,
TfTin
Timer Input Rise & Fall Timer
8A
TwIL
Int. Request Low Time
8B
TwIL
Int. Request Low Time
9
TwIH
Int. Request Input High Time
10
Twsm
Stop-Mode Recovery Width
Spec
11
Tost
Oscillator Start-up Time
TA = 0°C to +70°C
TA = -40° to +105°C
4 MHz
4 MHz
VCC [6]
Min
Max
Min
Max
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
250
250
DC
DC
25
25
250
250
DC
DC
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
125
125
100
100
3TpC
3TpC
4TpC
4TpC
125
125
100
100
3TpC
3TpC
4TpC
4TpC
100
100
100
70
3TpC
3TpC
3TpC
3TpC
12
12
100
70
3TpC
3TpC
3TpC
3TpC
12
12
5TpC
5TpC
5TpC
5TpC
Units Notes
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,3,7,8
1,3,7,8
1,2,7,8
1,2,7,8
4,8
4,8
4,8,9
4,8,9
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request via Port 3 (P33-P31)
3. Interrupt request via Port 3 (P30)
4. SMR-D5 = 1, POR STOP Mode delay is on.
5. Reg. WDTMR
6. The VCC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V ± 0.5V.
7. SMR D1 = 0
8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode
9. For LC oscillator and for oscillator driven by clock driver
8-12
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
For Z86E83 Only
Sym Parameter
VCH
VCL
VIH
VIL
Clock Input High
Voltage
Clock Input Low
Voltage
Input High Voltage
Input Low Voltage
VOH1 Ouput High Voltage
VOL1 Output Low Voltage
VOL2 Output Low Voltage
VRH
Reset Input High
Voltage
VOFFS Comparator Input
Offset Voltage
ET
IIL
IOL
IIR
ICC
ICC1
Input Leakage
Output Leakage
Reset Input Current
Supply Current
Standby Current
(HALT Mode)
VCC [3]
TA = 0° C
TA = -40° C
Typical
to +70° C
to +105° C
[13]
Min
Max
Min
Max
1
@25°C Units Conditions
Notes
3.5V
0.7 VCC VCC+0.3
1.3
V
5.5V
0.7 VCC VCC+0.3 0.7 VCC VCC+0.3
2.5
V
3.5V
GND-0.3 0.2 VCC
0.7
V
5.5V
GND-0.3 0.2 VCC GND-0.3 0.2 VCC
1.5
V
3.5V
0.7 VCC VCC+0.3
1.3
V
5.5V
0.7 VCC VCC+0.3 0.7 VCC VCC+0.3
2.5
V
3.5V
GND-0.3 0.2 VCC
0.7
V
5.5V
GND-0.3 0.2 VCC GND-0.3 0.2 VCC
1.5
V
3.5V
VCC-0.4
3.1
V
IOH = -2.0 mA
8
5.5V
VCC-0.4
4.8
V
IOH = -2.0 mA
8
0.2
V
IOH = +4.0 mA
8
0.1
V
IOH = +4.0 mA
8
0.3
V
IOH = +6.0 mA
8
0.3
V
IOH = +10.0 mA
8
1.5
V
2.1
V
VCC-0.4
3.5V
0.6
5.5V
0.4
3.5V
1.2
5.5V
1.2
3.5V
0.8VCC
VCC
5.5V
0.8VCC
VCC
0.4
1.2
0.8VCC
VCC
3.5V
GND-0.3 0.2VCC
1.1
V
5.5V
GND-0.3 0.2VCC GND-0.3 0.2VCC
1.7
V
3.5V
5.5V
3.5V
-1
25
25
1
5.5V
-1
1
3.5V
-1
1
5.5V
-1
1
3.5V
5.5V
3.5V
5.5V
3.5V
-130
-180
20
25
4.5
5.5V
8
3.5V
3.4
5.5V
7.0
DS97DZ80700
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-1
-1
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
25
10
10
<1
mV
mV
µA VIN = 0V, VCC
2
<1
µA VIN = 0V, VCC
<1
µA VIN = 0V, VCC
<1
µA VIN = 0V, VCC
-25
-40
7
20
2.0
µA
µA
mA @16 MHz
mA @16 MHz
mA VIN = 0V, VCC @ 16
MHz
mA VIN = 0V, VCC @ 16
MHz
mA Clock divide by 16 @
16 MHz
mA Clock divide by 16 @
16 MHz
2
-180
25
8
3.7
1.5
7.0
PRELIMINARY
2.9
10
10
1,4
1,4
1,4
1,4
1,4
1,4
8-13
Z86C83/C84/E83
CMOS Z8® MCU
Sym Parameter
ICC2
VICR
IALL
IALH
VLV
Standby Current
(STOP Mode)
Input Common
Mode
Auto Latch Low
Current
Auto Latch High
Current
VCC Low-Voltage
Protection Voltage
Zilog
VCC [3]
TA = 0° C
TA = -40° C
Typical
to +70° C
to +105° C
[13]
Min
Max
3.5V
8
5.5V
10
3.5V
500
5.5V
800
3.5V
0
3.5V
VCC1.0V
VCC1.0V
8
5.5V
0
5.5V
15
3.5V
-5
5.5V
-8
2.0
3.3
Min
Max
@25°C Units Conditions
1
20
2
310
1000
600
0
0
VCC-1.5V
µA VIN = 0V, VCC
WDT is not Running
µA VIN = 0V, VCC
WDT is not Running
µA VIN = 0V, VCC
WDT is Running
µA VIN = 0V, VCC
WDT is Running
V
1,6,11
1,6,11
1,6,11,
14
1,6,11,
14
10
V
10
5
µA 0V<VIN<VCC
9
11
µA 0V<VIN<VCC
9
-3
µA 0V<VIN<VCC
9
-10
-6
µA 0V<VIN<VCC
9
3.5
3.0
V
7
20
2.2
Notes
2 MHz max. Int. CLK
Frequency
Notes:
1. Combined digital VCC and analog AVCC supply currents
2. GND = 0V
3. VCC voltage specification of 3.5V guarantees 3.5V, and VCC voltage specification of 5.5V guarantees 5.0V ±0.5V
4. All outputs unloaded, I/O pins floating, inputs at rail
5. CL1 = CL2 = 100 pF
6. Same as note [4] except inputs at VCC
7. The VLV increases as the temperature decreases
8. Standard Mode (not Low EMI)
9. Auto Latch (mask option) selected
10. For analog comparator, inputs when analog comparators are enabled
11. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating
12. Excludes clock pins
13. Typicals are at VCC = 3.5V and 5.0V
14. Internal RC selected
8-14
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Diagram
1
3
1
Clock
2
7
2
3
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop-Mode
Recovery
Source
10
Figure 9. Additional Timing
DS97DZ80700
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PRELIMINARY
8-15
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table (SCLK/TCLK = XTAL/2) For Z86E83 Only
T = 0°C to +70°C
A
12 MHz
16 MHz
Min
Max
Min
Max
V
No
CC
Note 6
Symbol Parameter
1
TpC
Input Clock Period
2
TrC,TfC
Clock Input Rise & Fall Times
3
TwC
Input Clock Width
4
TwTinL
Timer Input Low Width
5
TwTinH
Timer Input High Width
6
TpTin
Timer Input Period
7
TrTin,
TfTin
8A TwIL
Timer Input Rise & Fall Timer
8B TwIL
Int. Request Low Time
9
TwIH
Int. Request Input High Time
10
Twsm
Stop-Mode Recovery Width Spec
11
Tost
Oscillator Start-up Time
12
Twdt
Watch-Dog Timer Delay Time
13
T
POR
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
Int. Request Low Time
83
83
DC
DC
15
15
41
41
100
70
5TpC
5TpC
8TpC
8TpC
62.5
62.5
Units
Notes
DC
DC
15
15
ns
ns
ns
ns
ms
ns
ms
ns
100
100
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1,2
1,3
1,3
1,2
1,2
31
31
100
70
5TpC
5TpC
8TpC
8TpC
100
100
100
70
5TpC
5TpC
5TpC
5TpC
12
12
100
70
5TpC
5TpC
5TpC
5TpC
12
12
5TpC
5TpC
ns
ns
5TpC
5TpC
WDTMR
5.5V
5.5V
5.5V
5.5V
3.5V
5.5V
Power On Reset Delay
6.25
12.5
25
100
7
3
24
13
6.25
12.5
25
100
7
3
25
14
Reg
ms
ms
ms
ms
ms
ms
4
4
D1,D0
0,0,[7]
0,1,[7]
1,0,[7]
1,1,[7]
7
7
Notes:
1. Timing Reference uses 0.7 V
for a logic 1 and 0.2 V
CC
2.
3.
4.
5.
6.
for a logic 0.
CC
Interrupt request via Port 3 (P31-P33).
Interrupt request via Port 3 (P30).
SMR-D5 = 0.
Reg. WDTMR.
The V voltage specification of 3.5V guarantees 3.5V, and the V
CC
voltage specification of 5.5V guarantees 5.0V ±0.5V.
CC
7. Using internal on-board RC oscillator.
8-16
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table (Low EMI Mode Only) For Z86E83 Only
T = 0°C to +70°C
A
4 MHz
Min
Max
V
CC
[Note 6]
No
Symbol
Parameter
1
TpC
Input Clock Period
2
TrC,TfC
3
Clock Input Rise & Fall Times
TwC
4
Input Clock Width
TwTinL
5
Timer Input Low Width
TwTinH
6
Timer Input High Width
TpTin
7
8A
8B
9
Timer Input Period
TrTin,
TfTin
TwIL
Timer Input Rise & Fall Timer
Int. Request Low Time
TwIL
Int. Request Low Time
TwIH
10
11
Int. Request Input High Time
Twsm
Stop-Mode Recovery Width
Spec
Tost
Oscillator Start-up Time
Notes:
1. Timing Reference uses 0.7 V
250
250
DC
DC
25
25
125
125
100
70
3TpC
3TpC
4TpC
4TpC
250
DC
25
125
70
ns
ns
ns
ns
ns
ns
ns
ns
3TpC
4TpC
100
100
100
70
3TpC
3TpC
3TpC
3TpC
12
12
100
70
ns
ns
ns
ns
3TpC
2TpC
ns
ns
12
5TpC
5TpC
for a logic 1 and 0.2 V
CC
2.
3.
4.
5.
6.
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
T = -40°C to +105°C
A
4 MHz
Min
Max
Units
5TpC
1
Notes
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,2,7,8
1,2,7,8
1,3,7,8
1,3,7,8
1,2,7,8
1,2,7,8
4,8
4,8
4,8,9
4,8,9
for a logic 0.
CC
Interrupt request via Port 3 (P31-P33)
Interrupt request via Port 3 (P30)
SMR-D5 = 1, POR STOP Mode delay is on.
Reg. WDTMR
The V voltage specification of 3.5V guarantees 3.5V,
CC
and the V
voltage specification of 5.5V guarantees 5.0V ±0.5V.
CC
7. SMR D1 = 0
8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode.
9. For LC oscillator and for oscillator driven by clock driver
DS97DZ80700
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PRELIMINARY
8-17
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
CAPACITANCE (Continued)
Additional Timing Table (SKLK/TCLK = XTAL/2) For Z86C83/C84 Only
TA = 0°C to +70°C
No Sym
Parameter
1
Input Clock Period
TpC
VCC
[6]
12 MHz
Min
Max
3.0V
83
DC
5.5V
83
DC
2
TrC,
Clock Input Rise &
3.0V
15
TfC
Fall Times
5.5V
15
3
TwC
Input Clock Width
3.0V
41
5.5V
41
4
TwTinL Timer Input Low
3.0V 100
Width
5.5V
70
5
TwTinH Timer Input High
3.0V 5TpC
Width
5.5V 5TpC
6
TpTin Timer Input Period
3.0V 8TpC
5.5V 8TpC
7
TrTin, Timer Input Rise &
3.0V
100
TfTin Fall Timer
5.5V
100
8A TwIL
Int. Request Low
3.0V 100
Time
5.5V
70
8B TwIL
Int. Request Low
3.0V 5TpC
Time
5.5V 5TpC
9
TwIH Int. Request High
3.0V 5TpC
Time
5.5V 5TpC
10 Twsm Stop-Mode Recovery 3.0V
12
Width Spec
5.5V
12
11 Tost
Oscillator Start-up
3.0V
5TpC
Time
5.5V
5TpC
12 Twdt
Watch-Dog Timer
Delay Time
5.5V 6.25
5.5V 12.5
5.5V
25
5.5V 100
13 TPOR Power On Reset
3.0V
7
24
Delay
5.5V
3
13
TA = -40°C to +150°C
16MHz
Min
Max
12 MHz
Min
Max
16 MHz
Min
Max
62.5
62.5
83
83
62.5
62.5
DC
DC
15
15
31
31
100
70
5TpC
5TpC
8TpC
8TpC
DC
DC
15
15
41
41
100
70
5TpC
5TpC
8TpC
8TpC
100
100
100
70
5TpC
5TpC
5TpC
5TpC
12
12
100
70
5TpC
5TpC
5TpC
5TpC
12
12
5TpC
5TpC
DC
DC
15
15
ns
ns
ns
ns
ns
ns
ns
ns
100
100
ns
ns
ns
ns
31
31
100
70
5TpC
5TpC
8TpC
8TpC
100
100
100
70
5TpC
5TpC
5TpC
5TpC
12
12
5TpC
5TpC
Units Notes
ns
ns
5TpC
5TpC
WDTMR Reg
6.25
12.5
25
100
7
3
25
14
6.25
12.5
25
100
7
3
24
13
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1,2
1,3
1,3
1,2
1,2
6.25
12.5
25
100
7
3
25
14
ms
ms
ms
ms
ms
ms
D1,D0
0,0 [6]
0,1 [6]
1,0 [6]
1,1 [6]
6
6
Notes:
1. Timing References used 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request via Port 3 (P31-P33)
3. Interrupt request via Port 3 (P30)
4. SMR-D5 = 0
5. The VCC voltage specification of 3.0V guarantees 3.3V± 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V ±0.5V.
6. Using internal on-board RC oscillator
8-18
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
For Z86C84 Only
Table 4. D/A Converter Electrical Characteristics
VCC = 3.3V ± 10%
Parameter
Resolution
Integral non-linearity
Differential non-linearity
Setting time, 1/2 LSB
Zero Error at 25°C
Full Scale error at 25°C
Supply Range
Power dissipation, no load
Ref Input resistance
Output noise voltage
VDHI range at 3 volts
VDLO range at 3 volts
VDHI–VDLO, at 3 volts
Capacitive output load, CL
Resistive output load, RL
Output slew rate
Minimum
1.5
0.2
1.3
Typical
8
0.25
0.25
1.5
10
0.25
3.3
10
4K
50
1.8
0.5
1.6
50K
1.0
3.0
3.0
2K
1
Maximum
1
0.5
3.0
20
0.5
3.6
10K
2.1
0.8
1.9
20
Units
Bits
LSB
LSB
µsec
mV
LSB
Volts
mW
Ohms
µVp-p
Volts
Volts
Volts
pF
Ohms
V/µsec
Notes:
Voltage: 3.0V – 3.6V
Temp: 0–70°C
For Z86C84 Only
Table 5. D/A Converter Electrical Characteristics
VCC = 5.0V ±10%
Parameter
Resolution
Integral non-linearity
Differential non-linearity
Setting time, 1/2 LSB
Zero Error at 25°C
Full Scale error at 25°C
Supply Range
Power dissipation, no load
Ref Input resistance
Output noise voltage
VDHI range at 5 volts
VDLO range at 5V volts
VDHI–VDLO, at 5V volts
Capacitive output load, CL
Resistive output load, RL
Output slew rate
Minimum
4.5
2K
Typical
8
0.25
0.25
1.5
10
1
5.0
50
4K
50
2.6
0.8
0.9
20K
1.0
Maximum
1
0.5
3.0†
20
2
5.5
85
10K
3.5
1.7
2.7
30
3.0
Units
Bits
LSB
LSB
µsec
mV
% FSR
Volts
mW
Ohms
µVp-p
Volts
Volts
Volts
pF
Ohms
V/µsec
Notes:
Voltage: 4.5V - 5.5V
Temp: 0-70°C
†
The C86C84 Emulator has maximum setting time of 20 µsec. (10 µsec. typical).
DS97DZ80700
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PRELIMINARY
8-19
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
CAPACITANCE (Continued)
For Z86C83/C84
Table 6. A/D Converter Electrical Characteristics
VCC = 3.3V ± 10%
Parameter
Resolution
Integral non-linearity
Differential non-linearity
Zero Error at 25°C
Supply Range
Power dissipation, no load
Clock frequency
Input voltage range
Conversion time
Input capacitance on ANA
VAHI range
VALO range
VAHI -–VALO
Minimum
2.7
Typical
8
0.5
0.5
3.0
20
VALO
25
VALO +2.5
ANGND
2.5
Maximum
Units
Bits
LSB
LSB
mV
Volts
mW
MHz
Volts
µsec
pF
Volts
Volts
Volts
1
1
5.0
3.3
40
16
VAHI
35 x SCLK
40
AVCC
AVCC–2.5
AVCC
Notes:
Voltage: 3.0V – 3.6V
Temp: 0-70°C
Conversion time is defined as the time from initiation of A-D conversion to storage of the digital result in the ADR register.
SCLK = Internal Z8 System Clock (Bus Speed)
For Z86C83/C84
Table 7. A/D Converter Electrical Characteristics
VCC = 5.0V ±10%
Parameter
Resolution
Integral non-linearity
Differential non-linearity
Zero Error at 25°C
Supply Range
Power dissipation, no load
Clock frequency
Input voltage range
Conversion time
Input capacitance on ANA
VAHI range
VALO range
VAHI -–VALO
Minimum
4.5
Typical
8
0.5
0.5
5.0
50
VALO
25
VALO +2.5
ANGND
2.5
Maximum
Units
Bits
LSB
LSB
mV
Volts
mW
MHz
Volts
µsec
pF
Volts
Volts
Volts
1
1
45
5.5
85
16
VAHI
35 x SCLK
40
AVCC
AVCC–2.5
AVCC
Notes:
Voltage: 4.5V –5.5V
Temp: 0-70°C
Conversion time is defined as the time from initiation of A-D conversion to storage of the digital result in the ADR register.
SCLK = Internal Z8 System Clock (Bus Speed)
8-20
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
For Z86E83
Table 8. A/D Converter Electrical Characteristics
VCC = 3.5V
Parameter
Resolution
Integral non-linearity
Differential non-linearity
Zero Error at 25°C
Supply Range
Power dissipation, no load
Clock frequency
Input voltage range
Conversion time
Input capacitance on ANA
VAHI range
VALO range
VAHI -–VALO
Minimum
1
Typical
8
0.5
0.5
Maximum
20
40
16
VAHI
35 x SCLK
40
AVCC
AVCC–2.5
AVCC
1
1
5.0
3.5
VALO
25
VALO +2.5
ANGND
2.5
Units
Bits
LSB
LSB
mV
Volts
mW
MHz
Volts
µsec
pF
Volts
Volts
Volts
Notes:
Voltage: 3.5V
Temp: 0-70°C
Conversion time is defined as the time from initiation of A-D conversion to storage of the digital result in the ADR register.
SCLK = Internal Z8 System Clock (Bus Speed)
For Z86E83
Table 9. A/D Converter Electrical Characteristics
VCC = 5.0V ±10%
Parameter
Resolution
Integral non-linearity
Differential non-linearity
Zero Error at 25°C
Supply Range
Power dissipation, no load
Clock frequency
Input voltage range
Conversion time
Input capacitance on ANA
VAHI range
VALO range
VAHI -–VALO
Minimum
4.5
Typical
8
0.5
0.5
5.0
50
VALO
4.3
25
VALO +2.5
ANGND
2.5
Maximum
1
1
45
5.5
85
16
VAHI
35 x SCLK
40
AVCC
AVCC–2.5
AVCC
Units
Bits
LSB
LSB
mV
Volts
mW
MHz
Volts
µsec
pF
Volts
Volts
Volts
Notes:
Voltage: 4.5V –5.5V
Temp: 0-70°C
Conversion time is defined as the time from initiation of A-D conversion to storage of the digital result in the ADR register.
SCLK = Internal Z8 System Clock (Bus Speed)
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8-21
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
PIN FUNCTIONS
EPROM Programming Mode (E83 Only)
Z86C83, Z86C84, and Standard Mode Z86E83
D7-D0. Data Bus. The data can be read from or written to
the EPROM through the data bus.
XTAL1. Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC network
or an external single-phase clock to the on-chip oscillator
input.
Clock. Address Clock. This pin is a clock input. The internal address counter increases by one with one clock signal.
Clear. Clear. (active High). This pin resets the internal address counter at the High Level.
VCC. Power Supply. This pin must supply 5V during the
EPROM Read Mode and 6V during other modes.
/CE. Chip Enable (active Low). This pin is active during
EPROM Read, Program, and Program Verify Modes.
/OE. Output Enable (active Low). This pin drives the direction of the Data Bus. When this pin is Low, the Data Bus is
output, when High, the Data Bus is input.
EPM. EPROM Program Mode. This pin controls the different EPROM Program Mode by applying different voltages.
VPP. Program Voltage. This pin supplies the program voltage.
XTAL2. Crystal 2 (time-based output). This pin connects a
parallel-resonant crystal, ceramic resonator, LC network to
the on-chip oscillator output.
Port 0 P00-P06 (P03-P06 is not available on the Z86C84).
Port 0 is a 7-bit, bidirectional, CMOS-compatible I/O port.
These seven I/O lines can be nibble programmable as
P00-P03 input/output and P04-P06 input/output, separately (Figure 10). All input buffers are Schmitt-triggered and
output drivers are push-pull.
Port 0 Auto Latch. (P03-P06 has the Auto Latches permanently enabled). The Auto Latch provides valid CMOS
Levels when P03-P06 are selected as inputs and not externally driven. It is impossible to determine if a non-driven
input is 1 or 0, however; the Auto Latch will sense the input
condition and drive a valid CMOS level, thereby eliminating a floating mode that could cause excessive current.
/PGM. Program Mode (active Low). When this pin is Low,
the data is programmed to the EPROM through the Data
Bus.
Application Precaution
The production test-mode environment may be enabled
accidentally during normal operation if excessive noise
surges above Vcc occur on the /RESET pin.
Processor operation of Z8 OTP devices may be affected
by excessive noise surges on the VPP, /EPM, /OE pins
while the microcontroller is in Standard Mode.
Recommendations for dampening voltage surges in both
test and OTP mode include the following:
■
Using a clamping diode to /RESET, VPP, /EPM, /OE
■
Adding a capacitor to the affected pin
8-22
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
1
Port 0 (I/O)
/OEN
Pad
Out
1.5
2.3 Hysteresis
In
Notes:
Auto Latch
C83/E83:
R
P03-P06 Permanent
500 kΩ
Figure 10. Port 0 Configuration
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8-23
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
PIN FUNCTIONS (Continued)
Port 2 (P27-P20) Port 2 is an 8-bit, bidirectional, CMOScompatible I/O port and an 8-channel muxed input to the
8-bit ADC. When configured as a digital input, by programming the Port2 Mode register, the Port 2 register can be
evaluated to read digital data applied to Port 2, or the ADC
result register can be read to evaluate the analog signals
applied to Port 2 after configuring the ADC Control Registers. The direction of each of the eight Port 2 I/O lines can
be configured individually (Figure 11).
In addition, all four versions of the device provide the capability of connecting 10K (±20%) pull-up resistors to each
of the Port 2 I/O lines individually. The pull-ups are connected when activated through software control of P2RES
register (Figure 67) when the corresponding Port 2 pin is
configured to be an input. The pull-up resistor of a Port 2
I/O line is automatically disabled when the corresponding
I/O is an output, regardless of the state of the corresponding P2RES bit value.
Note: The Z86C83/C84 Emulator does not emulate the
P2RES Register. Selection of the pull-ups are done via
jumper settings on the emulator.
P27
P26
P25
P24
Port 2 (I/O)
P23
P22
P21
P20
10K
/OEN
Data
Input_en
Select from
P2RES
Pad
P2
Analog Mux
ADC
ADC0 (Bits 7, 6, 5)
Figure 11. Port 2 Configuration
8-24
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
Port 3 (P36-P31) Port 3 is a 6-bit, CMOS-compatible port,
with three fixed inputs (P33-P31) and three fixed outputs
(P34-P36), configured under software control for Input/Output, Counter/Timers, interrupt, and port handshake. P31, P32, and P33 are standard CMOS inputs (no
Auto Latches). Pins P34, P35, and P36 are push-pull output lines (Figure 11). Low EMI output buffers can be globally programmed by the software.
Auto Latch. The Auto-Latch instruction puts valid CMOS
levels on CMOS inputs that are not externally driven.
Whether this level is 0 or 1, cannot be determined. A valid
CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer.
Two on-board comparators can process analog signals on
P31 and P32 with reference to the voltage on P33. The analog function is enabled by programming Port 3 Mode
Register (P3M bit 1). For Interrupt functions, Port 3, pin 3
is falling-edge interrupt input. P31 and P32 are programmable as rising, falling, or both edge triggered interrupts
(IRQ register bits 6 and bit 7). P33 is the comparator reference voltage input when in Analog Mode. Access to
Counter/Timers 1 is made through P31 (TIN) and P36
(TOUT). Handshake lines for Ports 0 and 2 are available on
P31/P36 and P32/P35 (Table 10).
Comparator Inputs. Port 3, P31 and P32, each have a
comparator front end. The comparator reference voltage,
P33, is common to both comparators. In analog mode, the
P33 input functions as a reference voltage to the comparators. In Analog Mode, the internal P33 register and its corresponding IRQ1 is connected to the Stop-Mode Recovery
source selected by the SMR register. In this mode, any of
the Stop-Mode Recovery sources are used to toggle the
P33 bit or generate IRQ1. In Digital Mode, P33 can be
used as a Port 3 register input or IRQ1 source. P34 outputs the comparator outputs by software programming the
PCON Register bit D0 to 1.
Port 3 also provides the following control functions: handshake for Ports 0 and 2 (/DAV and RDY); three external interrupt request signals (IRQ2-IRQ0); timer input and output signals (TIN and TOUT).
Note: When enabling/or disabling the analog mode, the
following is recommended:
Table 10. Port 3 Pin Assignments
Pin
P31
P32
P33
P34
P35
P36
I/O
CTC1 Analog
IN
TIN
AN1
IN
AN2
IN
REF
OUT
AN1-OUT
OUT
OUT TOUT
Int.
P0 HS P2 HS
IRQ2
D/R
IRQ0 D/R
IRQ1
Note: Pins 03, 04, 05, 06 have permanently enabled Auto
Latches.
1. allow two NOP delays before reading the comparator
output
2. disable interrupts, switch to analog mode, clear
interrupts, and then re-enable interrupts.
R/D
R/D
Notes:
HS = Handshake Signals
D = /DAV
R = RDY
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8-25
1
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
PIN FUNCTIONS (Continued)
P36
P35
P34
Port 3 (I/O)
P33
P32
P31
Port 3
R247 = P3M
D1
1 = Analog
0 = Digital
DIG.
P31 (AN1)
IRQ2, T IN, P31 Data Latch
+
AN
-
P32 (AN2)
IRQ0, P32 Data Latch
+
P33 (REF)
-
IRQ1, P33 Data Latch
From Stop-Mode Recovery
Source
Figure 12. Port 3 Input Configuration
8-26
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
Port Configuration Register (PCON). The PCON configures the ports individually for comparator output on Port 3.
The PCON Register is located in the Expanded Register
File at Bank F, location 00 (Figure 13).
Note: Only comparator output AN1 is multiplexed to a
Port 3 output. Comparator AN2 output is not connected to
any pins. Note that the PCON Register is reset upon the
occurrence of a WDT RESET (not in STOP Mode), and
Power-On Reset (POR).
Bit 0 multiplexes comparator AN1 Output at P34. A "1" in
this location brings the comparator output to P34
(Figure 14), and a "0" puts P34 into its standard I/O configuration.
PCON (F) 00
D7 D6
D5 D4 D3 D2
D1 D0
Comparator
Output Port 3
0 P34 Standard Output *
1 P34 Comparator Output
Reserved (Must be 1)
0 Port 0 Open-Drain
1 Port 0 Push-Pull*
Reserved (Must be 1)
* Default setting from Stop-Mode Recovery,
Power-On Reset, and any WDT Reset.
Figure 13. Port Configuration Register (PCON) (Write-Only)
P34
P34 OUT
Normal
PAD
AN1
P31
+
REF (P33)
PCON
D0
*
0 P34 Standard Output
1 P34 Comparator Output
* Reset Condition
Figure 14. Port 3 P34 Output Configuration
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8-27
1
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
FUNCTIONAL DESCRIPTION
RESET. (Input, Active Low). This pin initializes the MCU.
Reset is accomplished either through Power-On Reset
(POR), Watch-Dog Timer (WDT) Reset, or external reset.
During POR, and WDT Reset, the internally generated reset is driving the reset pin Low for the POR time. Any devices driving the reset line must be open-drain to
avoid damage from a possible conflict during reset
conditions. Pull-up is provided internally.
After the POR time, /RESET is a Schmitt-triggered input.
After the reset is detected, an internal RST signal is
latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. Program execution begins at location 000C
(hex), 5-10 TpC cycles after the RST is released. For POR,
the reset output time is TPOR.
Program Memory. C83/C84/E83/E84 can address up to
4 KB of internal Program Memory (Figure 15). The first 12
bytes of program memory are reserved for the interrupt
vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Bytes 13 to 4095
consist of on-chip, mask-programmed ROM.
ROM Protect. The 4 KB of Program Memory is mask programmable. A ROM protect feature will prevent dumping
of the ROM contents from an external program outside the
ROM.
Note: When using Zilog's Cross Assembler version 2.1 or
earlier, use the LD RP, #0X instruction rather than the SRP
#0X instruction to access the ERF.
2048/4096
Location of
First Byte of
Instruction
Executed
After RESET 12
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
Expanded Register File. The register file has been expanded to allow for additional system control registers and
for mapping of additional peripheral devices and input/output ports into the register address area. The Z8 register
address space R0 through R15 is implemented as 16
groups of 16 registers per group (Figure 16). These register banks are known as the Expanded Register File (ERF).
Bits 3-0 of the Register Pointer (RP) select the active ERF
bank. Bits 7-4 of register RP select the working register
group (Figure 16). Four system configuration registers reside in the ERF address space in Bank F and eight registers reside in Bank C. The rest of the ERF addressing
space is not physically implemented, and is open for future
expansion.
8-28
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PRELIMINARY
On-Chip
ROM
11
IRQ5
10
IRQ5
9
IRQ4
8
IRQ4
7
IRQ3
6
IRQ3
5
IRQ2
4
IRQ2
3
IRQ1
2
IRQ1
1
IRQ0
0
IRQ0
Figure 15. Program Memory Map
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
1
Figure 16. Expanded Register File Architecture
DS97DZ80700
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PRELIMINARY
8-29
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
FUNCTIONAL DESCRIPTION (Continued)
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
r7 r6
Expanded Register Group
r5 r4
r3 r2
r1 r0
R253
(Register Pointer)
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
Working Register Group
FF
Note: Default Setting After Reset = 00000000
R15 to R0
F0
Figure 17. Register Pointer Register
7F
Register File. The Register File consists of three I/O port
registers, 237 general-purpose registers, 15 control and
status registers, and four system configuration registers in
the Expanded Register Group (Figure 16). The instructions can access registers directly or indirectly through an
8-bit address field. This allows a short 4-bit register address using the Register Pointer (Figure 18). In the 4-bit
mode, the Register File is divided into 16 working register
groups, each occupying 16 continuous locations. The
Register Pointer (Figure 17) addresses the starting location of the active working-register group.
Note: Register Bank E0-EF is only accessed either as
working registers or through indirect addressing modes.
70
6F
60
5F
50
4F
30
2F
R254. The C83/C84/E83 has one extra general-purpose
register located at FEH (R254).
Specified Working
Register Group
20
1F
10
0F
00
CAUTION: D4 of Control Register P01M (R251) must
be 0.
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
40
3F
Register Group 1
R15 to R0
Register Group 0*
R15 to R4*
R3 to R0*
I/O Ports*
* Expanded Register File Bank (0) is selected
in this figure by handling bits D3 to D0 as "0"
in Register R253 (RP).
Figure 18. Register Pointer
Stack. The C83/C84/E83 has an 8-bit Stack Pointer
(R255) used for the internal stack that resides within the
236 general-purpose registers. Register R254 cannot be
used for stack.
General-Purpose Registers (GPR). These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
occurs in the VCC voltage-specified operating range. It will
not keep its last state from a VLV reset if the VCC drops below 1.8V. This includes Register R254.
Note: Register Bank E0-EF is only accessed either as
working register or through indirect addressing modes.
RAM Protect. The upper portion of the RAM’s address
spaces %80F to %EF (excluding the control registers) are
protected from writing. The user activates this feature from
the internal ROM code to turn off/on the RAM Protect by
loading either a 0 or 1 into the Interrupt Mask (IMR) register, bit D6. A 1 in D6 enables RAM Protect.
8-30
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DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
Counter/Timers. There are two 8-bit programmable
counter/timers (T0-T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 prescaler is
driven by the internal clock only (Figure 19).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256) that has been loaded into the counter. When the
counter reaches the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated.
The counters can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
The counters, but not the prescalers, are read at any
time without disturbing their value or count mode. The
clock source for T1 is user-definable and is either the internal microprocessor clock divide-by-four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a
trigger input that can be retriggerable or non-retriggerable,
or as a gate input for the internal clock. The counter/timers
can be cascaded by connecting the T0 output to the input
of T1. T IN Mode is enabled by setting R243 PRE1 Bit D1
to 0.
OSC
Internal Data Bus
D1 (SMR)
Write
Write
Read
÷2
PRE0
Initial Value
Register
T0
Initial Value
Register
6-Bit
Down
Counter
8-bit
Down
Counter
T0
Current Value
Register
D0 (SMR)
÷16
÷4
IRQ4
Internal
Clock
TOUT
P36
÷2
External Clock
Clock
Logic
÷4
Internal Clock
Gated Clock
Triggered Clock
TIN P31
Write
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
Write
IRQ5
T1
Current Value
Register
Read
Internal Data Bus
Figure 19. Counter/Timer Block Diagram
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8-31
1
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has six different interrupts from six different sources. These interrupts are maskable, prioritized
(Figure 20) and the six sources are divided as follows: four
sources are claimed by Port 3 lines P33-P30, and two in
counter/timers (Table 11). The Interrupt Mask Register
globally or individually enables or disables the six interrupt
requests.
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. An interrupt machine cycle is activated when an interrupt request is
granted. This action disables all subsequent interrupts,
saves the Program Counter and Status Flags, and then
branches to the program memory vector location reserved
for that interrupt.
IRQ0 IRQ2
IRQ1, 3, 4, 5
Interrupt
Edge
Select
IRQ (D6, D7)
IRQ
IMR
6
Global
Interrupt
Enable
Interrupt
Request
IPR
PRIORITY
LOGIC
Vector Select
Figure 20. Interrupt Block Diagram
Table 11. Interrupt Types, Sources, and Vectors
Name
IRQ0
IRQ1,
IRQ2
IRQ3
IRQ4
IRQ5
Source
/DAV0, IRQ0
IRQ1
/DAV2, IRQ2, TIN
IRQ3
T0
T1
8-32
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Vector Location
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
PRELIMINARY
Comments
External (P32), Rise Fall Edge Triggered
External (P33), Fall Edge Triggered
External (P31), Rise Fall Edge Triggered
By User Software
Internal
Internal
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
All Z8 interrupts are vectored through locations in the program memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request register is polled to determine which
of the interrupt requests need service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling, or both edge triggered, and are programmable by the user. The software
may poll to identify the state of the pin.
Clock. The Z8 on-chip oscillator has a high-gain, parallelresonant amplifier for connection to a crystal, LC, ceramic
resonator, or any suitable external clock source (XTAL1 =
Input, XTAL2 = Output). The crystal should be AT cut, 16
MHz max., with a series resistance (RS) of less than or
equal to 100 Ohms when clocking from 1 MHz to 16 MHz.
The crystal should be connected across XTAL1 and
XTAL2 using the vendor's recommended capacitor values
from each pin directly to the device Ground pin to reduce
Ground noise injection into the oscillator (Figure 21).
Note: For better noise immunity, the capacitors should be
tied directly to the device Ground pin (VSS).
Programming bits for the Interrupt Edge Select is located
in the IRQ Register (R250), bits D7 and D6. The configuration is shown in Table 12.
Table 12. IRQ Register
IRQ
D7
0
0
1
1
D6
0
1
0
1
Interrupt Edge
P31
P32
F
F
F
R
R
F
R/F
R/F
Notes:
F = Falling Edge
R = Rising Edge
XTAL1
C1
C1
VSS* *
VSS* *
XTAL2
C2
C2
VSS* *
VSS* *
XTAL1
XTAL1
XTAL2
XTAL2
L
LC
Ceramic Resonator or
Crystal
C1, C2 = 22 pF TYP *
f = 8 MHz
External Clock
* Preliminary value including pin parasitics
* * Device ground pin
Figure 21. Oscillator Configuration
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8-33
1
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Analog-to-Digital Converter
The Analog-to-Digital (ADC) is an 8-bit half flash converter
that uses two reference resistor ladders for its upper 4 bits
(MSBs) and lower 4 bits (LSBs) conversion. Two reference
voltage pins, AVCC and AGND, are provided for external
reference voltage supplies. During the sampling period
from one of the eight channel inputs, the converter is also
being auto-zeroed before starting the conversion. The
conversion time is dependent on the internal clock frequency. The minimum conversion time is 35 x SCLK (see
Figure 22).
The ADC is controlled by the Z8 and its three registers (two
Control and one Result) are mapped into the Extended
Register File. A conversion can be initiated by writing to
the ADC Control Register 0 after the ADC Control Register
1 is configured.
The start command is implemented in such a way as to begin a conversion at any time, if a conversion is in progress
and a new start command is received, then the conversion
in progress will be aborted and a new conversion will be
initiated. This allows the programmed values to be
changed without affecting a conversion-in-progress. The
new values will take effect only after a new start command
is received.
The ADC can be disabled (for low power) or enabled by a
Control Register bit.
Though the ADC will function for a smaller input voltage
and voltage reference, the noise and offsets remain constant over the specified electrical range. The errors of the
converter will increase and the conversion time may also
take slightly longer due to smaller input signals.
ADC Calibration Offset
Specially matched resistors are program-enabled to allow
35 percent or 50 percent offset from AGND. They may selectively enable these resistors to offset the AGND by 50
percent (2.5V to 5V) or 35 percent (1.75V to 5V) thereby
allowing the 8-bit ADC across a narrower voltage range.
This will allow significant resolution improvement within
the reduced voltage range.
Note: The AVCC must be the same value as VCC and
AGND must be the same value as GND.
EXT
Start
Converter
8
A/D
Control
Reg.
ADC0
Vref + VCC
AVCC
8
A/D
Result
Reg.
A/D
Converter
Sample
and Hold
ADR1
AGND
Vref- GND
8
4
A/D
Control
Reg.
ADC1
Selected Channel
ADC Register 9
D4, D5
Calibration Offset
Figure 22. ADC Architecture
8-34
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DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
ADE (bit 7). A zero powers down and disables power and
any A/D conversions or accessing any ADC registers except writing to ADE bit. A one Enables all ADC accesses.
ADC result register is shown in Figure 25.
ADC0 (A) Bank C, Register 8
D7 D6 D5 D4 D3 D2 D1 D0
CSEL0
CSEL1
CSEL2
ADR Bank C, Register A
SCAN
0 = No action*.
1 = Convert, then stop.
D7 D6 D5 D4 D3 D2 D1 D0
AIN/Input/Output Control
0 = No action*
1 = Enable selected channel
(D2,D1,D0) as analog input
on associated Port 20-27
Must be D7 = 0
D6 = 0
D5 = 1
Data
Figure 25. Result Register (Read-Only)
* Default after reset
Reg F
Reg E
Figure 23. ADC Control Register 0 (Read/Write)
Reg D
Reg C
Reg B
SCAN
0
1
No action*
Convert channel then stop
Reg A
AD Result 1
Reg 9
AD Control 1
Reg 8
AD Control 0
These registers
can be accessed.
Reg 7
Channel Select (bits 2, 1, 0)
* Default after reset
Reg 6
Reg 5
Reg 4
CSEL2
CSEL1
CSEL0
Channel
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 (P20)*
1 (P21)
2 (P22)
3 (P23)
4 (P24)
5 (P25)
6 (P26)
7 (P27)
Reg 3
Reg 2
Reg 1
Reg 0
Figure 26. Bank C
Note: ADCO D4 must equal 1 to allow Port bit as ADC input.
ADC1 Bank C, Register 9
D7
D6
D5
D4 D3
D2
D1
D0
Must be 0.
D5
0
1
0
1
D4
0
0
1
1
50 % AGND Offset
35% AGND Offset
Reserved
No Offset
Reserved (Must be 1)
ADE
0 Disable*
1 Enable
* Default after reset
Figure 24. ADC Control Register 1 (Read/Write)
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PRELIMINARY
8-35
1
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Figure 27 shows the input circuit of the ADC. When conversion starts the analog input voltage is connected to the
MSB and LSB flash converter inputs as shown in the Input
Impedance CKT diagram. Effectively, shunting 31 parallel
internal resistance of the analog switches and simultaneously charging 31 parallel 0.5 pF capacitors, which is
equivalent to seeing a 400 Ohms input impedance in par-
allel with a 16 pF capacitor. Other input stray capacitance
adds about 10 pF to the input load. For input source resistances up to 2 Kohms can be used under normal operating
condition without any degradation of the input settling time.
For larger input source resistance, increasing conversion
cycle time or adding a capacitor to the input may be required to compensate the input settling time problem.
CMOS Switch
on Resistance
2-5kΩ
C .5 pF
R Source
V Ref
C .5 pF
C Parasitic
31 CMOS Digital
Comparators
C .5 pF
Figure 27. Input Impedance of ADC
Typical Z8 A/D Conversion Sequence
3. Set the register pointer to Extended Bank (C), that is,
SRP #%0C instruction.
4. Next, set ADE flag by loading ADC1 Control Register
Bank (C) Register 9, bit 7. Also, load bits 0-4 of this
same register to select a AVCC or AGND offset value. A
precision voltage divider connected to the A/D
resistive ladder can offset conversion dynamic range
to specified limits within the AVCC and AGND limits. By
loading Bank (C) Register 9, bits 0-4, with the
appropriate value it is possible to select from these
groups:
a. No Offset. The Converter Dynamic range is from
0V to 5.0V for AVCC = 5.0V.
5. Select one of the eight A/D inputs for conversion by
loading Bank (C) Register 8 with the desired attributes:
Bits 0 - 2 select an A/D input, bits 3 and 4 select A/D
conversion (or digital port I/O).
6. Set Bank (C) Register 8, bit 3 to enable A/D
conversion. (This flag can be set concurrently with
step 3.) This flag is automatically reset when the A/D
conversion is completed, so a bit test can be
performed to determine A/D readiness if necessary.
7. Read the A/D result in Bank (C) Register A. Please
note that the A/D result is not valid (indeterminate)
unless ADE flag (Register 9, bit 7) was previously set,
otherwise A/D converter output is tri-stated.
b. 35 Percent A GND Offset. The Converter Dynamic
range is 1.75V - 5.0V for AVCC = 5.0V.
c.
50 Percent A GND Offset. The Converter Dynamic
range is 2.5V - 5.0V for AVCC = 5.0V.
8-36
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
Digital-to-Analog Converters
The Z86C84 has two Digital-to-Analog Converters
(DACs). Each DAC is an 8-bit resistor string, with a programmable 0.25X, 0.5X, or 1X gain output buffer. The
DAC output voltage settles after the internal data is latched
into the DAC Data register. The top and bottom ends of the
resistor ladder are register-selected to be connected to either the analog supply rails, AVCC and AGND, or two externally-provided reference voltages, VDHI and VDLO. External references are recommended to explicitly set the DAC
output limits. Since the gain stage cannot drive to the sup-
ply rails, VDHI and VDLO must be within ranges shown in
the specifications. If either reference approaches the analog supply rails, the output will be unable to span the reference voltage range. The externally provided reference
voltages should not exceed the supply voltages. The DAC
outputs are latch-up protected and can drive output loads
(Figure 28).
Note: The AVCC must be the same value as VCC and
AGND must be the same value as GND
PAD
VDHI
AVCC
8
DACn
Data
Register
8
Data
Bus
8
High
Analog
8-Bit
Resistor
Ladder
DACRn
Control
Register
Low
(n = 1 or 2)
DAC1
or
DAC2
PAD
+
AGND
Programmable
Gain
* Bits 0, 1
Note:
* DACRn Control Register Bits
PAD
VDLO
Figure 28. DAC Block Diagram
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PRELIMINARY
8-37
1
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
FUNCTIONAL DESCRIPTION (Continued)
The D/A conversion for DAC1 is driven by writing 8-bit data
to the DAC1 data register (Bank C, Register 06H). The
D/A conversion for DAC2 is controlled by the DAC2 data
register (Bank C, Register 07H). Each DAC data register
is initialized to midrange 80H on power-up.
DACR2 Bank C, Register 5
D7 D6 D5 D4 D3 D2 D1 D0
DAC2 Gain
0 0 1X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
There are two DAC control registers: DACR1 (Bank C,
Register 04H) for DAC1, and DACR2 (Bank C, Register
05H) for DAC2. Control register bits 0 and 1 set the DAC
gain. When DAC data is 80H, the DAC output is constant
for any gain setting (Figure 29 and Figure 31).
DAC2 Enable
(Must be 0 for C83)
0 Disable
1 Enable
DACR1 Bank C, Register 4
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
DAC1 Gain
0 0 1X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
Figure 31. D/A 2 Control Register
DAC2 Bank C, Register 7
D7 D6 D5 D4 D3 D2 D1 D0
DAC1 Enable
0 Disable
1 Enable
0 = Low Level
1 = High Level
Reserved (Must be 0)
Figure 32. D/A 2 Data Register
Figure 29. D/A 1 Control Register
DAC1 Bank C, Register 6
D7 D6 D5
D4 D3 D2
D1 D0
0 = Low Level
1 = High Level
Figure 30. D/A 1 Data Register
8-38
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
DAC Output in Volts
1
3.5
3.5V
VDHI
3.05
2% accuracy
2.6
2.15
2.15
1.7
1/4X
1/2X
1X
1.26
VDLO .8
0
80H
FFH
DAC Data Register Value
Notes:
Vcc = 5.0V ±10%
VDHI = 3.5V
VDLO = 0.8V
Figure 33. Gain Control on DAC
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator or by the XTAL oscillator is
used for the POR timer function. The POR time allows VCC
and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer
triggered by one of three conditions:
■
Power Fail to Power OK Status
■
Stop-Mode Recovery (If D5 of SMR Register = 1)
■
WDT Time-Out (Including from STOP Mode)
The POR time is T POR minimum. Bit 5 of the STOP Mode
Register determines whether the POR timer is bypassed
after Stop-Mode Recovery (typical for external clock and
LC oscillators with fast start up time).
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HALT. Turns off the internal CPU clock but not the XTAL
oscillation. The counter/timers and external interrupts
IRQ0, IRQ1, and IRQ2 remain active. The device is recovered by interrupts, either externally or internally generated
(a POR or a WDT time-out). An interrupt request must be
executed (enabled) to exit HALT Mode. After the interrupt
service routine, the program continues from the instruction
after the HALT. In case of a POR or a WDT time-out, program execution will restart at address 000CH.
STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current
to 10 µA (typical) or less. The STOP Mode is terminated by
a reset of either WDT time-out, POR, or Stop-Mode Recovery. This causes the processor to restart the application program at address 000CH.
PRELIMINARY
8-39
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
In order to enter STOP (or HALT) Mode, it is necessary to
first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute
a NOP (Opcode = FFH) immediately before the appropriate sleep instruction, that is,
FF
6F
NOP
STOP
FF
7F
NOP
HALT
; clear the pipeline
; enter STOP Mode
or
; clear the pipeline
; enter HALT Mode
Stop-Mode Recovery (SMR) Register. This register selects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 34 and Figure 35). All bits
are Write-Only, except bit 7, which is Read-Only. Bit 7 is a
flag bit that is hardware set on the condition of STOP recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level is required from the recovery
source. Bit 5 controls the reset delay after recovery. Bits 2,
3, and 4, or the SMR Register, specify the source of the
Stop-Mode Recovery signal. Bits 0 and 1 determine the
time-out period of the WDT. The SMR Register is located
in Bank F of the Expanded Register Group at address
0BH. When the Stop-Mode Recovery sources are selected
in this register, then SMR2 Register bits D0,D1 must be set
to 0.
SMR (FH) 0B
D7 D6 D5
D4 D3 D2 D1 D0
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,
P24,P25,P26,P27
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
Figure 35. Stop-Mode Recovery Register 2
([0F] DH: Write-Only)
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The control selectively reduces device power consumption during
normal processor execution (SCLK control) and/or HALT
mode (where TCLK sources counter/timers and interrupt
logic). This bit is reset to D0 = 0 after a Stop-Mode Recovery, WDT Time-out, and POR.
External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by-two circuitry. When this bit is
0, the System Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock HALT Mode frequency divided
by two. The SCLK/TCLK is equal to the external clock frequency when this bit is set (D1=1). Using this bit together
with D7 of PCON further helps lower EMI (that is, D7
(PCON) = 0, D1 (SMR) = 1). The default setting is zero.
Maximum external clock frequency is 8 MHz when SMR
Bit D1 = 1 where SCLK/TCLK = XTAL.
SCLK/TCLK Divide-by-16
0 OFF* *
1 ON
OSC
External Clock Divide-by-2
0 SCLK/TCLK = XTAL/2*
1 SCLK/TCLK = XTAL
SMR, D1
Stop-Mode Recovery Source
000 POR Only and/or External Reset*
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
÷2
÷ 16
SCLK
SMR, D0
TCLK
Stop Delay
0 OFF
1 ON *
Stop Recovery Level
0 Low *
1 High
Note: Not used in conjunction with SMR2
Source
* Default Setting After RESET
** Default setting after RESET and
Stop-Mode Recovery
Figure 36. SCLK Circuit
Stop Flag (Read-Only)
0 POR *
1 Stop Recovery
Figure 34. Stop-Mode Recovery Register (Write-Only
Except Bit D7, Which Is Read-Only)
8-40
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
Stop-Mode Recovery Source (D2, D3, and D4). These
three bits of the SMR register specify the wake-up source
of the STOP recovery (Figure 37 and Table 13). When the
Stop-Mode Recovery Sources are selected in this register
then SMR2 register bits D0,D1 must be set to zero. P33P31 and Port 2 cannot wake up from STOP Mode if the input lines are configured as analog inputs to the Analog
comparator or Analog-to-Digital Converter.
Note: If the Port 2 pin is configured as an output, this
output level will be read by the SMR circuitry.
Table 13. Stop-Mode Recovery Source
D4
0
0
0
0
1
1
1
1
SMR:432
D3
D2
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Operation
Description of Action
POR and/or external reset recovery
Reserved
P31 transition (not in Analog Mode)
P32 transition (not in Analog Mode)
P33 transition (not in Analog Mode)
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
WDT reset will override the selection and cause the reset
delay to occur.
Stop-Mode Recovery Edge Select (D6). A "1" in this bit
position indicates that a high level on the output to the exclusive Or-Gate input from the selected recovery source
wakes the Z86C83/C84/E83 from STOP Mode. A "0" indicates low-level recovery. The default is 0 on POR. This bit
is used for either SMR or SMR2.
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. A 0 in this bit (cold) indicates
that the device resets by POR/WDT reset. A "1" in this bit
(warm) indicates that the device awakens by a Stop-Mode
Recovery source.
Note: A WDT reset out of STOP Mode will also set this bit
to a "1".
Stop-Mode Recovery Register 2 (SMR2). This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this register then SMR Register Bits D2, D3, and D4 must be 0.
Table 14. Stop-Mode Recovery Source
Stop-Mode Recovery Delay Select (D5). This bit, if High,
enables the T POR /RESET delay after Stop-Mode Recovery. The default configuration of this bit is "1". A POR or
SMR:10
D1 D0
0
0
0
1
1
0
Operation
Description of Action
POR and/or external reset recovery
Logical AND of P20 through P23
Logical AND of P20 through P27
SMR2 D1 D0
0 0
SMR2 D1 D0
0 1
VDD
SMR
P20
P20
P23
P27
D4 D3 D2
0 0 0
SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2
VDD
1 0 1
0 1 0
1 0 0
0 1 1
P20
P31
P33
P27
P32
SMR D4 D3 D2
1 1 0
P23
SMR2
D1 D0
1 0
SMR D4 D3 D2
1 1 1
P20
P27
To POR
/RESET
Stop-Mode Recovery Edge
Select (SMR)
To P33 Data
Latch and IRQ1
MUX
P33 From Pads
Digital/Analog Mode
Select (P3M)
Figure 37. Stop-Mode Recovery Source
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PRELIMINARY
8-41
1
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit
is driven by an on-board RC oscillator or external oscillator
from the XTAL1 pin. The POR clock source is selected
with bit 4 of the WDT register (Figure 38).
WDT instruction affects the Z (Zero), S (Sign), and V
(Overflow) flags. The WDTMR must be written to within 64
internal system clocks. After that, the WDTMR is write protected.
Note: WDT time-out while in Stop-Mode will not reset
SMR, PCON, WDTMR, P2M, P3M, Ports 2 and 3 Data
Registers, but will cause the reset delay to occur.
The Power-On Reset (POR) clock source is selected with
bit 4 of the WDTMR. Bits 0 and 1 control a tap circuit that
determines the time-out period. Bit 2 determines whether
the WDT is active during HALT and bit 3 determines WDT
activity during STOP. If bits 3 and 4 of this register are both
set to "1," the WDT is only driven by the external clock during STOP Mode. This feature makes it possible to wake up
from STOP Mode from an internal source. Bits 5 through 7
of the WDTMR are reserved (Figure 39). This register is
accessible only during the first 60 processor cycles (60
SCLKs) from the execution of the first instruction after
Power-On-Reset, Watch-Dog Reset or a Stop-Mode Recovery. After this point, the register cannot be modified by
any means, intentional or otherwise. The WDTMR cannot
be read and is located in Bank F of the Expanded Register
group at address location 0FH.
/RESET
/Clear
CLK
18 Clock RESET
Generator
RESET
Internal
/RESET
WDT Select
(WDTMR)
WDT TAP SELECT
CK Source
Select
(WDTMR)
XTAL
M
U
X
On Board
RC OSC.
VCC
VLV
+
-
128 SCLK
POR
CK /CLR
256 512 1024 4096
SCLK SCLK SCLK SCLK
WDT/POR Counter Chain
3.0V Operating
Voltage Det.
/WDT
From Stop
Mode
Recovery
Source
12 ns Glitch Filter
Stop Delay
Select (SMR D5)
Figure 38. Resets and WDT
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
Notes:
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00 256
01 512
10 1024
11 4096
1. If WDT is permanently selected (always ON mode)
using internal on-board RC oscillator, the WDT will
continue to run even if set not to run in STOP or HALT
Mode.
SCLK
SCLK
SCLK
SCLK
2. WDT instructions affect the Z (Zero), S (Sign), and V
(Overflow) flags.
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
* Default setting after RESET
† XTAL=SCLK/TCLK shown
Figure 39. Watch-Dog Timer Mode Register
(Write Only)
WDT Time Select (D1, D0). Selects the WDT time-out period. It is configured as shown in Table 15.
Table 15. WDT Time Select (Min. @ 5.0V)
D1
0
0
1
1
D0
0
1
0
1
Time-Out of
Internal RC OSC
6.25 ms min
12.5 ms min
25 ms min
100 ms min
Time-Out of
SCLK Clock
256 SCLK
512 SCLK
1024 SCLK
4096 SCLK
Note: The minimum time shown is for VCC @ 5.0V.
WDT During HALT (D2). This bit determines whether or
not the WDT is active during HALT Mode. A "1" indicates
active during HALT. The default is "1".
Note: If WDT is permanently selected (always ON mode),
the WDT will continue to run even if set not to run in STOP
or HALT Mode.
WDT During STOP (D3). This bit determines whether or
not the WDT is active during STOP Mode. Since XTAL
clock is stopped during STOP Mode, unless as specified
below, the on-board RC has to be selected as the clock
source to the POR counter. A "1" indicates active during
STOP. The default is "1". If bits D3 and D4 are both set to
"1", the WDT only, is driven by the external clock during
STOP Mode.
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On-Board, Power-On-Reset RC or External XTAL1
Oscillator Select (D4). This bit determines which oscillator source is used to clock the internal POR and WDT
counter chain. If the bit is a "1", the internal RC oscillator is
bypassed and the POR and WDT clock source is driven
from the external pin, XTAL1. The default configuration of
this bit is 0, which selects the RC oscillator. If the XTAL1
pin is selected as the oscillator source for the WDT, during
STOP Mode, the oscillator will be stopped and the WDT
will not run. This is true even if the WDT is selected to run
during STOP Mode.
VCC Voltage Comparator. An on-board Voltage Comparator checks that VCC is at the required level to ensure correct operation of the device. RESET is globally driven if
VCC is below the specified voltage (typically 2.6V).
ROM Protect. ROM Protect is mask or OTP bit-programmable. It is selected by the customer at the time the ROM
code is submitted.
ROM Mask Selectable Options
There are two ROM mask options that must be selected at
the time the ROM mask is ordered (ROM code submitted)
for the Z86C83/C84 and three Z86E83 OTP bit options.
Table 16. Selectable Options
Option
Permanent WDT
ROM Protect
EPROM/TEST Mode Disable*
Selection
Yes/No
Yes/No
Yes/No
Note:
*For Z86E83 only
EPROM/TEST Mode Disable - On the Z86E83, the user can permanently disable entry into EPROM Mode and TEST Mode
by programming this bit.
PRELIMINARY
8-43
1
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
EXPANDED REGISTER FILE CONTROL REGISTERS (0C)
ADC0 Bank C, 8H
DACR1 Bank C, Register 4
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Channel Select (bits 2,1,0)
CSEL2
0
0
0
0
1
1
1
1
DAC1 Gain
0 0 1X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
CSEL1 CSEL0 Channel
0
0
0*
0
1
1
1
0
2
1
1
3
0
0
4
0
1
5
1
0
6
1
1
7
DAC1 Enable
(Must be 0 for Z86C83)
0 Disable
1 Enable
Scan 0 = No action*
1 = Convert channel then stop
Reserved (Must be 0)
AIN/Input/Output Control
0 = No Action (Digital Function)*
1 = Enable Selected Channel
(M2, M1, M0) as analog input on
associated Port P27-P20
Must be 0 0 1
Figure 43. D/A 1 Control Register
DACR2 Bank C, Register 5
* Default setting after reset.
D7 D6 D5 D4 D3 D2 D1 D0
DAC2 Gain
0 0 1X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
Figure 40. ADC Control Register 0 (Read/Write)
ADC1 Bank C, Register 9
DAC2 Enable
(Must be 0 for C83)
0 Disable
1 Enable
D7 D6 D5 D4 D3 D2 D1 D0
Must be 0.
D5
0
1
0
1
D4
0
0
1
1
Reserved (Must be 0)
50 % AGND Offset
35% AGND Offset
Reserved
No Offset
Reserved (Must be 1.)
ADE
0 Disable*
1 Enable
Figure 44. D/A 2 Control Register
DAC1 Bank C, Register 6
D7 D6 D5 D4 D3 D2 D1 D0
0 = Low Level
1 = High Level
Figure 41. ADC Control Register 1 (Read/Write)
Figure 45. D/A 1 Data Register
ADR1 Bank C, AH
D7 D6
D5
D4
D3 D2
D1
D0
DAC2 Bank C, Register 7
Data
D7 D6 D5 D4 D3 D2 D1 D0
0 = Low Level
1 = High Level
Figure 42. AD Result Register (Read Only)
Figure 46. D/A 2 Data Register
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
EXPANDED REGISTER FILE CONTROL REGISTERS
SMR (F) 0B
D7
D6
WDTMR (F) 0F
D5 D4
D3
D2
D1 D0
1
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
WDT TAP
00 256
01 512
10 1024
11 4096
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
STOP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
SCLK
SCLK
SCLK
SCLK
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
* Default setting after RESET
† XTAL=SCLK/TCLK shown
Stop Flag (Read only)
0 POR*
1 Stop Recovery
Figure 49. Watch-Dog Timer Mode Register
(Write-Only)
Note: Not used in conjunction with SMR2 Source
* Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
PCON (F) 00
D7 D6
Figure 47. Stop-Mode Recovery Register
(Write-Only, except Bit 7 which is Read-Only)
D6
D5 D4
D3
D2
D1
D4
D3
D2 D1
D0
Comparator
Output Port 3
0 P34 Standard Output*
1 P34 Comparator Output
SMR2 (F) DH
D7
D5
Reserved (Must be 1)
D0
0 Port 0 Open-Drain
1 Port 0 Push-Pull*
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,
P24,P25,P26,P27
11 Reserved
Reserved (Must be 0)
Reserved (Must be 1)
0 = Low EMI OSC
1 = Standard OSC
* Default setting from Stop-Mode Recovery
Power-On Reset, and any WDT Reset.
Note: Not used in conjunction with SMR Source
Figure 48. Watch-Dog Timer Mode Register 2
DS97DZ80700
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Figure 50. Port Configuration Register (PCON)
(Write-Only)
PRELIMINARY
8-45
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
Z8 CONTROL REGISTERS
R243 PRE1
R240
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 T1 Single Pass
1 T1 Modulo N
Reserved (Must be 0)
Clock Source
1 T1Internal
0 T1External Timing Input
(TIN) Mode
Figure 51. Reserved
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R241 TMR
D7 D6 D5 D4 D3 D2 D1 D0
Figure 54. Prescaler 1 Register (F3H: Write-Only)
0 No Function
1 Load T0
0 Disable T0 Count
1 Enable T0 Count
R244 T0
0 No Function
1 Load T1
D7 D6 D5
0 Disable T1 Count
1 Enable T1 Count
D4 D3
D2 D1 D0
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
TOUT Modes
00 Not Used
01 T0 Out
10 T1 Out
11 Internal Clock Out
Figure 52. Timer Mode Register (F1H: Read/Write)
T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T0 Current Value
(When Read)
Figure 55. Counter/Timer 0 Register (F4H: Read/Write)
R245 PRE0
D7
D6 D5
D4 D3 D2
D1 D0
R242 T1
Count Mode
0 T0 Single Pass
1 T0 Modulo N
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
T1 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T1 Current Value
(When Read)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
Figure 56. Prescaler 0 Register (F5H: Write-Only)
Figure 53. Counter/Timer 1 Register (F2H: Read/Write)
R247 P3M
D7 D6
D5 D4
D3 D2
D1 D0
0 Port 2 Open-Drain*
1 Port 2 Push-Pull
Port 3 Inputs
0 Digital*
1 Analog
Reserved (Must be 0)
*Default Setting After Reset
Figure 57. Port 3 Mode Register (F7H: Write-Only)
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
R250 IRQ
R246 P2M
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = Software Controlled
IRQ4 = T0
IRQ5 = T1
P27- P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
*Default Setting After Reset
Figure 58. Port 2 Mode Register (F6H: Write-Only)
Default Setting After Reset = 00H
Inter Edge
00 P31 ↓
01 P31 ↓
10 P31 ↑
11 P31 ↑↓
P32
P32
P32
P32
↓
↑
↓
↑↓
R248 P01M
D7
D6 D5
D4
D3
D2
D1
D0
Figure 61. Interrupt Request Register
(FAH: Read/Write)
P00-P03 Mode †
00 Output
01 Input
1X A11-A8
Reserved (Must be 1)
R251 IMR
Reserved (Must be 0)
D7 D6
D5
D4
D3
D2
D1 D0
P04-P06 Mode
00 Output
01 Input
1X A15-A12
1 Enables IRQ5-IRQ0
(D0 = IRQ0)
1 RAM Protect Enabled
0 RAM Protect Disabled *
1 Enables Interrupts
0 Disable interrupts
* (Default setting after RESET.)
Figure 59. Port 0 and 1 Mode Register
(F8H: Write-Only)
Figure 62. Interrupt Mask Register (FBH: Read/Write)
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
R252 Flags
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
Overflow Flag
Sign Flag
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
Zero Flag
Carry Flag
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Figure 63. Flag Register (FCH: Read/Write)
Reserved (Must be 0)
Figure 60. Interrupt Priority Register (F9H: Write-Only)
DS97DZ80700
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PRELIMINARY
8-47
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
Z8 CONTROL REGISTERS (Continued)
R253 RP
R255 SPL
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register File Pointer
Stack Pointer Lower
Byte (SP7-SP0)
0 = Low Level
1 = High Level
Working Register Pointer
Default Setting After Reset = 00H
Figure 64. Register Pointer (FDH: Read/Write)
R254 GPR
Figure 66. Stack Pointer (FFH: Read/Write)
P2RES Bank C, Register 3
D7 D6 D5 D4 D3 D2 D1 D0
D7
D6 D5
0 = Low Level
1 = High Level
8-48
D3
D2
D1 D0
Port 2 (P27-P20) 10K Pull-up
0 = Disabled
1 = Enabled
Figure 65. General-Purpose Register
(FEH: Read/Write)
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D4
Figure 67. Port 2 Pull-up Register
PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
PACKAGE INFORMATION
1
Figure 68. 28-Pin DIP Package Diagram
Figure 69. 28-Pin SOIC Package Diagram
DS97DZ80700
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8-49
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
PACKAGE INFORMATION (Continued)
Figure 70. 28-Pin PLCC Package Diagram
8-50
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PRELIMINARY
DS97DZ80700
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
ORDERING INFORMATION
Z86C83
16 MHz
1
Z86E83
16 MHz
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
Z86C8316PSC
Z86C8316PEC
Z86C8316SSC
Z86C8316SEC
Z86C8316VSC
Z86C8316VEC
Z86E8316PSC
Z86E8316PEC
Z86E8316SSC
Z86E8316SEC
Z86E8316VSC
Z86E8316VEC
Z86C84
16 MHz
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
Z86C8416PSC
Z86C8416PEC
Z86C8416SSC
Z86C8416SEC
Z86C8416VSC
Z86C8416VEC
For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
CODES
Package
Speed
P = Plastic DIP
S = Plastic SOIC
16 = 16 MHz
Environmental
Temperature
C = Plastic Standard
S = 0°C to + 70°C
E = -40°C to +105°C
Example:
Z 86C83 16 P S C
is a Z86C83, 16 MHz, DIP, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
DS97DZ80700
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PRELIMINARY
8-51
Z86C83/C84/E83
CMOS Z8® MCU
Zilog
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS,
STATUTORY, IMPLIED OR BY DESCRIPTION,
REGARDING THE INFORMATION SET FORTH HEREIN
OR REGARDING THE FREEDOM OF THE DESCRIBED
DEVICES
FROM
INTELLECTUAL
PROPERTY
INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
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PRELIMINARY
DS97DZ80700