PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z89320 16-BIT DSP DIGITAL SIGNAL PROCESSOR GENERAL DESCRIPTION The Z89320 is a second generation, 16-bit fractional, two’s complement CMOS Digital Signal Processor (DSP). Most instructions, including multiply and accumulate, are accomplished in a single clock cycle. The processor contains 1Kbyte of on-chip data RAM (two blocks of 256 16-bit words), 4K words of program ROM. Also, the processor features a 24-bit ALU, a 16x16 multiplier, a 24bit Accumulator and a shifter. Additionally, the processor contains a six-level stack, three vectored interrupts and two inputs for conditional program jumps. Each RAM block contains a set of three pointers which may be incremented or decremented automatically to affect hardware looping without software overhead. The data RAMs can be simultaneously addressed and loaded to the multiplier for a true single cycle multiply. Development tools for the IBM PC include a relocatable assembler, a linker loader, and an ANSI-C compiler. Also, the development tools include a simulator/debugger, a cross assembler for the TMS320 family assembly code and a hardware emulator. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VSS VDD The device includes a 16-bit I/O bus for transferring data or for mapping peripherals into the processor address space. Additionally, there are two general purpose user inputs and two user outputs. Operation with slow peripherals is accompished with a ready input pin. DC-4128-00 (12-2-92) 1 GENERAL DESCRIPTION (Continued) Register Pointer 0-2 256 Word RAM 0 256 Word RAM 1 PC Register Pointer 4-6 4K Word ROM Instruction Register 16 EXT0-15 D Bus 16-Bit Bus 16-bit I/O Port Switch S-Bus X Y 3 Stack Switch 16 x16 Multiplier /RDYE, ER//W, /EI EA0-2 Ready 24-bit P 24 24-Bit Bus Interrupt P Bus 3 INTO-2 /RESET MUX Shifter B A 2 Status (5) ALU ACC Functional Block Diagram 2 User Port UI0-1 2 UO0-1 PIN DESCRIPTION EXT12 1 40 VSS EXT13 2 39 EXT2 EXT14 3 38 EXT1 VSS 4 37 EXT0 EXT15 5 36 VSS EXT3 6 35 NC (must be VSS) EXT4 7 34 UO1 VSS 8 33 UO0 EXT5 9 32 INT0 EXT6 10 31 HALT EXT7 11 30 CK EXT8 12 29 /EI EXT9 13 28 VDD VSS 14 27 EA2 EXT10 15 26 EA1 EXT11 16 25 EA0 INT2 17 24 /RES INT1 18 23 /RDYE UI1 19 22 ER//W UI0 20 21 VDD Z89320 40-Pin DIP Pin Assignments 3 HALT 2 1 44 43 42 41 40 EA1 NC 3 EA2 INT0 4 VDD UO0 5 /EI Uo1 6 CK NC PIN DESCRIPTION (Continued) VSS 7 39 EA0 EXT0 8 38 /RES EXT1 9 37 /RDYE EXT2 10 36 ER//W VSS 11 35 VDD N/C 12 34 NC EXT12 13 33 UI0 EXT13 14 32 UI1 EXT14 15 31 INT1 VSS 16 30 INT2 EXT15 17 29 EXT11 Z89320 PLCC EXT10 VSS EXT9 EXT8 NC EXT7 EXT6 EXT5 VSS EXT4 EXT3 18 19 20 21 22 23 24 25 26 27 28 44-Pin PLCC Pin Assignments (Standard Mode) 4 ABSOLUTE MAXIMUM RATINGS Storage temperature range Lead temperature (if packaged) VDD Voltage to VSS All other pins -65°C to +150°C 300°C for 10 sec. -0.5 to 7.0V VDD+0.5V to VSS-0.5V Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability. STANDARD TEST CONDITIONS +5V The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to ground. Positive current flows into the referenced pin (Test Load Diagram). 2.1 K Ω From Output Under Test 9.1 K Ω 150 pF Test Load Diagram DC ELECTRICAL CHARACTERISTICS (VDD= 5V ± 5%, TA = 0°C to +70°C unless otherwise specified) Symbol Parameter Condition IDD Supply Current IDC DC Power Consumption VDD=5.25V fclock=10 MHz VDD=5.25V VIH VIL IL Input High Level Input Low Level Input Leakage VOH VOL IFL Output High Voltage Output Low Voltage Output Floating Leakage Current Min. 1 mA Max. Units 40 mA 5 mA 0.1 VDD 1 V V µA 0.5 5 V V µA 0.9 VDD IOH=-100 µA IOL=0.5 mA VDD-0.2 5 AC TIMING DIAGRAM TXWH TCY PWW TXVD CK TEAD TIED TIED /EI TEAD EXT Bus: Output ER//W Valid Data Out EXT (15:0) EA (2:0) Valid Address Out TEAD RDYS /RDYE RDYH WRITE to external device timing TXRH TCY PWW TXRS CK TEAD TIED TIED /EI ER//W EXT (15:0) EA (2:0) EXT Bus: Input Valid Data In Valid Address Out TEAD /RDYE RDYS RDYH READ from external device timing 6 AC ELECTRICAL CHARACTERISTICS (VDD = 5V ± 5%, TA = 0°C to +70°C unless otherwise specified) Symbol Parameter Min. Max. Units TCY PWW Tr Tf Clock Cycle Time Clock Pulse Width Clock Rise Time Clock Fall Time 100 45 2 2 1000 ns ns ns ns TEAD TXVD TXWH TXRS EA,ER//W Delay from CK EXT Data Output Valid from CK EXT Data Output Hold from CK EXT Data Input Setup Time 15 5 15 15 25 25 ns ns ns ns TXRH TIED RDYS RDYH EXT Data Input Hold from CK /EI Delay Time from CK Ready Setup Time Ready Hold Time 0 0 10 0 15 5 ns ns ns ns Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability 4 4 stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship. 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