ZILOG Z8L18010VSC

PRELIMINARY PRODUCT SPECIFICATION
1
Z80180/Z8S180/
Z8L180 SL1919
1
ENHANCED Z180 MICROPROCESSOR
FEATURES
■
Code Compatible with Zilog Z80® CPU
■
Two 16-Bit Counter/Timers
■
Extended Instructions
■
Two Enhanced UARTs (up to 512 Kbps)
■
Two Chain-Linked DMA Channels
■
Clock Speeds: 6, 8, 10, 20, 33 MHz
■
Low Power-Down Modes
■
Operating Range: 5V (3.3V@ 20 MHz)
■
On-Chip Interrupt Controllers
■
Operating Temperature Range: 0°C to +70°C
■
Three On-Chip Wait-State Generators
■
-40°C to +85°C Extended Temperature Range
■
On-Chip Oscillator/Generator
■
■
Expanded MMU Addressing (up to 1 MB)
■
Clocked Serial I/O Port
Three Packaging Styles
– 68-Pin PLCC
– 64-Pin DIP
– 80-Pin QFP
GENERAL DESCRIPTION
The enhanced Z80180/Z8S180/Z8L180™ significantly improves on the previous Z80180 models while still providing
full backward compatibility with existing Zilog Z80 devices.
The Z80180/Z8S180/Z8L180 now offers faster execution
speeds, power saving modes, and EMI noise reduction.
This enhanced Z180 design also incorporates additional
feature enhancements to the ASCIs, DMAs, and Icc
STANDBY Mode power consumption. With the addition of
“ESCC-like” Baud Rate Generators (BRGs), the two ASCIs
now have the flexibility and capability to transfer data asynchronously at rates of up to 512 Kbps. In addition, the ASCI
receiver has added a 4-byte First In First Out (FIFO) which
can be used to buffer incoming data to reduce the incidence of overrun errors. The DMAs have been modified to
allow for a “chain-linking” of the two DMA channels when
set to take their DMA requests from the same peripherals
device. This feature allows for non-stop DMA operation between the two DMA channels, reducing the amount of CPU
intervention (Figure 1).
Not only does the Z80180/Z8S180/Z8L180 consume less
power during normal operations than the previous model,
it has also been designed with three modes intended to further reduce the power consumption. Zilog reduced Icc power consumption during STANDBY Mode to a minimum of
10 µA by stopping the external oscillators and internal
clock. The SLEEP mode reduces power by placing the
CPU into a “stopped” state, thereby consuming less current while the on-chip I/O device is still operating. The
SYSTEM STOP mode places both the CPU and the onchip peripherals into a “stopped” mode, thereby reducing
power consumption even further.
A new clock doubler feature has been implemented in the
Z80180/Z8S180/Z8L180 device that allows the programmer to double the internal clock from that of the external
clock. This provides a systems cost savings by allowing
the use of lower cost, lower frequency crystals instead of
the higher cost, and higher speed oscillators.
The Enhanced Z180 is housed in 80-pin QFP, 68-pin
PLCC, and 64-pin DIP packages.
DS971800401
PRELIMINARY
1-1
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Power connections follow conventional descriptions below:
A18/TOUT
TXS
RXS/CTS1
INT2
INT1
INT0
/NMI
E
VSS
ST
GND
/RFSH
Ground
/BUSACK
VDD
/BUSREQ
VCC
/WAIT
Power
/HALT
Device
IORQ
/MREQ
/M1
/WR
/RD
Circuit
Bus State Control
Timing
Generator
Interrupt
CPU
16-bit
Programmable
Reload Timers
(2)
/DREQ1
DMACS
TEND1
(2)
TXA0
Clocked
Serial I/O
Port
Address Bus (16-Bit)
CKS
Connection
Asynchronous
SCI
(Channel 0)
Data Bus (8-Bit)
Ø
/RESET
XTAL
EXTAL
Notes: All Signals with a preceding front slash, “/” are active Low, for example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only). Alternatively, an overslash
may be used to signify active Low, for example WR
CKA0, /DREQ0
RXA0
/RTS0
/CTS0
/DCD0
TXA1
Asynchronous
SCI
(Channel 1)
MMU
Address
Buffer
Data
Buffer
A19-A0
D7-D0
CKA1, /TEND0
RXA1
VCC
VSS
Figure 1. Z80180/Z8S180/Z8L180 Functional Block Diagram
1-2
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
PIN DESCRIPTION
VSS
XTAL
EXTAL
/WAIT
/BUSACK
/BUSREQ
/RESET
/NMI
/INT0
/INT1
/INT2
ST
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18/TOUT
VCC
1
64
Z80180 64Pin DIP
32
33
1
PHI
/RD
/WR
/M1
E
/MREQ
/IORQ
/RFSH
/HALT
/TEND1
/DREQ
CKS
RXS//CTS
TXS
CKA1//TEND0
RXA1
TXA1
CKA//DREQ0
RXA0
TXA0
/DCD0
/CTS0
/RTS0
D7
D6
D5
D4
D3
D2
D1
D0
VSS
Figure 2. Z80180 64-Pin DIP Pin Configuration
DS971800401
PRELIMINARY
1-3
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
/NMI
/RESET
/BUSREQ
/BUSACK
/WAIT
EXTAL
XTAL
VSS
VSS
PHI
/RD
/WR
/M1
E
/MREQ
/IORQ
/RFSH
Zilog
/INT0
/INT1
/INT2
ST
A0
A1
A2
A3
VSS
A4
A5
A6
A7
A8
A9
A10
A11
9
10
1
61
60
Z80180/Z8S180/
Z8L180
68-Pin PLCC
43
A12
A13
A14
A15
A16
A17
A18/TOUT
VCC
A19
VSS
D0
D1
D2
D3
D4
D5
D6
27
/HALT
/TEND1
/DREQ1
CKS
RXS//CTS1
TXS
CKA1//TEND0
RXA1
TEST
TXA1
CKA0//DREQ0
RXA0
TXA0
/DCD0
/CTS0
/RTS0
D7
Figure 3. Z80180/Z8S180/Z8L180 68-Pin PLCC Pin Configuration
1-4
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
/RFSH
N/C
N/C
/HALT
/TEND1
/DREQ1
CKS
RXS/CTS1
TXS
CKA1//TEND0
RXA1
TEST
TXA1
N/C
CKA0//DREQ0
RXA0
TXA0
/DCD0
/CTS0
/RTS0
D7
N/C
N/C
D6
Zilog
64
/IORQ
/MREQ
E
/M1
/WR
/RD
PHI
VSS
VSS
XTAL
N/C
EXTAL
/WAIT
/BUSACK
/BUSREQ
/RESET
60
55
50
45
65
41
40
Z80180/Z8S180/Z8L180
80-Pin QFP
5
10
15
20
D5
D4
D3
D2
D1
D0
VSS
A19
VCC
A18/TOUT
NC
A17
A16
A15
A14
A13
24
/NMI
N/C
N/C
/INT0
/INT1
/INT2
ST
A0
A1
A2
A3
VSS
A4
N/C
A5
A6
A7
A8
A9
A10
A11
N/C
N/C
A12
1
1
Figure 4. Z80180/Z8S180/Z8L180 80-Pin QFP Pin Configuration
DS971800401
PRELIMINARY
1-5
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Table 1. Z80180/Z8S180/Z8L180 Pin Identification
Pin Number and Package Type
1-6
QFP
PLCC
DIP
Default Function
1
2
3
4
5
6
7
8
9
10
11
12
9
8
10
11
12
13
14
15
16
17
18
9
10
11
12
13
14
15
16
/NMI
NC
NC
/INT0
/INT1
/INT2
ST
A0
A1
A2
A3
VSS
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
19
17
20
21
22
23
24
25
26
18
19
20
21
22
23
24
27
28
29
30
31
32
25
26
27
28
29
30
33
31
A4
NC
A5
A6
A7
A8
A9
A10
A11
NC
NC
A12
A13
A14
A15
A16
A17
NC
A18
32
34
32
VCC
33
34
35
36
33
A19
VSS
35
36
37
38
39
40
41
42
43
44
45
37
38
39
40
41
42
43
34
35
36
37
38
39
40
44
45
41
42
Secondary
Function
Control
/TOUT
Bit 2 or Bit 3 of TCR
D0
D1
D2
D3
D4
D5
D6
NC
NC
D7
/RTS0
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Table 1. Z80180/Z8S180/Z8L180 Pin Identification
Pin Number and Package Type
QFP
PLCC
DIP
Default Function
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
46
47
48
49
50
43
44
45
46
47
51
52
53
54
55
56
57
58
59
60
48
61
62
63
64
65
66
67
68
1
57
58
59
60
61
62
63
64
1
/CTS0
/DCD0
TXA0
RXA0
CKA0
NC
TXA1
TEST
RXA1
CKA1
TXS
RXS
CKS
/DREQ1
/TEND1
/HALT
NC
NC
/RFSH
/IORQ
/MREQ
E
M1
/WR
/RD
PHI
VSS
73
2
74
75
76
77
78
79
80
3
2
4
5
6
7
8
3
4
5
6
7
DS971800401
49
50
51
52
53
54
55
56
Secondary
Function
Control
/DREQ0
Bit 3 or Bit 5 of DMODE
/TEND0
Bit 4 of CNTLA1
/CTS1
Bit 2 of STAT1
1
VSS
XTAL
NC
EXTAL
/WAIT
/BUSACK
/BUSREQ
/RESET
PRELIMINARY
1-7
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Table 2. Pin Status During RESET BUSACK and SLEEP
Pin Number and Package Type
1-8
Pin Status
Default
Function
Secondary
Function
RESET
BUSACK
SLEEP
IN
IN
IN
IN
IN
IN
1
3T
3T
3T
3T
GND
IN
IN
IN
?
3T
3T
3T
3T
GND
IN
IN
IN
1
1
1
1
1
GND
3T
3T
1
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
1
1
1
1
1
1
1
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
1
1
1
1
1
1
3T
3T
1
VCC
VCC
VCC
VCC
A19
VSS
3T
GND
3T
GND
1
GND
D0
D1
D2
D3
D4
D5
D6
NC
NC
D7
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
3T
QFP
PLCC
DIP
1
2
3
4
5
6
7
8
9
10
11
12
9
8
10
11
12
13
14
15
16
17
18
9
10
11
12
13
14
15
16
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
19
17
20
21
22
23
24
25
26
18
19
20
21
22
23
24
27
28
29
30
31
32
25
26
27
28
29
30
33
31
A4
NC
A5
A6
A7
A8
A9
A10
A11
NC
NC
A12
A13
A14
A15
A16
A17
NC
A18
32
34
32
33
34
35
36
33
35
36
37
38
39
40
41
42
43
44
37
38
39
40
41
42
43
34
35
36
37
38
39
40
44
41
/NMI
NC
NC
/INT0
/INT1
/INT2
ST
A0
A1
A2
A3
VSS
/TOUT
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Table 2. Pin Status During RESET BUSACK and SLEEP
Pin Number and Package Type
QFP
PLCC
DIP
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
45
46
47
48
49
50
42
43
44
45
46
47
51
52
53
54
55
56
57
58
59
60
48
61
62
63
64
65
66
67
68
1
57
58
59
60
61
62
63
64
1
73
2
74
75
76
77
78
79
80
3
2
4
5
6
7
8
3
4
5
6
7
DS971800401
49
50
51
52
53
54
55
56
Pin Status
Default
Function
1
Secondary
Function
RESET
BUSACK
SLEEP
/DREQ0
1
IN
IN
1
IN
3T
OUT
OUT
IN
OUT
IN
OUT
1
IN
IN
OUT
IN
OUT
1
OUT
OUT
IN
3T
1
IN
3T
IN
1
1
IN
IN
OUT
IN
I/O
3T
OUT
1
IN
IN
OUT
IN
I/O
IN
1
0
1
1
1
0
1
1
1
OUT
GND
OUT
3T
3T
OUT
1
3T
3T
OUT
GND
OUT
1
1
OUT
1
1
1
OUT
GND
VSS
GND
GND
GND
XTAL
NC
EXTAL
/WAIT
/BUSACK
/BUSREQ
/RESET
OUT
OUT
OUT
IN
IN
1
IN
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
/RTS0
/CTS0
/DCD0
TXA0
RXA0
CKA0
NC
TXA1
TEST
RXA1
CKA1
TXS
RXS
CKS
/DREQ1
/TEND1
/HALT
NC
NC
/RFSH
/IORQ
/MREQ
E
/M1
/WR
/RD
PHI
VSS
/TEND0
/CTS1
PRELIMINARY
1-9
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
PIN DESCRIPTIONS
A0-A19. Address Bus (Output, active High, tri-state). A0A19 form a 20-bit address bus. The Address Bus provides
the address for memory data bus exchanges, up to 1 MB,
and I/O data bus exchanges, up to 64K. The address bus
enters a high-impedance state during reset and external
bus acknowledge cycles. Address line A18 is multiplexed
with the output of PRT channel 1 (TOUT, selected as address output on reset) and address line A19 is not available in DIP versions of the Z80180.
BUSACK. Bus Acknowledge (Output, active Low).
/BUSACK indicated the requesting device, the MPU address and data bus, and some control signals, have entered their high-impedance state.
/BUSREQ. Bus Request (Input, active Low). This input is
used by external devices (such as DMA controllers) to request access to the system bus. This request has a higher
priority than /NMI and is always recognized at the end of
the current machine cycle. This signal will stop the CPU
from executing further instructions and places address and
data buses, and other control signals, into the high-impedance state.
CKA0, CKA1. Asynchronous Clock 0 and 1 (Bidirectional,
active High). When in output mode, these pins are the
transmit and receive clock outputs from the ASCI baud
rate generators. When in input mode, these pins serve as
the external clock inputs for the ASCI baud rate generators. CKA0 is multiplexed with /DREQ0, and CKA1 is multiplexed with /TEND0.
CKS. Serial Clock (Bidirectional, active High). This line is
clock for the CSIO channel.
PHI CLOCK. System Clock (Output, active High). The output is used as a reference clock for the MPU and the external system. The frequency of this output is equal to onehalf that of the crystal or input clock frequency.
/CTS0 - /CTS1. Clear to send 0 and 1 (Inputs, active Low).
These lines are modem control signals for the ASCI channels. /CTS1 is multiplexed with RXS.
D0 - D7. Data Bus = (Bidirectional, active High, tri-state).
D0 - D7 constitute an 8-bit bi-directional data bus, used for
the transfer of information to and from I/O and memory devices. The data bus enters the high-impedance state during reset and external bus acknowledge cycles.
DCD0. Data Carrier Detect 0 (Input, active Low). This is a
programmable modem control signal for ASCI channel 0.
/DREQ0, /DREQ1. DMA Request 0 and 1 (Input, active
Low). /DREQ is used to request a DMA transfer from one
of the on-chip DMA channels. The DMA channels monitor
these inputs to determine when an external device is ready
1-10
for a read or write operation. These inputs can be programmed to be either level or edge sensed. /DREQ0 is
multiplexed with CKA0.
E. Enable Clock (Output, active High). Synchronous machine cycle clock output during bus transactions.
EXTAL. External Clock Crystal (Input, active High). Crystal oscillator connections. An external clock can be input to
the Z80180/Z8S180/Z8L180 on this pin when a crystal is
not used. This input is Schmitt triggered.
/HALT. Halt/SLEEP (Output, active Low). This output is
asserted after the CPU has executed either the HALT or
SLP instruction, and is waiting for either non-maskable or
maskable interrupt before operation can resume. It is also
used with the /M1 and ST signals to decode status of the
CPU machine cycle.
/INT0. Maskable Interrupt Request 0 (Input, active Low).
This signal is generated by external I/O devices. The CPU
will honor these requests at the end of the current instruction cycle as long as the /NMI and /BUSREQ signals are
inactive. The CPU acknowledges this interrupt request
with an interrupt acknowledge cycle. During this cycle,
both the /M1 and /IORQ signals will become active.
/INT1, /INT2. Maskable Interrupt Request 1 and 2 (Inputs,
active Low). This signal is generated by external I/O devices. The CPU will honor these requests at the end of the
current instruction cycle as long as the /NMI, /BUSREQ,
and /INT0 signals are inactive. The CPU will acknowledge
these requests with an interrupt acknowledge cycle. Unlike
the acknowledgment for /INT0, during this cycle neither
the /M1 or /IORQ signals will become active.
/IORQ. I/O Request (Output, active Low, tri-state). /IORQ
indicates that the address bus contains a valid I/O address
for an I/O read or I/O write operation. /IORQ is also generated, along with /M1, during the acknowledgment of the
/INT0 input signal to indicate that an interrupt response
vector can be place onto the data bus. This signal is analogous to the /IOE signal of the Z64180.
/M1. Machine Cycle 1 (Output, active Low). Together with
/MREQ, /M1 indicates that the current cycle is the Opcode
fetch cycle of and instruction execution. Together with
/IORQ, /M1 indicates that the current cycle is for an interrupt acknowledge. It is also used with the /HALT and ST
signal to decode status of the CPU machine cycle. This
signal is analogous to the /LIR signal of the Z64180.
/MREQ. Memory Request (Output, active Low, tri-state).
/MREQ indicates that the address bus holds a valid address for a memory read or memory write operation. This
signal is analogous to the /ME signal of Z64180.
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
/NMI. Non-maskable Interrupt (Input, negative edge triggered). /NMI has a higher priority than /INT and is always
recognized at the end of an instruction, regardless of the
state of the interrupt enable flip-flops. This signal forces
CPU execution to continue at location 0066H.
/RD. ReOpcoded (Output, active Low, tri-state). /RD indicated that the CPU wants to read data from memory or an
I/O device. The addressed I/O or memory device should
use this signal to gate data onto the CPU data bus.
/RFSH. Refresh (Output, active Low). Together with
/MREQ, /RFSH indicates that the current CPU machine
cycle and the contents of the address bus should be used
for refresh of dynamic memories. The low order 8 bits of
the address bus (A7 - A10) contain the refresh address.
This signal is analogous to the /REF signal of the
Z64180.
/RTS0. Request to Send 0 (Output, active Low). This is a
programmable modem control signal for ASCI channel 0.
RXA0, RXA1. Receive Data 0 and 1 (Input, active High).
These signals are the receive data to the ASCI channels.
RXS. Clocked Serial Receive Data (Input, active High).
This line is the receiver data for the CSIO channel. RXS is
multiplexed with the /CTS1 signal for ASCI channel 1.
ST. Status (Output, active High). This signal is used with
the /M1 and /HALT output to decode the status of the CPU
machine cycle.
TOUT. Timer Out (Output, active High). TOUT is the pulse
output from PRT channel 1. This line is multiplexed with
A18 of the address bus.
TXA0, TXA1. Transmit Data 0 and 1 (Outputs, active
High). These signals are the transmitted data from the
ASCI channels. Transmitted data changes are with respect to the falling edge of the transmit clock.
TXS. Clocked Serial Transmit Data (Output, active High).
This line is the transmitted data from the CSIO channel.
/WAIT. Wait (Input, active Low). /WAIT indicated to the
MPU that the addressed memory or I/O devices are not
ready for a data transfer. This input is sampled on the falling edge of T2 (and subsequent wait states). If the input is
sampled Low, then the additional wait states are inserted
until the /WAIT input is sampled high, at which time execution will continue.
/WR. Write (Output, active Low, tri-state). /WR indicated
that the CPU data bus holds valid data to be stored at the
addressed I/O or memory location.
XTAL. Crystal (Input, active High). Crystal oscillator connection. This pin should be left open if an external clock is
used instead of a crystal. The oscillator input is not a TTL
level (reference DC characteristics).
Several pins are used for different conditions, depending
on the circumstance.
Multiplexed Pin Descriptions
Table 3. Status Summary
ST
/HALT
/M1
0
1
0
1
1
0
1
1
1
0
0
1
X
0
0
1
0
1
A18 / /TOUT
Operation
CPU Operation
(1st opcode fetch)
CPU Operation (2nd opcode and
3rd Opcode fetch)
CPU Operation
(MC except for Opcode fetch)
DMA Operation
HALT Mode
SLEEP Mode
(including SYSTEM STOP Mode)
Notes:
X = Reserved
MC = Machine Cycle
/TEND0, /TEND1. Transfer End 0 and 1 (Outputs, active
Low). This output is asserted active during the last write
cycle of a DMA operation. It is used to indicate the end of
the block transfer. /TEND0 is multiplexed with CKA1.
During RESET, this pin is initialized as
A18 pin. If either TOC1 or TOC0 bit of
the Timer Control Register (TCR) is set
to 1, TOUT function is selected. If
TOC1 and TOC0 are cleared to 0, A18
function is selected.
CKA0 / /DREQ0 During RESET, this pin is initialized as
CKA0 pin. If either DM1 or SM1 in
DMA Mode Register (DMODE) is set to
1, /DREQ0 function is always selected.
CKA1 / /TEND0 During RESET, this pin is initialized as
CKA1 pin. If CKA1D bit in ASCI control
register ch1 (CNTLA1) is set to 1,
/TEND0 function is selected. If CKA1D
bit is set to 0, CKA1 function is
selected.
RXS / /CTS1
During RESET, this pin is initialized as
RXS pin. If CTS1E bit in ASCI status
register ch1 (STAT1) is set to 1, /CTS1
function is selected. If CTS1E bit is set
to 0, RXS function is selected.
TEST. Test (Output, not in DIP version). This pin is for test
and should be left open.
DS971800401
PRELIMINARY
1-11
1
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
ARCHITECTURE
The Z180® combines a high-performance CPU core with a
variety of system and I/O resources useful in a broad
range of applications. The CPU core consists of five functional blocks: clock generator, bus state controller, Interrupt controller, memory management unit (MMU), and the
central processing unit (CPU). The integrated I/O resources make up the remaining four function blocks: direct
memory access (DMA) control (2 channels), asynchronous serial communication interface (ASCI, 2 channels)
programmable reload timers (PRT, 2 channels), and a
clock serial I/O (CSIO) channel.
Clock Generator. Generates system clock from an external crystal or clock input. The external clock is divided by
two or one and provided to both internal and external devices.
Bus State Controller. This logic performs all of the status
and bus control activity associated with both the CPU and
some on-chip peripherals. This includes wait-state timing,
reset cycles, DRAM refresh, and DMA bus exchanges.
Interrupt Controller. This logic monitors and prioritizes
the variety of internal and external interrupts and traps to
provide the correct responses from the CPU. To maintain
compatibility with the Z80® CPU, three different interrupts
modes are supported.
Central Processing Unit. The CPU is microcoded to provide a core that is object-code compatible with the Z80
CPU. It also provides a superset of the Z80 instruction set,
including 8-bit multiply. The core has been modified to allow many of the instructions to execute in fewer clock cycles.
DMA Controller. The DMA controller provides high speed
transfers between memory and I/O devices. Transfer operations supported are memory-to-memory, memory
to/from I/O, and I/O-to-I/O. Transfer modes supported are
request, burst, and cycle steal. DMA transfers can access
the full 1 MB address range with a block length up to 64
KB, and can cross over 64K boundaries.
Asynchronous Serial Communication Interface (ASCI). The ASCI logic provides two individual full-duplex
UARTs. Each channel includes a programmable baud rate
generator and modem control signals. The ASCI channels
can also support a multiprocessor communication format
as well as break detection and generation.
Programmable Reload Timers (PRT). This logic consists
of two separate channels, each containing a 16-bit counter
(timer) and count reload register. The time base for the
counters is derived from the system clock (divided by 20)
before reaching the counter. PRT channel 1 provides an
optional output to allow for waveform generation.
Memory Management Unit. The MMU allows the user to
“map” the memory used by the CPU (logically only 64KB)
into the 1 MB addressing range supported by the
Z80180/Z8S180/Z8L180. The organization of the MMU
object code maintains compatibility with the Z80 CPU,
while offering access to an extended memory space. This
is accomplished by using an effective “common areabanked area” scheme.
1-12
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Timer Data Register
Write (0004H)
Reset
Timer Data
Register
FFFFH
0004H
0 < t < 20 φ
20 φ
20 φ
0003H 0002H
20 φ
20 φ
FFFFH
20 φ
20 φ
20 φ
1
20 φ
0001H 0000H 0003H 0002H 0001H 0000H 0003H
Timer Reload Register Write (0003H)
Timer Reload
Register
20 φ
Reload
Reload
0003H
Write “1” to TDE
TDE Flag
TIF Flag
Timer Data Register Read
Timer Control Requestor Read
Figure 5. Timer Initialization, Count Down, and Reload Timing
φ
Timer Data
Reg. = 0001H
Timer Data
Reg. = 0000H
TOUT
Figure 6. Timer Output Timing
DS971800401
PRELIMINARY
1-13
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Clocked Serial I/O (CSI/O). The CSIO channel provides a
half-duplex serial transmitter and receiver. This channel
can be used for simple high-speed data connection to another microprocessor or microcomputer. TRDR is used for
both CSI/O transmission and reception. Thus, the system
design must ensure that the constraints of half-duplex operation are met (Transmit and Receive operation cannot
occur simultaneously). For example, if a CSI/O transmis-
sion is attempted while the CSI/O is receiving data, a
CSI/O will not work. Also note that TRDR is not buffered.
Therefore, attempting to perform a CSI/O transmit while
the previous transmit data is still being shifted out causes
the shift data to be immediately updated, thereby corrupting the transmit operation in progress. Similarly, reading
TRDR while a transmit or receive is in progress should be
avoided.
Internal Address/Data Bus
φ
Baud Rate
Generator
CSI/O Transmit/Receive
Data Register:
TRDR (8)
TXS
RXS
CKS
CSI/O Control Register:
CNTR (8)
Interrupt Request
Figure 7. CSIO Block Diagram
OPERATION MODES
Z80®
versus
64180
Compatibility.
The
Z80180/Z8S180/Z8L180 is descended from two different
“ancestor” processors, Zilog's original Z80 and the Hitachi
64180. The Operating Mode Control Register (OMCR),
shown in Figure 8, can be programmed to select between
certain Z80 and 64180differences.
D7 D6 D5 --
-- --
-- -Reserved
/IOC (R/W)
/M1TE (W)
M1E (R/W)
Figure 8. Operating Control Register
(OMCR: I/O Address = 3EH)
1-14
M1E (M1 Enable). This bit controls the M1 output and is
set to a 1 during reset.
When M1E=1, the M1 output is asserted Low during the
opcode fetch cycle, the INT0 acknowledge cycle, and the
first machine cycle of the NMI acknowledge.
On the Z80180/Z8S180/Z8L180, this choice makes the
processor fetch an RETI instruction once, and when fetching an RETI from zero-wait-state memory will use three
clock machine cycles, which are not fully Z80-timing compatible but are compatible with the on-chip CTCs.
When M1E=0, the processor does not drive M1 Low during
instruction fetch cycles, and after fetching an RETI instruction once with normal timing, it goes back and re-fetches
the instruction using fully Z80-compatible cycles that include driving M1 Low. This may be needed by some external Z80 peripherals to properly decode the RETI instruction. Figure 9 and Table 4 show the RETI sequence when
M1E=0.
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
φ
A0-A18 (A19)
T1
T2
T3
T1
T2
T3
TI
TI
TI
T1
T2
T3
PC+1
PC
EDH
TI
T1
T2
PC
4DH
T3
TI
1
PC+1
4DH
EDH
D0-D7
M1
MREQ
RD
ST
Figure 9. RETI Instruction Sequence with MIE=0
Table 4. RETI Control Signal States with MIE=0
Machine
Cycle States
1
2
3
4
5
6
T1-T3
T1-T3
Ti
Ti
Ti
T1-T3
Ti
T1-T3
T1-T3
T1-T3
Address
Data
1st Opcode
2nd Opcode
NA
NA
NA
1st Opcode
NA
2nd Opcode
SP
SP+1
EDH
4DH
Tri-State
Tri-State
Tri-State
EDH
Tri-State
4DH
Data
Data
RD
WR
MREQ
IORQ
0
0
1
1
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
M1TE (M1 Temporary Enable). This bit controls the temporary assertion of the /M1 signal. It is always read back
as a 1 and is set to 1 during reset.
When M1E is set to 0 to accommodate certain external
Z80 peripheral(s), those same device(s) may require a
pulse on M1 after programming certain of their registers to
complete the function being programmed.
DS971800401
M1
IOC=1 IOC=0
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
0
1
1
1
1
HALT
ST
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
For example, when a control word is written to the Z80 PIO
to enable interrupts, no enable actually takes place until
the PIO sees an active M1 signal. When M1TE=1, there is
no change in the operation of the /M1 signal and M1E controls its function. When M1TE=0, the M1 output will be asserted during the next opcode fetch cycle regardless of the
state programmed into the M1E bit. This is only momentary (one time) and the user need not preprogram a 1 to
disable the function (see Figure10).
PRELIMINARY
1-15
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
T1
T2
T3
T1
T2
T3
φ
/WR
/M1
Write into OMCR
Opcode Fetch
Figure 10. M1 Temporary Enable Timing
IOC. This bit controls the timing of the /IORQ and /RD signals. It is set to 1 by reset.
T1
T2
When /IOC=1, the /IORQ and /RD signals function the
same as the Z64180 (Figure 11).
TW
T3
φ
/IORQ
/RD
/WR
Figure 11. I/O Read and Write Cycles with IOC = 1
When /IOC = 0, the timing of the /IORQ and RD signals
match the timing of the Z80. The /IORQ and /RD signals
T1
T2
go active as a result of the rising edge of T2. (Figure 12.)
TW
T3
φ
/IORQ
/RD
/WR
Figure 12. I/O Read and Write Cycles with IOC = 0
1-16
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
HALT and Low-Power Operating Modes. The
Z80180/Z8S180/Z8L180 can operate in seven modes with
respect to activity and power consumption:
–
–
–
–
–
–
–
Normal Operation
HALT Mode
IOSTOP Mode
SLEEP Mode
SYSTEM STOP Mode
IDLE Mode
STANDBY Mode (with
RECOVERY)
or
without
QUICK
Normal Operation. The Z80180/Z8S180/Z8L180 processor is fetching and running a program. All enabled functions and portions of the device are active, and the HALT
pin is High.
HALT Mode. This mode is entered by the HALT instruction. Thereafter, the Z80180/Z8S180/Z8L180 processor
continually fetches the following opcode but does not execute it, and drives the HALT, ST and M1 pins all Low. The
oscillator and PHI pin remain active, interrupts and bus
granting to external masters, and DRAM refresh can occur
and all on-chip I/O devices continue to operate including
the DMA channels.
The Z80180/Z8S180/Z8L180 leaves HALT mode in response to a Low on RESET, on to an interrupt from an enabled on-chip source, an external request on NMI, or an
enabled external request on INT0, INT1, or INT2. In case
of an interrupt, the return address will be the instruction following the HALT instruction; at that point the program can
either branch back to the HALT instruction to wait for another interrupt, or can examine the new state of the system/application and respond appropriately.
INTi, NMI
A0-A19
HALT Opcode Address
HALT Opcode Address + 1
/HALT
/M1
/MREQ
/RD
Figure 13. HALT Timing
SLEEP Mode. This mode is entered by keeping the
IOSTOP bit (ICR5) bits 3 and 6 of the CPU Control Register (CCR3, CCR6) all zero and executing the SLP instruction. The oscillator and PHI output continue operating, but
are blocked from the CPU core and DMA channels to reduce power consumption. DRAM refresh stops but interrupts and granting to external master can occur. Except
when the bus is granted to an external master, A19-0 and
all control signals except /HALT are maintained High.
/HALT is Low. I/O operations continue as before the SLP
instruction, except for the DMA channels.
DS971800401
The Z80180/Z8S180/Z8L180 leaves SLEEP mode in response to a low on /RESET, an interrupt request from an
on-chip source, an external request on /NMI, or an external
request on /INT0, 1, or 2.
PRELIMINARY
1-17
1
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
If an interrupt source is individually disabled, it cannot
bring the Z80180/Z8S180/Z8L180 out of SLEEP mode. If
an interrupt source is individually enabled, and the IEF bit
is 1 so that interrupts are globally enabled (by an EI instruction), the highest priority active interrupt will occur,
with the return address being the instruction after the SLP
instruction. If an interrupt source is individually enabled,
but the IEF bit is 0 so that interrupts are globally disabled
(by a DI instruction), the Z80180/Z8S180/Z8L180 leaves
SLP 2nd Opcode
Fetch Cycle
φ
T2
T3
SLEEP mode by simply executing the following instruction(s).
This provides a technique for synchronization with highspeed external events without incurring the latency imposed by an interrupt response sequence. Figure 14
shows the timing for exiting SLEEP mode due to an interrupt request. Note that the Z80180/Z8S180/Z8L180 takes
about 1.5 clocks to restart.
Opcode Fetch or Interrupt
Acknowledge Cycle
SLEEP Mode
T1
T2
TS
TS
T1
T2
T3
/INTi, /NMI
A0-A19
SLP 2nd Opcode Address
FFFFFH
/HALT
M1
Figure 14. SLEEP Timing
IOSTOP Mode. IOSTOP mode is entered by setting the
IOSTOP bit of the I/O Control Register (ICR) to 1. In this
case, on-chip I/O (ASCI, CSI/O, PRT) stops operating.
However, the CPU continues to operate. Recovery from
IOSTOP mode is by resetting the IOSTOP bit in ICR to 0.
SYSTEM STOP Mode. SYSTEM STOP mode is the combination of SLEEP and IOSTOP modes. SYSTEM STOP
mode is entered by setting the IOSTOP bit in ICR to 1 followed by execution of the SLP instruction. In this mode,
on-chip I/O and CPU stop operating, reducing power consumption, but the PHI output continues to operate. Recovery from SYSTEM STOP mode is the same as recovery
from SLEEP mode except that internal I/O sources (disabled by IOSTOP) cannot generate a recovery interrupt.
IDLE
Mode.
Software
can
put
the
Z80180/Z8S180/Z8L180 into this mode by setting the
IOSTOP bit (ICR5) to 1, CCR6 to 0, CCR3 to 1 and executing the SLP instruction. The oscillator keeps operating
but its output is blocked to all circuitry including the PHI
pin. DRAM refresh and all internal devices stop, but external interrupts can occur. Bus granting to external masters
can occur if the BREST bit in the CPU control Register
(CCR5) was set to 1 before IDLE mode was entered.
The Z80180/Z8S180/Z8L180 leaves IDLE mode in response to a Low on RESET, an external interrupt request
on NMI, or an external interrupt request on /INT0, /INT1 or
/INT2 that is enabled in the INT/TRAP Control Register. As
previously described for SLEEP mode, when the
Z80180/Z8S180/Z8L180 leaves IDLE mode due to an
NMI, or due to an enabled external interrupt request when
the IEF flag is 1 due to an EI instruction, it starts by performing the interrupt with the return address being that of
the instruction after the SLP instruction.
If an external interrupt enables the INT/TRAP control register while the IEF1 bit is 0, Z80180/Z8S180/Z8L180
leaves IDLE mode; specifically, the processor restarts by
executing the instructions following the SLP instruction.
1-18
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Figure 15 shows the timing for exiting IDLE mode due to
an
interrupt
request.
Note
that
the
Z80180/Z8S180/Z8L180 takes about 9.5 clocks to restart.
1
Opcode Fetch or Interrupt
Acknowledge Cycle
IDLE Mode
T1
φ
T2
T3
T4
9.5 Cycle Delay from INTi Asserted
NMI
or
INTi
A19-A0
FFFFFH
HALT
M1
Figure 15. Z80180/Z8S180/Z8L180 IDLE Mode Exit due to External Interrupt
While the Z80180/Z8S180/Z8L180 is in IDLE mode, it will
grant the bus to an external master if the BREXT bit
(CCR5) is 1. Figure 16 shows the timing for this sequence.
Note that the part takes 8 clock cycles longer to respond to
the Bus Request than in normal operation.
DS971800401
After the external master negates the Bus Request, the
Z80180/Z8S180/Z8L180 disables the PHI clock and remains in IDLE mode.
PRELIMINARY
1-19
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Bus RELEASE Mode IDLE Mode
IDLE Mode
TX
φ
TX
9.5 Cycle Delay until BUSACK Asserted
BUSREQ
BUSACK
A19-A0
FFFFFH
FFFFFH
High Impedance
High
HALT
Low
M1
Figure 16. Bus Granting to External Master in IDLE Mode
STANDBY Mode (With or Without QUICK RECOVERY).
Software can put the Z80180/Z8S180/Z8L180 into this
mode by setting the IOSTOP bit (ICR5) to 1 and CCR6 to
1, and executing the SLP instruction. This mode stops the
on-chip oscillator and thus draws the least power of any
mode, less than 10µµA.
As with IDLE mode, the Z80180/Z8S180/Z8L180 will leave
STANDBY mode in response to a Low on RESET or on
NMI, or a Low on INT0-2 that is enabled by a 1 in the corresponding bit in the INT/TRAP Control Register, and will
grant the bus to an external master if the BREXT bit in the
CPU Control Register (CCR5) is 1. But the time required
for all of these operations is greatly increased by the need
to restart the on-chip oscillator and ensure that it has stabilized to square-wave operation.
When an external clock is connected to the EXTAL pin
rather than a crystal to the XTAL and EXTAL pins, and the
external clock runs continuously, there is little need to use
STANDBY mode because there is no time required to restart the oscillator, and other modes restart faster. However, if external logic stops the clock during STANDBY mode
(for example, by decoding HALT Low and M1 High for several clock cycles), then STANDBY mode can be useful to
allow the external clock source to stabilize after it is re-enabled.
When external logic drives RESET Low to being a
Z80180/Z8S180/Z8L180 out of STANDBY mode, and a
1-20
crystal is used or an external clock source has been
stopped, the external logic must hold RESET Low until the
on-chip oscillator or external clock source has restarted
and stabilized.
The
clock
stability
requirements
of
the
Z80180/Z8S180/Z8L180 are much less in the divide-bytwo mode that's selected by a Reset sequence and thereafter controlled by the Clock Divide bit in the CPU Control
Register (CCR7). Because of this, software should:
a. Program CCR7 to 0 to select divide-by-two mode,
before the SLP instruction that enters STANDBY
mode, and.
b. After a Reset, interrupt or in-line restart after the
SLP 01 instruction, delay programming CCR7
back to 1 to set divide-by-one mode, as long as
possible to allow additional clock stabilization
time.
If software sets CCR6 to 1 before the SLP instruction places the MPU in STANDBY mode, the value in the CCR3 bit
determines how long the Z80180/Z8S180/Z8L180 will wait
for oscillator restart and stabilization when it leaves
STANDBY mode due to an external interrupt request. If
CCR3 is 0, the Z80180/Z8S180/Z8L180 waits 217
(131,072) clock cycles, while if CCR3 is 1, it waits only 64
clock cycles. The latter is called QUICK RECOVERY
mode. The same delay applies to granting the bus to an
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
external master during STANDBY mode, when the BREXT
bit in the CPU Control Register (CCR5) is 1.
As described previously for SLEEP and IDLE modes,
when a Z80180/Z8S180/Z8L180 leaves STANDBY mode
due to NMI Low, or when it leaves STANDBY mode due to
an enabled INTO-2 low when the IEF, flag is 1 due to an
IE instruction, it starts by performing the interrupt with the
return address being that of the instruction following the
SLP instruction. If the Z80180/Z8S180/Z8L180 leaves
STANDBY mode due to an external interrupt request that's
enabled in the INT/TRAP Control Register, but the IEF, bit
is 0 due to a DI instruction, the processor restarts by executing the instruction(s) following the SLP instruction. If
INT0, or INT1 or 2 goes inactive before the end of the clock
stabilization delay, the Z80180/Z8S180/Z8L180 stays in
STANDBY mode.
Figure 17 shows the timing for leaving STANDBY mode
due to an interrupt request. Note that the
Z80180/Z8S180/Z8L180 takes either 64 or 217 (131,072)
clocks to restart, depending on the CCR3 bit.
Opcode Fetch or Interrupt
Acknowledge Cycle
STANDBY Mode
T1
φ
T2
T3
T4
217 or 64 Cycle Delay from INTi Asserted
NMI
or
INTi
A19-A0
FFFFFH
HALT
M1
Figure 17. Z80180/Z8S180/Z8L180 STANDBY Mode Exit due to External Interrupt
While the Z80180/Z8S180/Z8L180 is in STANDBY mode,
it will grant the bus to an external master if the BREXT bit
(CCR5) is 1. Figure 18 shows the timing of this sequence.
Note that the part takes 64 or 217 (131,072) clock cycles
to grant the bus depending on the CCR3 bit.
DS971800401
The latter (non-Quick-Recovery) case may be prohibitive
for many “demand driven” external masters. If so, QUICK
RECOVERY or IDLE mode can be used.
PRELIMINARY
1-21
1
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Bus Release Mode
STANDBY Mode
TX
φ
STANDBY Mode
TX
64 or 217 Cycle Delay after BUSREQ Asserted
BUSREQ
BUSACK
A19-A0
FFFFFH
FFFFFH
Low
HALT
High
M1
Figure 18. Bus Granting to External Master During STANDBY Mode
1-22
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
STANDARD TEST CONDITIONS
The DC Characteristics and Capacitance sections above
apply to the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (0V).
Positive current flows in to the referenced pin.
All AC parameters assume a load capacitance of 100 pF.
Add 10 ns delay for each 50 pF increase in load up to a
maximum of 200 pF for the data bus and 100 pF for the address and control lines. AC timing measurements are referenced to 1.5 volts (except for CLOCK, which is referenced to the 10% and 90% points). The Ordering
Information section lists temperature ranges and product
numbers. Package drawings are in the Package Information section. Refer to the Literature List for additional documentation.
+5 V
1
2.1k
From Output
Under Test
100 pF
250
µA
Figure 19. AC Load Capacitance Parameters
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply Voltage
Vcc
-0.3 ~ +7.0
V
Input Voltage
Vin
-0.3 ~ Vcc +0.3
V
Operating Temperature
Topr
0 ~ 70
°C
Extended Temperature
Text
-40 ~ 85
°C
Storage Temperature
Tstg
-55 ~ +150
°C
Note: Permanent LSI damage may occur if maximum
ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions
are exceeded, it could affect reliability of LSI.
DS971800401
PRELIMINARY
1-23
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DC CHARACTERISTICS
Note: Vcc = 5V + 10%, V ss = 0V over specified temperature range unless otherwise noted.
Symbol
Item
VIH1
Input “H” Voltage
/RESET, EXTAL, /NMI
Input “H” Voltage
Except /RESET, EXTAL, /NMI
Input “H” Voltage
Except CKS, CKA0, CKA1
Input “L” Voltage
/RESET, EXTAL, /NMI
Input “L” Voltage
Except /RESET, EXTAL, /NMI
Outputs “H” Voltage
All outputs
VIH2
VIH3
VIL1
VIL2
VOH
VOL
IIL
ITL
ICC*
Outputs “L” Voltage
All outputs
Input Leakage
Current All Inputs
Except XTAL, EXTAL
Three State Leakage
Current
Power Dissipation*
(Normal Operation)
Power Dissipation*
(SYSTEM STOP mode)
CP
Pin Capacitance
Condition
Min.
Typ.
Max.
Unit
Vcc -0.6
–
Vcc +0.3
V
2.0
–
Vcc +0.3
V
2.4
–
Vcc +0.3
V
-0.3
–
0.6
V
-0.3
–
0.8
V
IOH = -200 µA
2.4
–
–
V
IOH = -20 µA
Vcc -1.2
–
–
IOL = -2.2 µA
–
–
0.45
V
VIN = 0.5 ~ Vcc -0.5
–
–
1.0
µA
VIN = 0.5 ~ Vcc -0.5
–
–
1.0
µA
F = 6 MHz
F = 8 MHz
F = 10 MHz**
F = 6 MHz
F = 8 MHz
F = 10 MHz**
VIN = 0V, f = 1 MHz
Ta = 25° C
–
–
–
–
–
–
–
15
20
25
3.8
5
6.3
–
40
50
60
12.5
15
17.5
12
MA
pF
Note: **
VIHmin = VCC -1.0V, VILmax = 0.8V (all output terminals are at no load.) VCC = 5.0V
1-24
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
AC CHARACTERISTICS
Vcc = 5V + 10%, V ss = 0V, TA - 0 to +70° C, unless otherwise noted.
Z80180-6
No.
Symbol Item
Z80180-8
1
Z80180-10
Min.
Max.
Min.
Max.
Min.
Max.
Unit
1.
tcyc
Clock Cycle Time
162
2000
125
2000
100
2000
ns
2.
tCHW
Clock “H” Pulse Width
65
–
50
–
40
–
ns
3.
tCLW
Clock “L” Pulse Width
65
–
50
–
40
–
ns
4.
tcf
Clock Fall Time
–
15
–
15
–
10
ns
5.
tcr
Clock Rise Time
–
15
–
15
–
10
ns
6.
tAD
ØRise to Address Valid Delay
–
90
–
80
–
70
ns
7.
tAS
Address Valid to /MREQ Fall or /IORQ Fall)
30
–
20
–
10
–
ns
8.
tMED1
Ø Fall to /MREQ Fall Delay
–
60
–
50
–
50
ns
9.
tRDD1
Ø Fall to /RD Fall Delay
–
60
–
50
–
50
ns
–
65
–
60
–
55
10.
tM1D1
Ø Rise to /M1 Fall Delay
–
80
–
70
–
60
ns
11.
tAH
Address Hold Time from
(/MREQ, /IOREQ, /RD, /WR)
35
–
20
–
10
–
ns
12.
tMED2
Ø Fall to /MREQ Rise Delay
–
60
–
50
–
50
ns
13.
tRDD2
Ø Fall to /RD Rise Delay
–
60
–
50
–
50
ns
14.
tM1D2
Ø Rise to /M1 Rise Delay
–
80
–
70*
–
60
ns
15.
tDRS
Data Read Set-up Time
40
–
30
–
25
–
ns
16.
tDRH
Data Read Hold Time
0
–
0
–
0
–
ns
17.
tSTD1
Ø Fall to ST Fall Delay
–
90
–
70
–
60
ns
/IOC = 1
Ø Rise to /RD Rise Delay
/IOC = 0
18.
tSTD2
Ø Fall to ST Rise Delay
–
90
–
70
–
60
ns
19.
tWS
/WAIT Set-up Time to Ø Fall
40
–
40
–
30
–
ns
20.
tWH
/WAIT Hold Time from Ø Fall
40
–
40
–
30
–
ns
21.
tWDZ
Ø Rise to Data Float Delay
–
95
–
70
–
60
ns
22.
tWRD1
Ø Rise to /WR Fall Delay
–
65
–
60
–
50
ns
23.
tWDD
Ø Fall to Write Data Delay Time
–
90
–
80
–
60
ns
24.
tWDS
Write Data Set-up Time to /WR Fall
40
–
20
–
15
–
ns
25.
tWRD2
Ø Fall to /WR Rise Delay
–
80
–
60
–
50
ns
26.
tWRP
/WR Pulse Width
170
–
130
–
110
–
ns
26a.
27.
/WR Pulse Width (I/O Write Cycle)
Write Data Hold Time from (/WR Rise)
332
40
–
–
255
15
–
–
210
10
–
–
ns
tWDH
28.
tIOD1
Ø Fall to /IORQ Fall Delay
–
60
–
50
–
50
ns
–
65
–
60
–
55
Ø Rise to /IORQ Fall Delay
/IOC = 1
/IOC = 1
29.
tIOD2
Ø Fall to /IORQ Rise Delay
–
60
–
50
–
50
ns
30.
tIOD3
/M1 Fall to /IORQ Fall Delay
340
–
250
–
200
–
ns
31.
tINTS
/INT Set-up Time to Ø Fall
40
–
40
–
30
–
ns
32.
tINTS
/INT Hold Time from Ø Fall
40
–
40
–
30
–
ns
33.
tNMIW
/NMI Pulse Width
120
–
100
–
80
–
ns
34.
tBRS
/BUSREQ Set-up Time to Ø Fall
40
–
40
–
30
–
ns
35.
tBRH
/BUSREQ Hold Time from Ø Fall
40
–
40
36.
tBAD1
Ø Rise to /BUSACK Fall Delay
–
95
–
70
–
60
ns
37.
tBAD2
Ø Fall to /BUSACK Rise Delay
–
90
–
70
–
60
ns
38.
tBZD
Ø Rise to Bus Floating Delay Time
–
125
–
90
–
80
ns
39.
tMEWH /MREQ Pulse Width (HIGH)
110
–
90
–
70
–
ns
DS971800401
PRELIMINARY
30
ns
1-25
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Z80180-6
No.
Symbol Item
Min.
Z80180-8
Max.
Min.
Z80180-10
Max.
Min.
Max.
Unit
40.
tMEWL
/MREQ Pulse Width (LOW)
125
–
100
–
80
–
ns
41.
tRFD1
Ø Rise to /RFSH Fall Delay
–
90
–
80
–
60
ns
42.
tRFD2
Ø Rise to /RFSH Rise Delay
–
90
–
80
–
60
ns
43.
tHAD1
Ø Rise to /HALT Fall Delay
–
90
–
80
–
50
ns
44.
tHAD2
Ø Rise to /HALT Rise Delay
–
90
–
80
–
50
ns
45.
tDRQS
/DREQi Set-up Time to Ø Rise
40
–
40
–
30
–
ns
46.
tDRQH
/DREQi Hold Time from Ø Rise
40
–
40
–
30
–
ns
47.
tTED1
Ø Fall to /TENDi Fall Delay
–
70
–
60
–
50
ns
48.
tTED2
Ø Fall to /TENDI Rise Delay
–
70
–
60
–
50
ns
49.
tED1
Ø Rise to E Rise Delay
–
95
–
70
–
60
ns
50.
tED2
Ø Fall or Rise to E Fall Delay
–
95
–
70
–
60
ns
51.
PWEH
E Pulse Width (HIGH)
75
–
65
–
55
–
ns
52.
PWEL
E Pulse Width (LOW)
180
–
130
–
110
–
ns
53.
tEr
Enable Rise Time
–
20
–
20
–
20
ns
54.
tEf
Enable Fall Time
–
20
–
20
–
20
ns
55.
tTOD
Ø Fall to Timer Output Delay
–
300
–
200
–
150
ns
56.
tSTDI
–
200
–
200
–
150
ns
57.
tSTDE
–
1
1
7.5tcyc
+150
–
ns
1
7.5tcyc
+200
–
–
tSRSI
7.5tcyc
+300
–
–
58.
tcyc
59.
tSRHI
1
–
1
–
1
–
tcyc
60.
tSRSE
1
–
1
–
1
–
tcyc
61.
tSRHE
1
–
1
–
1
–
tcyc
62.
tRES
CSI/O Transmit Data Delay Time (Internal
Clock Operation)
CSI/O Transmit Data Delay Time (External
Clock Operation)
CSI/O Receive Data Set-up Time (Internal
Clock Operation)
CSI/O Receive Data Hold Time (Internal
Clock Operation)
CSI/O Receive Data Set-up Time (External
Clock Operation)
CSI/O Receive Data Hold Time (External
Clock Operation)
/RESET Set-up Time to Ø Fall
120
–
100
–
80
–
ns
63.
tREH
/RESET Hold Time from Ø Fall
80
–
70
–
50
–
ns
64.
tOSC
Oscillator Stabilization Time
–
20
–
20
–
TBD
ns
65.
tEXr
External Clock Rise Time (EXTAL)
–
25
–
25
–
25
ns
66.
tEXf
External Clock Fall Time (EXTAL)
–
25
–
25
–
25
ns
67.
tRr
/RESET Rise Time
–
50
–
50
–
50
ns
68.
tRf
/RESET Fall Time
–
50
–
50
–
50
ns
69.
tIr
Input Rise Time (except EXTAL, /RESET)
–
100
–
100
–
100
ns
70.
tIf
Input Fall Time (except EXTAL, /RESET)
–
100
–
100
–
100
ns
1-26
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
AC CHARACTERISTICS
(VCC = 5V ±10% or VCC = 3.3V ±10% over specified temperature range, unless otherwise noted, 33
MHZ characteristics apply only to 5V operation.)
Z80180-20
No.
Symbol
Item
Z80180-33
Min.
Max.
Min.
Max.
Unit
1.
tcyc
Clock Cycle Time
50
2000
33
2000
ns
2.
tCHW
Clock “H” Pulse Width
15
–
10
–
ns
3.
tCLW
Clock “L” Pulse Width
15
–
10
–
ns
4.
tcf
Clock Fall Time
–
10
–
5
ns
5.
tcr
Clock Rise Time
–
10
–
5
ns
6.
tAD
ØRise to Address Valid Delay
–
15
–
15
ns
7.
tAS
Address Valid to /MREQ Fall or /IORQ Fall)
20
–
5
–
ns
8.
tMED1
Ø Fall to /MREQ Fall Delay
–
15
–
15
ns
9.
tRDD1
Ø Fall to /RD Fall Delay
–
15
–
15
ns
–
15
–
15
10.
tM1D1
Ø Rise to /M1 Fall Delay
–
15
–
15
ns
11.
tAH
Address Hold Time from
(/MREQ, /IOREQ, /RD, /WR)
–
20
5
–
ns
12.
tMED2
Ø Fall to /MREQ Rise Delay
–
15
–
15
ns
13.
tRDD2
Ø Fall to /RD Rise Delay
–
15
–
15
ns
14.
tM1D2
Ø Rise to /M1 Rise Delay
–
15
–
15*
ns
15.
tDRS
Data Read Set-up Time
15
–
15
–
ns
16.
tDRH
Data Read Hold Time
0
–
0
–
ns
17.
tSTD1
Ø Fall to ST Fall Delay
–
15
–
15
ns
/IOC = 1
Ø Rise to /RD Rise Delay
/IOC = 0
18.
tSTD2
Ø Fall to ST Rise Delay
–
15
–
15
ns
19.
tWS
/WAIT Set-up Time to Ø Fall
15
–
15
–
ns
20.
tWH
/WAIT Hold Time from Ø Fall
5
–
5
–
ns
21.
tWDZ
Ø Rise to Data Float Delay
–
10
–
10
ns
22.
tWRD1
Ø Rise to /WR Fall Delay
–
15
–
15
ns
23.
tWDD
Ø Fall to Write Data Delay Time
–
20
–
20
ns
24.
tWDS
Write Data Set-up Time to /WR Fall
10
–
0
–
ns
25.
tWRD2
Ø Fall to /WR Rise Delay
–
15
–
15
ns
26.
tWRP
/WR Pulse Width
70
–
40
–
ns
26a.
27.
/WR Pulse Width (I/O Write Cycle)
Write Data Hold Time from (/WR Rise)
120
5
–
–
70
5
–
–
ns
tWDH
28.
tIOD1
–
15
–
15
ns
–
15
–
15
Ø Fall to /IORQ Fall Delay
Ø Rise to /IORQ Fall Delay
/IOC = 1
/IOC = 1
29.
tIOD2
Ø Fall to /IORQ Rise Delay
–
15
–
15
ns
30.
tIOD3
/M1 Fall to /IORQ Fall Delay
120
–
70
–
ns
31.
tINTS
/INT Set-up Time to Ø Fall
15
–
15
–
ns
32.
tINTS
/INT Hold Time from Ø Fall
10
–
10
–
ns
33.
tNMIW
/NMI Pulse Width
35
–
25
–
ns
34.
tBRS
/BUSREQ Set-up Time to Ø Fall
10
–
10
–
ns
35.
tBRH
/BUSREQ Hold Time from Ø Fall
10
–
10
36.
tBAD1
Ø Rise to /BUSACK Fall Delay
–
15
–
15
ns
37.
tBAD2
Ø Fall to /BUSACK Rise Delay
–
15
–
15
ns
DS971800401
PRELIMINARY
ns
1-27
1
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Z80180-20
No.
Symbol
Item
Z80180-33
Min.
Max.
Min.
Max.
Unit
38.
tBZD
Ø Rise to Bus Floating Delay Time
–
10
–
25
ns
39.
tMEWH
/MREQ Pulse Width (HIGH)
45
–
25
–
ns
40.
tMEWL
/MREQ Pulse Width (LOW)
45
–
25
–
ns
41.
tRFD1
Ø Rise to /RFSH Fall Delay
–
15
–
15
ns
42.
tRFD2
Ø Rise to /RFSH Rise Delay
–
15
–
15
ns
43.
tHAD1
Ø Rise to /HALT Fall Delay
–
15
–
15
ns
44.
tHAD2
Ø Rise to /HALT Rise Delay
–
15
–
15
ns
45.
tDRQS
/DREQi Set-up Time to Ø Rise
20
–
20
–
ns
46.
tDRQH
/DREQi Hold Time from Ø Rise
15
–
15
–
ns
47.
tTED1
Ø Fall to /TENDi Fall Delay
–
15
–
15
ns
48.
tTED2
Ø Fall to /TENDI Rise Delay
–
15
–
15
ns
49.
tED1
Ø Rise to E Rise Delay
–
15
–
15
ns
50.
tED2
Ø Fall or Rise to E Fall Delay
–
15
–
15
ns
51.
PWEH
E Pulse Width (HIGH)
45
–
20
–
ns
52.
PWEL
E Pulse Width (LOW)
70
–
20
–
ns
53.
tEr
Enable Rise Time
–
10
–
10
ns
54.
tEf
Enable Fall Time
–
10
–
10
ns
55.
tTOD
Ø Fall to Timer Output Delay
–
50
–
50
ns
56.
tSTDI
–
2
–
2
ns
57.
tSTDE
–
1
1
7.5tcyc
+60
–
ns
tSRSI
7.5tcyc
+75
–
–
58.
tcyc
59.
tSRHI
1
–
1
–
tcyc
60.
tSRSE
1
–
1
–
tcyc
61.
tSRHE
1
–
1
–
tcyc
62.
tRES
CSI/O Transmit Data Delay Time (Internal Clock
Operation)
CSI/O Transmit Data Delay Time (External Clock
Operation)
CSI/O Receive Data Set-up Time (Internal Clock
Operation)
CSI/O Receive Data Hold Time (Internal Clock
Operation)
CSI/O Receive Data Set-up Time (External Clock
Operation)
CSI/O Receive Data Hold Time (External Clock
Operation)
/RESET Set-up Time to Ø Fall
25
–
25
–
ns
63.
tREH
/RESET Hold Time from Ø Fall
15
–
15
–
ns
64.
tOSC
Oscillator Stabilization Time
–
20
–
20
ns
65.
tEXr
External Clock Rise Time (EXTAL)
–
10
–
5
ns
66.
tEXf
External Clock Fall Time (EXTAL)
–
10
–
5
ns
67.
tRr
/RESET Rise Time
–
50
–
50
ns
68.
tRf
/RESET Fall Time
–
50
–
50
ns
69.
tIr
Input Rise Time (except EXTAL, /RESET)
–
50
–
50
ns
70.
tIf
Input Fall Time (except EXTAL, /RESET)
–
50
–
50
ns
1-28
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
TIMING DIAGRAMS
Opcode fetch Cycle
T1
2
T2
T1
1
T1
3
4
ø
T3
TW
I/O Write Cycle *2
I/O Read Cycle *2
T2
TW
T3
5
1
6
ADDRESS
19
20 19
20
/WAIT
7
12 11
/MREQ
8
7
29 11
28
13
/IORQ
11
13
/RD
11
9
9
22
25
/WR
14
/M1
18
10
ST
17
15
16
15
Data IN
16 21
24
27
23
Data OUT
62
*1
63
62
/RESET
68
67
67
63
68
Notes:
*1. Output buffer is off at this point.
*2. Memory Read/Write Cycle timing are the same as I/O Read/Write Cycle except
there are no automatic wait states (TW), and /MREQ is active instead of /IORQ.
Figure 20. CPU Timing
(Opcode Fetch Cycle, Memory Read Cycle,
Memory Write Cycle, I/O Write Cycle, I/O Read Cycle)
DS971800401
PRELIMINARY
1-29
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
ø
/INTi
32
31
33
/NMI
/MI *1
30
10
14
28
/IORQ *1
29
15
16
Date IN *1
39
/MREQ *2
41
42
40
/RFSH *2
34
35
34
35
/BUSREQ
36
37
/BUSACk
38
38
ADDRESS
DATA
/MREQ /RD
/WR, /IORQ
*3
43
44
/HALT
Notes:
1. During /INT0 acknowledge cycle.
2. During refresh cycle.
3. Output buffer is off at this point.
Figure 21. CPU Timing
(/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode,
HALT Mode, SLEEP Mode, SYSTEM STOP Mode)
1-30
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
I/O Write Cycle
I/O Read Cycle
T1
T2
Tw
T3
T1
T2
Tw
1
T3
φ
ADDRESS
28
29
9
13
28
29
22
25
IROQ
RD
WR
CPU Timing (IOC=0)
I/O Read Cycle
I/O Write Cycle
Figure 22. CPU Timing (/IOC = 0)
(I/O Read Cycle, I/O Write Cycle)
T1
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)
T2
TW
T3
T1
ø
45
46*1
/DREQi
(at level sense)
*2
45 46
/DREQi
(at level sense)
*4
47
18
48
/TENDi
*3
17
ST
1.
*2.
*3.
*4.
tDRQS and tDHQH are specified for the rising edge of clock followed by T3.
tDRQS and tDHQH are specified for the rising edge of clock.
DMA cycle starts.
CPU cycle starts
Figure 23. DMA Control Signals
DS971800401
PRELIMINARY
1-31
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
T1
Zilog
T2
TW
TW
T3
ø
~ ~
~
~
49
50
E
(Memory Read//Write)
49
50
~
~
E
(I/O Read)
49
50
~
~
E
(I/O Write)
15
16
~
~ ~
~
D0 - D7
Figure 24. E Clock Timing
(Memory Read/Write Cycle, I/O Read/Write Cycle)
ø
E
BUS RELEASE mode
SLEEP mode
SYSTEM STOP mode
49
50
Figure 25. E Clock Timing
(BUS RELEASE Mode, SLEEP Mode, SYSTEM STOP Mode)
T2
TW
T3
T1
50
E
Example
I/O read
→ Opcode fetch
52
T2
49
50
49
54
53
51
53
54
Figure 26. E Clock Timing
(Minimum timing example of PWEL and PWEH)
1-32
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1
Timer Data
Reg.=0000H
A18/TOUT
55
Figure 27. Timer Output Timing
Next Opcode fetch
SLP Instruction fetch
T1
T2
TS
TS
~
~
T3
T1
T2
ø
31
/INTi
~
~
/NMI
32
~
~
33
~ ~
~ ~
~
~
A0 ~ A18
/MREQ, /MI
/RD
43
44
/HALT
~
~
Figure 28. SLP Execution Cycle
DS971800401
PRELIMINARY
1-33
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
CSI/O CLock
56
56
Transmit data
(Internal Clock)
57
57
Transmit data
(External Clock)
11tcyc
58
11tcyc
58
59
59
Receive data
(Internal Clock)
11.5tcyc
Receive data
(External Clock)
60
16.5tcyc
11.5tcyc
61
16.5tcyc
60
61
Figure 29. CSI/O Receive/Transmit Timing
65
EXTAL VIL1
66
VIH1
Input Rise Time and Fall Time
(Except EXTAL, /RESET)
VIH1
70
69
VIL1
External Clock Rise Time and Fall Time
Figure 30. Rise Time and Fall Times
1-34
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
CPU CONTROL REGISTER
CPU Control Register (CCR). This register controls the
basic clock rate, certain aspects of Power-Down modes,
and output drive/low noise options (Figure 31).
1
CPU Control Register (CCR)
D7 D6 D5 D4 D3 D2 D1 D0
LNAD/DATA
0 = Standard Drive
1 = 33% Drive on
A19-A0, D7-D0
Clock Divide
0 = XTAL/2
1 = XTAL/1
STANDBY/IDLE Enable
00 = No STANDBY
01 = IDLE After SLEEP
10 = STANDBY After SLEEP
11 = STANDBY After SLEEP
64-Cycle Exit
(QUICK RECOVERY)
LNCPUCTL
0 = Standard Drive
1 = 33% Drive on CPU
Control Signals
LNIO
0 = Standard Drive
1 = 33% Drive on
Group 1 I/O Signals
BREXT
0 = Ignore BUSREQ
on STANDBY/IDLE
1 = STANDBY/IDLE Exit
on BUSREQ
LNPHI
0 = Standard Drive
1 = 33% Drive on
PHI Pin
Figure 31. CPU Control Register (CCR) Address 1FH
Bit 7. Clock Divide Select. If this bit is 0, as it is after a Reset, the Z80180/Z8S180/Z8L180 divides the frequency on
the XTAL pin(s) by two to obtain its master clock PHI. If this
bit is programmed as 1, the part uses the XTAL frequency
as PHI without division.
When D6 and D3 are both 1, setting IOSTOP (ICR5) and
executing a SLP instruction puts the part into QUICK RECOVERY STANDBY mode, in which the on-chip oscillator
is stopped, and the part allows only 64 clock cycles for the
oscillator to stabilize when it's restarted.
If an external oscillator is used in divide-by-one mode, the
minimum pulse width requirement given in the AC Characteristics must be satisfied.
The latter section, HALT and LoW POWER Modes, describes the subject more fully.
Bits 6 and 3. STANDBY/IDLE Control. When these bits
are both 0, a SLP instruction makes the
Z80180/Z8S180/Z8L180 enter SLEEP or SYSTEM STOP
mode, depending on the IOSTOP bit (ICR5).
When D6 is 0 and D3 is 1, setting the IOSTOP bit (ICR5)
and
executing
a
SLP
instruction
puts
the
Z80180/Z8S180/Z8L180 into IDLE mode in which the onchip oscillator runs, but its output is blocked from the rest
of the part, including PHI out.
Bit 5 BREXT. This bit controls the ability of the
Z8S180/Z8L180 to honor a bus request during STANDBY
mode. If this bit is set to 1 and the part is in STANDBY
mode, a BUSREQ is honored after the clock stabilization
timer is timed out.
Bit 4 LNPHI. This bit controls the drive capability on the
PHI Clock output. If this bit is set to 1, the PHI Clock output
will be reduced to 33 percent of its drive capability.
When D6 is 1 and D3 is 0, setting IOSTOP (ICR5) and executing a SLP instruction puts the part into STANDBY
mode, in which the on-chip oscillator is stopped and the
part allows 217 (128K) clock cycles for the oscillator to stabilize when it's restarted.
DS971800401
PRELIMINARY
1-35
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Bit 2 LNIO. This bit controls the drive capability of certain
external I/O pins of the Z8S180/Z8L180. When this bit is
set to 1, the output drive capability of the following pins is
reduced to 33percent of the original drive capability:
Bit 0 LNAD/DATA. This bit controls the drive capability of
the Address/Data bus output drivers. If this bit is set to 1,
the output drive capability of the Address and Data bus
output is reduced to 33percent of its original drive
capability.
– /RTSO/TxS
– CKA1
– CKAO
– TXAO
– TXAI
– TOUT
Bit 1 LNCPUCTL. This bit controls the drive capability of
the CPU Control pins. When this bit is set to 1, the output
drive capability of the following pins is reduced to
33percent the original drive capability:
–
–
–
–
–
–
–
–
1-36
/BUSACK
/RD
/WR
/M1
/MREQ
/IORQ
/RFSH
/HALT
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
IASCI REGISTER DESCRIPTION
1
Internal Address/Data Bus
Interrupt Request
TXA0
RXA0
RTS0
CTS0
DCD0
ASCI Transmit Data Register
Ch 0: TDR0
ASCI Transmit Data Register
Ch 1: TDR1
ASCI Transmit Shift Register*
Ch 0: TSR0
ASCI Transmit Shift Register*
Ch 1: TSR1
ASCI Receive Data FIFO
Ch 0: RDR0
ASCI Receive Data FIFO
Ch 1: RDR1
ASCI Receive Shift Register*
Ch 0: RSR0 (8)
ASCI Receive Shift Register*
Ch 1: RSR1 (8)
ASCI Control Register A
Ch 0: CNTLA0 (8)
TXA1
RXA1
ASCI Control Register A
Ch 1: CNTLA1 (8)
ASCI
Control
ASCI Control Register B
Ch 0: CNTB0 (8)
ASCI Control Register B
Ch 1: CNTB1 (8)
ASCI Status FIFO
Ch 0
ASCI Status FIFO
Ch 1
ASCI Status Register
Ch 0: STAT0 (8)
ASCI Status Register
Ch 1: STAT1 (8)
ASCI Extension Control Reg.
Ch 0: ASEXT0 (7)
ASCI Extension Control Reg.
Ch 1: ASEXT1 (5)
ASCI Time Constant Low
Ch 0: ASTCOL (8)
ASCI Time Constant Low
Ch 1: ASTCIL (8)
ASCI Time Constant High
Ch 0: ASTCOH (8)
ASCI Time Constant High
Ch 1: ASTCIH (8)
CTS1
Note: *Not Program
Accessible.
CKA0
CKA1
Baud Rate
Generator 0
φ
Baud Rate
Generator 1
Figure 32. ASCI Block Diagram
DS971800401
PRELIMINARY
1-37
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
The following paragraphs explain the various functions of
the ASCI registers.
Register, the ASCI data transmit operation will not be affected by this read operation
ASCI Transmit Register 0. When the ASCI Transmit
Register receives data from the ASCI Transmit Data Register (TDR), the data is shifted out to the TxA pin. When
transmission is completed, the next byte (if available) is
automatically loaded from TDR into TSR and the next
transmission starts. If no data is available for transmission,
TSR IDLEs by outputting a continuous High level. This register is not program accessible
ASCI Receive Shift Register 0,1 (RSR0,1). This register
receives data shifted in on the RxA pin. When full, data is
automatically transferred to the ASCI Receive Data Register (RDR) if it is empty. If RSR is not empty when the next
incoming data byte is shifted in, an overrun error occurs.
This register is not program accessible.
ASCI Transmit Data Register 0,1 (TDR0, 1: I/O address
= 06H, 07H). Data written to the ASCI Transmit Data Register is transferred to the TSR as soon as TSR is empty.
Data can be written while TSR is shifting out the previous
byte of data. Thus, the ASCI transmitter is double buffered.
Data can be written into and read from the ASCI Transmit
Data Register. If data is read from the ASCI Transmit Data
ASCI Receive Data FIFO 0,1 (RDR0, 1:I/O Address = 08H,
09H). The ASCI Receive Data Register is a read-only register. When a complete incoming data byte is assembled
in RSR, it is automatically transferred to the 4 character
Receive Data First-In First-Out (FIFO) memory. The oldest
character in the FIFO (if any) can be read from the Receive
Data Register (RDR). The next incoming data byte can be
shifted into RSR while the FIFO is full. Thus, the ASCI receiver is well buffered.
ASCI STATUS FIFO
This 4 entry FIFO contains Parity Error, Framing Error, Rx
Overrun, and Break status bits associated with each character in the receive data FIFO. The status of the oldest
character (if any) can be read from the ASCI status registers as described below
1-38
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
ASCI CHANNEL CONTROL REGISTER A
ASCI Control Register A 0 (CNTLA0: I/O Address = 00H)
Bit
7
6
5
4
3
2
1
0
MPE
RE
TE
RTS0
MPBR/
EFR
MOD2
MOD1
MOD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
ASCI Control Register A 1 (CNTLA1: I/O Address = 01H)
Bit
7
6
5
4
3
2
1
0
MPE
RE
TE
CKA1D
MPBR/
EFR
MOD2
MOD1
MOD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 33. ASCI Channel Control Register A
MPE: Multi-Processor Mode Enable (bit 7). The ASCI
has a multiprocessor communication mode that utilizes an
extra data bit for selective communication when a number
of processors share a common serial bus. Multiprocessor
data format is selected when the MP bit in CNTLB is set to
1. If multiprocessor mode is not selected (MP bit in CNTLB
= 0), MPE has no effect. If multiprocessor mode is selected, MPE enables or disables the “wake-up” feature as follows. If MBE is set to 1, only received bytes in which the
MPB (multiprocessor bit) = 1 can affect the RDRF and error flags. Effectively, other bytes (with MPB = 0) are “ignored” by the ASCI. If MPE is reset to 0, all bytes, regardless of the state of the MPB data bit, affect the REDR and
error flags. MPE is cleared to 0 during RESET.
RTS0: Request to Send Channel 0 (bit 4 in CNTLA0
only). If bit 4 of the System Configuration Register is 0, the
RTS0/TxS pin has the RTS0 function. RTS0 allows the
ASCI to control (start/stop) another communication devices transmission (for example, by connecting to that device’s CTS input). RTS0 is essentially a 1 bit output port,
having no side effects on other ASCI registers or flags.
RE: Receiver Enable (bit 6). When RE is set to 1, the
ASCI transmitter is enabled. When TE is reset to 0, the
transmitter is disables and any transmit operation in
progress is interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held. TE is
cleared to 0 in IOSTOP mode during RESET.
MPBR/EFR: Multiprocessor Bit Receive/Error Flag Reset (bit 3). When multiprocessor mode is enabled (MP in
CNTLB = 1), MPBR, when read, contains the value of the
MPB bit for the last receive operation. When written to 0,
the EFR function is selected to reset all error flags (OVRN,
FE, PE and BRK in the ASEXT Register) to 0. MPBR/EFR
is undefined during RESET.
TE: Transmitter Enable (bit 5). When TE is set to 1, the
ASCI receiver is enabled. When TE is reset to 0, the transmitter is disabled and any transmit operation in progress is
interrupted. However, the TDRE flag is not reset and the
previous contents of TDRE are held. TE is cleared to 0 in
IOSTOP mode during RESET.
DS971800401
Bit 4 in CNTLA1 is used.
CKA1D = 1, CKA1/TEND0 pin = TEND0
CKA1D = 0, CKA1/TEND0 pin = CKA1
Cleared to 0 on reset.
PRELIMINARY
1-39
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
MOD2, 1, 0: ASCI Data Format Mode 2, 1, 0 (bits 2-0).
These bits program the ASCI data format as follows.
The data formats available based on all combinations of
MOD2, MOD1, and MOD0 are shown in Table 5-6.
Table 5. Data Formats
MOD2
= 0→7 bit data
= 1→8 bit data
MOD2 MOD1 MOD0 Data Format
0
0
0
0
1
1
1
1
MOD1
= 0→No parity
= 1→Parity enabled
MOD0
= 0→1 stop bit
= 1→2 stop bits
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Start + 7 bit data + 1 stop
Start + 7 bit data + 2 stop
Start + 7 bit data + parity + 1 stop
Start + 7 bit data + parity + 2 stop
Start + 8 bit data + 1 stop
Start + 8 bit data + 2 stop
Start + 8 bit data + parity + 1 stop
Start + 8 bit data + parity + 2 stop
ASCI CHANNEL CONTROL REGISTER B
ASCI Control Register B 0 (CNTLB0: I/O Address = 02H)
ASCI Control Register B 1 (CNTLB1: I/O Address = 03H)
Bit
7
6
5
4
3
2
1
0
MPBT
MP
CTS/
PS
PEO
DR
SS2
SS1
SS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 34. ASCI Channel Control Register B
MPBT: Multiprocessor Bit Transmit (bit 7). When multiprocessor communication format is selected (MP bit = 1),
MPBT is used to specify the MPB data bit for transmission.
If MPBT = 1, then MPB = 1 is transmitted. If MPBT = 0,
then MPB = 0 is transmitted. MPBT state is undefined during and after RESET.
MP: Multiprocessor Mode (bit 6). When MP is set to 1,
the data format is configured for multiprocessor mode
based on the MOD2 (number of data bits) and MOD0
(number of stop bits) bits in CNTLA. The format is as follows.
Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits
Note that multiprocessor (MP=1) format has no provision
for parity. If MP = 0, the data format is based on MOD0,
MOD1, MOD2, and may include parity. The MP bit is
cleared to 0 during RESET.
CTS/PS: Clear to Send/Prescale (bit 5). When read,
/CTS/PS reflects the state of the external /CTS input. If the
/CTS input pin is HIGH, /CTS/PS will be read as 1. Note
that when the /CTS input pin is HIGH, the TDRE bit is inhibited (i.e. held at 0). For channel 1, the /CTS input is multiplexed with RXS pin (Clocked Serial Receive Data).
1-40
Thus, /CTS/PS is only valid when read if the channel 1
CTS1E bit = 1 and the /CTS input pin function is selected.
The read data of /CTS/PS is not affected by RESET.
If the SS2-0 bits in this register are not 111, and the BRG
mode bit in the ASEXT register is 0, then writing to this bit
sets the prescale (PS) control as described in the following
“Clock Modes” section. Under those circumstances, a 0 indicates a divide by 10 prescale function while a 1 indicates
divide by 30. The bit resets to 0.
PEO: Parity Even Odd (bit 4). PEO selects oven or odd
parity. PEO does not affect the enabling/disabling of parity
(MOD1 bit of CNTLA). If PEO is cleared to 0, even parity
is selected. If PEO is set to 1, odd parity is selected. PEO
is cleared to 0 during RESET.
DR: Divide Ratio (bit 3). If the X1 bit in the ASEXT register is 0, this bit specifies the divider used to obtain baud
rate from the data sampling clock. If DR is reset to 0, divide- by-16 is used, while if DR is set to 1 divide-by-64 is
used. DR is cleared to 0 during RESET.
SS2,1,0: Source/Speed Select 2,1,0 (bits 2-0). First, if
these bits are 111, as they are after a Reset, the CKA pin
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
is used as a clock input, and is divided by 1, 16, or 64 depending on the DR bit and the X1 bit in the ASEXT register.
the CKA1 function when bit 0 of the Interrupt Edge register
is 1.
If these bits are not 111 and the BRG mode bit is ASEXT
is 0, then these bits specify a power-of-two divider for the
PHI clock as shown in Table 9.
Table 6. Divide Ratio
Setting or leaving these bits as 111 makes sense for a
channel only when its CKA pin is selected for the CKA
function. CKAO/CKS has the CKAO function when bit 4 of
the System Configuration Register is 0. DCD0/CKA1 has
SS2
SS1
SS0
Divide Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷1
÷2
÷4
÷8
÷16
÷32
÷64
External Clock
1
ASCI STATUS REGISTER 0, 1 (STAT0, 1)
Each channel status register allows interrogation of ASCI
communication, error and modem control signal status,
and enabling or disabling of ASCI interrupts.
ASCI Status Register 0 (STAT0: I/O Address = 04H)
Bit
7
6
5
4
3
2
1
0
RDRF
OVRN
PE
FE
RE
DCD0
TDRE
TIE
R
R
R
R
R/W
R
R
R/W
ASCI Status Register 1 (STAT1: I/O Address = 05H)
Bit
7
6
5
4
3
2
1
0
RDRF
OVRN
PE
FE
RE
CTSIE
TDRE
TIE
R
R
R
R
R/W
R/W
R
R/W
Figure 35. ASCI Status Registers
RDRF: Receive Data Register Full (bit 7). RDRF is set to
1 when an incoming data byte is loaded into an empty Rx
FIFO. Note that if a framing or parity error occurs, RDRF is
still set and the receive data (which generated the error) is
still loaded into the FIFO. RDRF is cleared to 0 by reading
RDR and last character in the FIFO from IOSTOP mode,
during RESET and for ASCI0 if the /DCD0 input is auto-enabled and is negated (High).
EFR bit in the CNTLA register, and also by Reset, in
IOSTOP mode, and for ASCI0 if the /DCD0 pin is auto enabled and is negated (High).
Note that when an overrun occurs, the receiver does not
place the character in the shift register into the FIFO, nor
any subsequent characters, until the last good character
has come to the top of the FIFO so that OVRN is set, and
software then writes a 1 to EFR to clear it.
OVRN: Overrun Error (bit 6). An overrun condition occurs if the receiver has finished assembling a character but
the Rx FIFO is full so there is no room for the character.
However, this status bit is not set until the last character received before the overrun becomes the oldest byte in the
FIFO. This bit is cleared when software writes a 1 to the
DS971800401
PRELIMINARY
1-41
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
PE: Parity Error (bit 5). A parity error is detected when
parity checking is enabled by the MOD1 bit in the CNT1LA
register being 1, and a character has been assembled in
which the parity does not match the PEO bit in the CNTLB
register. However, this status bit is not set until/unless the
error character becomes the oldest one in the RxFIFO. PE
is cleared when software writes a 1 to the EFR bit in the
CNTRLA register, and also by Reset, in IOSTOP mode,
and for ASCI0 if the /DCD0 pin is auto-enabled and is negated (High).
ASCI0 requests an interrupt when /DCD0 goes High. RIE
is cleared to 0 by Reset.
FE: Framing Error (bit 4). A framing error is detected
when the stop bit of a character is sampled as 0/Space.
However, this status bit is not set until/unless the error
character becomes the oldest one in the RxFIFO. FE is
cleared when software writes a 1 to the EFR bit in the
CNTLA register, and also by Reset, in IOSTOP mode, and
for ASCIO if the /DCDO pin is auto-enabled and is negated
(High).
Bit 2 = 0; Select RXS function.
REI: Receive Interrupt Enable (bit 3). RIE should be set
to 1 to enable ASCI receive interrupt requests. When RIE
is 1, the Receiver requests an interrupt when a character
is received and RDRF is set, but only if neither DMA channel has its Request-routing field set to receive data from
this ASCI. That is, if SM1-0 are 11 and SAR17-16 are 10,
or DIM1 is 1 and IAR17-16 are 10, then ASCI1 doesn't request an interrupt for RDRF. If RIE is 1, either ASCI requests an interrupt when OVRN, PE or FE is set, and
DCD0: Data Carrier Detect (bit 2 STAT0). This bit is set
to 1 when the pin is High. It is cleared to 0 on the first read
of STAT0 following the pin's transition from High to Low
and during RESET. Bit 6 of the ASEXT0 register is 0 to select auto-enabling, and the pin is negated (High). Channel
1 has an external CTS1 input which is multiplexed with the
receive data pin RSX for the CSI/O.
Bit 2 = 1; Select CTS1 function.
TDRE: Transmit Data Register Empty (bit 1). TDRE = 1
indicates that the TDR is empty and the next transmit data
byte is written to TDR. After the byte is written to TDR,
TDRE is cleared to 0 until the ASCI transfers the byte from
TDR to the TSR and then TDRE is again set to 1. TDRE is
set to 1 in IOSTOP mode and during RESET. On ASCIO,
if the CTS0 pin is auto-enabled in the ASEXT0 registers
and the pin is High, TDRE is reset to 0.
TIE: Transmit Interrupt Enable (bit 0). TIE should be set
to 1 to enable ASCI transmit interrupt requests. If TIE = 1,
an interrupt will be requested when TDRE = 1. TIE is
cleared to 0 during RESET.
ASCI TRANSMIT DATA REGISTERS
Register addresses 06H and 07H hold the ASCI transmit
data for channel 0 and channel 1, respectively.
Channel 1
Mnemonics TDR1
Channel 0
Address (07H)
Mnemonics TDR0
Address (06H)
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
ASCI Transmit
Channel 1
Figure 37. ASCI Register
ASCI Transmit
Channel 0
Figure 36. ASCI Register
1-42
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
ASCI Receive Register
Channel 1--
Register addresses 08H and 09H hold the ASCI receive
data for channel 0 and channel 1, respectively.
Mnemonics TSR1
1
Address (09H)
Channel 0
Mnemonics TSR0 -Address (08H)
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
ASCI Transmit Data
Figure 39. ASCI Receive Register Channel 1R
ASCI Transmit Data
Figure 38. ASCI Receive Register Channel 0
CSI/O CONTROL/STATUS REGISTER
(CNTR: I/O Address = 0AH). CNTR is used to monitor
CSI/O status, enable and disable the CSI/O, enable and
Bit
disable interrupt generation, and select the data clock
speed and source.
7
6
5
4
3
2
1
0
EF
EIE
RE
TE
__
SS2
SS1
SS0
R
R/W
R/W
R/W
R/W
R/W
R/W
Figure 40. CSI/O Control Register
EF: End Flag (bit 7). EF is set to 1 by the CSI/O to indicate
completion of an 8-bit data transmit or receive operation. If
EIE (End Interrupt Enable) bit = 1 when EF is set to 1, a
CPU interrupt request is generated. Program access of
TRDR only occurs if EF = 1. The CSI/O clears EF to 0
when TRDR is read or written. EF is cleared to 0 during
RESET and IOSTOP mode.
is input on the CKS pin. In either case, data is shifted in on
the RXS pin in synchronization with the (internal or external) data clock. After receiving 8 bits of data, the CSI/O automatically clears RE to 0, EF is set to 1, and an interrupt
(if enabled by EIE = 1) is generated. RE and TE are never
both set to 1 at the same time. RE is cleared to 0 during
RESET and ISTOP mode.
EIE: End Interrupt Enable (bit 6). EIE is set to 1 to generate a CPU interrupt request. The interrupt request is inhibited if EIE is reset to 0. EIE is cleared to 0 during RESET.
RE: Receive Enable (bit 5). A CSI/O receive operation is
started by setting RE to 1. When RE is set to 1, the data
clock is enabled. In internal clock mode, the data clock is
output from the CKS pin. In external clock mode, the clock
DS971800401
PRELIMINARY
1-43
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Transmit Enable (bit 4). A CSI/O transmit operation is
started by setting TE to 1. When TE is set to 1, the data
clock is enabled. When in internal clock mode, the data
clock is output from the CKS pin. In external clock mode,
the clock is input on the CKS pin. In either case, data is
shifted out on the TXS pin synchronous with the (internal
or external) data clock. After transmitting 8 bits of data, the
CSI/O automatically clears TE to 0, EF is set to 1, and an
interrupt (if enabled by EIE = 1) is generated. TE and RE
are never both set to 1 at the same time. TE is cleared to
0 during RESET and IOSTOP mode.
SS2, 1, 0: Speed Select 2, 1, 0 (bits 2-0). SS2, SS1 and
SS0 select the CSI/O transmit/receive clock source and
speed. SS2, SS1 and SS0 are all set to 1 during RESET.
Table 10 shows CSI/O Baud Rate Selection.
Table 7. CSI/O Baud Rate Selection
Timer Data Register Channel 0L
TMDR0L
0CH
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
ASCI Receive Data
Figure 42. Timer Register Channel OL
Timer Data Register Channel 0H
TMDR0H
SS2
SS1
SS0
Divide Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷20
÷40
÷80
÷160
÷320
÷640
÷1280
External Clock Input
(less than ÷20.)
0D H
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
Timer Data
Figure 43. Timer Data Register Channel OH
After RESET, the CKS pin is configured as an external
clock input (SS2, SS1, SS0 = 1). Changing these values
causes CKS to become an output pin and the selected
clock is output when transmit or receive operations are enabled.
CSI/O Transmit/Receive Data Register
(TRDR: I/O Address = 0BH).
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
CSI/O T/R Data
Figure 41. CSI/O Transmit/Receive Data Register 1R
1-44
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Timer Reload Register 0L
Timer Reload Register 0H
RLDR0L
RLDR0H
0E H
0F H
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Timer Reload Data
Timer Reload Data
Figure 44. Timer Reload Register Low
Figure 45. Timer Reload Register Channel
TIMER CONTROL REGISTER (TCR)
TCR monitors both channels (PRT0, PRT1) TMDR status.
It also controls enabling and disabling of down counting
Bit
and interrupts along with controlling output pin A18/TOUT
for PRT1.
7
6
5
4
3
2
1
0
TIF1
TIF0
TIE1
TIE0
TOC1
TOC0
TDE1
TDE0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Figure 46. Timer Control Register (TCR: I/O Address = 10H)
TIF1: Timer Interrupt Flag 1 (bit 7). When TMDR1 decrements to 0, TIF1 is set to 1. This generates an interrupt request if enabled by TIE1 = 1. TIF1 is reset to 0 when TCR
is read and the higher or lower byte of TMDR1 is read. During RESET, TIF1 is cleared to 0.
TIF0: Timer Interrupt Flag 0 (bit 6). When TMDR0 decrements to 0, TIF0 is set to 1. This generates an interrupt request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR
is read and the higher or lower byte of TMDR0 is read. During RESET, TIF0 is cleared to 0.
TIE1: Timer Interrupt Enable 1 (bit 5). When TIE0 is set
to 1, TIF1 = 1 generates a CPU interrupt request. When
TIE0 is reset to 0, the interrupt request is inhibited. During
RESET, TIE0 is cleared to 0.
DS971800401
TOC1, 0: Timer Output Control (bits 3, 2). TOC1 and
TOC0 control the output of PRT1 using the multiplexed
TOUT/DREQ pin as shown in Table 11. During RESET,
TOC1 and TOC0 are cleared to 0. If bit 3 of the IAR1B register is 1, the TOUT function is selected. By programming
TOC1 and TOC0, the TOUT/DREQ pin can be forced
High, Low, or toggled when TMDR1 decrements to 0.
Table 8. Timer Output Control
TOC1 TOC0
0
0
0
1
1
1
0
1
PRELIMINARY
Output
Inhibited The TOUT/DREQ pin is not
affected by the PRT.
Toggled If bit 3 of IAR1B is 1, the
TOUT/DREQ pin is toggles or
0
set Low or High as indicated.
1
1-45
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
TDE1, 0: Timer Down Count Enable (bits 1, 0). TDE1
and TDE0 enable and disable down counting for TMDR1
and TMDR0, respectively. When TDEn (n = 0, 1) is set to
1, down counting is stopped and TMDRn is freely read or
written. TDE1 and TDE0 are cleared to 0 during RESET
and TMDRn will not decrement until TDEn is set to 1.
ASCI EXTENSION CONTROL REGISTER CHANNEL 0 (ASEXT0) AND CHANNEL 1 (ASEXT1)
Note: This register controls functions that have been
added to the ASCIs in the Z80180/Z8S180/Z8L180 family.
Note: All bits in this register reset to zero.
ASCI Extension Control Register 0(ASEXT0 I/O Address = 12H)
Bit
7
6
Reserved DCDO
Bit
7
5
4
3
2
1
0
CTSO
XI
BRGO
Mode
Break
Nab
Break
Send
Break
ASCI Extension Control Register 1 (ASEXT1 I/O Address = 13H)
3
5
4
2
1
0
6
Reserved Reserved Reserved
XI
BRGI
Mode
Break
Enab
Break
Send
Break
Figure 47. ASCI Extension Control Registers, Channel 0 and 1
DCD0 dis (bit 6, ASCI0 only). If this bit is 0, then the
DCD0 pin “auto-enables” the ASCI0 receiver, such that
when the pin is negated/High, the Receiver is held in a RESET state. The state of the DCD-pin has no effect on receiver operation. In either state of this bit, software can
read the state of the DCD0 pin in the STAT0 register, and
the receiver will interrupt on a rising edge of DCD0.
0 bits, to obtain the clock that is presented to the transmitter and receiver and that can be output on the CKA pin. If
SS2-0 are not 111, and this bit is 1, the Baud Rate Generator divides PHI by twice (the 16-bit value programmed
into the Time Constant Registers, plus two). This mode is
identical to the operation of the baud rate generator in the
ESCC.
CTS0 dis (bit 5, ASCI0 only). If this bit is 0, then the CTS0
pin “auto-enables” the ASCIO transmitter, in that when the
pin is negated/high, the TDRE bit in the STAT0 register is
forced to 0. If this bit is 1, the state of the CTS0 pin has no
effect on the transmitter. Regardless of the state of this bit,
software can read the state of the CTS0 pin the CNTLB0
register.
Break Enable (bit 2). If this bit is 1, the receiver will detect
Break conditions and report them in bit 1, and the transmitter will send Breaks under the control of bit 0.
X1 (bit 4). If this bit is 1, the clock from the Baud Rate Generator or CKA pin is taken as a “1X” bit clock (this is sometimes called “isochronous” mode). In this mode, receive
data on the RXA pin must be synchronized to the clock on
the CKA pin, regardless of whether CKA is an input or an
output. If this bit is 0, the clock from the Baud Rate Generator or CKA pin is divided by 16 or 64 per the DR bit in
CNTLB register, to obtain the actual bit rate. In this mode,
receive data on the RxA pin need not be synchronized to
a clock.
Break Detect (bit 1). The receiver sets this read-only bit
to 1 when an all-zero character with a Framing Error becomes the oldest character in the Rx FIFO. The bit is
cleared when software writes a 0 to the EFR bit in CNTLA
register, also by Reset, by IOSTOP mode, and for ASCIO
if the DCD0 pin is auto-enabled and is negated (high).
Send Break (bit 0). If this bit and bit 2 are both 1, the transmitter holds the TXA pin low to send a Bread condition.
The duration of the Bread is under software control (one of
the PRTs or CTCs can be used to time it). This bit resets
to 0, in which state TXA carries the serial output of the
transmitter.
BRG Mode (bit 3). If the SS2-0 bits in the CNTLB register
are not 111, and this bit is 0, this ASCI's Baud Rate Generator divides PHI by 10 or 30, depending on the DR bit in
CNTLB, and then by a power of two selected by the SS2-
1-46
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Timer Data Register Channel 1L
Timer Reload Register Channel 1L
Mnemonic TMDR1L
Mnemonic RLDR1H
Address 14
Address 17
7
6
5
4
3
2
1
0
7
1
6
5
4
Timer Data
3
2
1
Reload Data
Figure 48. Timer Data Register 1L
Figure 51. Timer Relaod Register Channel 1L
Timer Data Register Channel 1H
Free Running Counter (Read Only)
Mnemonic TMDR1H
Mnemonic FRC
Address 15
Address 18
7
6
5
4
3
2
1
0
0
7
6
5
4
3
2
1
0
Counting Data
Timer Data
Figure 52. Free Running Counter
Figure 49. Timer Data Register 1H
Timer Reload Register Channel 1L
Mnemonic RLDR1L
Address 16
7
6
5
4
3
2
1
0
Reload Data
Figure 50. Timer Reload Channel 1L
DS971800401
PRELIMINARY
1-47
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
ASCI TIME CONSTANT REGISTERS
If the SS2-0 bits of the CNTLA register are not 111, and the
BRG Mode bit in the ASEXT register is 1, the ASCI divides
the PHI clock by twice (the 16-bit value in these registers,
plus two), to obtain the clock that is presented to the transmitter and receiver for division by 1, 16, or 64 and that can
be output on the CKA1 pin.
ASCI Time Constant Register 0 Low (ASTCOL, I/O Address IAH)
ASCI Time Constant Register 1 Low (ASTCIL), I/O Address ICH)
Bit
7
6
5
4
3
2
1
0
LS 8 Bits of Time Constant
ASCI Time Constant Register 0 High (ASTCOH, I/O Address IBH)
ASCI Time Constant Register 1 High (ASTCIH), I/O Address IDH)
Bit
7
6
5
4
3
2
1
0
MS 8 Bits of Time Constant
Figure 53. ASCI Time Constant Registers
1-48
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
CLOCK MULTIPLIER REGISTER (Z180 MPU ADDRESS 1EH)
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
RESERVED
LOW NOISE CRYSTAL
X2 CLOCK MULTIPLIER
Bit 6. Low Noise Crystal Option. Setting this bit to 1 will
enable the low noise option for the EXTAL and XTAL pins.
This option reduces the gain, in addition to reduction the
output drive capability to 30% of its original drive capability.
The Low Noise Crystal Option is recommended in the use
of crystals for PCMCIA applications where the crystal may
be driven too hard by the oscillator. Setting this bit to 0 will
select for normal operation of the EXTAL and XTAL pins.
The default for this bit is 0.
Note: Operating restrictions for device operation are listed
below. If low noise option is required, and normal device
operation is needed, use the clock multiplier feature.
Figure 54. Clock Multiplier Register
Table 9. Low Noise Option
Bit 7. X2 Clock Multiplier Mode. When this bit is set to 1,
this allows the programmer to double the internal clock
from that of the external clock. This feature will only operated effectively with frequencies of 10-16 MHz (20-32MHz
internal).
When this bit is set to 0, the
Z80180/Z8S180/Z8L180 device will operate in normal
mode. Upon powerup, this feature is disabled.
DS971800401
Low Noise
ADDR 1E, bit 6=1
20 MHz @ 4.5V, 100°C
10 MHz @ 3.0V, 100°C
PRELIMINARY
Normal
ADDR 1E, bit 6=0
33 MHz @ 4.5V, 100°C
20 MHz @ 3.0V, 100°C
1-49
1
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA SOURCE ADDRESS REGISTER CHANNEL 0
(SAR0: I/O Address = 20H to 22H) specifies the physical source address for channel 0 transfers. The register contains
20 bits and can specify up to 1024 KB memory addresses or up to 64 KB I/O addresses. Channel 0 source can be memory, I/O, or memory mapped I/O. For I/O, the MS bits of this register identify the Request Handshake signal.
DMA Source Address Register, Channel 0L
DMA Source Address Register Channel 0B
Mnemonic SAR0L
Mnemonics SAR0B
Address 20
Address 22
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
DMA Channel 0 Address
DMA Channel B Address
Figure 55. DMA Source Address Register 0L
Figure 57. DMA Source Address Register 0B
DMA Source Address Register, Channel 0H
Mnemonic SAR0H
Address 21
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
DMA Channel 0 Address
Figure 56. DMA Source Address Register 0H
1-50
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA DESTINATION ADDRESS REGISTER CHANNEL 0
(DAR0: I/O Address = 23H to 25H) specifies the physical destination address for channel 0 transfers. The register contains 20 bits and can specify up to 1024 KB memory addresses or up to 64 KB I/O addresses. Channel 0 destination can
be memory, I/O, or memory mapped I/O. For I/O, the MS bits of this register identify the Request Handshake signal for
channel 0.
DMA Destination Address Register Channel
0L
DMA Destination Address Register Channel
0B
Mnemonic DAR0L
Mnemonic DAR0B
Address 23
Address 25
Figure 58. DMA Destination Address Register
Channel 0L
Figure 60. DMA Destination Address Register
Channel 0B
DMA Destination Address Register Channel
0H
Note: In the R1 and Z Mask, these DMA registers are
expanded from 4 bit to 3 bits in the package version of CP68
Mnemonic DAR0H
Address 24
Figure 59. DMA Destination Address Register
Channel 0H
DS971800401
A19*
A18
A17
A16
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
PRELIMINARY
DMA Transfer
Request
DREQ0
TDR0 (ASCI0)
TDR1 (ASCI1)
Not Used
1-51
1
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA BYTE COUNT REGISTER CHANNEL 0
(BCRO: I/O Address = 26H to 27H) specifies the number of bytes to be transferred. This register contains 16 bits and may
specify up to 64 KB transfers. When one byte is transferred, the register is decremented by one. If “n” bytes should be
transferred, “n” must be stored before the DMA operation.
Note: All DMA Count Register channels are undefined during reset.
DMA Byte Count Register Channel 0L
DMA Byte Count Register Channel 1L
Mnemonic BCR0L
Mnemonic BCR1L
Address 26
Address 2E
Figure 61. DMA Byte Count Register 0L
Figure 63. DMA Byte Count Register 1L
DMA Byte Count Register Channel 0H
DMA Byte Count Register Channel 0H
Mnemonic BCR0H
Mnemonic BCR1H
Address 27
Address 2F
Figure 62. DMA Byte Count Register 0H
1-52
Figure 64. DMA Byte Count Register 0H
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA MEMORY ADDRESS REGISTER CHANNEL 1
(MAR1: I/O Address = 28H to 2AH) specifies the physical memory address for channel 1 transfers. This may be destination or source memory address. The register contains 20 bits and may specify up to 1024 KB memory address.
DMA Memory Address Register, Channel 1L
DMA Memory Address Register, Channel 1B
Mnemonic MAR1L
Mnemonic MAR1B
Address 28
Address 2A
Figure 65. DMA Memory Address Register,
Channel 1L
Figure 67. DMA Memory Address Register,
Channel 1B
DMA Memory Address Register, Channel 1H.
Mnemonic MAR1H
Address 29
Figure 66. DMA Memory Address Register,
Channel 1H
DS971800401
PRELIMINARY
1-53
1
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA I/O ADDRESS REGISTER CHANNEL 1
(IAR1: I/O Address = 2BH to 2DH) specifies the I/O address for channel 1 transfers. This may be destination or
source I/O address. The register contains 16 bits of I/O address; its most significant byte identifies the Request
Bit
7
6
A/T
F
A/T
C
5
4
Handshake signal and controls the Alternating Channel
feature.
All bits in IAR1B reset to 0.
3
1
2
TOUT
/DREQ
0
Req 1 Sel
Figure 68. IAR MS Byte Register (IARIB: I/O Address 2DH)
DMA I/O Address Register Channel 1L
DMA I/O Address Register Channel 1B
Mnemonic IAR1L
Mnemonic IAR1B
Address 2B
Address 2D
Figure 69. DMA I/O Address Register Channel 1L
Figure 71. DMA I/O Address Register Channel 1B
DMA I/O Address Register Channel 1H
Mnemonic IAR1H
Address 2C
Figure 70. DMA I/O Address Register Channel 1H
1-54
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA STATUS REGISTER (DSTAT)
DSTAT is used to enable and disable DMA transfer and
DMA termination interrupts. DSTAT also indicates DMA
transfer status, in other words, completed or in progress.
Bit
Mnemonic DSTAT
1
Address 30
1
7
6
5
4
3
2
DE1
DE0
DWE1
DWE0
DIE1
DIE0
DME
R/W
R/W
W
W
R/W
R/W
R
0
Figure 72. DMA Status Register (DSTAT: I/O Address = 30H)
DE1: DMA Enable Channel 1 (bit 7). When DE1 = 1 and
DME = 1, channel 1 DMA is enabled. When a DMA transfer terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC.
When DE1 = 0 and the DMA interrupt is enabled (DIE1 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE1, DWE1 should be written with 0 during the same register write access. Writing
DE1 to 0 disables channel 1 DMA, but DMA is restartable.
Writing DE1 to 1 enables channel 1 DMA and automatically sets DME (DMA Main Enable) to 1. DE1 is cleared to 0
during RESET.
DE0: DMA Enable Channel 0 (bit 6). When DE0 = 1 and
DME = 1, channel 0 DMA is enabled. When a DMA transfer terminates (BCR0 = 0), DE0 is reset to 0 by the DMAC.
When DE0 = 0 and the DMA interrupt is enabled (DIE0 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE0, DWE0 should be written with 0 during the same register write access. Writing
DE0 to 0 disables channel 0 DMA. Writing DE0 to 1 enables channel 0 DMA and automatically sets DME (DMA
Main Enable) to 1. DE0 is cleared to 0 during RESET.
DWE1: DE1 Bit Write Enable (bit 5). When performing
any software write to DE1, DWE1 should be written with 0
during the same access. DWE1 always reads as 1.
DS971800401
DWE0: DE0 Bit Write Enable (bit 4). When performing
any software write to DE0, DWE0 should be written with 0
during the same access. DWE0 always reads as 1.
DIE1: DMA Interrupt Enable Channel 1 (bit 3). When
DIE0 is set to 1, the termination channel 1 DMA transfer
(indicated when DE1 = 0) causes a CPU interrupt request
to be generated. When DIE0 = 0, the channel 0 DMA termination interrupt is disabled. DIE0 is cleared to 0 during
RESET.
DIE0: DMA Interrupt Enable Channel 0 (bit 2). When
DIE0 is set to 1, the termination channel 0 of DMA transfer
(indicated when DE0=0) causes a CPU interrupt request to
be generated. When DIE0=0, the channel 0 DMA termination interrupt is disabled. DIE0 is cleared to 0 during RESET.
DME: DMA Main Enable (bit 0). A DMA operation is only
enabled when its DE bit (DE0 for channel 0, DE1 for channel 1) and the DME bit is set to 1.
When NMI occurs, DME is reset to 0, thus disabling DMA
activity during the NMI interrupt service routine. To restart
DMA, DE- and/or DE1 should be written with 1 (even if the
contents are already 1). This automatically sets DME to 1,
allowing DMA operations to continue. Note that DME cannot be directly written. It is cleared to 0 by NMI or indirectly
set to 1 by setting DE0 and/or DE1 to 1. DME is cleared to
0 during RESET.
PRELIMINARY
1-55
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA MODE REGISTER (DMODE).
DMODE is used to set the addressing and transfer mode
for channel 0.
Mnemonic DMODE
Address 31H
Bit
7
6
5
4
3
2
1
DM1
DM0
SM1
SM0
MMOD
R/W
R/W
R/W
R/W
R/W
0
Figure 73. DMA Mode Register (DMODE: I/O Address = 31H)
DM1, DM0: Destination Mode Channel 0 (bits 5,4) specifies whether the destination for channel 0 transfers is
memory or I/O, and whether the address should be incremented or decremented for each byte transferred. DM1
and DM0 are cleared to 0 during RESET.
SM1, SM0: Source Mode Channel 0 (bits 3, 2) specifies
whether the source for channel 0 transfers is memory or
I/O, and whether the address should be incremented or
decremented for each byte transferred.
Table 11. Channel 0 Source
Table 10. Channel 0 Destination
DM1
DM0
Memory I/O
Memory
Increment/Decrement
0
0
1
1
0
1
0
1
Memory
Memory
Memory
I/O
+1
–1
fixed
fixed
1-56
SM1
SM0
Memory I/O
Memory
Increment/Decrement
0
0
1
1
0
1
0
1
Memory
Memory
Memory
I/O
+1
–1
fixed
fixed
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Table 12 shows all DMA transfer mode combinations of
DM0, DM1, SM0, and SM1. Since I/O to/from I/O transfers
are not implemented, 12 combinations are available.
1
Table 12. Transfer Mode Combinations
DM1
DM0
SM1
SM0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
0
Note: * Includes memory mapped I/O.
Transfer Mode
Memory→Memory
Memory→Memory
Memory*→Memory
I/O→Memory
Memory→Memory
Memory→Memory
Memory*→Memory
I/O→Memory
Memory→Memory*
Memory→Memory*
Reserved
Reserved
Memory→I/O
Memory I/O
Reserved
Reserved
MMOD: Memory Mode Channel 0 (bit). When channel 0
is configured for memory to/from memory transfers there is
no Request Handshake signal to control the transfer timing. Instead, two automatic transfer timing modes are selectable: burst (MMOD = 1) and cycle steal (MMOD = 0).
For burst memory to/from memory transfers, the DMAC
takes control of the bus continuously until the DMA transfer
completes (as shown by the byte count register = 0). In cycle steal mode, the CPU is given a cycle for each DMA
byte transfer cycle until the transfer is completed.
DS971800401
Address
Increment/Decrement
SAR0+1, DAR0+1
SAR0–1, DAR0+1
SAR0 fixed, DAR0+1
SAR0 fixed, DAR0+1
SAR0+1, DAR0–1
SAR0–1, DAR0–1
SAR0 fixed, DAR0–1
SAR0 fixed, DAR0–1
SAR0+1, DAR0 fixed
SAR0–1, DAR0 fixed
SAR0+1, DAR0 fixed
SAR0–1, DAR0 fixed
For channel 0 DMA with I/O source or destination, the selected Request signal times the transfer and thus MMOD
is ignored. MMOD is cleared to 0 during RESET.
PRELIMINARY
1-57
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA/WAIT CONTROL REGISTER (DCNTL)
DCNTL controls the insertion of wait states into DMAC
(and CPU) accesses of memory or I/O. Also, it defines the
Request signal for each channel as level or edge sense.
5
4
MWI1 MWI0
IWI1
IWI0
R/W
R/W
R/W
Bit
7
6
R/W
DCNTL also sets the DMA transfer mode for channel 1,
which is limited to memory to/from I/O transfers.
3
DMS1 DMS0
R/W
1
0
DIM1
DIM0
R/W
R/W
2
R/W
Figure 74. DMA/WAIT Control Register (DCNTL: I/O Address = 32H)
MWI1, MWI0: Memory Wait Insertion (bits 7-6). Specifies the number of wait states introduced into CPU or
DMAC memory access cycles. MWI1 and MWI0 are set to
1 during RESET.
MWI1
MWI0
Wait State
0
0
1
1
0
1
0
1
0
1
2
3
IWI1, IWI0: I/O Wait Insertion (bits 5-4). Specifies the
number of wait states introduced into CPU or DMAC I/O
access cycles. IWI1 and IWI0 are set to 1 during RESET.
See the section on Wait-State Generation for details.
1-58
IWI1
IWI0
Wait State
0
0
1
1
0
1
0
1
0
2
3
4
DMS1, DMS0: DMA Request Sense (bits 3-2). DMS1
and DMS0 specify the DMA request sense for channel 0
and channel 1 respectively. When reset to 0, the input is
level sense. When set to 1, the input is edge sense. DMS1
and DMS0 are cleared to 0 during RESET.
DMSi
Sense
1
0
Edge Sense
Level Sense
Typically, for an input/source device, the associated DMS
bit should be programmed as 0 for level sense because
the device has a relatively long time to update its Request
signal after the DMA channel reads data from it in the first
of the two machine cycles involved in transferring a byte.
An output/destination device has much less time to update
its Request signal, after the DMA channel starts a write operation to it, as the second machine cycle of the two cycles
involved in transferring a byte. With zero-wait state I/O cycles, which apply only to the ASCIs, it is impossible for a
device to update its Request signal in time, and edge sensing must be used.
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
With one-wait-state I/O cycles (the fastest possible except
for the ASCIs), it is unlikely that an output device will be
able to update its Request in time, and edge sense is required.
DIM1, DIM0: DMA Channel 1 I/O and Memory Mode
(bits 1-0). Specifies the source/destination and address
modifier for channel 1 memory to/from I/O transfer modes.
DIM1 and DIM0 are cleared to 0 during RESET.
1
Table 13. Channel 1 Transfer Mode
DIM1 DMI0 Transfer Mode
0
0
1
1
0
1
0
1
Memory→I/O
Memory→I/O
I/O→Memory
I/O→Memory
Address
Increment/Decrement
MAR1 +1, IAR1 fixed
MAR1–1, IAR1 fixed
IAR1 fixed, MAR1 + 1
IAR1 fixed, MAR1 –1
INTERRUPT VECTOR LOW REGISTER
Mnemonic: IL
Bits 7-5 of IL are used as bits 7-5 of the synthesized interrupt vector during interrupts for the INT1 and INT2 pins
and for the DMAs, ASCIs, PRTs, and CSI/O. These three
bits are cleared to 0 during Reset (Figure 75).
Address 33
7
6
5
4
3
2
1
0
IL 7
IL 6
IL 5
––
––
––
––
––
R/W
R/W
R/W
Bit
Interrupt Source Dependent Code
Programmable
Figure 75. Interrupt Vector Low Register (IL: I/O Address = 33H)
INT/TRAP CONTROL REGISTER
Mnemonics ITC
Address 34
INT/TRAP Control Register (ITC, I/O Address 34H).
This register is used in handling TRAP interrupts and to
enable or disable Maskable Interrupt Level 0 and the INT1
and INT2 pins.
Bit
7
6
TRAP UFO
R/W
R
5
4
3
––
––
––
2
1
0
ITE2 ITE1 ITE0
R/W R/W R/W
TRAP (bit 7). This bit is set to 1 when an undefined Opcode is fetched. TRAP can be reset under program control
by writing it with a 0, however, it cannot be written with 1
under program control. TRAP is reset to 0 during RESET.
UFO: Undefined Fetch Object (bit 6). When a TRAP interrupt occurs, the contents of UFO allow determination of
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the starting address of the undefined instruction. This is
necessary since the TRAP may occur on either the second
or third byte of the Opcode. UFO allows the stacked PC
value to be correctly adjusted. If UFO = 0, the first Opcode
should be interpreted as the stacked PC-1. If UFO = 1, the
first Opcode address is stacked PC-2. UFO is Read-Only.
ITE2, 1, 0: Interrupt Enable 2, 1, 0 (bits 2-0). ITE2 and
ITE1 enable and disable the external interrupt inputs /INT2
and /INT1, respectively. ITE0 enables and disables interrupts from the on-chip ESCC, CTCs and Bidirectional Centronics controller as well as the external interrupt input
/INT0. A 1 in a bit enables the corresponding interrupt level
while a 0 disables it. A Reset sets ITE0 to 1 and clears
ITE1 and ITE2 to 0.
TRAP Interrupt. The Z80180/Z8S180/Z8L180 generates
a non-maskable (not affected by the state of IEF1) TRAP
interrupt when an undefined Opcode fetch occurs. This
feature can be used to increase software reliability, implement an “extended” instruction set, or both. TRAP may occur during Opcode fetch cycles and also if an undefined
PRELIMINARY
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
in ITC will reveal whether the restart at physical
address 00000H was caused by RESET or TRAP.
Opcode is fetched during the interrupt acknowledge cycle
for INT0 when Mode 0 is used.
When
a
TRAP
interrupt
occurs,
Z80180/Z8S180/Z8L180 operates as follows:
the
1. The TRAP bit in the Interrupt TRAP/Control (ITC)
register is set to 1.
2. The current PC (Program Counter) value, reflecting
the location of the undefined Opcode, is saved on the
stack.
3. The Z80180/Z8S180/Z8L180 vectors to logical
address 0. Note that if logical address 0000H is
mapped to physical address 00000H, the vector is the
same as for RESET. In this case, testing the TRAP bit
All TRAP interrupts occur after fetching an undefined second Opcode byte following one of the “prefix” Opcodes
CBH, DDH, EDH, or FDH, or after fetching an undefined
third Opcode byte following one of the “double prefix” Opcodes DDCBH or FDCBH.
The state of the Undefined Fetch Object (UFO) bit in ITC
allows TRAP software to correctly “adjust” the stacked PC,
depending on whether the second or third byte of the Opcode generated the TRAP. If UFO=0, the starting address
of the invalid instruction is equal to the stacked PC-1. If
UFO=1, the starting address of the invalid instruction is
equal to the stacked PC-2.
Restart
from 0000H
φ
T1
T2
T3
Opcode
Fetch Cycle
PC Stacking
2nd Opcode
Fetch Cycle
TTP Ti
A0-A18 (A19)
Ti
Ti
Ti
Ti
T1 T2
PC
D0-D7
T3
T1
T2
T3
SP-1
SP-2
PCH
PCL
T1
T2
T3
0000H
Undefined
Opcode
M1
MREQ
RD
WR
Figure 76. TRAP Timing-2nd Opcode Undefined
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Restart
from 0000H
Memory
Read Cycle
3nd Opcode
Fetch Cycle
φ
PC Stacking
T1 T2 T3 T1 T2 TTP T3 Ti
PC
A0-A18 (A19)
Ti
Ti
Ti
IX + d, IY + d
T1 T2 T3
SP-1
PC-1H
D0-D7
T1 T2 T3
SP-2
1
Opcode
Fetch Cycle
T1 T2 T3
0000H
PC-1L
Undefined
Opcode
M1
MREQ
RD
WR
Figure 77. TRAP Timing-3rd Opcode Undefined
REFRESH CONTROL REGISTER
REFE: Refresh Enable (bit 7). REFE = disables the refresh controller while REFE = 1 enables refresh cycle insertion. REFE is set to 1 during RESET.
Mnemonic RCR
Address 36
7
-
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
REFE
REFW
REFW: Refresh Wait (bit 6). REFW = 0 causes the refresh cycle to be two clocks in duration. REFW = 1 causes
the refresh cycle to be three clocks in duration by adding a
refresh wait cycle (TRW). REFW is set to 1 during RESET.
Cyc0
Cyc1
Reserved
Figure 78. Refresh Control Register
(RCA: I/O Address = 36H)
CYC1, 0: Cycle Interval (bit 1,0). CYC1 and CYC0 specify the interval (in clock cycles) between refresh cycles. In
the case of dynamic RAMs requiring 128 refresh cycles every 2 ms (0r 256 cycles in every 4 ms), the required refresh
interval is less than or equal to 15.625 µs. Thus, the underlined values indicate the best refresh interval depending
on CPU clock frequency. CYC0 and CYC1 are cleared to
0 during RESET (see Table 14).
The RCR specifies the interval and length of refresh cycles, while enabling or disabling the refresh function.
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Table 14. DRAM Refresh Intervals
CYC1
CYC0
Insertion
Interval
Ø: 10 MHz
8 MHz
Time Interval
6 MHz
4 MHz
2.5 MHz
0
0
1
1
0
1
0
1
10 states
20 states
40 states
80 states
(1.0 µs)*
(2.0 µs)*
(4.0 µs)*
(8.0 µs)*
(1.25 µs)*
(2.5 µs)*
(5.0 µs)*
(10.0 µs)*
1.66 µs
3.3 µs
6.6 µs
13.3 µs
2.5 µs
5.0 µs
10.0 µs
20.0 µs
4.0 µs
8.0 µs
16.0 µs
32.0 µs
Note: *calculated interval
Refresh Control and Reset. After RESET, based on the
initialized value of RCR, refresh cycles will occur with an
interval of 10 clock cycles and be 3 clock cycles in duration.
Dynamic RAM Refresh Operation
1. Refresh Cycle insertion is stopped when the CPU is in
the following states:
a. During RESET
b. When the bus is released in response to
BUSREQ.
c.
During SLEEP mode.
d. During WAIT states.
2. Refresh cycles are suppressed when the bus is
released in response to BUSREQ. However, the
refresh timer continues to operate. Thus, the time at
which the first refresh cycle occurs after the
Z80180/Z8S180/Z8L180 re-acquires the bus depends
on the refresh timer and has no timing relationship with
the bus exchange.
3. Refresh cycles are suppressed during SLEEP mode.
If a refresh cycle is requested during SLEEP mode,
the refresh cycle request is internally “latched” (until
replaced with the next refresh request). The “latched”
refresh cycle is inserted at the end of the first machine
cycle after SLEEP mode is exited. After this initial
cycle, the time at which the next refresh cycle occurs
depends on the refresh time and has no relationship
with the exit from SLEEP mode.
4. The refresh address is incremented by one for each
successful refresh cycle, not for each refresh. Thus,
independent of the number of “missed” refresh
requests, each refresh bus cycle will use a refresh
address incremented by one from that of the previous
refresh bus cycles.
MMU COMMON BASE REGISTER
Mnemonic CBR
MMU Common Base Register (CBR). CBR specifies the
base address (on 4 KB boundaries) used to generate a 20bit physical address for Common Area 1 accesses. All bits
of CBR are reset to 0 during RESET.
Address 38
Bit
7
6
5
4
3
2
1
0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 79. MMU Common Base Register (BBR: I/O Address = 38H)
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
MMU BANK BASE REGISTER (BBR).
Mnemonic BBR
BBR specifies the base address (on 4 KB boundaries)
used to generate a 19-bit physical address for Bank Area
accesses. All bits of BBR are reset to 0 during RESET.
Address 39
Bit
7
6
5
4
3
2
1
0
BB7
BB6
BB5
BB4
BB3
BB2
BB1
BB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 80. MMU Bank Base Register (BBR: I/O Address = 39H)
MMU COMMON/BANK AREA REGISTER (CBAR).
Mnemonic CBAR
CBAR
specifies
boundaries
within
the
Z80180/Z8S180/Z8L180 64 KB logical address space for
up to three areas; Common Area), Bank Area and Common Area 1.
Address 3A
MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH)
Bit
7
6
5
4
3
2
1
0
CA3
CA2
CA1
CA0
BA3
BA2
BA1
BA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 81. MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
CA3-CA0:CA (bits 7-4). CA specifies the start (Low) address (on 4 KB boundaries) for the Common Area 1. This
also determines the last address of the Bank Area. All bits
of CA are set to 1 during RESET.
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BA-BA0 (bits 3-0). BA specifies the start (Low) address
(on 4 KB boundaries) for the Bank Area. This also determines the last address of the Common Area 0. All bits of
BA are set to 1 during RESET.
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
OPERATION MODE CONTROL REGISTER
Mnemonic OMCR
M1E (M1 Enable). This bit controls the M1 output and is
set to a 1 during reset.
Address 3E
The Z80180/Z8S180/Z8L180 is descended from two different “ancestor” processors, Zilog's original Z80 and the
Hitachi 64180. The Operating Mode Control Register (OMCR) can be programmed to select between certain differences between the Z80 and the 64180.
D7 D6 D5 --
-- --
-- --
When M1E=1, the M1 output is asserted Low during the
opcode fetch cycle, the INT0 acknowledge cycle, and the
first machine cycle of the NMI acknowledge.
On the Z80180/Z8S180/Z8L180, this choice makes the
processor fetch an RETI instruction once, and when fetching an RETI from zero-wait-state memory will use three
clock machine cycles which are not fully Z80-timing compatible but are compatible with the on-chip CTCs.
When MIE=0, the processor does not drive M1 Low during
instruction fetch cycles, and after fetching an RETI instruction once with normal timing, it goes back and re-fetches
the instruction using fully Z80-compatible cycles that include driving M1 Low. This may be needed by some external Z80 peripherals to properly decode the RETI instruction.I/O Control Register (ICR).
Reserved
IOC (R/W)
M1TE (W)
M1E (R/W)
Figure 82. Operating Control Register
(OMCR: I/O Address = 3EH)
φ
T1
T2
A0-A18 (A19)
T3
T1
T2
T3
TI
TI
TI
T1
T2
T3
PC+1
PC
EDH
TI
PC
4DH
T1
T2
T3
TI
PC+1
4DH
EDH
D0-D7
M1
MREQ
RD
ST
Figure 83. RETI Instruction Sequence with MIE=0
ICR allows relocating of the internal I/O addresses. ICR also controls enabling/disabling of the IOSTOP mode (Figure 84).
Bit
7
6
5
IOA7
IOA6
IOSTP
R/W
R/W
R/W
4
--
3
2
1
0
--
--
--
--
Figure 84. I/O Control Register (ICR: I/O Address = 3FH)
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
IOA7, 6: I/O Address Relocation (bits 7,6). IOA7 and
IOA6 relocate internal I/O as shown in Figure 85. Note that
the high-order 8 bits of 16-bit internal I/O address are always 0. IOA7 and IOA6 are cleared to 0 during Reset.
1
00FFH
IOA7-IOA6 = 1 1
00COH
00BFH
IOA7-IOA6 = 1 0
008OH
007OH
IOA7- IOA6 = 0 1
004OH
003FH
IOA7-IOA6 = 0 0
000OH
Figure 85. I/O Address Relocation
IOSTP. IOSTOP Mode (bit 5). IOSTOP mode is enabled
when IOSTP is set to 1. Normal I/O operation resumes
when IOSTOP is reprogrammed or Reset to 0
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
PACKAGE INFORMATION
Figure 86. 80-Pin QFP Package Diagram
1-66
PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1
Figure 87. 64-Pin DIP Package Diagram
Figure 88. 68-Pin PLCC Package Diagram
DS971800401
PRELIMINARY
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
ORDERING INFORMATION
Z80180
6, 8, 10MHz
Z8L180
20MHz
Z8S180
20, 33MHz
Please check availability before placing order.
CODES
Package
F = Plastic Quad Flatpack
P = Plastic Dual In Line
V = Plastic Leaded Chip Carrier
Temperature
S = 0°C to +70°C
E = -40C to +85C
Speeds
06 = 6 MHz
08 = 8 MHz
10 = 10 MHz
20 = 20 MHz
33 = 33 MHz
Environmental
C = Plastic Standard
Example:
Z 80180 08 P S C
is a Z80180, 08 MHz, Plastic DIP, 0° to +70°C, Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
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PRELIMINARY
DS971800401
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
DS971800401
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
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