STMICROELECTRONICS ST9040

ST9040

16K ROM HCMOS MCU
WITH EEPROM, RAM AND A/D CONVERTER
Register oriented 8/16 bit CORE with
RUN, WFI and HALT modes
Minimum instruction cycle time : 500ns
(12MHz internal)
Internal Memory :
ROM
16K bytes
RAM
256 bytes
EEPROM
512 bytes
224 general purpose registers available as RAM,
accumulators or index registers (register file)
PQFP80
80-pin PQFP package for ST9040Q
68-lead PLCC package for ST9040C
DMA controller, Interrupt handler and Serial Peripheral Interface as standard features
Up to 56 fully programmable I/O pins
Up to 8 external plus 1 non-maskableinterrupts
16 bit Timer with 8 bit Prescaler, able to be used
as a WatchdogTimer
Two 16 bit Multifunction Timers, each with an 8
bit prescaler and 13 operating modes
PLCC68
(Ordering Information at the end of the Datasheet)
8 channel 8 bit Analog to Digital Converter, with
Analog Watchdogs and external references
Serial Communications Interface with asynchronous and synchronous capability
Rich Instruction Set and 14 Addressingmodes
Division-by-Zero trap generation
Versatile developmenttools, including assembler,
linker, C-compiler, archiver, graphic oriented debuggerand hardware emulators
Real Time Operating System
Windowed and One Time Programmable EPROM
parts available for prototyping and pre-production
developmentphases
Pin to pin compatible with ST9036
February 1997
1/56
TABLE OF CONTENTS
ST9040
. . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 GENERAL DESCRIPTION . . . . . . . . . . . .
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . .
1.2.1 I/O Port Alternate Functions . . . . . . .
1.3 MEMORY . . . . . . . . . . . . . . . . . . . .
1.3.1 INTRODUCTION . . . . . . . . . . . . .
1.3.2 EEPROM . . . . . . . . . . . . . . . . .
1.3.2.1 Introduction . . . . . . . . . . . .
1.3.2.2 EEPROM Programming Procedure
1.3.2.3 Parallel Programming Procedure .
1.3.2.4 EEPROM Programming Voltage .
1.3.2.5 EEPROM Programming Time . . .
1.3.2.6 EEPROM Interrupt Management .
1.3.2.7 EEPROM Control Register . . . .
1.3.3 REGISTER MAP . . . . . . . . . . . . .
2
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1
5
6
6
10
10
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12
12
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
ST90E40 / ST90T40
. . . . . . . . . . . . . . .
1.1 GENERAL DESCRIPTION . . . . . . . . . .
1.2 PIN DESCRIPTION . . . . . . . . . . . . . .
1.2.1 I/O PORT ALTERNATE FUNCTIONS
1.1 MEMORY . . . . . . . . . . . . . . . . . . .
1.2 EPROM PROGRAMMING . . . . . . . . . .
1.2.1 Eprom Erasing . . . . . . . . . . . .
ST90R40 . . . . . . . . . . . . . . . . . . . . . . . .
1.1 GENERAL DESCRIPTION . . . . . . . . . .
1.2 PIN DESCRIPTION . . . . . . . . . . . . . .
1.2.1 I/O PORT ALTERNATE FUNCTIONS
1.3 MEMORY . . . . . . . . . . . . . . . . . . .
2/56
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35
38
39
39
42
42
42
49
51
52
52
55
ST9040
Figure 1. 80 Pin PQFP Package
Table 1. ST9040Q Pin Description
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
AVSS
25
P34/T1INA
64
P20/NMI
80
AVDD
2
NC
26
P33/T0OUTB
63
NC
79
NC
3
NC
27
P32/T0INB
62
VSS
78
P47/AIN7
4
P44/AIN4
28
P31/T0OUTA
61
P70/SIN
77
P46/AIN6
5
P57
29
P30/P/D/T0INA
60
P71/SOUT
76
P45/AIN5
6
P56
30
A15
31
A14
P72/INT4/TXCLK
/CLKOUT
P43/AIN3
P55
59
75
7
74
P42/AIN2
8
P54
32
NC
58
P73/INT5
/RXCLK/ADTRG
73
P41/AIN1
72
P40/AIN0
71
P27/RRDY5
70
P26/INT3
/RDSTB5/P/D
69
P25/WRRDY5
68
P24/INT1
/WRSTB5
9
INT7
33
A13
10
INT0
34
A12
57
P74/P/D/INT6
11
P53
35
A11
56
P75/WAIT
12
NC
36
A10
13
P52
37
A9
55
P76/WDOUT
/BUSREQ
14
P51
38
A8
15
P50
39
P00/A0/D0
54
P77/WDIN
/BUSACK
16
OSCOUT
40
P01/A1/D1
53
R/W
67
P23/SDO
17
VSS
52
NC
66
P22/INT2/SCK
18
VSS
51
DS
65
P21/SDI/P/D
19
NC
50
AS
20
OSCIN
49
NC
21
RESET
48
VDD
22
P37/T1OUTB
47
VDD
23
P36/T1INB
46
P07/A7/D7
24
P35/T1OUTA
45
P06/A6/D6
44
P05/A5/D5
43
P04/A4/D4
42
P03/A3/D3
41
P02/A2/D2
3/56

ST9040
Figure 2. 68 Pin PLCC Package
Table 2. ST9040C Pin Description
Pin
Name
Pin
Name
Pin
Name
Pin
Name
61
P44/AIN4
10
P35/T1OUTA
43
P70/SIN
60
AVSS
62
P57
11
P34/T1INA
42
P71/SOUT
59
AVDD
63
P56
12
P33/T0OUTB
13
P32/T0INB
P72/CLKOUT
/TXCLK/INT4
P47/AIN7
P55
41
58
64
57
P46/AIN6
65
P54
14
P31/T0OUTA
INT7
15
P30/P/D/T0INA
P73/ADTRG
/RXCLK/INT5
P45/AIN5
66
40
56
55
P43/AIN3
67
INT0
16
P17/A15
39
P74/P/D/INT6
54
P42/AIN2
38
P75/WAIT
53
P41/AIN1
37
P76/WDOUT
/BUSREQ
52
P40/AIN0
51
P27/RRDY5
36
P77/WDIN
/BUSACK
50
P26/INT3
/RDSTB5/P/D
49
P25/WRRDY5
48
P24/INT1
/WRSTB5
68
P53
17
P16/A14
● 1
P52
18
P15/A13
2
P51
19
P14/A12
3
P50
20
P13/A11
4
OSCOUT
21
P12/A10
5
VSS
22
P11/A9
35
R/W
6
OSCIN
23
P10/A8
34
DS
7
RESET
24
P00/A0/D0
33
AS
8
P37/T1OUTB
25
P01/A1/D1
32
VDD
47
P23/SDO
9
P36/T1INB
26
P02/A2/D2
31
P07/A7/D7
46
P22/INT2/SCK
30
P06/A6/D6
45
P21/SDI/P/D
29
P05/A5/D5
44
P20/NMI
28
P04/A4/D4
27
P03/A3/D3
4/56

ST9040
1.1GENERAL DESCRIPTION
The ST9040 is a ROM member of the ST9 family of
microcontrollers, completely developed and produced by SGS-THOMSON Microelectronics using
a proprietary n-well HCMOS process.
The ST9040 peripheral and functional actions are
fully compatible throughout the ST903x/4x family.
This datasheet will thus provide only information
specific to this ROM device.
THE READER IS ASKED TO REFER TO THE
DATASHEET OF THE ST9036 ROM-BASED DEVICE FOR FURTHER DETAILS.
The nucleus of the ST9040 is the advanced Core
which includes the Central Processing Unit (CPU),
the Register File, a 16 bit Timer/Watchdog with 8
bit Prescaler, a Serial Peripheral Interface supporting S-bus, I2C-bus and IM-bus Interface,plus two 8
bit I/O ports. The Core has independent memory
and register buses allowing a high degree of pipelining to add to the efficiency of the code execution
speed of the extensive instruction set. The powerful I/O capabilities demanded by microcontroller
applications are fulfilled by the ST9040 with up to
56 I/O lines dedicated to digital Input/Output.
These lines are grouped into up to seven 8 bit I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
an address/databus for interfacing external memory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel I/O with or
without handshake.
Three basic memory spaces are available to support
this wide range of configurations: Program Memory
(internaland external), Data Memory (internaland external)andtheRegisterFile, which includesthecontrol
andstatus registers of theon-chip peripherals.
Two 16 bit MultiFunction Timers, each with an 8 bit
Prescaler and 13 operating modes allow simple
use for complex waveform generation and measurement, PWM functions and many other system
timing functionsby the usage of the two associated
DMA channels for each timer. In addition there is
an 8 channel Analog to Digital Converter with integral sample and hold, fast 11µs conversion time
and 8 bit resolution. An Analog Watchdog feature
is included for two input channels.
Completing the device is a full duplex Serial Communications Interface with an integral 110 to
375,000 baud rate generator, asynchronous and
1.5Mbyte/s synchronous capability (fully programmable format) and associated address/wake-up
option, plus two DMA channels.
5/56

ST9040
1.2 PIN DESCRIPTION
AS. Address Strobe (output, active low, 3-state).
Address Strobe is pulsed low once at the beginning of each memory cycle. The rising edge of AS
indicates that address, Read/Write (R/W), and
Data Memory signals are valid for program or data
memory transfers. Under program control, AS can
be placed in a high-impedance state along with
Port 0 and Port 1, Data Strobe (DS) and R/W.
DS. Data Strobe (output, active low, 3-state). Data
Strobe provides the timing for data movement to or
from Port 0 for each memory transfer. During a
write cycle, data out is valid at the leading edge of
DS. During a read cycle, Data In must be valid prior
to the trailing edge of DS. When the ST9040 accesses on-chip memory, DS is held high during the
whole memory cycle. It can be placed in a high impedancestate alongwith Port 0, Port 1, AS and R/W.
R/W. Read/Write (output, 3-state). Read/Write
determines the direction of data transfer for external memory transactions. R/W is low when writing
to external program or data memory, and high for
all other transactions. It can be placed in a high impedancestate along with Port 0, Port 1, AS and DS.
RESET. Reset (input, active low). The ST9 is initialisedby the Reset signal. With the deactivationof RESET, program execution begins from the Program
memory location pointed to by the vector contained
in program memory locations 00h and 01h.
INT0, INT7. External interrupts (input, active on rising or falling edge). External interrupt inputs 0 and
7 respectively. INT0 channel may also be used for
the timer watchdog interrupt.
OSCIN, OSCOUT. Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the input of the oscillator inverter and internal clock generator; OSCOUT is the output of the oscillator
inverter.
AVDD. AnalogVDD ofthe Analogto Digital Converter.
AVSS. Analog VSS of the Analog to Digital Converter. Must be tied to VSS.
VDD. Main Power Supply Voltage (5V ± 10%)
VSS. Digital Circuit Ground.
P0.0-P0.7, P1.0-P1.7, P2.0-P2.7 P3.0-P3.7, P4.0P4.7, P5.0-P5.7, P7.0-P7.7 I/O Port Lines (Input/Output, TTL or CMOS compatible). 56 lines
grouped into I/O ports of 8 bits, bit programmable
under program control as general purpose I/O or
as alternate functions.
1.2.1 I/O Port Alternate Functions
Each pin of the I/O ports of the ST9040 may assume software programmable Alternative Functions as shown in the Pin Configuration Drawings.
Table 1-3 shows the Functions allocated to each
I/O Port pins and a summary of packagesfor which
they are available.
Figure 3. ST9040 Block Diagram
IN T0
INT7
8
16-Bit TIMER / WATCHDOG + SPI
16k Bytes
512 Bytes
256 Bytes
256 Bytes
ROM
EEPROM
RAM
REGISTER FILE
CPU
SCI
I/O PORT 7
WITH DMA
( SCI )
MEMORY BUS
REGISTER BUS
I/O PORT 0
( Address/Data )
I/O PORT 1
( Address )
I/O PORT 2
( SPI )
I/O PORT 3
( TIMERS )
8
8
8
8
2 x 16-bi t TIMER
W ITH DMA
I/O PORT 4
( Analog Inputs )
A / D
CONVERTER
8
I/O PORT 5
WITH HANDSHAKE
8
AVD D
AVS S
VR001385
6/56

ST9040
PIN DESCRIPTION (Continued)
Table 3. ST9040 I/O Port Alternate Function Summary
I/O PORT
Name
Function
Alternate Function
Port. bit
Pin Assignment
PLCC
PQFP
P0.0
A0/D0
I/O
Address/Data bit 0 mux
24
39
P0.1
A1/D1
I/O
Address/Data bit 1 mux
25
40
P0.2
A2/D2
I/O
Address/Data bit 2 mux
26
41
P0.3
A3/D3
I/O
Address/Data bit 3 mux
27
42
P0.4
A4/D4
I/O
Address/Data bit 4 mux
28
43
P0.5
A5/D5
I/O
Address/Data bit 5 mux
29
44
P0.6
A6/D6
I/O
Address/Data bit 6 mux
30
45
P0.7
A7/D7
I/O
Address/Data bit 7 mux
31
46
P1.0
A8
O
Address bit 8
23
38
P1.1
A9
O
Address bit 9
22
37
P1.2
A10
O
Address bit 10
21
36
P1.3
A11
O
Address bit 11
20
35
P1.4
A12
O
Address bit 12
19
34
P1.5
A13
O
Address bit 13
18
33
P1.6
A14
O
Address bit 14
17
31
P1.7
A15
O
Address bit 15
16
30
P2.0
NMI
I
Non-Maskable Interrupt
44
64
P2.0
ROMless
I
ROMless Select (Mask option)
44
64
P2.1
P/D
O
Program/Data Space Select
45
65
P2.1
SDI
I
SPI Serial Data Out
45
65
P2.2
INT2
I
External Interrupt 2
46
66
P2.2
SCK
O
SPI Serial Clock
46
66
P2.3
SDO
O
SPI Serial Data In
47
67
P2.4
INT1
I
External Interrupt 1
48
68
P2.4
WRSTB5
I
Handshake Write Strobe P5
48
68
P2.5
WRRDY5
O
Handshake Write Ready P5
49
69
P2.6
INT3
I
External Interrupt 3
50
70
P2.6
RDSTB5
I
Handshake Read Strobe P5
50
70
P2.6
P/D
O
Program/Data Space Select
50
70
P2.7
RDRDY5
O
Handshake Read Ready P5
51
71
P3.0
T0INA
I
MF Timer 0 Input A
15
29
P3.0
P/D
O
Program/Data Space Select
15
29
P3.1
T0OUTA
O
MF Timer 0 Output A
14
28
P3.2
T0INB
I
MF Timer 0 Input B
13
27
P3.3
T0OUTB
O
MF Timer 0 Output B
12
26
P3.4
T1INA
I
MF Timer 1 Input A
11
25
7/56

ST9040
PIN DESCRIPTION (Continued)
Table 4. ST9040 I/O Port Alternate Function Summary(Continued)
I/O PORT
Name
Function
Alternate Function
Port. bit
Pin Assignment
PLCC
PQFP
P3.5
T1OUTA
O
MF Timer 1 Output A
10
24
P3.6
T1INB
I
MF Timer 1 Input B
9
23
P3.7
T1OUTB
O
MF Timer 1 Output B
8
22
P4.0
AIN0
I
A/D Analog Input 0
52
72
P4.1
AIN1
I
A/D Analog Input 1
53
73
P4.2
AIN2
I
A/D Analog Input 2
54
74
P4.3
AIN3
I
A/D Analog Input 3
55
75
P4.4
AIN4
I
A/D Analog Input 4
61
4
P4.5
AIN5
I
A/D Analog Input 5
56
76
P4.6
AIN6
I
A/D Analog Input 6
57
77
P4.7
AIN7
I
A/D Analog Input 7
58
78
P5.0
I/O
I/O Handshake Port 5
3
15
P5.1
I/O
I/O Handshake Port 5
2
14
P5.2
I/O
I/O Handshake Port 5
1
13
P5.3
I/O
I/O Handshake Port 5
68
11
P5.4
I/O
I/O Handshake Port 5
65
8
P5.5
I/O
I/O Handshake Port 5
64
7
P5.6
I/O
I/O Handshake Port 5
63
6
P5.7
I/O
I/O Handshake Port 5
62
5
P7.0
SIN
I
SCI Serial Input
43
61
P7.1
SOUT
O
SCI Serial Output
42
60
P7.1
ROMless
I
ROMless Select (Mask option)
42
60
P7.2
INT4
I
External Interrupt 4
41
59
P7.2
TXCLK
I
SCI Transmit Clock Input
41
59
P7.2
CLKOUT
O
SCI Byte Sync Clock Output
41
59
P7.3
INT5
I
External Interrupt 5
40
58
P7.3
RXCLK
I
SCI Receive Clock Input
40
58
P7.3
ADTRG
I
A/D Conversion Trigger
40
58
P7.4
INT6
I
External Interrupt 6
39
57
P7.4
P/D
O
Program/Data Space Select
39
57
P7.5
WAIT
I
External Wait Input
38
56
P7.6
WDOUT
O
T/WD Output
37
55
P7.6
BUSREQ
I
External Bus Request
37
55
P7.7
WDIN
I
T/WD Input
36
54
P7.7
BUSACK
O
External Bus Acknowledge
36
54
8/56

ST9040
ADDRESS SPACES
Table 1-4. Group F Peripheral Organization
Applicable for ST9040
DEC
DEC
HEX
00
00
02
02
R255
RFF RESERVED RESERVED
03
03
08
08
09
09
10
0A
24
18
63
3F
RFF
RESERVED
R254
RFE
RFE
PORT 7
MSPI
PORT 3
R253
RFD
R252
RFC
R251
RFB
R250
RFA
R249
RF9
R248
RF8
R247
RF7
R246
RF6
R245
RF5
R244
RF4
R243
RF3
R242
RF2
R241
RF1 EEPROMCR
R240
RF0 RESERVED
RFD
RESERVED
WCR
RFC
RESERVED
T/WD
RFB
RFA
RESERVED
MFT 1
PORT 2
MFT 0
A/D
MFT
RESERVED
EXT INT
RF8
SCI
PORT 5
MFT 1
PORT1
RF9
RF7
RF6
RF5
RF4
RESERVED RESERVED
RF3
MFT0
PORT 0
PORT 4
RF2
RF1
RF0
9/56

ST9040
1.3 MEMORY
1.3.1 INTRODUCTION
The memory of the ST9 is divided into two spaces:
- Data memory with up to 64K (65536) bytes
- Program memory with up to 64K (65536) bytes
Thus, there is a total of 128K bytes of addressable
memory space.
The 16K bytes of on-chip ROM memory of the
ST9040 are selected at memory addresses 0
through 3FFFh (hexadecimal) in the PROGRAM
space.
The DATA space includes the 512 bytes of on-chip
EEPROM at addresses 0 through 1FFh and the
256 bytes of on-chip RAM memory at addresses
200h through 2FFh.
1.3.2 EEPROM
1.3.2.1 Introduction
The EEPROMmemory provides user-programmable non-volatile memory on-chip, allowing fast and
reliable storage of user data. As there is also no
off-chip access required, as for an external serial
EEPROM, high security levels can be achieved.
The EEPROM memory is read as normal RAM
memory at Data Space addresses 0 to 1FFh, however one WAIT cycle is automatically added for a
Read cycle, while a byte write cycle to the
Figure 1-4. Memory Map
10/56

EEPROM will cause the start of an ERASE/WRITE
cycle at the addressed location. Word (16 bit)
writes are not allowed.
The programming cycle is self-timed, with a typical
programming time of 6ms. The voltage necessary
for programming the EEPROM is internally generated with a +18V charge pump circuit.
Up to 16 bytes of data may be programmed into
the EEPROM during the same write cycle by using
the PARALLEL WRITE function.
A standbymode is also available which disables all
power consumption sources within the EEPROM
for low power requirements. When STBY is high,
any attempt to access the EEPROM memory will
produce unpredictable results. After the re-enabling of the EEPROM, a delay of 6 INTCLK cycles
must be allowed before the selection of the
EEPROM.
The EEPROM of the ST9040 has been implemented in a high reliability technology developed
by SGS-THOMSON, this, together with the double
bit structure,allow 300k Erase/Write cycles and 10
year data retention to be achieved on a microcontroller.
Control of the EEPROM is performed through one
registermapped at register addressR241 in Page0.
ST9040
EEPROM (Continued)
1.3.2.2 EEPROM Programming Procedure
The programming of a byte of EEPROMmemory is
equivalent to writing a byte into a RAM location after verifying that EEBUSY bit is low. Instructions
operating on word data (16 bits) will not access the
EEPROM.
The EEPROM ENABLE bit EEWEN must first be
set before writing to the EEPROM. When this bit is
low, attempts to write data to the EEPROM have
no affect, this prevents any spurious memory accesses from affecting the data in the EEPROM.
Termination of the write operation can be detected
by polling on the EEBUSY status bit, or by interrupt, taking the interrupt vector from the External
Interrupt 4 channel. The selection of the interrupt is
made by EEPROM Interrupt enable bit EEIEN. It
should be noted that the Mask bit of External Interrupt 4 should be set, and the Interrupt Pending bit
reset, before the setting of EEIEN to prevent unwanted interrupts. A delay (eg a nop instruction)
should also be included between the operationson
the mask and pending bits of External Interrupt 4.
If polling on EEBUSY is used, a delay of 6 INTCLK
clock cycles is necessary after the end of programming, this can be a nop instruction or, normally,
therequired time to test the EEBUSY bit and to
branch to the next instruction will be sufficient.
While EEBUSY is active, any attempt to access the
EEPROM matrix will be aborted and the data read
will be invalid. EEBUSY is a read only bit and cannot be reset by the user if active.
An erased bit of the EEPROM memory will read as
a logic “0”, while a programmed cell will be read as
a logic “1”. For applications requiring the highest
level of reliability, the Verify Mode, set by EEPROM
control register bit VRFY, allows the reading of the
EEPROM memory cells with a reduced gate voltage (typically 20%). If the EEPROM memory cell
has been correctly programmed, a logic “1” will be
read with the reduced voltage,otherwise a logic “0”
will be read.
1.3.2.3 Parallel Programming Procedure
Parallel programming is a feature of the EEPROM
macrocell. One up to sixteen bytes of a same row
can be programmed at once.
The constraint is that each of the bytes occur in the
same ROW of the EEPROM memory (A4 constant,
A3-A0 variable). To operate this mode, the Parallel
Mode enable bit, PLLEN, must be set. The data
written is then latched into buffers (at the addresses specified, which may be non-sequential)
and then transferred to the EEPROM memory by
the setting of the PLLST bit of the control register.
Both PLLST and PLLEN are internally reset at the
end of the programming cycle. Any attempt to read
the EEPROM memory when PLLEN is set will give
invalid data. In the event that the data in the buffer
latches is not required to be written into the memory
by the setting of PLLST, the correct way to terminate
the operation is to reset PLLEN and to perform a
dummy read of theEEPROMmemory. This termination will clear all data present in the latches.
1.3.2.4 EEPROM Programming Voltage
No external Vpp voltage is required, an internal
18Volt charge-pump gives the required energy by
a dedicated oscillator pumping at a typical frequency of 5MHz, regardless of the external clock.
1.3.2.5 EEPROM Programming Time
No timing routine is required to control the programming time as dedicated circuitry takes care of
the EEPROM programming time (The typical programming time is 6ms).
1.3.2.6 EEPROM Interrupt Management
At the end of each write procedure the EEPROM
sends an interrupt request (if EEIEN bit is set). The
EEPROM shares its interrupt channel with the external interrupt source INT4, from which the priority
level is derived.
Care must be taken when EEIEN is reset. The associated external interrupt channel must be disabled (by reseting bit 4 of EIMR, R244) along with
reseting the interrupt pending bit (bit 4 of EIPR,
R243) to prevent unwanted interrupts. A delay instruction (at least 1 nop instruction) must be inserted between these two operations
WARNING. The content of the EEPROM of the
ST9040 family after the out-going test at SGSTHOMSON’s manufacturing location is not guarenteed.
11/56

ST9040
EEPROM (Continued)
1.3.2.7 EEPROM Control Register
EECR R241 (F1h) Page 0 Read/Write
(except EEBUSY: read only)
EEPROM Control Register
Reset value : 0000 0000b (00h)
7
0
0
VERIFY EESTBY EEIEN PLLST PLLEN EEBUSY EEWEN
bit 7 = B7: This bit is forced to “0” after reset and
MUST not be modified by the user.
bit 6 = VERIFY: Set Verify mode. Verify (active
high) is used to activate the verify mode.
The verify mode provides a guarentee of good retention of the programmed bit. When active, the
reading voltage on the cell gate is decreased from
1.2V to 0.0V, decreasing the current from the programmed cell by 20%. If the cell is well programmed (to “1”), a “1” will still be read, otherwise
a “0” will be read.
Note . The verify mode must not be used during an
erasing or a programming cycle).
bit 5 = EESTBY: EEPROM Stand-By. EESTBY =
“1” switches off all power consumption sources inside the EEPROM. Any attempt to access the
EEPROM when EESTBY = “1” will produce unpredictable results.
Note. After EESTBY is reset, the user must wait 6
CPUCLK cycles (e.g. 1 nop instruction) before selecting the EEPROM.
bit 4 = EEIEN: EEPROM Interrupt Enable. INTEN
= “1” disables the external interrupt source INT4,
and enables the EEPROM to send its interrupt request to the central interrupt unit at the end of each
write procedure.
bit 3 = PLLST: Parallel Write Start. Setting PLLST
to “1” starts the parallel writing procedure.It can be
set only if PLLEN is alreadyset. PLLST is internally
reset at the end of the programming sequence.
bit 2 = PLLEN: Parallel write Enable. Setting
PLLEN to “1” enables the parallel writing mode
which allows the user to write up to 16 bytes at the
same time. PLLEN is internally reset at the end of
the programming sequence.
bit 1 = EEBUSY: BUSY. When this read only bit is
high, an EEPROM write operation is in progress
and any attempt to access the EEPROM is
aborted.
bit 0 = EEWEN: EEPROM Write Enable. Setting
this bit allows programming of the EEPROM, when
low a writing attempt has no effect.
1.3.3 REGISTER MAP
Please refer to the Register Map of the ST9036 for
all general registers with the exceptionof the register shown in the following table.
Table 1-5. Register Map Addendum
EECR
R241
(F1h)
Page 0
Read/Write
Figure 1-5. EEPROM Parallel Programming Rows
12/56

Control Registers
ST9040
2 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
AVDD, AVSS
Parameter
Supply Voltage
Analog Supply Voltage
Value
Unit
– 0.3 to 7.0
V
VSS = AVSS < AVDD ≤ VDD
V
VI
Input Voltage
– 0.3 to VDD +0.3
V
VO
Output Voltage
– 0.3 to VDD +0.3
V
– 55 to + 150
°C
TSTG
Storage Temperature
IINJ
Pin Injection Current Digital Input
-5 to +5
mA
IINJ
Pin Injection Current Analog Input
-5 to +5
mA
-50 to +50
mA
Maximum Accumulated Pin injection Current in the device
Note: Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability. All voltages are referenced to V SS
RECOMMENDED OPERATING CONDITIONS
Symbol
Value
Parameter
Min.
TA
Unit
Max.
– 40
85
°C
4.5
5.5
V
External Oscillator Frequency
24
MHz
Internal Clock Frequency (INTCLK)
12
MHz
Operating Temperature
VDD
Operating Supply Voltage
fOSCE
fOSCI
13/56

ST9040
DC ELECTRICAL CHARACTERISTICS
VDD = 5V ± 10% TA = – 40 °C to + 85°C, unless otherwise specified)
Symbol
Parameter
Test Conditions
Value
Min.
Typ.
Max.
Unit
VIHCK
Clock Input High Level
External Clock
0.7 VDD
VDD + 0.3
V
VILCK
Clock Input Low Level
External Clock
– 0.3
0.3 VDD
V
VIH
Input High Level
VIL
Input Low Level
2.0
VDD + 0.3
V
0.7 VDD
VDD + 0.3
V
TTL
– 0.3
0.8
V
CMOS
– 0.3
0.3 VDD
V
TTL
CMOS
VIHRS
RESET Input High Level
0.7 VDD
VDD + 0.3
V
VILRS
RESET Input Low Level
–0.3
0.3 VDD
V
VHYRS
RESET Input Hysteresis
0.3
1.5
V
VOH
VOL
IWPU
Output High Level
Push Pull, Iload = – 0.8mA
Output Low Level
Push Pull or Open Drain,
Iload = 1.6mA
Weak Pull-up Current
VDD – 0.8
V
0.4
V
Bidirectional Weak Pullup, VOL = 0V
– 50
– 200
– 420
µA
– 200
– 420
µA
IAPU
Active Pull-up Current,
for INT0 and INT7 only
VIN < 0.8V, under Reset
– 80
ILKIO
I/O Pin Input Leakage
Input/Tri-State,
0V < VIN < VDD
– 10
+ 10
µA
ILKRS
Reset Pin Input Leakage
ILKAD
A/D Pin Input Leakage
0V < VIN < VDD
– 30
+ 30
µA
Alternate Function,
Open Drain,
0V < VIN < VDD
–3
+3
µA
ILKAP
Active Pull-up Input
Leakage
0V < VIN < 0.8V
– 10
+ 10
µA
ILKOS
OSCIN Pin Input Leakage
0V < VIN < VDD
– 10
+ 10
µA
Note: All I/O Ports are configured in Bidirectional Weak Pull-up Mode with no DC load, External Clock pin (OSCIN) is driven by square wave
external clock. No peripheral working.
DC TEST CONDITIONS
14/56

ST9040
AC ELECTRICAL CHARACTERISTICS
(VDD = 5V ± 10% TA = – 40 °C to + 85°C, unless otherwise specified)
Symbol
Parameter
Value
Test Conditions
Min.
Typ.
Unit
Max.
IDD
Run Mode Current
no CPUCLK prescale,
Clock divide by 2
24MHz, Note 1
40
mA
IDP2
Run Mode Current
Prescale by 2
Clock divide by 2
24MHz, Note 1
30
mA
IWFI
WFI Mode Current
no CPUCLK prescale,
Clock divide by 2
24MHz, Note 1
20
mA
IHALT
HALT Mode Current
24MHz, Note 1
100
µA
Note 1: All I/O Ports are configured in Bidirectional Weak Pull-up Mode with no DC load, External Clock pin (OSCIN) is driven by square wave
external clock. No peripheral working.
15/56

ST9040
CLOCK TIMING TABLE
(VDD = 5V ± 10%, TA = – 40°C to + 85°C, INTCLK = 12MHz, unless otherwise specified)
N°
Symbol
Value
Parameter
Unit
Note
41.5
ns
1
83
ns
2
Min.
1
TpC
OSCIN Clock Period
2
TrC, TfC
OSCIN Rise and Fall Time
3
TwCL, TwCH
OSCIN Low and High Width
17
38
Notes:
1.
Clock divided by 2 internally (MODER.DIV2=1)
2.
Clock not divided by 2 internally (MODER.DIV2=0)
CLOCK TIMING
16/56

Max.
12
ns
25
ns
1
ns
2
ST9040
EXTERNAL BUS TIMING TABLE
(VDD = 5V ± 10%,TA = – 40 °C to + 85 °C, Cload = 50pF, CPUCLK = 12MHz, unless otherwise specified)
Value (Note)
N°
Symbol
Parameter
OSCIN Divided
By 2
Unit
OSCIN Not Divided
Min. Max.
By 2
1
TsA (AS)
Address Set-up Time
before AS ↑
TpC (2P+1) –22
TWCH+PTpC –18
20
ns
2
ThAS (A)
Address Hold Time after AS ↑
TpC –17
TwCL –13
25
ns
3
TdAS (DR)
AS ↑ to Data Available (read)
TpC (4P+2W+4) –52 TpC (2P+W+2) –51
4
TwAS
AS Low Pulse Width
TpC (2P+1) –7
TwCH+PTpC –3
35
ns
5
TdAz (DS)
Address Float to DS ↓ t
12
12
12
ns
6
TwDSR
DS Low Pulse Width (read)
TpC (4P+2W+3) –20
TwCH+TpC
(2P+W+1) –16
105
ns
7
TwDSW
DS Low Pulse Width (write)
TpC (2P+2W+2) –13 TpC (P+W+1) –13
70
ns
8
TdDSR (DR)
DS ↓ toData Valid Delay (read)
TpC (4P+2W-3) –50
TwCH+TpC(2P+W+1)
–46
9
ThDR (DS)
Data to DS ↑ Hold Time (read)
0
0
115
75
ns
ns
0
ns
10
TdDS (A)
DS ↑ to Address Active Delay
TpC –7
TwCL –3
35
ns
11
TdDS (AS)
DS ↑ to AS ↓ Delay
TpC –18
TwCL –14
24
ns
12
TsR/W (AS)
R/W Set-up Time before AS ↑
TpC (2P+1) –22
TwCH+PTpC –18
20
ns
13
TdDSR (R/W)
DS ↑ to R/W and Address Not
Valid Delay
TpC –9
TwCL –5
33
ns
14
TdDW (DSW)
Write Data Valid to DS ↓ Delay
(write)
TpC (2P+1) –32
TwCH+PTpC –28
10
ns
15
ThDS (DW)
Data Hold Time after DS ↑ (write) TpC –9
TwCL –5
33
ns
16
TdA (DR)
Address Valid to Data Valid
Delay (read)
TpC (6P+2W+5) –68
TwCH+TpC
(3P+W+2) –64
17
TdAs (DS)
AS ↑ to DS ↓ Delay
TpC –18
TwCL –14
140
24
ns
ns
EXTERNAL WAIT TIMING TABLE
(VDD = 5V ± 10%,TA = –40°C to +85°C, Cload = 50pF,
INTCLK = 12MHz, Push-pull output configuration, unless otherwise specified)
Value (Note)
N°
Symbol
Parameter
OSCIN Divided
By 2
Unit
OSCIN Not Divided
Min. Max.
By 2
1
TdAs (WAIT)
AS ↑ to WAIT ↓ Delay
2(P+1)TpC –29
2(P+1)TpC –29
2
TdAs (WAIT)
AS ↑ to WAIT ↓ Min. Delay
2(P+W+1)TpC –4
2(P+W+1)TpC –4
3
TdAs (WAIT)
AS ↑ to WAIT ↓ Max. Delay
2(P+W+1)TpC –29
2(P+W+1)TpC –29
40
80
ns
ns
83W+
ns
40
Note: (for both tables) The value in the left hand two columns show the formula used to calculate the timing minimum or maximum from the
oscillator clock period, prescale value and number of wait cycles inserted.
The value in the right hand two columns show the timing minimum and maximum for an external clock at 24 MHz divided by 2, prescaler value
of zero and zero wait status.
Legend:
P = Clock Prescaling Value
W = Wait Cycles
TpC =OSCIN Period
TwCH =High Level OSCIN half period
TwCL =Low Level OSCIN half period
17/56

ST9040
EXTERNAL BUS TIMING
EXTERNAL WAIT TIMING
18/56

ST9040
HANDSHAKE TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +85°C, Cload = 50pF, INTCLK = 12MHz,
Push-pull output configuration, unless otherwise specified)
Value (Note)
N°
Symbol
Parameter
OSCIN Divided
By 2
Min.
1
TwRDY
RDRDY, WRRDY Pulse
2TpC
Width in One Line
(P+W+1) –18
Handshake
2
TwSTB
RDSTB, WRSTB Pulse
Width
3
TdST
(RDY)
RDSTB, or WRSTB ↑
to RDRDY or WRRDY ↓
4
TsPD
(RDY)
Port Data to RDRDY ↑
Set-up Time
5
TsPD
(RDY)
Max.
2TpC+12
OSCIN Not Divided
By 2
Min.
Min. Max. Unit
Max.
TpC
(P+W+1) –
18
65
ns
TpC+12
95
ns
(TpC-TwCL)
+45
TpC+45
87
ns
(2P+2W+1)
TpC –25
TwCH+
(W+P)
TpC –25
16
ns
Port Data to WRRDY ↓
Set-up Time in One Line
Handshake
43
43
43
ns
6
ThPD
(RDY)
Port Data to WRRDY ↓
Hold
Time in One Line
Handshake
0
0
0
ns
7
TsPD
(STB)
Port Data to WRSTB ↑
Set-up Time
10
10
10
ns
8
ThPD
(STB)
Port Data to WRSTB ↑
Hold Time
25
25
25
ns
9
TdSTB
(PD)
RDSTBD ↑ to Port Data
Delay Time in
Bidirectional Handshake
35
35
35
ns
10
TdSTB
(PHZ)
RDSTB ↑ to Port High-Z
Delay Time in
Bidirectional Handshake
25
25
25
ns
Note: The value in the left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock
period, prescale value and number of wait cycles inserted.
The value in the right hand two columns show the timing minimum and maximum for an external clock at 24 MHz divided by 2, prescaler value
of zero and zero wait status.
Legend:
P
= Clock Prescaling Value (R235.4,3,2)
W
= Programmable Wait Cycles (R252.2.1.0/5,4,3) + External Wait Cycles
19/56

ST9040
HANDSHAKE TIMING
20/56

ST9040
BUS REQUEST/ACKNOWLEDGE TIMING TABLE (VDD = 5V ± 10%,TA = –40°C to +85°C, Cload = 50pF,
INTCLK = 12MHz, Push-pull output configuration, unless otherwise specified)
Value (Note)
N°
1
Symbol
TdBR (BACK)
Parameter
Unit
OSCIN Divided
By 2
OSCIN Not Divided
By 2
TpC+8
TwCL+12
TpC(6P+2W+7)+65
TpC(3P+W+3)+TwCL+65
360
ns
3TpC+60
TpC+TwCL+60
185
ns
BREQ ↓ to BUSACK ↓
Min. Max.
50
ns
2
TdBR (BACK)
BREQ ↑ to BUSACK ↑
3
TdBACK (BREL)
BUSACK ↓ to Bus
Release
20
20
20
ns
4
TdBACK (BACT)
BUSACK ↑ to Bus
Active
20
20
20
ns
Note: The value left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock period,
prescale value and number of wait cycles inserted.
The value right hand two columns show the timing minimum and maximum for an external clock at 24MHz divided by 2, prescale value of zero
and zero wait status.
BUS REQUEST/ACKNOWLEDGE TIMING
Note : MEMINT = Group of memory interface signals: AS, DS, R/W, P00-P07, P10-P17
21/56

ST9040
EXTERNAL INTERRUPT TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +85°C, Cload = 50pF,
INTCLK = 12MHz, Push-pull output configuration, unless otherwise specified)
Value (Note)
OSCIN
OSCIN Not
Unit
Divided By Divided By Min. Max.
2 Min.
2 Min.
N°
Symbol
Parameter
1
TwLR
Low Level Minimum Pulse Width in Rising Edge Mode
2TpC+12
TpC+12
95
ns
2
TwHR
High Level Minimum Pulse Width in Rising Edge Mode
2TpC+12
TpC+12
95
ns
3
TwHF
High Level Minimum Pulse Width in Falling Edge Mode
2TpC+12
TpC+12
95
ns
4
TwLF
Low Level Minimum Pulse Width in Falling Edge Mode
2TpC+12
TpC+12
95
ns
Note: The value left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock period,
prescale value and number of wait cycles inserted.
The value right hand two columns show the timing minimum and maximum for an external clock at 24 MHz divided by 2, prescale value of zero
and zero wait status.
EXTERNAL INTERRUPT TIMING
22/56

ST9040
SPI TIMING TABLE (VDD = 5V ± 10%, T A = –40°C to +85°C, Cload = 50pF, INTCLK = 12MHz,
Output Alternate Function set as Push-pull)
N°
Symbol
Value
Parameter
Min.
Unit
Max.
1
TsDI
Input Data Set-up Time
100
ns
2
ThDI (1)
Input Data Hold Time
1/2 TpC+100
ns
3
TdOV
SCK to Output Data Valid
4
ThDO
Output Data Hold Time
-20
ns
5
TwSKL
SCK Low Pulse Width
300
ns
6
TwSKH
SCK High Pulse Width
300
ns
100
ns
Note: TpC is the OSCIN Clock period.
SPI TIMING
23/56

ST9040
WATCHDOG TIMING TABLE(VDD = 5V ± 10%, TA = – 40 °C to +85°C, Cload = 50pF,
CPUCLK = 12MHz, Push-pull output configuration, unless otherwise specified )
N°
Symbol
Values
Parameter
Min.
Unit
Max.
1
TwWDOL
WDOUT Low Pulse Width
620
ns
2
TwWDOH
WDOUT High Pulse Width
620
ns
3
TwWDIL
WDIN High Pulse Width
350
ns
4
TwWDIH
WDIN Low Pulse Width
350
ns
WATCHDOG TIMING
24/56

ST9040
A/D CONVERTER
EXTERNAL TRIGGER TIMING (VDD = 5V ± 10%, TA = –40°C to +85°C, Cload = 50pF)
N°
Symbol
Parameter
Oscin divided
by 2 (1)
Min.
Max.
Oscin not
divided (1)
Min.
Max.
Value(2)
Min.
Unit
Max.
1
TLOW
External Trigger pulse width
2xT PC
TPC
83
ns
2
THIGH
External Trigger pulse
2xT PC
TPC
83
ns
3
TEXT
External trigger active
edges distance
138xTPC
69xTPC
5.75
µs
4
TSTR
Internal delay between
EXTRG falling edge and first
conversion start
TPC
3xTPC
0.5xTPC 1.5xTPC
41.5
125
ns
Notes:
1.
Variable clock (TPC=OSCIN clock period)
2.
INTCLK=12MHz
A/D External Trigger Timing
25/56

ST9040
A/D INTERNAL TRIGGER TIMING TABLE
N°
Symbol
OSCIN
Divided by 2 (2)
Parameter
Min.
Max.
OSCIN
Not Divided by 2 (2)
Min.
Max.
Value (3)
Unit
Min.
Max.
1
TwHIGH
Internal trigger
pulse width
Tpc
.5 x Tpc
41.5
-
ns
2
TwLOW
Internal trigger
pulse distance
6 x Tpc
3 x Tpc
250
-
ns
3
TwEXT
Internal trigger
active edges
distance (1)
276n x Tpc
138n x Tpc
n x 11.5
-
µs
TwSTR
Internal delay
between INTRG
rising edge and
first conversion
start
41.5
125
ns
4
Tpc
3 x Tpc
A/D INTERNAL TRIGGER TIMING
26/56

.5 x Tpc
1.5 x Tpc
ST9040
A/D CHANNEL ENABLE TIMING TABLE
N°
Symbol
OSCIN
Divided by 2 (2)
Parameter
Min.
1
TwEXT
CEn Pulse width
(1)
Max.
276n x Tpc
OSCIN
Not Divided by 2 (2)
Min.
138n x Tpc
Max.
Value (3)
Unit
Min.
Max.
n x 11.5
-
µs
Notes:
1.
n = number of autoscanned channels (1 < n < 8)
2.
Variable clock (Tpc = OSCIN clock period)
3.
CPUCLK = 12MHz
A/D CHANNEL ENABLE TIMING
27/56

ST9040
A/D ANALOG SPECIFICATIONS
Parameter
Typical (1)
Minimum
Maximum
Units (2)
3
AVCC
VCC
V
Analog Input Range
A VCC
Notes
11.5
µs
(3, 4)
Sample time
3
µs
(3)
Power-up time
60
µs
8
βιτσ
00
Hex
Conversion time
Resolution
8
Monotonicity
GUARANTEED
No missing codes
GUARANTEED
Zero input reading
Full scale reading
FF
Hex
Offset error
.5
1
LSBs
(2,6)
Gain error
.5
1
LSBs
(6)
Diff. Non Linearity
±.3
±.5
LSBs
(6)
Int. Non Linearity
1
LSBs
(6)
Absolute Accuracy
1
LSBs
(6)
45
49
dB
13.5
16
11
KΩ
12
8
15
KΩ
Hold Capacitance
30
pF
Input Leakage
±3
µA
±.2
S/N
AVCC/AVSS Resistance
Input Resistance
Notes:
1.
The values are expected at 25 degree Centigrade with AVCC = 5V
2.
“LSBs”, as used here, has a value of AVCC/256
3.
@ 12MHz internal clock
4.
Including sample time
5.
It must be intended as the internal series resistance before the sampling capacitor
6.
This is a typical expected value, but not a tested production parameter.
If V(i) is the value of the i-th transition level (0 < i < 254), the performance of the A/D co nverter has been valued as follows:
OFFSET ERROR = deviation between the actual V(0) and the ideal V(0) (=1/2 LSB)
GAIN ERROR = deviation between the actual V(254) and the ideal V(254) (=AVCC-3/2 LSB)
DNL ERROR = max {[V(i) - V(i-1)]/LSB - 1}
INL ERROR = max {[V(i) - V(0)]/LSB - i}
28/56

(5)
ST9040
MULTIFUNCTION TIMER UNIT EXTERNAL TIMING TABLE
N°
Symbol
OSCIN
Divided
by 2
Parameter
(3)
OSCIN
Not
Divided
by 2
(3)
Value (4)
Min.
Max.
Unit
Note
1
TwCTW
External clock/trigger pulse width
2n x Tpc
n x Tpc
n x 83
-
ns
1
2
TwCTD
External clock/trigger pulse distance
2n x Tpc
n x Tpc
n x 83
-
ns
1
3
TwAED
Distance between two active edges
6 x Tpc
3 x Tpc
249
-
ns
4
TwGW
Gate pulse width
12 x Tpc
6 x Tpc
498
-
ns
5
TwLBA
Distance between TINB pulse edge and
the following TINA pulse edge
2 x Tpc
Tpc
83
-
ns
2
6
TwLAB
Distance between TINA pulse edge and
the following TINB pulse edge
0
0
-
ns
2
7
TwAD
Distance between two TxINA pulses
0
0
-
ns
2
8
TwOWD
Minimum output pulse width/distance
6 x Tpc
249
-
ns
Notes:
1.
n = 1 if the input is rising OR falling edge sensitive
n = 3 if the input is rising AND falling edge sensitive
3 x Tpc
2.In Autodiscrimination mode
3.Variable clock ( Tpc = OSCIN period )
4.INTCLK = 12 MHz
MULTIFUNCTION TIMER UNIT EXTERNAL TIMING
29/56

ST9040
SCI TIMING TABLE
(VDD = 5V ± 10%, TA = - 40°C to +85°C, Cload = 50pF, INTCLK = 12MHz,
Output Alternate Function set as Push-pull)
N°
Symbol
Parameter
Value
Condition
Min.
FRxCKIN
TwRxCKIN
FTxCKIN
TwTxCKIN
Frequency of RxCKIN
RxCKIN shortest pulse
Frequency of TxCKIN
TxCKIN shortest pulse
1 x mode
FCK/8
Hz
16 x mode
FCK/4
Hz
1 x mode
4 TCK
s
16 x mode
2 TCK
s
1 x mode
FCK/8
Hz
16 x mode
FCK/4
Hz
1 x mode
4 TCK
s
16 x mode
2 TCK
s
TPC/2
ns
1
TsDS
DS (Data Stable) before rising
edge of RxCKIN
1 x mode reception with RxCKIN
2
TdD1
TxCKIN to Data out delay Time
1 x mode transmission with
external clock C load <100pF
3
TdD2
CLKOUT to Data out delay Time
1 x mode transmission with
CLKOUT
Note: FCK = 1/TCK
SCI TIMING
30/56

Unit
Max.
2.5 TPC
350
ns
ns
ST9040
PACKAGE MECHANICAL DATA
80-Pin Plastic Quad Flat Package
Dim.
mm
Min
Typ
A
A2
inches
Max
Min
Typ
3.40
2.55 2.80
Max
0.134
3.05 0.100 0.110 0.120
D
22.95 23.20 24.45 0.903 0.913 0.923
D1
19.90 20.00 20.10 0.783 0.787 0.791
D3
18.40
0.724
E
16.95 17.20 17.45 0.667 0.677 0.687
E1
13.90 14.00 14.10 0.547 0.551 0.555
E3
12.00
e
0.80
0.472
0.032
Number of Pins
N
80
ND
24
NE
16
Short Footprint recommended Padding
Short Footprint Measurement
31/56

ST9040
68-Pin Plastic Leadless Chip Carrier
Dim.
A
A1
A3
B
B1
D
D1
D3
E
E1
E3
K1
h
e
N
ND
NE
mm
Min Typ Max Min
4.20
5.08 0.165
0.51
0.020
2.29
3.30 0.090
25.02
25.27 0.985
24.13
24.33 0.950
20.32
25.02
25.27 0.985
24.13
24.33 0.950
20.32
1.27
inches
Typ Max
0.200
-
0.130
0.995
0.958
0.800
0.995
0.958
0.800
-
0.050
Number of Pins
68
16
16
ORDERING INFORMATION
Sales Type
Frequency
Temperature Range
ST9040Q1/XX
ST9040C1/XX
0°C to + 70°C
24MHz
Package
PQFP80
PLCC68
ST9040C6/XX
-40°C to + 85°C
PLCC68
Note: ”XX” is the ROM code identifier that is allocated by SGS-THOMSON after receipt of all requi red options and the related ROM file.
32/56

-
ST9040
ST9040 STANDARD OPTION LIST
Please copy this page (enlarge if possible) and complete ALL sections.
Send the form, with the ROM code image required, to your local SGS-THOMSON sales office.
Customer Company :
Company Address :
Telephone :
FAX :
Contact :
[. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ]
[. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ]
[. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ]
[. . . . . . . . . . . . . . . . . . . . . . . . . . ]
[. . . . . . . . . . . . . . . . . . . . . . . . . . ]
Telephone (Direct) : [. . . . . . . . . . . . . . . . . . . . . . . . . . ]
[. . . . . . . . . . . . . . . . . . . . . . . . . . ]
Please confirm characteristics of device :
Device
ST9040
Package
[
] PQFP80
Temperature Range
[
] -40°C to +85°C
[
] PLCC68
[
] 0°C to +70°C
Special Marking
[ ] No
[ ] Yes
14 characters [ | | | | | | | | | | | | | ]
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Please consult your local SGS-THOMSON sales office for other marking details if required.
Notes :
Code :
[
[
] EPROM (27128, 27256)
] HEX format files on IBM-PC compatible disk
filename : [. . . . . . . . . . . . . . . . . . . . . . ]
Confirmation :
[
] Code checked with EPROM device in application
Yearly Quantity forecast :
- for a period of :
[. . . . . . . . . . . . . . . . . . . . . . . . . . . ] k units
[. . . . . . . . . . . . . . . . . . . . . . . . . . . ] years
Preferred Production start dates : [. .. . . . . . . . . . . . . . . . . . . . . ] (YY/MM/DD)
Customer Signature :
Date :
33/56

ST9040
NOTES :
34/56

ST90E40
ST90T40

16K EPROM HCMOS MCU
WITH EEPROM, RAM AND A/D CONVERTER
Register oriented 8/16 bit CORE with
RUN, WFI and HALT modes
Minimum instruction cycle time: 500ns
(12MHz internal)
Internal Memory :
EPROM
16Kbytes
RAM
256 bytes
EEPROM
512 bytes
224 general purpose registers available as
RAM, accumulators or index pointers
(Register File)
PQFP80
80-pin Plastic Quad Flat Pack package for
ST90T40Q
68-lead Plastic Leaded Chip Carrier package for
ST90T40C
80-pin Windowed Ceramic Quad Flat Pack
package for ST90E40G
PLCC68
68-lead Windowed Ceramic LeadedChip Carrier
package for ST90E40L
DMA controller, Interrupt handler and Serial Peripheral Interface as standard features
56 fully programmable I/O pins
Up to 8 external plus 1 non-maskableinterrupts
16 bit Timer with 8 bit Prescaler, able to be used
as a WatchdogTimer
CQFP80W
Two 16 bit Multifunction Timers, each with an 8
bit prescaler and 13 operating modes
8 channel 8 bit Analog to Digital Converter, with
Analog Watchdogs and external references
Serial Communications Interface with asynchronous and synchronous capability
Rich Instruction Set and 14 Addressingmodes
CLCC68W
Division-by-Zero trap generation
Versatile Development tools,including assembler,
linker, C-compiler, archiver, graphic oriented debuggerand hardware emulators
(Ordering Information at the end of the Datasheet)
Real Time Operating System
Compatible with ST9036 and ST9040 16K ROM
devices
March 1994
35/56
ST90E40 - ST90T40
Figure 1. 80 Pin QFP Package
Table 1. ST90E40G-ST90T40QPin Description
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
AVSS
25
P34/T1INA
64
P20/NMI
80
AVDD
2
NC
26
P33/T0OUTB
63
NC
79
NC
3
NC
27
P32/T0INB
62
VSS
78
P47/AIN7
4
P44/AIN4
28
P31/T0OUTA
61
P70/SIN
77
P46/AIN6
5
P57
29
P30/P/D/T0INA
60
P71/SOUT
76
P45/AIN5
6
P56
30
P17/A15
P43/AIN3
7
P55
31
P16/A14
P72/INT4/TXCLK
/CLKOUT
75
74
P42/AIN2
8
P54
32
NC
58
P73/INT5
/RXCLK/ADTRG
73
P41/AIN1
72
P40/AIN0
71
P27/RRDY5
70
P26/INT3
/RDSTB5/P/D
69
P25/WRRDY5
68
P24/INT1
/WRSTB5
59
9
INT7
33
P15/A13
10
INT0
34
P14/A12
57
P74/P/D/INT6
11
P53
35
P13/A11
56
P75/WAIT
12
NC
36
P12/A10
13
P52
37
P11/A9
55
P76/WDOUT
/BUSREQ
14
P51
38
P10/A8
15
P50
39
P00/A0/D0
54
P77/WDIN
/BUSACK
16
OSCOUT
40
P01/A1/D1
53
R/W
67
P23/SDO
17
VSS
52
NC
66
P22/INT2/SCK
18
VSS
51
DS
65
P21/SDI/P/D
19
NC
50
AS
20
OSCIN
49
NC
21
RESET/VPP
48
VDD
22
P37/T1OUTB
47
VDD
23
P36/T1INB
46
P07/A7/D7
24
P35/T1OUTA
45
P06/A6/D6
44
P05/A5/D5
43
P04/A4/D4
42
P03/A3/D3
41
P02/A2/D2
36/56

ST90E40 - ST90T40
Figure 2. 68 Pin LCC Package
Table 2. ST90E40L-ST90T40C
Pin
Name
Pin
Name
Pin
Name
Pin
Name
61
P44/AIN4
10
P35/T1OUTA
43
P70/SIN
60
AVSS
62
P57
11
P34/T1INA
42
P71/SOUT
59
AVDD
63
P56
12
P33/T0OUTB
13
P32/T0INB
P72/CLKOUT
/TXCLK/INT4
P47/AIN7
P55
41
58
64
57
P46/AIN6
65
P54
14
P31/T0OUTA
INT7
15
P30/P/D/T0INA
P73/ADTRG
/RXCLK/INT5
P45/AIN5
66
40
56
55
P43/AIN3
67
INT0
16
P17/A15
39
P74/P/D/INT6
54
P42/AIN2
68
P53
17
P16/A14
38
P75/WAIT
53
P41/AIN1
● 1
P52
18
P15/A13
19
P14/A12
P76/WDOUT
/BUSREQ
P40/AIN0
P51
37
52
2
51
P27/RRDY5
3
P50
20
P13/A11
4
OSCOUT
21
P12/A10
36
P77/WDIN
/BUSACK
50
P26/INT3
/RDSTB5/P/D
49
P25/WRRDY5
48
P24/INT1
/WRSTB5
5
VSS
22
P11/A9
35
R/W
6
OSCIN
23
P10/A8
34
DS
7
RESET/VPP
24
P00/A0/D0
33
AS
8
P37/T1OUTB
25
P01/A1/D1
32
VDD
47
P23/SDO
9
P36/T1INB
26
P02/A2/D2
31
P07/A7/D7
46
P22/INT2/SCK
30
P06/A6/D6
45
P21/SDI/P/D
29
P05/A5/D5
44
P20/NMI
28
P04/A4/D4
27
P03/A3/D3
37/56

ST90E40 - ST90T40
1.1 GENERAL DESCRIPTION
The ST90E40 and ST90T40 (following mentioned
as ST90E40)are EPROM members ofthe ST9 familyof microcontrollers, in windowed ceramic (E) and
plastic OTP (T) packages respectively, completely
developed and produced by SGS-THOMSON Microelectronics using a n-well proprietary HCMOS
process.
The EPROM parts are fully compatible with their
ROM versions and this datasheet will thus provide
only information specific to the EPROM based devices.
THE READER IS ASKED TO REFER TO THE
DATASHEET OF THE ST9040 ROM-BASED DEVICE FOR FURTHER DETAILS.
The EPROM ST90E40 may be used for the prototyping and pre-production phases of development,
and can be configured as: a standalone microcontroller with 16K bytes of on-chip EPROM, a microcontroller able to manageexternal memory, or as a
parallel processing element in a system with other
processors and peripheral controllers.
The nucleus of the ST90E40 is the advanced Core
which includes the Central Processing Unit (CPU),
the Register File, a 16 bit Timer/Watchdog with 8
bit Prescaler, a Serial Peripheral Interface supporting S-bus, I2C-bus and IM-bus Interface,plus two 8
bit I/O ports. The Core has independent memory
and register buses allowing a high degree of pipelining to add to the efficiency of the code execution
speed of the extensive instruction set.
The powerful I/O capabilities demanded by microcontroller applications are fulfilled by the ST90E40
with up to 56 I/O lines dedicated to digital Input/Output. These lines are grouped into up to
seven 8 bit I/O Ports and can be configured on a bit
basis under software control to provide timing,
status signals, an address/data bus for interfacing
external memory, timer inputs and outputs, analog
inputs, external interrupts and serial or parallel I/O
with or without handshake.
Figure 3. ST90E40 Block Diagram
INT0
INT7
8
1 6-Bit TIMER / WATCHDOG + SPI
16k Bytes
512 Bytes
256 Bytes
256 Bytes
EPROM
EEPROM
RAM
REGISTER FILE
CPU
SCI
WITH DMA
I/O PORT 7
( SCI )
MEMORY BUS
REGISTER BUS
I/O PORT 0
( Address/Data )
I/O PORT 1
( Address )
I/O PORT 2
( SPI )
I/O PORT 3
( TIMERS )
8
8
8
8
2 x 16-bit TIMER
W ITH DM A
I/O PORT 4
( Ana log Inpu ts )
A /D
CONVERTER
I/O PORT 5
WITH HANDSHAKE
8
8
AVD D
AVS S
VR0A1385
38/56

ST90E40 - ST90T40
GENERAL DESCRIPTION (Continued)
Three basic memory spaces are available to support this wide range of configurations: Program
Memory (internal and external),Data Memory (external) and the Register File, which includes the
control and status registers of the on-chip peripherals.
Two 16 bit MultiFunction Timers, each with an 8 bit
Prescaler and 13 operating modes allow simple
use for complex waveform generation and measurement, PWM functions and many other systemmsiming functions by the usage of the two
associated DMA channels for each timer.
In addition there is an 8 channel Analog to Digital
Converter with integral sample and hold, fast 11µs
conversion time and 8 bit resolution. An Analog
Watchdog feature is included for two input channels.
Completing the device is a full duplex Serial Communications Interface with an integral 110 to
375,000 baud rate generator, asynchronous and
1.5Mbyte/s synchronous capability (fully programmable format) and associated address/wake-up
option, plus two DMA channels.
1.2 PIN DESCRIPTION
AS. Address Strobe (output, active low, 3-state).
Address Strobe is pulsed low once at the beginning of each memory cycle. The rising edge of AS
indicates that address, Read/Write (R/W), and
Data Memory signals are valid for program or data
memory transfers. Under program control, AS can
be placed in a high-impedance state along with
Port 0 and Port 1, Data Strobe (DS) and R/W.
DS. Data Strobe (output, active low, 3-state). Data
Strobe provides the timing for data movement to or
from Port 0 for each memory transfer. During a write
cycle, data out is valid at the leading edge of DS.
During a readcycle, DataIn must be valid prior to the
trailing edge of DS. When the ST9040 accessesonchipmemory, DS is held high duringthe wholememory cycle. It can be placed in a high impedancestate
along with Port 0, Port 1, AS andR/W.
R/W. Read/Write (output, 3-state). Read/Write determines the direction of data transfer for external
memorytransactions.R/W is low when writing to external program or data memory,and high for all other
transactions. It can be placed in a high impedance
state along with Port 0, Port 1, AS and DS.
RESET/VPP. Reset (input, active low) or VPP (input). The ST9 is initialised by the Reset signal.
With the deactivation of RESET, program execution begins from the Program memory location
pointed to by the vector contained in program
memory locations 00h and 01h. In the EPROM
programming Mode, this pin acts as the programming voltage input VPP.
iNT0, INT7. Externalinterrupts (input, active on rising or falling edge). External interrupt inputs 0 and
7 respectively. INT0 channel may also be used for
the timer watchdog interrupt.
OSCIN, OSCOUT. Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the input of the oscillator inverter and internal clock generator; OSCOUT is the output of the oscillator
inverter.
AVDD. Analog VDD of the Analog to Digital Converter.
AVSS. Analog VSS of the Analog to Digital Converter. Must be tied to VSS.
VDD. Main Power Supply Voltage (5V ± 10%)
VSS. Digital Circuit Ground.
P0.0-P0.7, P1.0-P1.7, P2.0-P2.7 P3.0-P3.7, P4.0P4.7, P5.0-P5.7, P7.0-P7.7 I/O Port Lines (Input/Output, TTL or CMOS compatible). 56 lines
grouped into I/O ports of 8 bits, bit programmable
under program control as general purpose I/O or
as alternate functions.
1.2.1 I/O PORT ALTERNATE FUNCTIONS
Each pin of the I/O ports of the ST90E40/T36 may
assume software programmable Alternative Functions as shown in the Pin Configuration Tables.
Due to Bonding options for the packages, some
functions may not be present, Table 3 shows the
Functions allocatedto each I/O Port pin and a summary of packages for which they are available.
39/56

ST90E40 - ST90T40
PIN DESCRIPTION (Continued)
Table 3. ST90E40, T40 I/O Port Alternate Function Summary
I/O PORT
Name
Function
Alternate Function
Port. bit
Pin Assignment
PLCC
PQFP
P0.0
A0/D0
I/O
Address/Data bit 0 mux
24
39
P0.1
A1/D1
I/O
Address/Data bit 1 mux
25
40
P0.2
A2/D2
I/O
Address/Data bit 2 mux
26
41
P0.3
A3/D3
I/O
Address/Data bit 3 mux
27
42
P0.4
A4/D4
I/O
Address/Data bit 4 mux
28
43
P0.5
A5/D5
I/O
Address/Data bit 5 mux
29
44
P0.6
A6/D6
I/O
Address/Data bit 6 mux
30
45
P0.7
A7/D7
I/O
Address/Data bit 7 mux
31
46
P1.0
A8
O
Address bit 8
23
38
P1.1
A9
O
Address bit 9
22
37
P1.2
A10
O
Address bit 10
21
36
P1.3
A11
O
Address bit 11
20
35
P1.4
A12
O
Address bit 12
19
34
P1.5
A13
O
Address bit 13
18
33
P1.6
A14
O
Address bit 14
17
31
P1.7
A15
O
Address bit 15
16
30
P2.0
NMI
I
Non-Maskable Interrupt
44
64
P2.0
ROMless
I
ROMless Select (Mask option)
44
64
P2.1
P/D
O
Program/Data Space Select
45
65
P2.1
SDI
I
SPI Serial Data Out
45
65
P2.2
INT2
I
External Interrupt 2
46
66
P2.2
SCK
O
SPI Serial Clock
46
66
P2.3
SDO
O
SPI Serial Data In
47
67
P2.4
INT1
I
External Interrupt 1
48
68
P2.4
WRSTB5
I
Handshake Write Strobe P5
48
68
P2.5
WRRDY5
O
Handshake Write Ready P5
49
69
P2.6
INT3
I
External Interrupt 3
50
70
P2.6
RDSTB5
I
Handshake Read Strobe P5
50
70
P2.6
P/D
O
Program/Data Space Select
50
70
P2.7
RDRDY5
O
Handshake Read Ready P5
51
71
P3.0
T0INA
I
MF Timer 0 Input A
15
29
P3.0
P/D
O
Program/Data Space Select
15
29
P3.1
T0OUTA
O
MF Timer 0 Output A
14
28
P3.2
T0INB
I
MF Timer 0 Input B
13
27
P3.3
T0OUTB
O
MF Timer 0 Output B
12
26
P3.4
T1INA
I
MF Timer 1 Input A
11
25
40/56

ST90E40 - ST90T40
PIN DESCRIPTION (Continued)
Table 4. ST90E40, T40 I/O Port Alternate Function Summary
I/O PORT
Name
Function
Alternate Function
Port. bit
Pin Assignment
PLCC
PQFP
P3.5
T1OUTA
O
MF Timer 1 Output A
10
24
P3.6
T1INB
I
MF Timer 1 Input B
9
23
P3.7
T1OUTB
O
MF Timer 1 Output B
8
22
P4.0
Ain0
I
A/D Analog Input 0
52
72
P4.1
Ain1
I
A/D Analog Input 1
53
73
P4.2
Ain2
I
A/D Analog Input 2
54
74
P4.3
Ain3
I
A/D Analog Input 3
55
75
P4.4
Ain4
I
A/D Analog Input 4
61
4
P4.5
Ain5
I
A/D Analog Input 5
56
76
P4.6
Ain6
I
A/D Analog Input 6
57
77
P4.7
Ain7
I
A/D Analog Input 7
58
78
P5.0
I/O
I/O Handshake Port 5
3
15
P5.1
I/O
I/O Handshake Port 5
2
14
P5.2
I/O
I/O Handshake Port 5
1
13
P5.3
I/O
I/O Handshake Port 5
68
11
P5.4
I/O
I/O Handshake Port 5
65
8
P5.5
I/O
I/O Handshake Port 5
64
7
P5.6
I/O
I/O Handshake Port 5
63
6
I/O
P5.7
I/O Handshake Port 5
62
5
P7.0
SIN
I
SCI Serial Input
43
61
P7.1
SOUT
O
SCI Serial Output
42
60
P7.1
ROMless
I
ROMless Select (Mask option)
42
60
P7.2
INT4
I
External Interrupt 4
41
59
P7.2
TXCLK
I
SCI Transmit Clock Input
41
59
P7.2
CLKOUT
O
SCI Byte Sync Clock Output
41
59
P7.3
INT5
I
External Interrupt 5
40
58
P7.3
RXCLK
I
SCI Receive Clock Input
40
58
P7.3
ADTRG
I
A/D Conversion Trigger
40
58
P7.4
INT6
I
External Interrupt 6
39
57
P7.4
P/D
O
Program/Data Space Select
39
57
P7.5
WAIT
I
External Wait Input
38
56
P7.6
WDOUT
O
T/WD Output
37
55
P7.6
BUSREQ
I
External Bus Request
37
55
P7.7
WDIN
I
T/WD Input
36
54
P7.7
BUSACK
O
External Bus Acknowledge
36
54
41/56

ST90E40 - ST90T40
1.1 MEMORY
1.2 EPROM PROGRAMMING
The memory of the ST90E40is functionallydivided
into two areas, the Register File and Memory. The
Memory is divided into two spaces, each having a
maximum of 65,536 bytes. The two memory
spaces are separated by function, one space for
Program code, the other for Data. The ST90E40
16K bytes of on-chip EPROM memory are selected at memory addresses 0 through 3FFFh
(hexadecimal) in the PROGRAM space, while the
ST90T40 OTP version has the top 64 bytes of the
EPROM reserved by SGS-THOMSON for testing
purposes. The DATA space includes the 512 bytes
of on-chip EEPROM at addresses 0 through 1FFh
and the 256 bytes of on-chip RAM memory at
memory addresses 200h through 2FFh.
WARNING. The ST90T40has its 64 upper bytes in
the internal EPROM reserved for testing purpose.
External memory may be addressed using the multiplexed address and data buses (Alternate Functions of Ports 0 and 1). At addresses greater than
the first 16K of program space, the ST90E40 executes external memory cycles for instruction
fetches. Additional Data Memory may be decoded
externally by using the P/D Alternate Function output. The on-chip general purpose (GP) Registers
may also be used as RAM memory for minimum
chip count systems.
The 16384 bytes of EPROM memory of the
ST90E40 (16320 for the ST90T40) may be programmed by using the EPROM Programming
Boards (EPB) available from SGS-THOMSON.
1.2.1 Eprom Erasing
The EPROM of the windowed package of the
ST90E40may be erased by exposureto Ultra-Violet
light.
The erasure characteristic of the ST90E40 is such
that erasure begins when the memory is exposed
to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlight and
some types of fluorescent lamps have wavelengths in the range 3000-4000Å. It is thus recommended that the window of the ST90E40
packages be covered by an opaque label to prevent unintentional erasure problems when testing
the application in such an environment.
The recommended erasure procedure of the
EPROM is the exposure to short wave ultraviolet
light which have a wave-length 2537Å. The integrated dose (i.e. U.V. intensity x exposuretime) for
erasure should be a minimum of 15W-sec/cm2.
The erasure time with this dosage is approximately
15 to 20 minutes using an ultraviolet lamp with
12000µW/cm2 power rating. The ST90E40 should
be placed within 2.5cm (1Inch) of the lamp tubes
during erasure.
Figure 4. Memory Spaces
42/56

ST90E40 - ST90T40
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
AVDD, AVSS
Parameter
Value
Unit
– 0.3 to 7.0
V
VSS = AVSS < AVDD ≤ VDD
V
Supply Voltage
Analog Supply Voltage
VI
Input Voltage
– 0.3 to VDD +0.3
V
VO
Output Voltage
– 0.3 to VDD +0.3
V
VPP
Input Voltage on VPP Pin
TSTG
Storage Temperature
-0.3 to 13.5
V
– 55 to + 150
°C
IINJ
Pin Injection Current Digital
-5 to 5
mA
IINJ
Pin Injection Current Analog
-5 to 5
mA
-50 to 50
mA
Maximum accumulated pin injection Current in the device
Note: Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability. All voltages are referenced to V SS
RECOMMENDED OPERATING CONDITIONS
Symbol
TA
Value
Parameter
Operating Temperature
Unit
Min.
Max.
– 40
85
°C
4.5
5.5
V
VDD
Operating Supply Voltage
fOSCE
External Oscillator Frequency
24
MHz
fOSCI
Internal Clock Frequency (INTCLK)
12
MHz
DC ELECTRICAL CHARACTERISTICS
VDD = 5V ± 10% TA = – 40°C to + 85°C, unless otherwise specified)
Symbol
Parameter
Test Conditions
Value
Min.
Typ.
Max.
Unit
VIHCK
Clock Input High Level
External Clock
0.7 VDD
VDD + 0.3
V
VILCK
Clock Input Low Level
External Clock
– 0.3
0.3 VDD
V
2.0
VDD + 0.3
V
0.7 VDD
VDD + 0.3
V
VIH
Input High Level
VIL
Input Low Level
TTL
CMOS
TTL
– 0.3
0.8
V
CMOS
– 0.3
0.3 VDD
V
VIHRS
RESET Input High Level
0.7 VDD
VDD + 0.3
V
VILRS
RESET Input Low Level
–0.3
0.3 VDD
V
VHYRS
RESET Input Hysteresis
0.3
1.5
V
VOH
VOL
Output High Level
Push Pull, Iload = – 0.8mA
Output Low Level
Push Pull or Open Drain,
Iload = 1.6mA
VDD – 0.8
V
0.4
V
43/56

ST90E40 - ST90T40
DC ELECTRICAL CHARACTERISTICS (continued)
Symbol
IWPU
Parameter
Weak Pull-up Current
Test Conditions
Value
Unit
Min.
Typ.
Max.
Bidirectional Weak Pullup, VOL = 0V
– 50
– 200
– 420
µA
– 200
– 420
µA
IAPU
Active Pull-up Current,
for INT0 and INT7 only
VIN < 0.8V, under Reset
– 80
ILKIO
I/O Pin Input Leakage
Input/Tri-State,
0V < VIN < VDD
– 10
+ 10
µA
ILKRS
Reset Pin Input Leakage
0V < VIN < VDD
– 30
+ 30
µA
Alternate Function,
Open Drain,
0V < VIN < VDD
–3
+3
µA
ILKAD
A/D Pin Input Leakage
ILKAP
Active Pull-up Input
Leakage
0V < VIN < 0.8V
– 10
+ 10
µA
ILKOS
OSCIN Pin Input Leakage
0V < VIN < VDD
– 10
+ 10
µA
VPP
EPROM Programming
Voltage
12.8
V
IPP
EPROM Programming
Current
30
mA
12.2
DC TEST CONDITIONS
44/56

12.5
ST90E40 - ST90T40
AC ELECTRICAL CHARACTERISTICS
(VDD = 5V ± 10% TA = – 40°C to + 85°C, unless otherwise specified)
Symbol
Parameter
Value
Test Conditions
Min.
Typ.
Unit
Max.
IDD
Run Mode Current
no CPUCLK prescale,
Clock divide by 2
24MHz
40
mA
IDP2
Run Mode Current
Prescale by 2
Clock divide by 2
24MHz
30
mA
IWFI
WFI Mode Current
no CPUCLK prescale,
Clock divide by 2
24MHz
20
mA
IHALT
HALT Mode Current
24MHz
100
µA
50
45/56

ST90E40 - ST90T40
PACKAGE MECHANICAL DATA
80-Pin Ceramic Quad Flat Package with Window
Dim.
mm
Min
A
Typ
inches
Max
Min
Typ
3.55
0.14
A2
3.40
0.133
D
23.90
0.941
D1
20.00
0.787
D3
18.40
0.724
E
17.90
0.705
E1
14.00
0.551
E3
12.00
0.472
Ø
7.62
0.3
e
0.80
0.032
Max
Number of Pins
N
80
ND
24
NE
16
68-Pin Ceramic Leadless Chip Carrier with Window
Dim.
Min

Max
Min
inches
Typ Max
A
A1
A3
B
B1
4.47
0.89
0.48
-
0.176
0.035
0.019
-
D
D1
25.1
23.6
0.990
0.930
D3
E
E1
E3
Ø
20.3
25.1
23.6
20.3
8
0.800
0.990
0.930
0.800
0.32
e
1.27
0.050
Number of Pins
N
ND
NE
46/56
mm
Typ
68
16
16
ST90E40 - ST90T40
ORDERING INFORMATION
Sales Type
ST90E40L0
Frequency
Temperature Range
(1)
ST90E40G0
25°C
(1)
Package
CLCC68W
CQFP80W
24MHz
ST90T40C6
-40°C to + 85°C
PLCC68
ST90T40Q1
0°C to + 70°C
PQFP80
Note . EPROM parts are tested at 25°C only
47/56

ST90E40 - ST90T40
Notes:
48/56

ST90R40

ROMLESS HCMOS MCU
WITH EEPROM, RAM AND A/D CONVERTER
Register oriented 8/16 bit CORE with
RUN, WFI and HALT modes
Minimum instruction cycle time:500ns
(12MHz internal)
ROMless to allow maximum external memory
flexibility
Internal Memory :
RAM
256 bytes
EEPROM
512 bytes
224 general purpose registers available as
RAM, accumulators or index pointers
(register file)
68-lead Plastic Leaded Chip Carrier package for
ST90R40C
PLCC68
(Ordering Information at the end of the Datasheet)
DMA controller, Interrupt handler and Serial Peripheral Interface as standard features
40 fully programmable I/O pins
Up to 8 external plus 1 non-maskableinterrupts
16 bit Timer with 8 bit Prescaler, able to be used
as a WatchdogTimer
Two 16 bit Multifunction Timers, each with an 8
bit prescaler and 13 operating modes
8 channel 8 bit Analog to Digital Converter, with
Analog Watchdogs and external references
Serial Communications Interface with asynchronous and synchronous capability
Rich Instruction Set and 14 Addressingmodes
Division-by-Zero trap generation
Versatile developmenttools, including assembler,
linker, C-compiler, archiver, graphic orinted debuggerand hardware emulators
Real Time Operating System
Compatible with ST9040 16K ROM device (also
availablein windowedand One Time Programmable EPROM packages)
March 1994
49/56
ST90R40
Figure 1. 68 Pin PLCC Package
Table 1. ST90R40C Pin Description
Pin
Name
Pin
Name
Pin
Name
Pin
Name
61
P44/Ain4
10
P35/T1OUTA
43
P70/SIN
60
AVSS
62
P57
11
P34/T1INA
42
P71/SOUT
59
AVDD
63
P56
12
P33/T0OUTB
P55
13
P32/T0INB
P72/CLKOUT
/TXCLK/INT4
P47/Ain7
64
41
58
57
P46/Ain6
65
P54
14
P31/T0OUTA
66
INT7
15
P30/P/D/T0INA
40
P73/ADTRG
/RXCLK/INT5
67
INT0
16
A15
39
P74/P/D/INT6
54
P42/Ain2
68
P53
17
A14
38
P75/WAIT
53
P41/Ain1
● 1
P52
18
A13
19
A12
P76/WDOUT
/BUSREQ
P40/Ain0
P51
37
52
2
51
P27/RRDY5
3
P50
20
A11
4
OSCOUT
21
A10
36
P77/WDIN
/BUSACK
50
P26/INT3
/RDSTB5/P/D
49
P25/WRRDY5
48
P24/INT1
/WRSTB5
5
VSS
22
A9
35
R/W
6
OSCIN
23
A8
34
DS
7
RESET
24
A0/D0
33
AS
56
P45/Ain5
55
P43/Ain3
8
P37/T1OUTB
25
A1/D1
32
VDD
47
P23/SDO
9
P36/T1INB
26
A2/D2
31
A7/D7
46
P22/INT2/SCK
30
A6/D6
45
P21/SDI/P/D
29
A5/D5
44
P20/NMI
28
A4/D4
27
A3/D3
50/56

ST90R40
1.1 GENERAL DESCRIPTION
The ST90R40 is a ROMLESS member of the ST9
family of microcontrollers, completely developed
and produced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process.
The ROMLESS part may be used for the prototyping and pre-production phases of development,
and offers the maximum in program flexibility in
production systems.
The ST90R40 is fully compatible with the ST9040
ROM version and this datasheet will thus provide
only information specific to the ROMLESS device.
THE READER IS ASKED TO REFER TO THE
DATASHEET OF THE ST9040 ROM-BASED DEVICE.
The ROMLESS ST90R40 can be configured as a
microcontroller able to manage external memory,
or as a parallel processing element in a system
with other processors and peripheral controllers.
The nucleus of the ST90R40 is the advancedCore
which includes the Central Processing Unit (CPU),
the Register File, a 16 bit Timer/Watchdog with 8
bit Prescaler, a Serial Peripheral Interface supporting S-BUS, I2C-bus and IM-bus Interface, plus two
8 bit I/O ports. The Core has independentmemory
and register buses allowing a high degree of pipelining to add to the efficiency of the code execution
speed of the extensive instruction set.
The powerful I/O capabilities demanded by microcontroller applications are fulfilled by the ST90R40
with up to 56 I/O lines dedicated to memory addressing or digital Input/Output. These lines are
grouped into up to seven 8 bit I/O Ports and can be
configured on a bit basis under software control to
provide timing and status signals, address lines,
timer inputs and outputs, analog inputs, external
interrupts and serial or parallel I/O with or without
handshake.
Three memory spaces are available: Program Memory (external), Data Memory (internal and external)
and the Register File, which includes the control and
statusregisters of the on-chip peripherals.
Two 16 bit MultiFunction Timers, each with an 8 bit
Prescaler and 13 operating modes allow simple
use for complex waveform generation and measurement, PWM functions and many other system
timing functionsby the usage of the two associated
DMA channels for each timer.
Figure 2. Block Diagram
INT0
INT7
8
1 6-Bit TIMER / WATCHDOG + SPI
512 Bytes
256 Bytes
256 Bytes
EEPROM
RAM
REGISTER FILE
CPU
SCI
WITH DMA
I/O PORT 7
( SCI )
MEMORY BUS
REGISTER BUS
I/O PORT 0
( Address/Data )
I/O PORT 1
( Address )
I/O PORT 2
( SPI )
I/O PORT 3
( TIMERS )
8
8
8
8
2 x 16-bit TIMER
W ITH DM A
I/O PORT 4
( Ana log Inpu ts )
A /D
CONVERTER
8
I/O PORT 5
WITH HANDSHAKE
8
AVD D
AVS S
VR0B1385
51/56

ST90R40
GENERAL DESCRIPTION (Continued)
In addition there is an 8 channel Analog to Digital
Converter with integral sample and hold, fast 11µs
conversion time and 8 bit resolution. An Analog
Watchdog feature is included for two input channels.
Completing the device is a full duplex Serial Communications Interface with an integral 110 to
375000 baud rate generator, asynchronous and
1.5Mbyte/s synchronous capability (fully programmable format) and associated address/wake-up
option, plus two DMA channels.
1.2 PIN DESCRIPTION
OSCIN, OSCOUT. Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the input of the oscillator inverter and internal clock generator; OSCOUT is the output of the oscillator
inverter.
AVDD. Analog V DD of the Analog to Digital Converter.
AVSS. Analog VSS of the Analog to Digital Converter. Must be tied to VSS.
VDD. Main Power Supply Voltage (5V±10%)
VSS. Digital Circuit Ground.
AD0-AD7, (P0.0-P0.7) Address/Data Lines (Input/Output, TTL or CMOS compatible). 8 lines providing a multiplexed address and data bus, under
control of the AS and DS timing signals.
A8-A15 Address Lines (Output, TTL or CMOS
compatible). 8 lines providing non-multiplexing address bus, under control of the AS and DS timing
signals.
P2.0-P2.7 P3.0-P3.7, P4.0-P4.7, P5.0-P5.7, P7.0P7.7 I/O Port Lines (Input/Output, TTL or CMOS
compatible). 40 lines grouped into I/O ports of 8
bits, bit programmable under program control as
general purpose I/O or as Alternate functions (see
next section).
AS. Address Strobe (output, active low, 3-state).
Address Strobe is pulsed low once at the beginning of each memory cycle. The rising edge of AS
indicates that address, Read/Write (R/W), and
Data Memory signals are valid for program or data
memory transfers. Under program control, AS can
be placed in a high-impedance state along with
Port 0 and Port 1, Data Strobe (DS) and R/W.
DS. Data Strobe (output, active low, 3-state). Data
Strobe provides the timing for data movement to or
from Port 0 for each memory transfer. During a
write cycle, data out is valid at the leading edge of
DS. During a read cycle, Data In must be valid prior
to the trailing edge of DS. When the ST90R40 accesses on-chip Data memory, DS is held high during the whole memory cycle. It can be placed in a
high impedance state along with Port 0, Port 1, AS
and R/W.
R/W. Read/Write (output, 3-state). Read/Write determines the direction of data transfer for memory
transactions. R/W is low when writing to program
or data memory, and high for all other transactions.
It can be placed in a high impedance state along
with Port 0, Port 1, AS and DS.
RESET. Reset (input, active low). The ST9 is initialised by the Reset signal. With the deactivation
of RESET, program executionbegins from the Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
52/56

1.2.1 I/O PORT ALTERNATE FUNCTIONS
Each pin of the I/O ports of the ST90R40 may assume software programmable Alternative Functions as shown in the Pin Configuration Drawings.
Table 2 shows the Functions allocated to each I/O
Port pins.
ST90R40
PIN DESCRIPTION (Continued)
Table 2. I/O Port Alternate Function Summary
I/O PORT
Name
Port.bit
Function
IN/OUT
Alternate Function
P0.0
A0/D0
I/O
Address/Data bit 0 mux
24
P0.1
A1/D1
I/O
Address/Data bit 1 mux
25
P0.2
A2/D2
I/O
Address/Data bit 2 mux
26
P0.3
A3/D3
I/O
Address/Data bit 3 mux
27
P0.4
A4/D4
I/O
Address/Data bit 4 mux
28
P0.5
A5/D5
I/O
Address/Data bit 5 mux
29
P0.6
A6/D6
I/O
Address/Data bit 6 mux
30
P0.7
A7/D7
I/O
Address/Data bit 7 mux
31
P1.0
A8
O
Address bit 8
23
P1.1
A9
O
Address bit 9
22
P1.2
A10
O
Address bit 10
21
P1.3
A11
O
Address bit 11
20
P1.4
A12
O
Address bit 12
19
P1.5
A13
O
Address bit 13
18
P1.6
A14
O
Address bit 14
17
P1.7
A15
O
Address bit 15
16
P2.0
NMI
I
Non-Maskable Interrupt
44
P2.1
P/D
O
Program/Data Space Select
45
P2.1
SDI
I
SPI Serial Data Out
45
P2.2
INT2
I
External Interrupt 2
46
P2.2
SCK
O
SPI Serial Clock
46
P2.3
SDO
O
SPI Serial Data In
47
P2.4
INT1
I
External Interrupt 1
48
P2.4
WRSTB5
O
Handshake Write Strobe P5
48
P2.5
WRRDY5
I
Handshake Write Ready P5
49
P2.6
INT3
I
External Interrupt 3
50
P2.6
RDSTB5
I
Handshake Read Strobe P5
50
P2.6
P/D
O
Program/Data Space Select
50
P2.7
RDRDY5
O
Handshake Read Ready P5
51
P3.0
T0INA
I
MF Timer 0 Input A
15
P3.0
P/D
O
Program/Data Space Select
15
P3.1
T0OUTA
O
MF Timer 0 Output A
14
P3.2
T0INB
I
MF Timer 0 Input B
13
P3.3
T0OUTB
O
MF Timer 0 Output B
12
P3.4
T1INA
I
MF Timer 1 Input A
11
53/56

ST90R40
PIN DESCRIPTION (Continued)
Table 2. I/O Port Alternate Function Summary (Continued)
I/O PORT
Name
Port.bit
Function
IN/OUT
Alternate Function
P3.5
T1OUTA
O
MF Timer 1 Output A
10
P3.6
T1INB
I
MF Timer 1 Input B
9
P3.7
T1OUTB
O
MF Timer 1 Output B
8
P4.0
Ain0
I
A/D Analog Input 0
52
P4.1
Ain1
I
A/D Analog Input 1
53
P4.2
Ain2
I
A/D Analog Input 2
54
P4.3
Ain3
I
A/D Analog Input 3
55
P4.4
Ain4
I
A/D Analog Input 4
61
P4.5
Ain5
I
A/D Analog Input 5
56
P4.6
Ain6
I
A/D Analog Input 6
57
P4.7
Ain7
I
A/D Analog Input 7
58
P5.0
I/O
I/O Handshake Port 5
3
P5.1
I/O
I/O Handshake Port 5
2
P5.2
I/O
I/O Handshake Port 5
1
P5.3
I/O
I/O Handshake Port 5
68
P5.4
I/O
I/O Handshake Port 5
65
P5.5
I/O
I/O Handshake Port 5
64
P5.6
I/O
I/O Handshake Port 5
63
P5.7
I/O
I/O Handshake Port 5
62
P7.0
SIN
I
SCI Serial Input
43
P7.1
SOUT
O
SCI Serial Output
42
P7.2
INT4
I
External Interrupt 4
41
P7.2
TXCLK
I
SCI Transmit Clock Input
41
P7.2
CLKOUT
O
SCI Byte Sync Clock Output
41
P7.3
INT5
I
External Interrupt 5
40
P7.3
RXCLK
I
SCI Receive Clock Input
40
P7.3
ADTRG
I
A/D Conversion Trigger
40
P7.4
INT6
I
External Interrupt 6
39
P7.4
P/D
O
Program/Data Space Select
39
P7.5
WAIT
I
External Wait Input
38
P7.6
WDOUT
O
T/WD Output
37
P7.6
BUSREQ
I
External Bus Request
37
P7.7
WDIN
I
T/WD Input
36
P7.7
BUSACK
O
External Bus Acknowledge
36
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
ST90R40
1.3 MEMORY
The memory of the ST90R40 is functionallydivided
into two areas, the Register File and Memory. The
Memorymay optionallybe divided into two spaces,
each having a maximum of 65,536 bytes. The two
memory spaces are separated by function, one
space for Program code, the other for Data. The
ST90R40 addresses all program memory in the
external PROGRAM space. The DATA space includes the 512 bytes of on-chip EEPROM at addresses 0 through 1FFh and the 256 bytes of
on-chip RAM memory at addresses 200h through
2FFh.
The External Memory spaces are addressedusing
the multiplexed address and data buses on Ports 0
and 1. Data Memory may be decodedexternally by
using the P/D Alternate Function output. The onchip general purpose (GP) Registers may be used
as RAM memory.
Figure 3. Memory Spaces
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
ST90R40
ORDERING INFORMATION
Sales Type
Frequency
Temperature Range
Package
ST90R40C6
24MHz
-40°C to + 85°C
PLCC68
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express
written approval of SGS-THOMSON Microelectronics.
 1997 SGS-THOMSON Microelectronics - All rights reserved.
2
2
Purchase of I C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I C Patent.
2
2
Rights to use these components in an I C system is granted provided that the system conforms to the I C Standard
Specification as defined by Philips.
SGS-THOMSON Microelectronics Group of Companies
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco
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