CYPRESS Z9951

Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Product Features
Frequency Table
•
•
•
•
•
•
•
•
•
•
•
SEL (A:D)
QA
QB
QC (0,1)
QD (0:4)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
180MHz Clock Support
TM
Supports PowerPC , Intel and RISC Processors
9 Clock Outputs: Frequency Configurable
Two Reference Clock Inputs for Dynamic Toggling
Oscillator or PECL Reference Input
Output Disable Control
Spread Spectrum Compatible
3.3V Power Supply
Pin Compatible with MPC951
Industrial Temp. Range: -40°C to +85°C
32-Pin TQFP Package
Block Diagram
SELA
PLL_EN
TCLK
Table 1
REF_SEL
Cypress Semiconductor Corporation
http://www.cypress.com
PLL_EN
TCLK
VSS
QA
VDDC
QB
VSS
29
28
27
26
25
14
15
16
QD3
VDDC
QD2
Figure 1
13
QD4
VSS
QD3
Z9951
12
QD2
24
23
22
21
20
19
18
17
QD4
QD1
SELD
1
2
3
4
5
6
7
8
11
QD0
VDD
FB_IN
SELA
SELB
SELC
SELD
VSS
PECL_CLK
VDDC
Power-On Reset
4/ 8
30
QC0
QC1
SELC
MR/OE#
REF_SEL
4/ 8
31
QB
32
4/ 8
Pin Configuration
9
FB_IN
SELB
QA
10
LPF
2/ 4
MR/OE#
VCO
200480MHz
Phase
Detector
PECL_CLK#
PECL_CLK
PECL_CLK#
Document#: 38-07084 Rev. *B
QC0
VDDC
QC1
VSS
QD0
VDDC
QD1
VSS
12/22/2002
Page 1 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Pin Description
PIN
8
9
30
28
26
22, 24
12, 14, 16,
18, 20
2
10
NAME
PECL_CLK
PECL_CLK#
TCLK
QA
QB
QC(1,0)
QD(4:0)
PWR
FB_IN
MR/OE#
I
I
31
PLL_EN
I
32
REF_SEL
I
3, 4, 5, 6
SEL(A:D)
I
11, 15, 19,
23, 27
1
7, 13, 17, 21,
25, 29
VDDC
Master Reset/Output Enable Input. When asserted high, resets
all of the internal flip-flops and also disables all of the outputs.
When pulled low, releases the internal flip-flops from reset and
enables all of the outputs.
PLL Enable Input. When asserted high, PLL is enabled. And
when set low, PLL is bypassed.
Reference Select Input. When high, TCLK is the reference clock
and when low, PECL clock is selected.
Frequency Select Inputs. See Frequency Table.
If SEL_ = 1, then QA divider = ÷4, QB:D divider = ÷8
If SEL_ = 0, then QA divider = ÷2, QB:D divider = ÷4
3.3V Power Supply for Output Clock Buffers.
VDD
VSS
3.3V Power Supply for PLL
Common Ground
VDDC
VDDC
VDDC
VDDC
I/O
I
I
I
O
O
O
O
TYPE
PU
Description
PECL Input Clock.
PECL Input Clock.
External Test Clock Input.
Clock Output. See Frequency Table.
Clock Output. See Frequency Table.
Clock Outputs. See Frequency Table.
Clock Outputs. See Frequency Table.
PD
Feedback Clock Input. Connect to an output for normal operation.
PD = Internal Pull-Down, PU = Internal Pull-Up.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
Page 2 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Maximum Ratings¹
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
-65°C to + 150°C
-40°C to +85°C
Maximum ESD protection
2KV
Maximum Power Supply:
Maximum Input Current:
VSS<(Vin or Vout)<VDD
5.5V
±20mA
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Input Low Voltage
Input High Voltage
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
PECL_CLK
Symbol
Min
VIL
VIH
IIL
IIH
VPP
VSS
2.0
VCMR
VDD2.0
Typ
-
300
-
Max
Units
Conditions
0.8
VDD
-120
120
1000
V
V
µA
µA
mV
Note 2
VDD0.6
V
0.5
V
IOL = 40mA, Note 4
V
IOH = -40mA, Note 4
Note 3
Output Low Voltage
VOL
Output High Voltage
VOH
2.4
Quiescent Supply Current
IDDC
-
15
20
mA
All VDDC and VDD
PLL Supply Current
IDD
-
15
20
mA
VDD only
Input Capacitance
Cin
-
-
4
pF
VDD = VDDC = 3.3V ±5%, TA = -40°°C to +85°°C
Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT
required.
Note 2: Inputs have pull-up, pull-down resistors that affect input current.
Note 3: The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when
the “High” input is within the VCMR range and the input lies within the VPP specification.
Note 4: Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Output buffers are dual staged to control
drive strength in order to reduce over / under shoot.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
Page 3 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
AC Parameters1
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Tr / Tf
TCLK Input Rise / Fall
Fref
Reference Input Frequency
FrefDC
Reference Input Duty Cycle
25
75
%
Fvco
PLL VCO Lock Range
200
480
MHz
10
ms
0.10
1.0
ns
0.8V to 2.0V
180
MHz
QA = (÷2)
Tlock
Tr / Tf
Fout
FoutDC
Note 2
Maximum PLL lock Time
Output Clocks Rise / Fall Time
4,5
Maximum Output Frequency
Output Duty Cycle
-
4,5
TCYCLE/2 –
1
3.0
ns
Note 2
MHz
CONDITIONS
120
QA/QB = (÷4)
60
QB = (÷8)
TCYCLE/2 + 1
ns
tpZL, tpZH
Output enable time (all outputs)
6
ns
tpLZ, tpHZ
Output disable time (all outputs)
7
ns
ps
TCCJ
Tpd
Cycle to Cycle Jitter (peak to peak)
4,5
3
TCLK to FB_IN Delay
3
PECL_CLK to FB_IN Delay
TSKEW0
4,5
Any Output to Any Output Skew
+/- 100
ps
50
250
400
-950
-770
-600
ps
-
200
350
ps
Fref = 50MHz,
Feedback = VCO/8
VDD = VDDC = 3.3V +/- 5%, TA = -40°°C to +85°°C
Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production.
Note 2: Maximum and minimum input reference is limited by the VCO lock range.
Note 3: The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the
minimum limits with an increase/decrease of the input reference clock period.
Note 4: Driving series or parallel terminator 50Ω (or 50Ω to VDD/2) transmission lines.
Note 5: Outputs loaded with 30pF each
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
Page 4 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Description
The Z9951 has an integrated PLL that provides low skew and low jitter clock outputs for high performance
microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480
MHz. This allows a wide range of output frequencies from 25MHz to 180MHz.
The phase detector compares the input reference clock to the external feedback input. For normal operation, the
external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input
reference clock set by SEL(A:D) select inputs, see Table 2. The VCO frequency is then divided down to provide the
required output frequencies. The use of even dividers ensures that the output duty cycle remains at 50%.
SELA
0
1
QA
÷2
÷4
SELB
0
1
QB
÷4
÷8
SELC
0
1
QC
÷4
÷8
SELD
0
1
QD
÷4
÷8
Table 2
Zero Delay Buffer
When used as a zero delay buffer the Z9951 will likely be in a nested clock tree application. For these applications the
Z9951 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far superior skew performance. The Z9951 then can lock onto the
LVPECL reference and translate with near zero delay to low skew outputs.
By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static
phase offset is a function of the reference clock the Tpd of the Z9951 is a function of the configuration used.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
Page 5 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Package Drawing and Dimensions
32 Pin TQFP Outline Dimensions
INCHES
SYMBOL
D
MIN
MIN
NOM
MAX
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
-
0.041
0.95
-
1.05
D
-
0.354
-
-
9.00
-
D1
-
0.276
-
-
7.00
-
b
0.012
-
0.018
0.30
-
0.45
L
12°
MAX
A
e
D1
NOM
MILLIMETERS
0.031 BSC
0.018
-
0.80 BSC
0.030
0.45
-
0.75
A1
A
L
Cypress Semiconductor Corporation
http://www.cypress.com
e
b
Document#: 38-07084 Rev. *B
12/22/2002
Page 6 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Ordering Information
Part Number
Package Type
Production Flow
Z9951AA
32 PIN TQFP
Industrial, -40°C to +85°C
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example:
Cypress
Z9951AA
Date Code, Lot #
Z9951AA
Package
A = TQFP
Revision
Device Number
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
Page 7 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Notice
Cypress Semiconductor Corp. reserves the right to make changes to its products in order to improve design,
performance or reliability. Cypress Semiconductor Corp. assumes no responsibility for the use of its products in life
supporting and medical applications where the failure or malfunction of the product could cause failure of the life
supporting and medical systems. Products are not authorized for use in such applications unless a written approval is
requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corp. for the use of its
products in the life supporting and medical applications.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
Page 8 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Document Title: Z9951 3.3V, 180 MHz, Multi-Output Zero Delay Buffer
Document Number: 38-07084
Rev. ECN
No.
**
107120
*A
108063
Issue
Date
06/12/01
07/03/01
Orig. of
Change
IKA
NDP
*B
12/22/02
RBI
122769
Cypress Semiconductor Corporation
http://www.cypress.com
Description of Change
Convert from IMI to Cypress
Changed Commercial to Industrial (See page 7)
Delete Pull down in pin 9,10,30& 32; Delete Pull up in pin
3,4,5,6, & 31 (See page 2)
Add power up requirements to maximum ratings
information
Document#: 38-07084 Rev. *B
12/22/2002
Page 9 of 9