INTERSIL ZL2005P

ZL2005P
Data Sheet
February 18, 2009
FN6849.0
Digital-DC™ Controller with Drivers and POLA/DOSA Trim
Description
Features Power Conversion
The ZL2005P is an innovative mixed-signal power
conversion and management IC that combines a compact, efficient, synchronous DC-DC buck controller,
adaptive drivers and key power and thermal management functions in one IC, providing flexibility and
scalability while decreasing board space requirements
and design complexity. Zilker Labs Digital-DC technology enables a unique blend of performance and
features not available in either traditional analog or
newer digital approaches, resolving the issues associated with providing multiple low-voltage power
domains on a single PCB.
• Efficient synchronous buck controller
• 3 V to 14 V input range
• 0.54 V to 5.5 V output range (with margin)
• Optional output voltage setting with VADJ pin
• ± 1% output accuracy
• Internal 3 A drivers support >40 A power stage
• Fast load transient response
• Phase interleaving
• RoHS compliant (6 x 6 mm) QFN package
Power Management
• Digital soft start/stop
• Precision delay and ramp-up
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• I2C/SMBus communication
• Output overvoltage and overcurrent protection
• Internal non-voltatile memory (NVM)
• PMBus compliant
The ZL2005P is designed to be configured either as a
standard ZL2005 or as POLA/DOSA compatible
device.
All operating features can be configured by simple
pin-strap selection, resistor selection or through the
on-board serial port. The PMBus™-compliant
ZL2005P uses the SMBus™ serial interface for communication with other Digital-DC products or a host
controller.
Applications
•
•
•
Servers/storage equipment
Telecom/datacom equipment
Power supplies (memory, DSP, ASIC, FPGA)
DLY FC ILIM
EN PG (0,1) (0,1) (0,1) CFG UVLO V25 VR VDD
SS (0,1)
VTRK
MGN
SYNC
VADJ
SCL
SDA
SALRT
POWER
MANAGEMENT
LDO
DRIVER
NONVOLATILE
MEMORY
PWM
CONTROLLER
I2 C
MONITOR
ADC
SA (0,1)
XTEMP VSEN
CURRENT
SENSE
BST
GH
SW
GL
ISENA
ISENB
TEMP
SENSOR
PGND SGND DGND
Figure 1. Block Diagram
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ZL2005P
Table of Contents
1
2
3
4
5
6
7
8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZL2005P Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
ZL2005 - ZL2005P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Power Conversion Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Conversion Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Internal Bias Regulators and Input Supply Connections. . . . . . . . . . . . . . . . . . . . . .
5.2
High-side Driver Boost Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
Start-up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5
Soft Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8
Selecting Power Train Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
Current Limit Threshold Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Non-Linear Response Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Efficiency Optimized Driver Dead-time Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Input Undervoltage Lockout (UVLO) Standard Mode . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8
I2C/SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9
I2C/SMBus Device Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 Monitoring via I2C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Temperature Monitoring Using the XTEMP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 Non-volatile Memory and Device Security Features. . . . . . . . . . . . . . . . . . . . . . . . .
Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
7
9
10
10
10
11
12
12
14
14
14
14
18
19
20
20
22
25
28
29
29
30
30
30
31
31
32
32
33
33
34
34
35
36
37
37
38
39
39
39
FN6849.0
February 18, 2009
ZL2005P
1
Electrical Characteristics
Table 1. Absolute Maximum Ratings
Operating beyond these limits may cause permanent damage to the device. Functional operation beyond the recommended
operating conditions is not implied. Unless otherwise specified, all voltages are measured with respect to SGND.
Parameter
Pin(s)
Value
Unit
DC supply voltage
VDD
DLY(0,1), EN, ILIM(0,1),
MGN, PG, SA(0,1), SALRT,
SCL, SDA, SS(0,1), SYNC,
VADJ, UVLO, V(0,1)
ISENB, VSEN, VTRK,
XTEMP,
ISENA
Logic I/O voltage
Analog input voltages
-0.3 to 17
V
-0.3 to 6.5
V
-0.3 to 6.5
V
V
V
mA
V
mA
V
V
V
MOSFET drive reference
VR
Logic reference
V25
High-side supply voltage
High-side drive voltage
Low-side drive voltage
Boost to switch differential voltage
(VBST - VSW)
Switch node continuous
Switch node transient
(<100 ns)
Ground voltage differential
(VDGND-VSGND), (VPGND-VSGND)
Junction temperature
Storage temperature range
Lead temperature
(soldering, 10 s)
BST
GH
GL
-1.5 to +30
-0.3 to 6.5
120
-0.3 to 3
120
-0.3 to +30
(VSW - 0.3) to (VBST+0.3)
(PGND-0.3) to (VR+0.3+PGND)
BST, SW
-0.3 to 8
V
SW
(PGND-0.3) to 30
V
SW
(PGND-5) to 30
V
DGND, SGND, PGND
-0.3 to +0.3
V
–
–
-55 to 150
-55 to 150
oC
–
300
3
o
C
o
C
FN6849.0
February 18, 2009
ZL2005P
Table 2. Recommended Operating Conditions and Thermal Information
Parameter
Symbol
VR tied to VDD (Figure 9)
Input Supply Voltage Range, VDD
VR floating (Figure 9)
Output Voltage Range
VOUT (RDSON sensing)
Output Voltage Range
VOUT (DCR sensing)
Operating Junction Temperature Range
TJ
Junction to Ambient Thermal
ΘJA
Impedance1
ΘJC
Junction to Case Thermal Impedance2
Min
Typ
Max
Unit
3.0
4.5
0.54
0.6
-40
–
–
–
5.5
14
5.5
3.63
125
V
V
V
V
°C
–
35
–
°C/W
–
5
–
°C/W
NOTES:
1. ΘJA is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance ground plane
using multiple vias.
2. For ΘJC, the “case” temperature is measured at the center of the exposed metal pad
3. With margin
Table 3. Electrical Specifications
Unless otherwise specified VDD = 12 V, TA = -40oC to +85oC. Typical values are at TA = 25oC.
Parameter
Condition
Min
Input and Supply Characteristics
Supply current (IDD)
(No load on GH and GL)
Standby supply current (IDD)
VR reference voltage (VR)
V25 reference voltage (V25)
fSW = 200 kHz
fSW = 1,000 kHz
EN = Low
no I2C/SMBus activity
VDD ≥ 6 V
IVR < 50 mA
VR ≥ 3 V
IV25 < 50 mA
Typ
Max
Unit
–
–
16
25
30
50
mA
mA
–
2
5
mA
4.5
5.2
5.5
V
2.25
2.5
2.75
V
0.6
–
–
10
Table 8
±0.025
5.5
–
V
mV
–
% of
F.S.1
%
µA
Output Characteristics
Output voltage adjustment range
Output voltage setpoint resolution
Output voltage accuracy
VSEN input bias current
Current sense differential input
voltage (ground referenced)
Current sense differential input
voltage (VOUT referenced)
Current sense input bias current
Current sense input bias current
(VOUT referenced,
VOUT <= 3.6V)
Soft start delay duration range
Soft start delay duration accuracy
4
Set using resistors on V(0,1)
Set using resistor on VADJ
Set using I2C/SMBus
–
Over line and load
VSEN = 5.5 V
-1
–
110
1
200
VISENA - VISENB
-100
–
100
mV
VISENA - VISENB
-50
–
50
mV
Ground referenced
ISENA
-100
-1
–
–
100
1
µA
µA
ISENB
-100
–
100
µA
Configurable via I2C/SMBus
0.007
–
–
6
500
–
s
ms
FN6849.0
February 18, 2009
ZL2005P
Table 3. Electrical Specifications
Unless otherwise specified VDD = 12 V, TA = -40oC to +85oC. Typical values are at TA = 25oC. (Continued)
Parameter
Condition
Min
Typ
Max
Soft start ramp duration range
Soft start ramp duration accuracy
2
Unit
Configurable via I C/SMBus
0
–
–
100
200
–
ms
µs
EN, PG, SCL, SDA, SALRT
-10
–
–
2
–
–
1.4
–
10
0.8
–
–
μA
V
V
V
Logic Input/Output Characteristics
Logic input bias current
Logic input low threshold (VIL)
Logic input OPEN (N/C)
Logic input high threshold (VIH)
Multi-mode logic pins
Logic output low (VOL)
IOL <= 4 mA
–
–
0.4
V
Logic output high (VOH)
IOH >= - 2 mA
2.25
–
–
V
200
–
1400
kHz
-5
–
5
%
95
150
-13
–
–
–
–
–
13
%
ns
%
–
4.5
–
V
2
3
–
A
–
0.8
2
Ω
–
0.5
2
Ω
VR = 5 V
–
2.5
–
A
VR = 5 V
–
1.8
–
A
–
1.2
2
Ω
–
0.5
2
Ω
–
5
20
ns
–
5
20
ns
–
– 100
110
200
100
µA
mV
Oscillator and Switching Characteristics
Switching frequency range
Switching frequency setpoint
accuracy
Maximum PWM duty cycle
Minimum SYNC pulse width
Input clock frequency drift tolerance
Predefined settings
(See table 13)
Factory default
External clock signal
Gate Drivers
High-side driver voltage
(VBST - VSW)
High-side driver peak gate drive
current (pull down)
High-side driver pull-up resistance
High-side driver pull-down
resistance
Low-side driver peak gate drive
current (pull-up)
Low-side driver peak gate drive
current (pull-down)
Low-side driver pull-up resistance
Low-side driver pull-down
resistance
(VBST - VSW) = 4.5 V
(VBST - VSW) = 4.5 V,
(VBST - VGH) = 50 mV
(VBST - VSW) = 4.5 V,
(VGH - VSW) = 50 mV
VR = 5 V,
(VR - VGL) = 50 mV
VR = 5 V,
(VGL - PGND) = 50 mV
Switching timing
GH rise and fall time
GL rise and fall time
(VBST - VSW) = 4.5 V,
CLOAD = 2.2 nF
VR = 5 V,
CLOAD = 2.2 nF
Tracking
VTRK input bias current
VTRK tracking threshold
VTRK = 5.5 V
VTRK >= 0.3 V
5
FN6849.0
February 18, 2009
ZL2005P
Table 3. Electrical Specifications
Unless otherwise specified VDD = 12 V, TA = -40oC to +85oC. Typical values are at TA = 25oC. (Continued)
Parameter
Condition
Min
Typ
Max
Fault Protection Characteristics
UVLO threshold range
UVLO setpoint accuracy
UVLO hysteresis
ZL2005P configuration
Factory default
Configurable via I2C/SMBus
2.85
-3
–
0
–
–
–
3
–
–
16
3
–
100
2.5
Power good VOUT low threshold
Factory default
–
90
–
Power good VOUT high threshold
Factory default
–
115
–
Factory default
Configurable via I2C/SMBus
–
0
5
–
–
500
85
–
–
110
115
–
UVLO delay
Power good VOUT hysteresis
Power good delay range
Factory default
V
%
%
%
µs
%
VOUT
%
VOUT
%
s
%
VOUT
%
VOUT
%
VOUT
%
VOUT
µs
µs
VSEN undervoltage threshold
Configurable via I2C/SMBus
0
Factory default
VSEN overvoltage threshold
VSEN undervoltage/overvoltage
fault response time
Current limit setpoint accuracy
(VOUT referenced)
Current limit setpoint accuracy2
(Ground referenced)
Current limit protection delay
Temperature compensation of
current limit protection threshold
Thermal protection threshold
Unit
Configurable via I2C/SMBus
0
–
115
Factory default
Configurable via I2C/SMBus
–
5
16
–
–
60
–
±10
–
%
F.S.1
|VISENA - VISENB|> 12 mV
–
±10
–
% F.S.
Factory default
Configurable via I2C/SMBus
Factory default
Configurable via I2C/SMBus
Factory default
Configurable via I2C/SMBus
–
1
–
100
–
- 40
–
5
–
4400
–
125
–
15
–
32
–
12700
–
125
–
tSW3
Thermal protection hysteresis
ppm/
°C
°C
°C
°C
NOTES:
1. Percentage of Full Scale (F.S.) with temperature compensation applied
2. TA = 0oC to +85oC
3. tSW = 1/fSW, fSW switching frequency
4. Automatically set to same value as soft start ramp time
6
FN6849.0
February 18, 2009
ZL2005P
Pin Descriptions
28
29
31
30
32
34
33
1
27
2
26
36-Pin QFN
6 x 6 mm
3
4
25
24
5
23
6
7
Exposed Paddle
22
Connect to SGND
21
18
17
16
15
14
VDD
BST
GH
SW
PGND
GL
VR
ISENA
ISENB
FC0
FC1
V0
V1
UVLO
SS0
SS1
VTRK
VSEN
12
19
13
20
9
11
8
10
DGND
SYNC
SA0
SA1
ILIM0
ILIM1
SCL
SDA
SALRT
35
36
PG
DLY1
DLY0
EN
CFG
MGN
VADJ
XTEMP
V25
2
Figure 2. Pin Assignments (top view)
Table 4. Pin Descriptions
Pin
Label
Type1
1
DGND
PWR
2
SYNC
I/O, M2
3
4
5
6
7
8
9
10
11
12
13
SA0
SA1
ILIM0
ILIM1
SCL
SDA
SALRT
FC0
FC1
V0
V1
14
UVLO
15
16
17
SS0
SS1
VTRK
Description
Digital ground. Connect to low impedance ground plane.
Clock synchronization input. Used to set the frequency of the internal switch
clock, to sync to an external clock or to output internal clock.
I, M
Serial address select pins. Used to assign unique address for each individual
device or to enable certain management features.
I, M
Current limit select. Sets the overcurrent threshold voltage for ISENA, ISENB.
I/O
I/O
O
I
I
Serial clock. Connect to external host and/or to other ZL2005s.
Serial data. Connect to external host and/or to other ZL2005s.
Serial alert. Connect to external host if desired.
I, M
Output voltage selection pins. Used to set VOUT setpoint and VOUT max.
I, M
Undervoltage lockout selection. Sets the minimum value for VDD voltage to
enable VOUT.
I, M
Soft start pins. Set the output voltage ramp time during turn-on and turn-off.
I
Loop compensation selection pins.
Tracking sense input. Used to track an external voltage source.
NOTES:
1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pin (refer to Section 4.5, “Multi-mode Pins,” )
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
3. VDD is measured internally and the value is used to modify the PWM loop gain.
7
FN6849.0
February 18, 2009
ZL2005P
Table 4. Pin Descriptions (Continued)
Pin
Label
Type1
Description
18
19
20
21
22
23
24
25
26
27
28
VSEN
ISENB
ISENA
VR
GL
PGND
SW
GH
BST
VDD3
V25
I
I
I
PWR
O
PWR
PWR
O
PWR
PWR
PWR
29
XTEMP
I
30
31
VADJ
MGN
I
I
32
CFG
I
33
34
35
36
EN
DLY0
DLY1
PG
I
Output voltage feedback. Connect to output regulation point.
Differential voltage input for current limit.
Differential voltage input for current limit. High voltage tolerant.
Internal 5V reference used to power internal drivers.
Low side FET gate drive.
Power ground. Connect to low impedance ground plane.
Drive train switch node.
High-side FET gate drive.
High-side drive boost voltage.
Supply voltage.
Internal 2.5 V reference used to power internal circuitry.
External temperature sensor input. Connect to external 2N3904 diode connected
transistor.
Output voltage setting pin (POLA/DOSA mapping)
Digital VOUT margin control
Configuration pin. Used to control the switching phase offset, sequencing and
other management features.
Enable. Active signal enables PWM switching.
I, M
ePad
SGND
PWR
O
Softstart delay select. Sets the delay from when EN is asserted until the output
voltage starts to ramp.
Power good output.
Exposed thermal pad. Connect to low impedance ground plane. Internal
connection to SGND.
NOTES:
1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pin (refer to Section 4.5, “Multi-mode Pins,” )
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
3. VDD is measured internally and the value is used to modify the PWM loop gain.
8
FN6849.0
February 18, 2009
ZL2005P
Typical Application Example
VIN 12V
VADJ
12.1 kOhm
CIN
3 x 10 µF
25 V
VR
10
kOhm
10
µF
4V
CV25
GH 25
4 SA1
SW 24
ZL2005P
COUT
2 x 47 µF
6.3 V
EPAD
110
kOhm
QL
NTMSF4108
CVR
SGND
18 VSEN
17 VRTK
16 SS1
15 SS0
14 UVLO
ISENB 19
13 V1
9 SALRT
12 V0
ISENA 20
11 FC1
VR 21
8 SDA
1.5 kOhm
0.56
µH
GL 22
7 SCL
VOUT
LOUT
PGND 23
6 ILIM1
9.09
kOhm
CB
BST 26
3 SA0
5 ILIM0
EN/
INHIBIT
1 µF
16 V
VDD 27
2 SYNC
I2C/SMBus
OPTIONAL
QH
Si7114
DB
BAT54
V25 28
XTEMP 29
MGN 31
EN 33
CFG 32
VADJ 30
1 DGND
DLY0 34
PG 36
V25
DLY1 35
POWER GOOD OUTPUT
10 FC0
4.7 µF
RTN
6.3 V
Notes:
1. Conditions: VIN = 12 V, VOUT = 1.2 V, Freq = 400 kHz, IOUT = 20 A
2. The I2C/SMBus requires pullup resistors. Please refer to the I2C/SMBus specifications for more details.
Figure 3. Typical Application Circuit POLA
100
VOUT = 3.3V
VOUT = 1.5V
95
90
Efficiency (%)
3
85
80
75
70
65
60
VIN = 12V
fSW = 400kHz
Circuit of Figure 3
55
50
0
2
4
6
8
10
12
14
16
18
20
Load Current (A)
Figure 4. Typical Efficiency Curves
9
FN6849.0
February 18, 2009
ZL2005P
4
ZL2005P Overview
4.1
Digital-DC Architecture
The ZL2005P is an innovative mixed-signal power
conversion and power management IC based on Zilker
Labs’ patented Digital-DC technology that provides
an integrated, high performance step-down converter
for a wide variety of power supply applications. Its
unique digital PWM loop utilizes an innovative
mixed-signal topology to enable precise control of the
power conversion process with no software required,
resulting in a very flexible device that is also easy to
use. An extensive set of power management functions
is fully integrated and can be configured using simple
pin connections or via the I2C/SMBus hardware interface using standard PMBus commands. The user configuration can be saved in an on-chip non-volatile
memory (NVM), allowing ultimate flexibility.
4.2
ZL2005 - ZL2005P
By default, the ZL2005P is configured as a standard
ZL2005 device.
The main differences between the ZL2005P configured as a ZL2005P and the initial ZL2005 are the following:
•
•
•
•
TACH pin is not used (reserved for ZL2005P
POLA configuration).
VADJ pin to adjust voltage through an external
resistor, similar to POLA method.
Additional configuration option for Synchronization.
DEFAULT STORE only
Once enabled, the ZL2005P is immediately ready to
regulate power and perform power management tasks
with no programming required. The ZL2005P can be
configured by simply connecting its pins according to
the tables provided in this document. Advanced configuration options and real-time configuration changes
are available via the I2C/SMBus interface if desired,
and continuous monitoring of multiple operating
parameters is possible with minimal interaction from a
host controller. Integrated sub-regulation circuitry
enables single supply operation from any supply
between 3V and 14V with no secondary bias supplies
needed.
Zilker Labs provides a comprehensive set of on-line
tools and application notes to assist with power supply
design and simulation. An evaluation board is also
available to help the user become familiar with the
device. This board can be evaluated as a stand-alone
platform using pin configuration settings. Additionally, a Windows™-based GUI is provided to enable
full configuration and monitoring capability via the
I2C/SMBus interface using an available computer and
the included USB cable.
Please refer to www.zilkerlabs.com for access to the
most up-to-date documentation and the PowerPilotTM
simulation tool, or call your local Zilker Labs’ sales
office to order an evaluation kit.
10
FN6849.0
February 18, 2009
ZL2005P
4.3
Power Conversion Overview
INPUT VOLTAGE BUS
PG
VTRK
EN
V(0,1)
POWER MANAGEMENT
DIGITAL
COMPENSATOR
SYNC
GEN
VDD
VR LDO
NVM
VR
BST
MOSFET
DRIVERS
D-PWM
NLR
PLL
SYNC
VADJ
GH
SW
GL
VOUT
- VSEN
ADC
Σ
+
REFCN
DAC
ISENB
ISENA
ADC
SMBUS
{
VDD
SALRT
SDA
SCL
SA(0,1)
COMMUNICATION
ADC
MUX
VSEN
XTEMP
TEMP
SENSOR
Figure 5. ZL2005P Detailed Block Diagram
The ZL2005P operates as a voltage-mode, synchronous buck converter with a selectable, constant frequency Pulse Width Modulator (PWM) control
scheme that uses external MOSFETs, inductor and
capacitors to perform power conversion.
QH is on as a fraction of the total switching period is
known as the duty cycle D, which is described by the
following equation:
V OUT
D ≈ ---------------V IN
Figure 6 illustrates the basic synchronous buck converter topology showing the primary power train components. This converter is also called a step-down
converter, as the output voltage must always be lower
than the input voltage.
During time D, QH is on and VIN –VOUT is applied
across the inductor. The current ramps up as shown in
Figure 7.
VIN
VIN – VOUT
DB
BST
ZL
SW
GL
L1
CB
VOUT
QL
COUT
0
Io
ILv
-VOUT
Figure 6. Synchronous Buck Converter
In its most simple configuration, the ZL2005P requires
two external N-channel power MOSFETs, one for the
top control MOSFET (QH) and one for the bottom
synchronous MOSFET (QL). The amount of time that
11
D
CURRENT (A)
QH
GH
ILpk
CIN
VOLTAGE
(V)
VR
1-D
Time
Figure 7. Inductor Waveform
FN6849.0
February 18, 2009
ZL2005P
When QH turns off (time 1-D), the current flowing in
the inductor must continue to flow from the ground up
through QL, during which the current ramps down.
Since the output capacitor COUT exhibits a low impedance at the switching frequency, the AC component of
the inductor current is filtered from the output voltage
so the load sees nearly a DC voltage.
Typically, buck converters specify a maximum duty
cycle that effectively limits the maximum output voltage that can be realized for a given input voltage. This
duty cycle limit ensures that the low-side MOSFET is
allowed to turn on for a minimum amount of time during each switching cycle, which enables the bootstrap
capacitor (CB in Figure 6) to be charged up and provide adequate gate drive voltage for the high-side
MOSFET. See Section 5.2, “High-side Driver Boost
Circuit,” for more details.
In general, the size of components L1 and COUT as
well as the overall efficiency of the circuit are
inversely proportional to the switching frequency, fSW.
Therefore, the highest efficiency circuit may be realized by switching the MOSFETs at the lowest possible
frequency; however, this will result in the largest component size. Conversely, the smallest possible footprint may be realized by switching at the fastest
possible frequency but this gives a somewhat lower
efficiency. Each user should determine the optimal
combination of size and efficiency when determining
the switching frequency for each application.
The block diagram for the ZL2005P is illustrated in
Figure 5. In this circuit, the target output voltage is
regulated by connecting the VSEN pin directly to the
output regulation point. The VSEN signal is then compared to a reference voltage that has been set to the
desired output voltage level by the user. The error signal derived from this comparison is converted to a digital value with a low-resolution analog to digital (A/D)
converter. The digital signal is applied to an adjustable
digital compensation filter, and the compensated signal is used to derive the appropriate PWM duty cycle
for driving the external MOSFETs in a way that produces the desired output.
The ZL2005P also incorporates a non-linear response
(NLR) loop to reduce the response time and output
deviation in response to a load transient. The ZL2005P
has an efficiency optimization circuit that continuously monitors the power converter’s operating conditions and adjusts the turn-on and turn-off timing of the
12
high-side and low-side MOSFETs to optimize the
overall efficiency of the power supply.
4.4
Power Management Overview
The ZL2005P incorporates a wide range of configurable power management features that are simple to
implement with no external components. Additionally, the ZL2005P includes circuit protection features
that continuously safeguard the load from damage due
to unexpected system faults. The ZL2005P can continuously monitor input voltage, output voltage/current,
internal temperature, and the temperature of an external thermal diode. A Power Good output signal is provided to enable power-on reset functionality for an
external processor.
All power management functions can be configured
using either simple pin configuration techniques (Figure 8) or via the I2C/SMBus interface. Monitoring
parameters can be pre-configured to provide alerts for
specific conditions. See Application Note AN13 for
more details on SMBus monitoring.
4.5
Multi-mode Pins
In order to simplify circuit design, the ZL2005P incorporates patented multi-mode pins that allow the user to
easily configure many aspects of the device without
requiring the user to program the IC. For the ZL2005P
only a few of the power management features can be
configured using these pins. The multi-mode pins can
respond to four different connections as shown in
Table 5. Any combination of connections is allowed
among the multi-mode pins. These pins are sampled
when power is applied or by issuing a PMBus Restore
command (See Application Note AN13).
Table 5. Multi-mode Pin Configuration
Pin Tied To
GND
(Logic low)
OPEN
(N/C)
HIGH
(Logic high)
Resistor to SGND
Value
< 0.8 VDC
No connection
> 2.0 VDC
Set by resistor value
FN6849.0
February 18, 2009
ZL2005P
Logic
high
Open
ZL
ZL
Multi-mode Pin
Multi-mode Pin
RSET
Logic
low
Pin-strap
Settings
Resistor
Settings
Figure 8. Pin-strap and Resistor Setting
Examples
Pin-strap Settings: This is the simplest implementation method, as no external components are required.
Using this method, each pin can take on one of three
possible states: GND, OPEN, or HIGH. These pins
can be connected to the VR or V25 pins for logic
HIGH settings, as either pin provides a regulated voltage greater than 2V. Using a single pin, the user can
select one of three settings, and using two pins, the
user can select one of nine settings.
13
Resistor Settings: This method allows a greater range
of adjustability when connecting a finite valued resistor (in a specified range) between the multi-mode pin
and SGND. Standard 1% resistor values are used, and
only every fourth E96 resistor value is used so that the
device can reliably recognize the value of resistance
connected to the pin while eliminating the errors associated with the resistor accuracy. A total of 25 unique
selections are available using a single resistor.
I2C/SMBus Settings: Almost any ZL2005P function
can be configured via the I2C/SMBus interface using
standard PMBus commands. Additionally, any value
that has been configured using the pin-strap or resistor
setting methods can also be re-configured and/or verified via the I2C/SMBus. See Application Note AN13
for details.
The SMBus device address and VOUT_MAX are the
only parameters that must be set by external pins. All
other device parameters can be set via the I2C/SMBus.
the device address is set using the SA0 and SA1 pins.
The VOUT_MAX is determined as 10% greater than
the voltage set by the V0/V1 pins or VADJ pin.
FN6849.0
February 18, 2009
ZL2005P
5
Power Conversion Functional Description
5.1
Internal Bias Regulators and Input
Supply Connections
The ZL2005P employs two internal low dropout
(LDO) regulators to supply bias voltages for internal
circuitry, allowing it to operate from a single input
supply. The internal bias regulators are as follows:
VR: The VR LDO provides a regulated 5V bias supply
for the MOSFET driver circuits. It is powered
from the VDD pin and can supply up to 100 mA
output current. A 4.7 µF filter capacitor is
required at the VR pin.
V25: The V25 LDO provides a regulated 2.5V bias
supply for the main controller circuitry. It is
powered from an internal 5V node and can supply up to 50 mA output current. A 10 µF filter
capacitor is required at the V25 pin.
Note: The internal bias regulators are designed for
powering internal circuitry only. Do not attach external loads to any of these pins. The multi-mode pins
may be connected to the VR or V25 pins for logic
HIGH settings.
When the input supply (VDD) is higher than 5.5V, the
VR pin should not be connected to any other pin. It
should only have a filter capacitor attached as shown
in Figure 9. Due to the dropout voltage associated with
the VR bias regulator, the VDD pin must be connected
to the VR pin for designs operating from a VDD supply from 3.0V to 5.5V. Figure 9 illustrates the required
connections for both cases. For input supplies between
4.5V and 5.5V, either method can be used.
Figure 9. Input Supply Connections
14
5.2
High-side Driver Boost Circuit
The gate drive voltage for the upper MOSFET driver
is generated by a floating bootstrap capacitor, CB (see
Figure 3). When the lower MOSFET (QL) is turned
on, the SW node is pulled to ground and the capacitor
is charged from the internal VR bias regulator through
diode DB. When QL turns off and the upper MOSFET
(QH) turns on, the SW node is pulled up to VDD and
the voltage on the BST pin is boosted approximately
5V above VIN to provide the necessary voltage for the
high-side driver. A Schottky diode should be used for
DB to maximize the high-side drive voltage.
5.3
Output Voltage Selection
Standard Mode (ZL2005)
The output voltage may be set to any voltage between
0.6V and 5.0V provided that the input voltage is
higher than the desired output voltage by an amount
sufficient to prevent the device from exceeding its
maximum duty cycle specification. By connecting the
V0 and V1 pins to logic high, logic low, or leaving
them floating, VOUT can be set to any of nine standard
voltages as shown in Table 6.
Table 6. Pin-strap Output Voltage Settings
V1
LOW
OPEN
HIGH
LOW
0.6V
1.2V
2.5V
V0
OPEN
0.8V
1.5V
3.3V
HIGH
1.0V
1.8V
5.0V
If an output voltage other than those in Table 6 is
desired, the resistor setting method can be used. Using
this method, resistors R0 and R1 are selected to produce a specific voltage between 0.6V and 5.0V in 10
mV steps. Resistor R1 provides a coarse setting and
R0 a fine adjustment, thus eliminating the additional
errors associated with using two 1% resistors in a standard analog implementation (this typically adds 1.4%
error using two 1% resistors).
To set VOUT using resistors, follow the steps below to
calculate an index value and then use Table 7 to select
the resistor that corresponds to the calculated index
value as follows:
FN6849.0
February 18, 2009
ZL2005P
1. Calculate Index1:
Index1 = 4 x VOUT
2. Round the result down to the nearest whole number.
3. Select the value for R1 from Table 7 using the
Index1 rounded value from step 2.
4. Calculate Index0 using equation
Index0 = 100 x VOUT - 25 x Index1...
5. Select the value for R0 from Table 7 using Index0
from step 4.
Table 7. Resistors for Setting Output Voltage
Index
R0 or R1
Index
R0 or R1
0
1
2
3
4
5
6
7
8
9
10
11
12
10 kΩ
11 kΩ
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
13
14
15
16
17
18
19
20
21
22
23
24
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
75 kΩ
82.5 kΩ
90.9 kΩ
100 kΩ
Figure 10. Output Voltage Resistor Setting
The output voltage may also be set to any value
between 0.6V and 5.0V using the I2C/SMBus interface. The maximum voltage that can be set is limited
to 110% of the pin-strap value. See Application Note
AN13 for details.
POLA/DOSA Trim Method
The output voltage can also be set using the VADJ pin
to map the standard analog resistor method. This mode
is activated by setting the PMBus private command
POLA_VADJ_CONFIG to 1.
The POLA/DOSA mode can also be set up by pinstrap
using a resistor on V0.
A 110 kΩ resistor on V0 will set to POLA mode 1.
A 120 kΩ resistor on V0 will set to POLA mode 2.
In POLA mode 1 and 2, V0 and V1 pins are inactive,
and the ZL2005P uses the following table to set the
output voltage.
Example:
For VOUT = 1.33V:
Index1 = 4 x 1.33V = 5.32 (5);
From Table 7, using Index = 5
R1 = 16.2 kΩ
Index0 = (100 x 1.33V) - (25 x 5) = 8;
From Table 7; R0 = 21.5 kΩ
15
FN6849.0
February 18, 2009
ZL2005P
Table 8. Resistors for Setting POLA Output
Voltage with VADJ
VOUT
RSET
VOUT
RSET
in series with
10kΩ resistor
0.7V
0.752V
0.758V
0.765V
0.772V
0.79V
0.80V
0.821V
0.834V
0.848V
0.880V
0.899V
0.919V
0.965V
in series with
10kΩ resistor
162 kΩ
110 kΩ
100 kΩ
90.9 kΩ
82.5 kΩ
75.0 kΩ
56.2 kΩ
51.1 kΩ
46.4 kΩ
42.2 kΩ
34.8 kΩ
31.6 kΩ
28.7 kΩ
23.7 kΩ
0.991V
1.00V
1.10V
1.158V
1.200V
1.25V
1.50V
1.669V
1.80V
2.295V
2.506V
3.30V
5.00V
21.5 kΩ
19.6 kΩ
16.2 kΩ
13.3 kΩ
12.1 kΩ
9.09 kΩ
7.50 kΩ
5.62 kΩ
4.64 kΩ
2.87 kΩ
2.37 kΩ
1.21 kΩ
0.162 kΩ
The standard method for adjusting output voltage used
in POLA, is defined by the following equation:
Rset = 10kΩ x 0.69V/(VOUT – 0.69V) – 1.43kΩ
Rset is an external resistor.
POLA Module
0.69V
+
VOUT
-
MODULE
ZL2005P
VADJ
1.43
kOhm
10
kOhm
10
kOhm
RSET
RSET
method will provide the same output voltage with the
ZL2005P.
DOSA Voltage Trim Method
For DOSA output voltage selection, a 8.66 kΩ resistor
needs to be used in place of the 10 kΩ resistor. This
will allow setting the output voltage according to
DOSA equation:
Rset = 6900/(VOUT – 0.69V).
Table 9. Resistors for Setting DOSA Output
Voltage with VADJ
VOUT
Rset
VOUT
in series with
8.66kΩ
resistor
0.7V
0.752V
0.758V
0.765V
0.772V
0.79V
0.80V
0.821V
0.834V
0.848V
0.880V
0.899V
0.919V
0.965V
162 kΩ
113 kΩ
100 kΩ
90.9 kΩ
82.5 kΩ
75.0 kΩ
57.6kΩ
52.3 kΩ
47.5 kΩ
43.2 kΩ
36.5 kΩ
33.2 kΩ
30.1 kΩ
25.5 kΩ
Rset
in series with
8.66kΩ
resistor
0.991V
1.00V
1.10V
1.158V
1.200V
1.25V
1.50V
1.669V
1.80V
2.295V
2.506V
3.30V
5.00V
22.6 kΩ
21.0 kΩ
17.8 kΩ
14.7kΩ
13.3 kΩ
10.5 kΩ
8.87 kΩ
6.98 kΩ
6.04 kΩ
4.32 kΩ
3.74 kΩ
2.61 kΩ
1.50 kΩ
UVLO (POLA Mode)
In POLA mode 1 and 2, undervoltage threshold
(UVLO) is set following POLA standard methodology.
Figure 11. Output Voltage Resistor Setting
POLA - ZL2005P
In the POLA standard, a resistor on the UVLO pin sets
the corresponding voltage value.
To stay compatible with existing methods for adjusting
output voltage and to keep the same external Rset
resistor, the module manufacturer can add a 10 kΩ
resistor on the module.
For a module supplier, a 1.5 kΩ 1% pull-up resistor
from EN to UVLO is required to be compatible with
the POLA Inhibit/UVLO features (Figure 12). EN
must be driven by an open collector/drain driver, and
will default to Enabled unless pulled low. The driver
must remain open after a transition for a minimum of 1
ms to allow the measurement of the resistor on the
UVLO pin.
RVADJ = RSET +10 kΩ
By adding this additional resistor, now the same resistor used to set an output voltage with the analog POLA
By default UVLO is set to 4.5V.
16
FN6849.0
February 18, 2009
ZL2005P
ZL2005P
UVLO
ZL2005P
MODULE
MODULE
EN
UVLO
EN
1.5 kOhm
1.5 kOhm
Inhibit/
UVLO
Inhibit/
UVLO
RUVLO
1 = Inhibit
RUVLO
Q1
Figure 12. UVLO Circuit
Figure 12 shows how to select UVLO based on an
external resistor RSET.
RUVLO maps the POLA equation to set the UVLO
threshold:
RUVLO = (9690 - (137*VIN))/(137*VIN-585) in kΩ
Table 10 shows a chart of standard resistor values for
RUVLO:
Table 10. Resistors for Setting UVLO with
RUVLO
UVLO
RUVLO
UVLO
in series with
1.5 kΩ
resistor
4.3V
4.5V
4.87V
4.93V
4.99V
5.07V
5.15V
5.23V
5.33V
5.43V
5.55V
5.67V
5.81V
RUVLO
in series with
1.5 kΩ
resistor
162 kΩ
121 kΩ
110 kΩ
100 kΩ
90.9 kΩ
82.5 kΩ
75.0 kΩ
68.1 kΩ
61.9 kΩ
56.2 kΩ
51.1 kΩ
46.4 kΩ
42.2 kΩ
6.20V
6.60V
6.96V
7.22V
7.50V
7.81V
8.13V
8.50V
8.92V
9.34V
9.81V
10.86V
11.46V
38.3 kΩ
28.7 kΩ
23.7 kΩ
21.5 kΩ
19.6 kΩ
17.8 kΩ
16.2 kΩ
14.7 kΩ
13.3 kΩ
12.1 kΩ
11.0 kΩ
9.09 kΩ
8.25 kΩ
Figure 13. INHIBIT Circuit
Figure 13 shows the typical application of the Inhibit
function. The inhibit input has its own internal pull-up.
An open-drain transistor is recommended for control.
Flexible pin
When POLA_VADJ_CONFIG is set to mode 2, the
ZL2005P uses the VADJ pin for output voltage setting
and it also disables the SYNC pin. In this mode, the
ZL2005P is not checking the SYNC pin for synchronization to an external signal. Otherwise the resistor
measurement may not be accurate. This configuration
allows a module supplier to connect both VADJ and
SYNC pin to a common pin on the module (Flex pin).
A single module pin can then be used for one or the
other function.
In this mode UVLO will also follow the POLA
method.
FLEX PIN
10kO
SYNC
VADJ
ZL2005P
MODULE
Figure 14. Output Voltage Resistor Setting
Example
For a POLA module, the Inhibit feature is combined
with UVLO.
17
FN6849.0
February 18, 2009
ZL2005P
5.4
Start-up Procedure
The ZL2005P follows a specific internal start-up procedure after power is applied to the VDD pin. Table 11
describes the start-up sequence.
If the device is to be synchronized to an external clock
source, the clock must be stable prior to asserting the
EN pin. The device requires approximately 10-20 ms
to check for specific values stored in its internal memory.
If the user has stored values in memory, those values
will be loaded. The device will then check the status of
all multi-mode pins and load the values associated
with the pin settings.
Once this process is completed, the device is ready to
accept commands via the I2C/SMBus interface and the
device is ready to be enabled. Once enabled, the
device requires approximately 6 ms before its output
voltage may be allowed to start its ramp-up process. If
a soft start delay period less than 6 ms has been configured (using the DLY (0,1) pins), the device will
default to a 6 ms delay period. If a delay period of 6
ms or higher is configured, the device will wait for the
configured delay period before starting to ramp its output.
After the delay period has expired, the output will
begin to ramp towards its target voltage according to
the pre-configured soft-start ramp time.
Table 11. ZL2005P Start-up Sequence
Step #
Step Name
1
Power Applied
2
3
4
5
Description
Input voltage is applied to the ZL2005P’s VDD pin
The device will check for values stored in its internal
Internal Memory
memory. This step is also performed after a Restore
Check
command.
Multi-mode
The device loads values configured by multi-mode
Pin Check
pins.
Device Ready The device is ready to accept an ENABLE signal.
The device requires approximately 6 ms following an
enable signal and prior to ramping its output.
Pre-ramp Delay
Additional pre-ramp delay may be configured using
the Delay pins.
18
Time Duration
Depends on input supply
ramp time
Approx 10-20 ms (device
will ignore an enable signal
or PMBus traffic during this
period)
—
Approx. 6 ms
FN6849.0
February 18, 2009
ZL2005P
The soft start delay and ramp times can be set to standard values according to Table 12 and Table 13
respectively.
RDLY
N/C
ZL2005P
RSS
SS1
The soft start delay period begins when the Enable pin
is asserted and ends when the delay time expires. The
soft-start delay period is set via the I2C/SMBus interface.The soft start ramp enables a controlled ramp to
the nominal VOUT value that begins once the delay
period has timed out. The ramp-up is guaranteed
monotonic and its slope may be precisely set by setting the soft-start ramp time using the SS (0,1) pins.
Note: Do not connect a resistor to the DLY1 or SS1
pin. These pins are not utilized for setting soft-start
delay and ramp times. Connecting an external resistor
to these pins may cause conflicts with other device settings.
SS0
In some system applications, it may be necessary to set
a delay from when an enable signal is received until
the output voltage starts to ramp to its nominal value.
In addition, the designer may wish to precisely set the
time required for VOUT to ramp to its nominal value
after the delay period has expired. The ZL2005P gives
the system designer several options for precisely and
independently controlling both the delay and ramp
time periods for VOUT. These features may be used as
part of an overall in-rush current management strategy
or to precisely control how fast a load IC is turned on.
resistor from the DLY0 or SS0 pin to SGND using the
appropriate resistor value from Table 14. The value of
this resistor is measured upon start-up or Restore and
will not change if this resistor is varied after power has
been applied to the ZL2005. See Figure 15 for typical
connections using resistors.
DLY1
Soft Start Delay and Ramp Times
DLY0
5.5
N/C
Figure 15. DLY and SS Pin Resistor
Connections
Table 12. Soft Start Delay Settings
LOW
LOW
DLY1
OPEN
HIGH
0 ms
1
ms1
5
50 ms
DLY0
OPEN
HIGH
Reserved
10 ms
20 ms
100 ms
200 ms
NOTE:
1. When the device is set to 0 ms or 5 ms delay, it will begin its ramp up
after the internal circuitry has initialized (approx. 6 ms).
Table 13. Soft Start Ramp Settings
LOW
LOW
SS1
OPEN
HIGH
1
0 ms
5 ms
50 ms
SS0
OPEN
1 ms
HIGH
2 ms
10 ms
100 ms
20 ms
200 ms
NOTE:
1. When the soft start ramp is set to zero, the device will ramp up as
quickly as the internal circuitry and output load capacitance will
allow.
If the desired soft start delay and ramp times are not
one of the values listed in Table 11 and Table 12, the
times can be set to a custom value by connecting a
19
FN6849.0
February 18, 2009
ZL2005P
Table 14. DLY and SS Resistor Values
DLY or
SS
RDLY or
RSS
DLY or
SS
RDLY or
RSS
0 ms
10 ms
20 ms
30 ms
40 ms
50 ms
60 ms
70 ms
80 ms
90 ms
100 ms
10 kΩ
11 kΩ
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
110 ms
120 ms
130 ms
140 ms
150 ms
160 ms
170 ms
180 ms
190 ms
200 ms
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
be driven by an internal oscillator or driven from an
external clock source connected to the SYNC pin.
When using the internal oscillator, the SYNC pin can
be configured as a clock output for use by other
devices. The SYNC pin is a unique pin that can perform multiple functions depending on how it is configured. The CFG pin is used to select the operating mode
of the SYNC pin as shown in Table 15. Figure 16
illustrates the typical connections for each mode.
Table 15. SYNC Pin Function Selection
CFG Pin
LOW
OPEN
HIGH
SYNC Pin Function
SYNC is configured as an input
Auto Detect mode
SYNC is configured as an output
fSW = 400 kHz (default)
The soft start delay and ramp period can be set to custom values via the I2C/SMBus interface. When the
soft start delay is set to 0 ms, the device will begin its
ramp up after the internal circuitry has initialized
(approx. 6ms).
5.6
Power Good
The ZL2005P provides a Power Good (PG) signal that
indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. By
default, the PG pin will assert if the output is within 10% to +15% of the target voltage These limits may
be changed via the I2C/SMBus interface. See Application Note AN13 for details.
A PG delay period is defined as the time from when all
conditions within the ZL2005P for asserting PG are
met to when the PG pin is actually asserted. This feature is commonly used instead of using an external
reset controller to control external digital logic. By
default, the ZL2005P PG delay is set equal to the softstart ramp time setting. Therefore, if the soft-start
ramp time is set to 10 ms, the PG delay will be set to
10 ms. The PG delay may be set independently of the
soft-start ramp using the I2C/SMBus as described in
Application Note AN13.
5.7
Switching Frequency and PLL
The ZL2005P incorporates an internal phase locked
loop (PLL) to clock the internal circuitry. The PLL can
20
FN6849.0
February 18, 2009
ZL2005P
SYNC
200 kHz – 1.4 MHz
200 kHz – 1.4 MHz
ZL
ZL
A) SYNC = output
ZL
Open
OR
Logic
low
SYNC
N/C
ZL
SYNC
OR
R SYNC
CFG
N/C
Logic
high
CFG
SYNC
200 kHz – 1.4 MHz
B) SYNC = input
CFG
N/C
CFG
SYNC
CFG
Logic
high
ZL
C) SYNC = Auto Detect
Figure 16. SYNC Pin Configurations
Configuration A: SYNC OUTPUT
Configuration C: SYNC AUTO DETECT
When the SYNC pin is configured as an output (CFG
pin is tied HIGH), the device will operate from its
internal oscillator and will drive the resulting internal
oscillator signal (preset to 400 kHz) onto the SYNC
pin so other devices can be synchronized to it. The
SYNC pin will not be checked for an incoming clock
signal while in this configuration.
When the SYNC pin is configured in auto detect mode
(CFG pin is left OPEN), the device will automatically
check for a clock signal on the SYNC pin after enable
is asserted.
Configuration B: SYNC INPUT
When the SYNC pin is configured as an input (CFG
pin is tied LOW), the device will automatically check
for a clock signal on the SYNC pin each time EN is
asserted. The ZL2005P’s oscillator will then synchronize with the rising edge of external clock.
The incoming clock signal must be in the range of 200
kHz to 1.4 MHz and must be stable when the enable
pin is asserted. The clock signal must also exhibit the
necessary performance requirements (see Table 3). In
the event of a loss of the external clock signal, the output voltage may show transient over/undershoot.
If this happens, the ZL2005P will turn off the power
FETs (QH and QL in Figure 4) typically within 10 μS.
Users are discouraged from removing an external
SYNC clock while the ZL2005P is operating with
Enable asserted.
21
If a clock signal is present, The ZL2005P’s oscillator
will then synchronize the rising edge of the external
clock. Refer to SYNC INPUT description.
If no incoming clock signal is present, the ZL2005P
will configure the switching frequency according to
the state of the SYNC pin as listed in Table 16. In this
mode, the ZL2005P will only read the SYNC pin connection during the start-up sequence. Changes to
SYNC pin connections will not affect fSW until the
power (VDD) is cycled off and on.
Table 16. Switching Frequency Selection
SYNC Pin Setting
LOW
OPEN
HIGH
Resistor
Frequency
200 kHz
400 kHz
1 MHz
See Table 17
If the user wishes to run the ZL2005P at a frequency
other than those listed in Table 16, the switching frequency can be set using an external resistor, RSYNC,
connected between SYNC and SGND using Table 17.
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February 18, 2009
ZL2005P
Table 17. RSYNC Resistor Values
fSW
RSYNC
fSW
RSYNC
200 kHz
222 kHz
242 kHz
267 kHz
296 kHz
320 kHz
364 kHz
400 kHz
421 kHz
471 kHz
10 kΩ
11 kΩ
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
533 kHz
571 kHz
615 kHz
667 kHz
727 kHz
889 kHz
1000 kHz
1143 kHz
1333 kHz
26.1 kΩ
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
68.1 kΩ
The switching frequency can also be set to any value
between 200 kHz and 1.4 MHz using the I2C/SMBus
interface. The available frequencies are bounded by
the relation fsw = 8 MHz/N, (with 6<= N <= 40). See
Application Note AN13 for details on configuring the
switching frequency using the I2C/SMBus interface.
If multiple ZL2005Ps are used together, connecting
the SYNC pins together will force all devices to synchronize to one another. The CFG pin of one device
must have its SYNC pin set as an output and the
remaining devices must have their SYNC pins set as
an input or all devices must be driven by the same
external clock source.
Note: The switching frequency read back using the
appropriate PMBus command will differ slightly from
the selected value in Table 17. The difference is due to
hardware quantization.
5.8
Selecting Power Train Components
The ZL2005P is a synchronous buck controller that
uses external MOSFETs, inductor and capacitors to
perform the power conversion process. The proper
selection of the external components is critical for
optimized performance. Zilker Labs offers an online
circuit design and simulation tool, PowerPilot, to
assist designers in this task.
Please visit http://www.zilkerlabs.com to access PowerPilot. For more detailed guidelines regarding component selection, please refer to Application Note
AN11.
22
To select the appropriate power stage components for
a set of desired performance goals, the power supply
requirements listed in Table 18 must be known.
Table 18. Power Supply Requirements
Example
Parameter
Example
Value
Range
Input voltage (VIN)
3.0 – 14.0 V
Output voltage (VOUT)
0.6 – 5.0 V
0 to ~25 A
Output current (IOUT)
Output voltage ripple
< 3% of
(Vorip)
VOUT
Output load step (Iostep)
< Io
Output load step rate
—
Allowable output
—
deviation due to load step
Maximum PCB temp.
120°C
Desired efficiency
—
Other considerations
Various
12 V
1.2 V
20 A
1% of
VOUT
50% of Io
10 A/µS
± 50 mV
85°C
85%
Optimize
for small
size
Design Trade-offs
The design of a switching regulator power stage
requires the user to consider trade-offs between cost,
size and performance. For example, size can be optimized at the expense of efficiency. Additionally, cost
can be optimized at the expense of size. For a detailed
description of circuit trade-offs, refer to Application
Note AN11.
To start a design, select a switching frequency (fSW)
based on Table 19. This frequency is a starting point
and may be adjusted as the design progresses.
Table 19. Circuit Design Considerations
Frequency
Range
Efficiency
Circuit Size
200 – 400 kHz
400 – 800 kHz
800 – 1400 kHz
Highest
Moderate
Lower
Larger
Smaller
Smallest
Inductor Selection
The output inductor selection process will include several trade-offs. A high inductance value will result in a
low ripple current (Iopp), which will reduce the output
capacitance requirement and produce a low output ripple voltage, but may also compromise output transient
load performance. Therefore, a balance must be
FN6849.0
February 18, 2009
ZL2005P
struck between output ripple and optimal load transient performance. A good starting point is to select
the output inductor ripple current (Iopp) equal to the
expected load transient step magnitude (Iostep):
I opp = I ostep
(3)
Now the output inductance can be calculated using the
following equation:
LOUT =
(
VOUT × 1 − VVOUT
INM
f sw × I opp
)
(4)
where VINM is the maximum input voltage.
The average inductor current is equal to the maximum
output current. The peak inductor current (ILpk) is calculated using the following equation where IOUT is the
maximum output current:
IL pk = I OUT +
I opp
2
(5)
Select an inductor rated for the average DC current
with a peak current rating above the peak current computed above.
In over-current or short-circuit conditions, the inductor
may have currents greater than 2X the normal maximum rated output current. It is desirable to use an
inductor that is not saturated at these conditions to protect the load and the power supply MOSFETs from
damaging currents.
Once an inductor is selected, the DCR and core losses
in the inductor are calculated. Use the DCR specified
in the inductor manufacturer’s datasheet.
PLDCR = DCR × I Lrms
2
(6)
ILrms is given by:
to the maximum power dissipation recommendation in
the inductor datasheet.
Output Capacitor Selection
Several trade-offs also must be considered when
selecting an output capacitor. Low ESR values are
needed to have a small output deviation during transient load steps (Vosag) and low output voltage ripple
(Vorip). However, capacitors with low ESR, such as
semi-stable (X5R and X7R) dielectric ceramic capacitors, also have relatively low capacitance values.
Many designs can use a combination of high capacitance devices and low ESR devices in parallel.
For high ripple currents, a low capacitance value can
cause a significant amount of output voltage ripple.
Likewise, in high transient load steps, a relatively
large amount of capacitance is needed to minimize the
output voltage deviation while the inductor current
ramps up to the new steady state output current value.
As a starting point, allocate one-half of the output voltage ripple to the capacitor ESR and the other half to its
capacitance, as shown in the following equations:
COUT =
ESR =
I opp
8 × f sw ×
Vorip
I Lrms = I OUT +
2
I opp
Use these values to make an initial capacitor selection,
using a single capacitor or several capacitors in parallel.
After a capacitor has been selected, the resulting output voltage ripple can be calculated using the following equation:
I opp
(10)
8 × f sw × COUT
(7)
12
where IOUT is the maximum output current. Next, calculate the core loss of the selected inductor. Since this
calculation is specific to each inductor and manufacturer, refer to the chosen inductor’s datasheet. Add the
core loss and the DCR loss and compare the total loss
23
(9)
2 × I opp
Vorip = I opp × ESR +
2
(8)
Vorip
2
Because each part of this equation was made to be less
than or equal to half of the allowed output ripple voltage, the Vorip should be less than the desired maximum
output ripple.
For more information on the performance of the power
supply in response to a transient load, refer to Application Note AN11.
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February 18, 2009
ZL2005P
Input Capacitor
It is highly recommended that dedicated input
capacitors be used in any point-of-load design, even
when the supply is powered from a heavily filtered 5
or 12 V “bulk” supply. This is because of the high
RMS ripple current that is drawn by the buck
converter topology. This input ripple (ICINrms) can be
determined from the following equation:
I CINrms = I OUT × D × (1 − D )
(11)
Calculate the desired maximum RDS(ON) as follows:
2
(14)
= P /I
R
DS(ON)
Note that the RDS(ON) given in the manufacturer’s
datasheet is measured at 25°C. The actual RDS(ON) in
the end-use application will be much higher. For
example, a Vishay Si7114 MOSFET with a junction
temperature of 125°C has an RDS(ON) 1.4 times higher
than the value at 25°C.
Select a candidate MOSFET, and calculate the
required gate drive current as follows:
Please refer to Application Note AN11 for detailed
derivation including efficiency and ripple current.
Without capacitive filtering near the power supply
input circuit, this current would flow through the supply bus and return planes, coupling noise into other
system circuitry. The input capacitors should be rated
at 1.2X the ripple current calculated above to avoid
overheating of the capacitors due to the high ripple
current, which can cause premature failure. Ceramic
capacitors with X7R or X5R dielectric with low ESR
and 1.1X the maximum expected input voltage are recommended.
Bootstrap Circuit Component Selection
The high-side driver boost circuit utilizes an external
Schottky diode (DB) and an external bootstrap capacitor (CB) to supply sufficient gate drive for the highside MOSFET driver. DB should be a 20 mA, 30 V
Schottky diode or equivalent device and CB should be
a 1 µF ceramic type rated for at least 6.3V.
QL Selection
The bottom MOSFET should be selected primarily
based on the device’s RDS(ON) and secondarily based
on its gate charge. To choose QL, use the following
equation and allow 2–5% of the output power to be
dissipated in the RDS(ON) of QL (lower output voltages
and higher step-down ratios will be closer to 5%):
PQL
= 0 . 05 × V OUT × I OUT
(12)
Calculate the RMS current in QL as follows:
I botrms = I Lrms × 1 − D
QL botrms
I g = f sw × Qg
(15)
Keep in mind that the total allowed gate drive current
for both QH and QL is 80 mA.
MOSFETs with lower RDS(ON) tend to have higher
gate charge requirements, which increases the current
and resulting power required to turn them on and off.
Since the MOSFET gate drive circuits are integrated
in the ZL2005P, this power is dissipated in the
ZL2005P according to the following equation:
PQL = f sw × Qg × VINM
(16)
QH Selection
In addition to the RDS(ON) loss and gate charge loss,
QH also has switching loss. The procedure to select
QH is similar to the procedure for QL. First, assign 2–
5% of the output power to be dissipated in the RDS(ON)
of QH using the equation for QL above. As was done
with QL, calculate the RMS current as follows:
I toprms = I Lrms × D
(17)
Calculate a starting RDS(ON) as follows, in this example using 5%:
PQH
= 0 . 05 × V OUT × I OUT
RDS(ON) = PQH / Itoprms2
(18)
(19)
(13)
Select a MOSFET and calculate the resulting gate
drive current. Verify that the combined gate drive current from QL and QH does not exceed 80 mA.
24
FN6849.0
February 18, 2009
ZL2005P
Next, calculate the switching time using
tsw =
Qg
VIN
GH
(20)
ZL
GL
where Qg is the gate charge of the selected QH and
Igdr is the peak gate drive current available from the
ZL2005P.
Although the ZL2005P has a typical gate drive current
of 3 A, use the minimum guaranteed current of 2 A for
a conservative design. Using the calculated switching
time, calculate the switching power loss in QH using
Pswtop = VINM × t sw × I OUT × f sw
(21)
The total power dissipated by QH is given by the following equation:
P QHtot
VOUT
SW
I gdr
= P QH + P swtop
(22)
CL
R2
Figure 17. DCR Current Sensing
These components should be selected according to the
following equation:
τRC = L / DCR-------------------------- (24)
R1 should be in the range of 500 Ω to 5 kΩ in order to
minimize the power dissipation through it. The user
should make sure the resistor package size is appropriate for the power dissipated. Once R1 has been calculated, the value of R2 should be selected based on the
following equation:
R2 = 5 x R1 -----------------------------(25)
MOSFET Thermal Check
Once the power dissipations for QH and QL have been
calculated, the MOSFET’s junction temperature can
be estimated. Using the junction-to-case thermal resistance (Rth) given in the MOSFET manufacturer’s
datasheet and the expected maximum printed circuit
board temperature, calculate the junction temperature
as follows:
Tj max = Tpcb + PQ × Rth
ISENA
ISENB
R1
(23)
Current Sensing Components
Once the current sense method has been selected
(Refer to Section 5.9, “Current Limit Threshold Selection,” ), the procedure to select the component is the
following:
When using the inductor DCR sensing method, the
user must also select an R/C network comprised of R1
and CL (see Figure 17).
If RDS(ON) is being used the external low side MOSFET will act as the sensing element as indicated in
Figure 18.
5.9
Current Limit Threshold Selection
It is recommended that the user include a current limiting mechanism in their design to protect the power
supply from damage and prevent excessive current
from being drawn from the input supply in the event
that the output is shorted to ground or an overload condition is imposed on the output. Current limiting is
accomplished by sensing the current flowing through
the circuit during a portion of the duty cycle.
Output current sensing can be accomplished by measuring the voltage across a series resistive sensing element according to equation 26.
VLIM = ILIM x RSENSE ---------- -------(26)
Where:
ILIM is the desired maximum current that should
flow in the circuit
RSENSE is the resistance of the sensing element
VLIM is the voltage across the sensing element at
the point the circuit should start limiting the output current.
25
FN6849.0
February 18, 2009
ZL2005P
The ZL2005P supports “lossless” current sensing, by
measuring the voltage across a resistive element that is
already present in the circuit. This eliminates additional efficiency losses incurred by devices that must
use an additional series resistance in the circuit.
To set the current limit threshold, the user must first
select a current sensing method. The ZL2005P incorporates two methods for current sensing, synchronous
MOSFET RDS(ON) sensing and inductor DC resistance
(DCR) sensing; Figure 18 shows a simplified schematic for each method.
VIN
The current sensing method can be selected using the
ILIM1 pin using Table 20. The ILIM0 pin must have a
finite resistor connected to ground in order for
Table 20 to be valid. If no resistor is connected
between ILIM0 and ground, the default method is
MOSFET RDS(ON) sensing. The current sensing
method can be modified via the I2C/SMBus interface.
Please refer to Application note AN13 for details.
In addition to selecting the current sensing method, the
ZL2005P gives the power supply designer several
choices for the fault response during over or under
current condition. The user can select the number of
violations allowed before declaring fault, a blanking
time and the action taken when a fault is detected.
GH
ZL
The blanking time represents the time when no current
measurement is taken. This is to avoid taking a reading
just after a current load step (Less accurate due to
potential ringing). It is a configurable parameter.
VOUT
SW
ISENA
GL
ISENB
MOSFET RDS,ON Sensing
Table 20 includes default parameters for the number of
violations and the blanking time using pin-strap.
VIN
GH
VOUT
SW
ZL
GL
ISENA
ISENB
Inductor DCR Sensing
Figure 18. Current Sensing Methods
Table 20. Current Sensing Method Selection
ILIM0 Pin 1
ILIM1 Pin
RILIM0
LOW
RILIM0
OPEN
RILIM0
HIGH
Current Limiting Configuration
Ground-referenced (RDS,ON) sensing
Blanking time: 672 ns
Output-referenced, down-slope sensing
(Inductor DCR sensing)
Blanking time: 352 ns
Output-referenced, up-slope sensing
(Inductor DCR sensing)
Blanking time: 352 ns
Resistor
Number of
Violations Allowed2
Comments
4
Best for low duty
cycle and low fSW
4
Best for low duty
cycle and high fSW
4
Best for high duty
cycle
Depends on resistor value used; see Table 21
NOTES:
1. 10 kΩ < RILIM0 < 100 kΩ
2. The number of violations allowed prior to issuing a fault response.
26
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February 18, 2009
ZL2005P
Table 21. Resistor Configured Current Sensing Method Selection
RILIM1
10 kΩ
11 kΩ
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
75 kΩ
82.5 kΩ
90.9 kΩ
Number of Violations
Allowed1
Current Sensing Method
1
3
5
7
9
11
13
15
1
3
5
7
9
11
13
15
1
3
5
7
9
11
13
15
Ground-referenced (RDS,ON) sensing
Best for low duty cycle and low fSW
Blanking time: 672 ns
Output-referenced, down-slope sensing (Inductor DCR sensing)
Best for low duty cycle and high fSW
Blanking time: 352 ns
Output-referenced, up-slope sensing (Inductor DCR sensing)
Best for high duty cycle
Blanking time: 352 ns
NOTES:
1. The number of violations allowed prior to issuing a fault response.
Once the sensing method has been selected, the user
must select the voltage threshold (VLIM) based on
equation 26, the desired current limit threshold, and
the resistance of the sensing element.
The current limit threshold can be selected by simply
connecting the ILIM0 and ILIM1 pins as shown in
Table 22. The ground-referenced sensing method is
being used in this mode.
Table 22. Current Limit Threshold Voltage Settings
ILIM1
LOW
OPEN
HIGH
LOW
20 mV
50 mV
80 mV
27
ILIM0
OPEN
30 mV
60 mV
90 mV
HIGH
40 mV
70 mV
100 mV
The threshold voltage can also be selected in 5 mV
increments by connecting a resistor, RLIM0, between
the ILIM0 pin and ground according to Table 23. This
method is preferred if the user does not desire to use or
does not have access to the I2C/SMBus interface and
the desired threshold value is contained in Table 23.
Table 23. Current Limit Threshold Voltage Settings
VLIM
RLIM0
VLIM
RLIM0
0 mV
5 mV
10 kΩ
11 kΩ
12.1 kΩ
55 mV
60 mV
28.7 kΩ
31.6 kΩ
34.8 kΩ
10 mV
15 mV
20 mV
25 mV
13.3 kΩ
14.7 kΩ
16.2 kΩ
65 mV
70 mV
75 mV
80 mV
38.3 kΩ
42.2 kΩ
46.4 kΩ
FN6849.0
February 18, 2009
ZL2005P
Table 23. Current Limit Threshold Voltage Settings
30 mV
35 mV
40 mV
45 mV
50 mV
85 mV
17.8 kΩ
19.6 kΩ
90 mV
95 mV
100 mV
21.5 kΩ
23.7 kΩ
26.1 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
The current limit threshold can be set via the I2C/
SMBus interface. Please refer to Application Note
AN13 for further details on setting current limit
parameters.
5.10 Loop Compensation
The ZL2005P operates as a voltage-mode synchronous buck controller with a fixed frequency PWM
scheme. Although the ZL2005P uses a digital control
loop, it operates much like a traditional analog PWM
controller. See Figure 19 for a simplified block diagram of the ZL2005P control loop, which differs from
an analog control loop by the constants in the PWM
and compensation blocks. As in the analog controller
case, the compensation block compares the output
voltage to the desired voltage reference and compensation zeros are added to keep the loop stable. The
resulting integrated error signal is used to drive the
PWM logic, converting the error signal into a duty
cycle value to drive the external MOSFETs.
VIN
D
L
VOUT
DPWM
1-D
C
RO
RC
Compensation
Figure 19. Control Loop Block Diagram
In the ZL2005P, the compensation zeros are set by
configuring the FC0 pin or via the I2C/SMBus interface once the user has calculated the required settings.
Most applications can be served by using the pin-strap
compensation settings listed in Table 24. These settings will yield a conservative crossover frequency.
The parameters of the feedback compensation can also
be set using the I2C/SMBus interface. A sofware
(CompZLTM) is also available from Zilker Labs to calculate automatically the compensation parameters.
FC1 pin is not used in the ZL2005P.
Table 24. Pin-Strap Setting for Loop
Compensation
28
FC0 Pin
Description
HIGH
OPEN
LOW
High Q, Low Bandwidth
Real zeros, High Bandwidth
Low Q, Low Bandwidth
FN6849.0
February 18, 2009
ZL2005P
5.11 Non-Linear Response Settings
The ZL2005P incorporates a non-linear response
(NLR) loop that decreases the response time and the
output voltage deviation in the event of a sudden output load current step. The NLR loop incorporates a
secondary error signal processing path that bypasses
the primary error loop when the output begins to transition outside of the standard regulation limits. This
scheme results in a higher equivalent loop bandwidth
than is possible using a traditional linear loop.
When a load current step function imposed on the output causes the output voltage to drop below the lower
regulation limit, the NLR circuitry will force a positive
correction signal that will turn on the upper MOSFET
and quickly force the output to increase. A negative
load step will cause the NLR circuitry to force a negative correction signal that will turn on the lower MOSFET and quickly force the output to decrease.
5.12 Efficiency Optimized Driver Deadtime Control
The ZL2005P utilizes a closed loop algorithm to optimize the dead-time applied between the gate drive signals for the top and bottom FETs. In a synchronous
buck converter, the MOSFET drive circuitry must be
designed such that the top and bottom MOSFETs are
never in the conducting state at the same time. (Potentially damaging currents flow in the circuit if both top
and bottom MOSFETs are simultaneously on for periods of time exceeding a few nanoseconds.) Conversely, long periods of time in which both MOSFETs
are off reduce overall circuit efficiency by allowing
current to flow in their parasitic body diodes.
It is therefore advantageous to minimize this deadtime to provide optimum circuit efficiency. In the first
order model of a buck converter, the duty cycle is
determined by the equation:
D = VOUT /VIN -------------------- (29)
However, non-idealities exist that cause the real duty
cycle to extend beyond the ideal. Deadtime is one of
those non-idealities that can be manipulated to
improve efficiency. The ZL2005P has an internal algorithm that constantly adjusts deadtime non-overlap to
minimize duty cycle, thus maximizing efficiency. This
circuit will null out deadtime differences due to component variation, temperature and loading effects.
This algorithm is independent of application circuit
parameters such as MOSFET type, gate driver delays,
rise and fall times and circuit layout. In addition, it
does not require drive or MOSFET voltage or current
waveform measurements.
29
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February 18, 2009
ZL2005P
6
Power Management Functional Description
6.1
Input Undervoltage Lockout (UVLO)
Standard Mode
The input undervoltage lockout (UVLO) prevents the
ZL2005P from operating when the input falls below a
preset threshold, indicating the input supply is out of its
specified range. The UVLO threshold (VUVLO) can be
set between 2.85 V and 16 V using the UVLO pin. The
simplest implementation is to connect the UVLO pin as
shown in Table 25. If the UVLO pin is left unconnected, the UVLO threshold will default to 4.5 V.
Table 25. UVLO Threshold Settings
Pin Setting
UVLO Threshold
LOW
OPEN
HIGH
3V
4.5 V
10.8 V
3. Initiate an immediate shutdown until the fault has
been cleared. The user can select a specific number of retry attempts.
The default response from a UVLO fault is an immediate shutdown of the device. The device will continuously check for the presence of the fault condition. If
the fault condition is no longer present, the ZL2005P
will be re-enabled.
Please refer to Application Note AN13 for details on
how to configure the UVLO threshold or to select specific UVLO fault response options via the I2C/SMBus
interface.
6.2
If the desired UVLO threshold is not one of the listed
choices, the user can configure a threshold between
2.85 V and 16 V by connecting a resistor between the
UVLO pin and GND by selecting the appropriate
resistor from Table 26.
Table 26. UVLO Resistor Values
UVLO
RUVLO
UVLO
RUVLO
2.85 V
3.14 V
3.44 V
3.79 V
4.18 V
4.59 V
5.06 V
5.57 V
6.13 V
6.75 V
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
7.42 V
8.18 V
8.99 V
9.9 V
10.9 V
12 V
13.2 V
14.54 V
16 V
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
75 kΩ
82.5 kΩ
90.9 kΩ
100 kΩ
VUVLO can also be set to any value between 2.85 V
and 16 V via I2C/SMBus.
Once an input undervoltage fault condition occurs, the
device can respond in a number of ways as follows:
1. Continue operating without interruption.
2. Continue operating for a given delay time, followed by shutdown if the fault still persists at the
30
end of the delay period. The device will remain in
shutdown until permitted to restart.
Output Overvoltage Protection
The ZL2005P offers an internal output overvoltage
protection circuit that can be used to protect sensitive
load circuitry from being subjected to a voltage higher
than its prescribed limits. This feature is especially
useful in protecting expensive processors, FPGAs, and
ASICs from excessive voltages.
A hardware comparator is used to compare the actual
output voltage (seen at the VSEN pin) to a threshold set
to 15% higher than the target output voltage by default.
If the voltage at the VSEN pin exceeds this upper
threshold level, the PG pin will de-assert. The device
can then respond in a number of ways as follows:
1. Initiate an immediate shutdown until the fault has
been cleared. The user can select a specific number of retry attempts.
2. Turn off the high-side MOSFET and turn on the
low-side MOSFET. The low-side MOSFET
remains ON until the device attempts a restart.
The default response from an overvoltage fault is an
immediate shutdown of the device. The device will
continuously check for the presence of the fault condition. If the fault condition is no longer present, the
ZL2005P will be re-enabled.
Please refer to Application Note AN13 for details on
how to select specific overvoltage fault response
options via the I2C/SMBus interface.
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ZL2005P
6.3
Output Pre-Bias Protection
An output pre-bias condition exists when an externally
applied voltage is present on a power supply’s output
before the power supply’s control IC is enabled. Certain applications require that the converter not be
allowed to sink current during start up if a pre-bias
condition exists at the output. The ZL2005P provides
pre-bias protection by sampling the output voltage
prior to initiating an output ramp.
If a pre-bias voltage lower than the target voltage
exists after the pre-configured delay period has
expired, the target voltage is set to match the existing
pre-bias voltage and both drivers are enabled. The output voltage is then ramped to the final regulation value
at the ramp rate set by the SS (0,1) pins. The actual
time the output will take to ramp from the pre-bias
voltage to the target voltage will vary depending on
the pre-bias voltage but the total time elapsed from
when the delay period expires and when the output
reaches its target value will match the pre-configured
ramp time. See Figure 20.
If the pre-bias voltage is higher than the target voltage
exists after the pre-configured delay period has
expired, the target voltage is set to match the existing
pre-bias voltage and both drivers are enabled with a
PWM duty cycle that would ideally create the pre-bias
voltage. Once the pre-configured soft-start ramp
period has expired, the Power Good pin will be
asserted (assuming the pre-bias voltage is not higher
than the overvoltage limit). The PWM will then adjust
its duty cycle to match the original target voltage and
the output will ramp down to the pre-configured output voltage.
If a pre-bias voltage higher than the overvoltage limit,
the device will not initiate a turn-on sequence and will
declare an overvoltage fault condition to exist. In this
case, the device will respond based on the output overvoltage fault response method that has been selected.
See Section 6.2, “Output Overvoltage Protection,” for
response options due to an overvoltage condition.
6.4
Output Overcurrent Protection
The ZL2005P can protect the power supply from damage if the output is shorted to ground or if an overload
condition is imposed on the output. Once the current
limit threshold has been selected (see Section 5.9,
“Current Limit Threshold Selection,” ), the user may
determine the desired course of action to be taken
when an overload condition exists.
I
VOUT
Target
voltage
Pre-bias
voltage
SS
Delay
Time
SS
Ramp
The following overcurrent protection response options
are available:
1. Initiate a shutdown and attempt to restart an infinite number of times with a preset delay time.
VPREBIAS < VTARGET
2. Initiate a shutdown and attempt to restart the
power supply a preset number of times with a preset delay between attempts.
VOUT
Pre-bias
voltage
Target
voltage
3. Continue operating throughout a specific delay
time, followed by shutdown.
SS
Delay
SS
Ramp
Time
PG
Delay
VPREBIAS > VTARGET
Figure 20. Output Response to Pre-Bias
Voltages
31
4. Continue operating throughout the fault (this
could result in permanent damage to the power
supply).
5. Initiate an immediate shutdown.
The default response from an overcurrent fault is an
immediate shutdown of the device. The device will
continuously check for the presence of the fault condition. If the fault condition is no longer present, the
ZL2005P will be re-enabled.
FN6849.0
February 18, 2009
ZL2005P
Please refer to Application Note AN15 for details on
how to select specific overcurrent fault response
options via the I2C/SMBus interface.
6.5
Thermal Protection
The ZL2005P includes an on-chip thermal sensor that
continuously measures the internal temperature of the
die and will shut down the device when the temperature exceeds the preset limit. The default temperature
limit is set to 125°C in the factory, but the user may set
the limit to a different value if desired. See Application Note AN13 for details. Note that setting a higher
thermal limit via the I2C/SMBus interface may result
in permanent damage to the device. Once the device
has been disabled due to an internal temperature fault,
the user may select one of several fault response
options as follows:
1. Initiate a shutdown and attempt to restart an infinite number of times with a preset delay time.
2. Initiate a shutdown and attempt to restart the
power supply a preset number of times with a preset delay between attempts.
3. Continue operating throughout a specific delay
time, followed by shutdown.
4. Continue operating throughout the fault (this
could result in permanent damage to the power
supply).
5. Initiate an immediate shutdown.
If the user has configured the device to restart, the
device will wait the preset delay period (if configured
to do so) and will then check the temperature. If the
temperature has dropped below a value that is approximately 15°C lower than the selected temperature limit
(the over-temperature warning threshold), the device
will attempt to re-start. If the temperature is still
above the over-temperature warning threshold, the
device will wait the preset delay period and retry
again.
6.6
Voltage Tracking
Numerous high performance systems place stringent
demands on the order in which the power supply voltages are turned on. This is particularly true when
powering FPGAs, ASICs, and other advanced processor devices that require multiple supply voltages to
power a single die. In most cases, the I/O operates at a
higher voltage than the Core and therefore the Core
supply voltage, must not exceed the I/O supply voltage
by some amount (typically 300 mV).
Voltage tracking protects these sensitive ICs by limiting the differential voltage between multiple power
supplies during the power-up and power down
sequence. The ZL2005P integrates a lossless tracking
scheme that allows its output to track a voltage that is
applied to the VTRK pin with no external components
required. The VTRK pin is an analog input that, when
tracking mode is enabled, configures the voltage
applied to the VTRK pin to act as a reference for the
device’s output regulation.
The ZL2005P offers two modes of tracking:
1. Coincident. This mode configures the ZL2005P to
ramp its output voltage at the same rate as the voltage applied to the VTRK pin.
2. Ratiometric. This mode configures the ZL2005P
to ramp its output voltage at a rate that is a percentage of the voltage applied to the VTRK pin.
The default setting is 50%, but an external resistor
string may be used to configure a different tracking ratio.
Figure 21 illustrates the typical connection and the two
tracking modes.
The Tracking feature is not supported for ZL2005P
devices in a current sharing group.
The default response from a temperature fault is an
immediate shutdown of the device. The device will
continuously check for the presence of the fault condition. If the fault condition is no longer present, the
ZL2005P will be re-enabled.
Please refer to Application Note AN13 for details on
how to select specific temperature fault response
options via the I2C/SMBus interface.
32
FN6849.0
February 18, 2009
ZL2005P
6.7
VIN
Q1
GH
ZL
VTRK
SW
L1
Q2
GL
VOUT
C1
VTRK
VOUT
Voltage Margining
The ZL2005P offers a simple means to vary its output
higher or lower than its nominal voltage setting in
order to determine whether the load device is capable
of operating over its specified supply voltage range.
The MGN pin is a TTL-compatible input that is continuously monitored and can be driven directly by a
processor I/O pin or other logic-level output.
VTRK
VOUT
Time
Coincident
VOUT
VTRK
VOUT
Time
The ZL2005P output will be forced higher than its
nominal setpoint when the MGN pin is driven HIGH,
and the output will be forced lower than its nominal
setpoint when the MGN pin is driven LOW. When the
MGN pin is left floating (high impedance), the
ZL2005P output voltage will be set to its nominal voltage setpoint determined by the V0 and V1 pins and/or
the I2C/SMBus settings that configure the nominal
output voltage. Default margin limits of VNOM ±5%
are pre-loaded in the factory, but the margin limits can
be modified through the I2C/SMBus interface to as
high as VNOM + 10% or as low as 0V, where VNOM is
the nominal output voltage setpoint determined by the
V0 and V1 pins.
Ratiometric
Figure 21. Tracking Modes
The master ZL2005P device in a tracking group is
defined as the device that has the highest target output
voltage within the group. This master device will control the ramp rate of all tracking devices and is not
configured for tracking mode. A delay of at least 10
ms must be configured into the master device, and the
user may also configure a specific ramp rate using
PMBus.
Any device that is configured for tracking mode will
ignore its soft-start delay and ramp time settings and
its output will take on the turn-on/turn-off characteristics of the reference voltage present at the VTRK pin.
The tracking mode for all other devices can be set by
PMBus. All of the ENABLE pins in the tracking group
must be connected together and driven by a single
logic source.
The margin limits and the MGN command can both be
set individually through the I2C/SMBus interface.
Additionally, the transition rate between the nominal
output voltage and either margin limit can be configured through the I2C/SMBus interface. Please refer to
Application Note AN13 for detailed instructions on
modifying the margining configurations.
6.8
I2C/SMBus Communications
The ZL2005P provides an I2C/SMBus digital interface
that enables the user to configure all aspects of the
device operation as well as monitor the input and output parameters. The ZL2005P can be used with any
standard 2-wire I2C host device. In addition, the
device is compatible with SMBus version 2.0 and
includes an SALRT line to help mitigate bandwidth
limitations related to continuous fault monitoring. The
ZL2005P accepts most standard PMBus commands.
Please refer to Application Note AN13 for details on
how to configure tracking via the I2C/SMBus interface.
33
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February 18, 2009
ZL2005P
I2C/SMBus Device Address Selection
When communicating with multiple ZL2005Ps using
the I2C/SMBus serial interface, each device must have
its own unique address so the host can distinguish
between the devices. The device address can be set
according to the pin-strap options listed in Table 27 to
provide up to eight unique device addresses. Address
values are right-justified.
Using this method, the user can theoretically configure
up to 625 unique SMBus addresses; however, the
SMBus is inherently limited to 128 devices so
attempting to configure an address higher than 128
will cause the device address to repeat (i.e, attempting
to configure a device address of 129 would result in a
device address of 1). Therefore, the user should use
index values 0-4 on the SA1 pin and the full range of
index values on the SA0 pin, which will provide 125
device address combinations.
Table 27. Serial Bus Device Address Selection
Table 29. SMBus Address Index Values
6.9
SA1
SA0
LOW
OPEN
HIGH
LOW
OPEN
HIGH
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
Reserved
If additional device addresses are required, a resistor
can be connected to the SA0 pin according to Table 28
to provide up to 25 unique device addresses. In this
case the SA1 pin should be tied to SGND with a zero
ohm resistor.
Table 28. SMBus Address Values
SMBus
Address
RSA0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
10 kΩ
11 kΩ
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
SMBus
Address
RSA0
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
34.8 kΩ
38.3kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
75 kΩ
82.5 kΩ
90.9 kΩ
100 kΩ
If more than 25 unique device addresses are required
or if other SMBus address values are desired, both the
SA0 and SA1 pins can be configured with a resistor to
SGND according to the equation (30) and Table 29.
SMBus addr = 25x(SA1 index)+(SA0 index) (30)
34
SA0 or
SA1 Index
RSA
0
1
2
3
4
5
6
7
8
9
10
11
12
10 kΩ
11 kΩ
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
SA0 or
SA1
Index
RSA
13
14
15
16
17
18
19
20
21
22
23
24
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
75 kΩ
82.5 kΩ
90.9 kΩ
100 kΩ
6.10 Phase Spreading
When multiple point of load converters share a common DC input supply, it is desirable to adjust the clock
phase offset of each device such that not all devices
start to switch simultaneously. Setting each converter
to start its switching cycle at a different point in time
can dramatically reduce input capacitance requirements and efficiency losses. Since the peak current
drawn from the input supply is effectively spread out
over a period of time, the peak current drawn at any
given moment is reduced and the power losses proportional to the IRMS2 are reduced dramatically.
In order to enable phase spreading, all converters must
be synchronized to the same switching clock. The
CFG pin is used to set the configuration of the SYNC
pin for each device as described in Section 5.7,
“Switching Frequency and PLL,” .
FN6849.0
February 18, 2009
ZL2005P
Selecting the phase offset for the device is accomplished by selecting a device address according to the
following equation:
Phase offset = device address x 45°
For example:
A device address of 0x00 or 0x20 would configure no
phase offset
A device address of 0x01 or 0x21 would configure 45° of phase offset
A device address of 0x02 or 0x22 would configure 90° of phase offset.
The group will turn on in order starting with the device
with the lowest address and will continue to turn on
each device in the address chain until all devices connected have been turned on. When turning off, the
device with the highest address will turn off first followed in reverse order by the other devices in the
group.
Sequencing is configured by connecting a resistor
from the CFG pin to ground as described in Table 30.
The CFG pin is used to set the configuration of the
SYNC pin as well as to determine the sequencing
method and order. Please refer to Switching Frequency
and PLL for more details on the operating parameters
of the SYNC pin.
The phase offset of each device may also be set to any
value between 0° and 337.5° in 22.5° increments via
the I2C/SMBus interface. Please refer to Application
Note AN13 for details.
6.11 Output Sequencing
A group of ZL2005P devices may be configured to
power up in a predetermined sequence. This feature is
especially useful when powering advanced processors,
FPGAs, and ASICs that require one supply to reach its
operating voltage prior to another supply reaching its
operating voltage. Multi-device sequencing can be
achieved by configuring each device through the I2C/
SMBus interface or by using Zilker Labs’ proprietary
Autonomous SequencingTM mode.
Autonomous sequencing mode configures sequencing
using status information broadcast by ZL2005P onto
the I2C/SMBus pins SCL and SDA. No I2C or SMBus
host device is involved in this method, but the SCL
and SDA pins must be interconnected between all
devices that the user wishes to sequence using this
method. Note: Pull-up resistors on SCL and SDA are
required and should be selected using the criteria in
the SMBus 2.0 specification.
The sequence order is determined using each device’s
I2C/SMBus device address.
Using autonomous
sequencing mode (configured using the CFG pin), the
devices must exhibit sequential device addresses with
no missing addresses in the chain. This mode will also
constrain each device to have a phase offset according
to its device address as described in Section 6.10,
“Phase Spreading” on this page.
35
FN6849.0
February 18, 2009
ZL2005P
.
Table 30. CFG Pin Configurations for Sequencing
RCFG
10 kΩ
11 kΩ
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
Sequencing Configuration
SYNC Pin Config
Input
Auto detect
Output
Auto detect
Input
Auto detect
Output
Auto detect
Input
Auto detect
Output
Auto detect
Input
Auto detect
Output
Auto detect
Input
Sequencing is disabled
The ZL2005P is configured as the first device in a nested
sequencing group. Turn-on order is based on the device SMBus
address.
The ZL2005P is configured as a last device in a nested sequencing
group. Turn-on order is based on the device SMBus address.
The ZL2005P is configured as the middle device in a nested
sequencing group. Turn-on order is based on the device SMBus
address.
Sequencing is disabled
Multiple device sequencing may also be achieved by
issuing PMBus commands to assign the preceding
device in the sequencing chain as well as the device
that will follow in the sequencing chain. This method
places fewer restrictions on device address (no need of
sequential address) and also allows the user to assign
any phase offset to any device irrespective of its
device address.
Event-based sequencing and fault spreading are broadcast in address groups of up to sixteen ZL2005P
devices. An address group consists of all devices
whose addresses differ in only the four least significant bits of the address. For example, addresses 20, 25
and 2F are all within the same group. Addresses 1F, 20
and 35 are all in different groups. Devices in the same
address group can broadcast power on and power off
sequencing and fault spreading events with each other.
Devices in different groups cannot.
The Enable pins of all devices in a sequencing group
must be tied together and driven high to initiate a
sequenced turn-on of the group. Enable must be driven
low to initiate a sequenced turnoff of the group.
Please refer to Application Note AN13 for details on
sequencing via the I2C/SMBus interface.
36
6.12 Monitoring via I2C/SMBus
A system controller can monitor a wide variety of different ZL2005P system parameters through the I2C/
SMBus interface. The controller can monitor for fault
conditions by monitoring the SALRT pin, which will
be asserted when any number of pre-configured fault
or warning conditions occur. The system controller
can also continuously monitor for any number of
power conversion parameters including but not limited
to the following:
1. Input voltage
2. Output voltage
3. Output current
4. Internal junction temperature
5. Temperature of an external device
6. Switching frequency
7. Duty cycle
Please refer to Application Note AN13 for details on
how to monitor specific parameters via the I2C/
SMBus interface.
When using the ZL2005P with other controllers on the
same bus, these controllers need to be compliant with
FN6849.0
February 18, 2009
ZL2005P
multi master specifications. Please refer to http://
www.i2c-bus.org/multimaster/ for more information.
6.13 Temperature Monitoring Using the
XTEMP Pin
The ZL2005P supports measurement of an external
device temperature using either a thermal diode integrated in a processor, FPGA or ASIC, or using a discrete diode-connected NPN transistor such as a
2N3904 or equivalent. Figure 22 illustrates the typical
connections required.
XTEMP
100pF
ZL2005P
2N3904
SGND
Discrete NPN
XTEMP
ZL2005P
100pF
SGND
µP
FPGA
DSP
ASIC
6.14 Non-volatile Memory and Device
Security Features
The ZL2005P has internal non-volatile memory where
user configurations are stored. Integrated security
measures ensure that the user can only restore the
device to a level that has been made available to them.
During the initialization process, the ZL2005P checks
for stored values contained in its internal memory. The
ZL2005P offers one internal memory storage unit (two
for the ZL2005) called Default Store.
A system designer or a power supply module manufacturer may want to protect the device by preventing
the user from being able to modify certain values. In
this case, he would use the Default Store and would
allow the user to restore the device to its default setting but would restrict the user from restoring the
device to the factory setting. Please refer to Application Note AN13 for details on how to set specific security measures via the I2C/SMBus interface.
Embedded Thermal Diode
Figure 22. External Temp Monitoring
37
FN6849.0
February 18, 2009
ZL2005P
7
Package Dimensions
NOTES:
1.
DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14.5M. – 1994.
2.
ALL DIMENSIONS ARE IN MILLIMETERS (mm), O IS IN DEGREES.
3.
N IS THE TOTAL NUMBER OF TERMINALS.
4.
DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM
TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
5.
ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE, RESPECTIVELY.
6.
MAXIMUM PACKAGE WARPAGE IS 0.05 mm.
7.
MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.
8.
PIN #1 ID ON TOP WILL BE LASER MARKED.
9.
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
10. THIS DRAWING CONFORMS TO JEDEC REGISTERED OUTLINE MO-220.
38
FN6849.0
February 18, 2009
ZL2005P
8
Ordering Information
Related Documentation
The following application support documents and tools are available to help simplify your design.
Item
Description
ZL2005EVK1
AN10
AN11
AN13
AN15
AN16
AN21
AN22
AN23
Evaluation Kit: DC-DC Converter with Power Management
Application Note: ZL2005 and ZL2105 Thermal and Layout Guidelines
Application Note: ZL2005 Component Selection Guide
Application Note: PMBus Command Set
Application Note: ZL2005 Current Protection and Measurement
Application Note: ZL2005 Digital Control Loop Compensation
Application Note: Protecting Configuration During Manufacturing
Application Note: Autonomous Sequencing Technology
Application Note: Voltage Tracking with the ZL2005
Revision History
Revision Number
Description
Date
1.0
1.1
FN6849.0
Initial Release
Updated Ordering Information
Assigned file number FN6849 to datasheet as this will be
the first release with an Intersil file number. Replaced
header and footer with Intersil header and footer. Updated
disclaimer information to read "Intersil and it's subsidiaries
including Zilker Labs, Inc." No changes to datasheet
content.
10/08/07
8/12/08
2/18/09
39
FN6849.0
February 18, 2009
ZL2005P
Zilker Labs, Inc.
4301 Westbank Drive
Building A-100
Austin, TX 78746
Tel: 512-382-8300
Fax: 512-382-8329
© 2006, Zilker Labs, Inc. All rights reserved. Zilker Labs, Digital-DC, Autonomous Sequencing and
the Zilker Labs logo are trademarks of Zilker Labs, Inc. All other products or brand names mentioned
herein are trademarks of their respective holders.
This document contains information on a product under development. Specifications are subject to
change without notice. Pricing, specifications and availability are subject to change without notice.
Please see www.zilkerlabs.com for updated information. This product is not intended for use in connection with any high-risk activity, including without limitation, air travel, life critical medical operations, nuclear facilities or equipment, or the like.
The reference designs contained in this document are for reference and example purposes only. THE
REFERENCE DESIGNS ARE PROVIDED "AS IS" AND "WITH ALL FAULTS" AND INTERSIL
CORPORATION AND IT'S SUBSIDIARIES INCLUDING ZILKER LABS, INC. DISCLAIMS ALL
WARRANTIES, WHETHER EXPRESS OR IMPLIED. ZILKER LABS SHALL NOT BE LIABLE
FOR ANY DAMAGES, WHETHER DIRECT, INDIRECT, CONSEQUENTIAL (INCLUDING
LOSS OF PROFITS), OR OTHERWISE, RESULTING FROM THE REFERENCE DESIGNS OR
ANY USE THEREOF. Any use of such reference designs is at your own risk and you agree to indemnify Intersil Corporation and it's subsidiaries including Zilker Labs, Inc. for any damages resulting
from such use.
40
FN6849.0
February 18, 2009