ZARLINK ZL50053QCC

ZL50051/3
8 K Channel Digital Switch with High Jitter
Tolerance, Single Rate (8 or 16 Mbps),
and 64 Inputs and 64 Outputs
Data Sheet
Features
•
December 2003
Ordering Information
8,192 channel x 8,192 channel non-blocking
unidirectional switching. The Backplane and
Local inputs and outputs can be combined to form
a non-blocking switching matrix with 64 input
streams and 64 output streams
ZL50051GAC
ZL50053QCC
256 ball PBGA
256 pin LQFP
•
4,096 channel x 4,096 channel non-blocking
Backplane input to Local output stream switch
•
4,096 channel x 4,096 channel non-blocking
Local input to Backplane output stream switch
•
Per-stream bit delay for Local and Backplane
input streams
•
4,096 channel x 4,096 channel non-blocking
Backplane input to Backplane output switch
•
Per-stream advancement for Local and Backplane
output streams
•
4,096 channel x 4,096 channel non-blocking
Local input to Local output stream switch
•
Constant 2-frame throughput delay for frame
integrity
•
Backplane port accepts 32 input and 32 output
ST-BUS streams with a fixed data rate of
8.192 Mbps, or 16 input and 16 output ST-BUS
streams with a fixed data rate of 16.384 Mbps
•
Per-channel high impedance output control for
Local and Backplane streams
•
Per-channel driven-high output control for Local
and Backplane streams
•
Per-channel message mode for Local and
Backplane output streams
•
Connection memory block programming for fast
device initialization
•
•
-40°C to +85°C
Local port accepts 32 input and 32 output STBUS streams with a fixed data rate of
8.192 Mbps, or 16 input and 16 output ST-BUS
streams with a fixed data rate of 16.384 Mbps
Exceptional input clock jitter tolerance (17 ns)
VDD_IO VDD_CORE
Backplane
Connection Memory
(4,096 locations)
Backplane
Interface
BSTo0-31
ODE
Local
Interface
Local
Connection Memory
(4,096 locations)
LSTo0-31
LORS
Input
Timing Unit
PLL
VDD_PLL
Output
Timing
Unit
Microprocessor Interface
and Internal Registers
DS CS R/W
A14-0
DTA
LSTi0-31
Local
Interface
Local Data Memories
(4,096 channels)
BORS
C8i
RESET
Backplane Data Memories
(4,096 channels)
BSTi0-31
FP8i
VSS (GND)
Test Port
D15-0
TMS TDi TDo TCK TRST
Figure 1 - ZL50051/3 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
FP8o
FP16o
C8o
C16o
ZL50051/3
•
Automatic selection between ST-BUS and GCI-Bus operation
•
Non-multiplexed Motorola microprocessor interface
•
Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
•
Memory Built-In-Self-Test (BIST), controlled via microprocessor register
•
1.8 V core supply voltage
•
3.3 V I/O supply voltage
•
5 V tolerant inputs, outputs and I/Os
Applications
•
Central Office Switches (Class 5)
•
Media Gateways
•
Class-Independent Switches
•
Access Concentrators
•
Scalable TDM-Based Architectures
•
Digital Loop Carriers
2
Zarlink Semiconductor Inc.
Data Sheet
ZL50051/3
Data Sheet
Device Overview
The ZL50051 and ZL50053 are two different packages of the same device. They have the same functionality
except that ZL50053 does not have 16.384 MHz output clock and frame pulse (C16o and FP16o) due to package
differences. The ZL50051/3 has two data ports, the Backplane and the Local port. The device can operate at two
different data rates, 8.192 Mbps or 16.384 Mbps. All 64 input and 64 output streams must operate at the same data
rate.
The ZL50051/3 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:
•
Input-to-Output Unidirectional, supporting 8 K x 8 K switching
•
Backplane-to-Local Bi-directional, supporting 4 K x 4 K data switching
•
Local-to-Backplane Bi-directional, supporting 4 K x 4 K data switching
•
Backplane-to-Backplane Bi-directional, supporting 4 K x 4 K data switching
•
Local-to-Local Bi-directional, supporting 4 K x 4 K data switching
The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly
from the connection memory contents (Message Mode).
In Connection Mode, the contents of the connection memory define, for each output stream and channel, the
source stream and channel, (stored in data memory), to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing
for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCIBus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the
establishment of full switch functionality. During this period, the input frame pulse format is determined before
switching begins.
The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of
the Backplane and Local ports.
A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and
switching configurations. The microprocessor port provides access for Register read/write, Connection Memory
read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and four
control signals. The microprocessor may monitor channel data in the Backplane and Local data memories.
The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.
The ZL50051 and ZL50053 are each available in one package:
•
ZL50051: a 17 mm x 17 mm body, 1 mm ball-pitch, 256-PBGA
•
ZL50053: a 28 mm x 28 mm body, 0.40 mm pin-pitch, 256-LQFP
3
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Table of Contents
1.0 Unidirectional and Bi-directional Switching Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 Flexible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration) . . . . . . . . . . . . . . . . . . 18
1.1.2 Non-Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.3 Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.1 Unidirectional Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.2 Backplane-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.3 Local-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.4 Backplane-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.5 Local-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.6 Port Data Rate Modes and Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.6.1 Local Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1.6.2 Backplane Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 Frame Pulse Input and Master Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Input Frame Pulse and Generated Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 Input Clock Jitter Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.0 Input and Output Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Input Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.1 Input Bit Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Output Advancement Programming (Backplane and Local Output Streams) . . . . . . . . . . . . . . . . . . . . . . 24
4.0 Port High Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.0 Device Power-Up, Initialization and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.0 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 Local Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 Backplane Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.3.1 Memory Block Programming Procedure: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2.2.3 The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12.0 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13.0 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Table of Contents
13.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.3 Local Input Bit Delay Registers (LIDR0 to LIDR31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.3.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.5 Local Output Advancement Registers (LOAR0 to LOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.6 Backplane Output Advancement Registers (BOAR0 - BOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13.8 Bit Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.9 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
List of Figures
Figure 1 - ZL50051/3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50053 LQFP Connections (256 LQFP, 28 mm x 28 mm) Pin Diagram
(as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3 - ZL50051 PBGA Connections (256 PBGA, 17 mm x 17 mm) Pin Diagram
(as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4 - 8,192 x 8,192 Channels (8 Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 - 4,096 x 4,096 Channels (8 Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6 - 6,144 x 2,048 Channels (8 Mbps) Blocking Bi-directional Configuration. . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8 - Input and Output Frame Pulse Alignment for Different Data Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps . . . . . . . . . . . . . . . . . 23
Figure 10 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of
8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16 Mbps . . . . . . . . . . . 25
Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13 - Data Throughput Delay with Input Ch0 Switched to Output Ch13. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14 - Data Throughput Delay with Input Ch13 Switched to Output Ch0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15 - Hardware RESET De-assertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16 - Frame Boundary Conditions, ST-BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 17 - Frame Boundary Conditions, GCI-Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 18 - Input and Output Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 19 - Input and Output Clock Timing Diagram for GCI-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 20 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 21 - ST-BUS Local/Backplane Data Timing Diagram (16 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 22 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 23 - GCI-Bus Local/Backplane Data Timing Diagram (16 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 24 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 25 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 26 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 27 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
List of Tables
Table 1 - Local and Backplane Output Enable Control Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2 - Variable Range for Input Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3 - Variable Range for Output Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 5 - Local Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6 - Backplane Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 4 - Local and Backplane Connection Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7 - Address Map for Data and Connection Memory Locations (A14 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8 - Local Data Memory (LDM) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9 - Backplane Data Memory (BDM) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10 - LCM Bits for Source-to-Local Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11 - BCM Bits for Source-to-Backplane Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12 - Address Map for Registers (A14 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13 - Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14 - Block Programming Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15 - Local Input Bit Delay Register (LIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 16 - Local Input Bit Delay and Sampling Point Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17 - Backplane Input Bit Delay Register (BIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 18 - Backplane Input Bit Delay and Sampling Point Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 19 - Local Output Advancement Register (LOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 20 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 21 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 22 - Backplane Output Advancement (BOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 23 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 24 - Bit Rate Register (BRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 25 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7
Zarlink Semiconductor Inc.
ZL50051/3
BSTo9
BSTo8
GND
VDD_IO
BSTo6
BST07
BSTo4
BST05
BSTo2
BSTo3
BSTo0
BSTo1
A1
A0
A3
A2
VDD_CORE
GND
GND
VDD_IO
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
IC_GND
IC_GND
IC_GND
IC_GND
DS
VDD_CORE
GND
GND
VDD_IO
R/W
CS
DTA
ODE
RESET
TMS
TDO
TDI
TRST
TCK
IC_OPEN
IC_OPEN
IC_OPEN
IC_OPEN
IC_OPEN
IC_OPEN
GND
VDD_CORE
VDD_IO
GND
IC_OPEN
IC_OPEN
LSTo0
LSTo1
Data Sheet
190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132
128
194
126
196
124
198
122
200
120
202
118
204
116
206
114
208
112
210
110
212
108
214
106
216
104
218
102
220
222
256 PIN LQFP
224
(TOP VIEW)
100
98
96
226
94
228
92
230
90
232
88
234
86
236
84
238
82
240
80
242
78
244
76
246
74
248
72
250
70
252
68
254
66
256
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30 32
34
36
38
40
42
44
46
48
50
52
54
56
58 60
62
LSTo2
LSTo3
LSTo4
LSTo5
VDD_CORE
GND
GND
LSTo6
VDD_IO
LSTo8
LSTo7
LSTo10
LSTo9
LSTo12
LSTo11
LSTo13
VDD_CORE
GND
GND
VDD_IO
LSTo14
LSTo15
LSTo16
LSTo17
LSTo18
LSTo19
LSTo20
LSTo21
GND
VDD_IO
LSTo22
LSTo23
LSTo24
LSTo25
LSTo26
LSTo27
LSTo28
LSTo29
VDD_CORE
GND
GND
VDD_IO
LSTo30
LSTo31
LORS
LSTi0
LSTi2
LSTi1
LSTi4
LSTi3
LSTi6
LSTi5
LSTi8
LSTi7
LSTi10
LSTi9
LSTi12
LSTi11
GND
VDD_CORE
GND
VDD_IO
LSTi13
LSTi14
64
BSTi25
BSTi26
BSTi27
BSTI28
BSTI30
BSTi29
VDD_IO
BSTi31
GND
GND
D15
VDD_CORE
D13
D14
D11
D12
D10
D9
D8
VDD_IO
GND
GND
VDD_CORE
D7
D6
D5
D4
D3
D2
D1
D0
IC_GND
IC_GND
VDD_IO
GND
VDD_CORE
C8i
GND
VDD_PLL
GND
C8o
FP8o
FP8i
LSTi31
LSTi30
LSTi29
GND
VDD_IO
VDD_CORE
GND
LSTi27
LSTi28
LSTi25
LSTi26
LSTi23
LSTi24
LSTi21
LSTi22
LSTi19
LSTi20
LSTi18
LSTi17
LSTi16
LSTi15
BST010
BSTo11
BSTo12
BSTo14
BSTo13
VDD_IO
BSTo15
GND
GND
VDD_CORE
BSTo16
BSTo18
BSTo17
BSTo20
BSTo19
BSTo22
BSTo21
BSTo23
VDD_IO
GND
GND
VDD_CORE
BSTo24
BSTo25
BSTo26
BSTo27
BSTo28
BSTo29
BSTo30
BSTo31
BORS
VDD_IO
GND
GND
VDD_CORE
BSTi0
BSTi1
BSTi2
BSTi3
BSTi4
BSTi5
BSTi6
BSTi7
BSTi8
BSTi10
BSTi9
BSTi12
BSTi11
BSTi14
BSTi13
VDD_IO
BSTi15
GND
GND
VDD_CORE
BSTi16
BSTi18
BSTi17
BSTi20
BSTi19
BSTi22
BSTi21
BSTi23
BSTi24
Figure 2 - ZL50053 LQFP Connections (256 LQFP, 28 mm x 28 mm) Pin Diagram
(as viewed through top of package)
8
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Pinout Diagram: (as viewed through top of package)
A1 corner identified by metallized marking
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
A0
A1
A2
A3
A4
DS
R/W
CS
IC_
OPEN
IC_
OPEN
IC_
OPEN
IC_
OPEN
IC_
OPEN
IC_
OPEN
IC_
OPEN
IC_
OPEN
B
BSTo0
BSTo1
BSTo2
BSTo3
A5
A6
A7
A8
A9
ODE
RESET
TMS
LSTo0
LSTo1
LSTo2
LSTo3
C
BSTo4
BSTo5
BSTo6
BSTo7
A10
A11
A12
A13
A14
DTA
TDi
TDo
LSTo4
LSTo5
LSTo6
LSTo7
D
BSTo8
BSTo9
BSTo10 BSTo11
TCK
TRST
LORS
LSTo8
LSTo9
LSTo10
LSTo11
E
BSTo12 BSTo13 BSTo14 BSTo15 VDD_IO VDD_IO
F
BSTo16 BSTo17 BSTo18 BSTo19 VDD_IO
G
BORS
IC_GND IC_GND IC_GND IC_GND
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_IO VDD_IO LSTo12 LSTo13 LSTo14 LSTo15
VDD_
CORE
GND
GND
GND
GND
VDD_
CORE
VDD_IO LSTo16 LSTo17 LSTo18 LSTo19
BSTo20 BSTo21 BSTo22 BSTo23 VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO LSTo20 LSTo21 LSTo22 LSTo23
H
BSTo24 BSTo25 BSTo26 BSTo27 VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO LSTo24
J
BSTo28 BSTo29 BSTo30 BSTo31
VDD_
CORE
GND
GND
GND
GND
GND
GND
VDD_
CORE
LST25
LSTo26 LSTo27
LSTo28 LSTo29 LSTo30 LSTo31
K
BSTi0
BSTi1
BSTi2
BSTi3
VDD_
CORE
GND
GND
GND
GND
GND
GND
VDD_
CORE
LSTi0
LSTi1
LSTi2
LSTi3
L
BSTi4
BSTi5
BSTi6
BSTi7
VDD_IO
VDD_
CORE
VDD_
CORE
GND
GND
VDD_
CORE
VDD_
CORE
VDD_IO
LSTi4
LSTi5
LSTi6
LSTi7
M
BSTi8
BSTi9
BSTi10
BSTi11 VDD_IO
D3
D2
D1
D0
VDD_
PLL
NC
VDD_IO
LSTi8
LSTi9
LSTi10
LSTi11
N
BSTi12
BSTi13
BSTi14
BSTi15
BSTi16
D7
D6
D5
D4
IC_
OPEN
IC_
OPEN
LSTi12
LSTi13
LSTi14
LSTi15
LSTi16
P
BSTi17
BSTi18
BSTi19
BSTi20
BSTi21
D11
D10
D9
D8
C16o
FP16o
LSTi17
LSTi18
LSTi19
LSTi20
LSTi21
R
BSTi22
BSTi23
BSTi24
BSTi25
BSTi26
D15
D14
D13
D12
FP8o
FP8i
LSTi22
LSTi23
LSTi24
LSTi25
LSTi26
T
BSTi27
BSTi28
BSTi29
BSTi30
BSTi31 IC_GND IC_GND IC_GND IC_GND
C8i
C8o
LSTi27
LSTi28
LSTi29
LSTi30
LSTi31
Figure 3 - ZL50051 PBGA Connections (256 PBGA, 17 mm x 17 mm) Pin Diagram
(as viewed through top of package)
9
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Pin Description
ZL50053
Package
Coordinates
(256 pin
LQFP)
ZL50051
Package
Coordinates
(256 ball
PBGA)
C8i
37
T10
Master Clock (5 V Tolerant Schmitt-Triggered Input)
This pin accepts an 8.192 MHz clock. The internal frame
boundary is aligned with the clock falling or rising edge, as
controlled by the C8IPOL bit in the Control Register. Input data
on both the Backplane and Local sides (BSTi0-31 and
LSTi0-31) must be aligned to this clock and the accompanying
input frame pulse, FP8i.
FP8i
43
R11
Frame Pulse Input (5 V Tolerant Schmitt-Triggered Input)
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin accepts a 122 ns-wide
frame pulse. When the FPW bit is HIGH, this pin accepts a
244 ns-wide frame pulse. The device will automatically detect
whether an ST-BUS or GCI-Bus style frame pulse is applied.
Input data on both the Backplane and Local sides (BSTi0-31
and LSTi0-31) must be aligned to this frame pulse and the
accompanying input clock, C8i.
C8o
41
T11
C8o Output Clock (5 V Tolerant Three-state Output)
This pin outputs an 8.192 MHz clock generated within the
device. The clock falling edge or rising edge is aligned with the
output frame boundary presented on FP8o; this edge polarity
alignment is controlled by the COPOL bit of the Control
Register. Output data on both the Backplane and Local sides
(BSTo0-31 and LSTo0-31) will be aligned to this clock and the
accompanying output frame pulse, FP8o.
FP8o
42
R10
Frame Pulse Output (5 V Tolerant Three-state Output)
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin outputs a 122 ns-wide
frame pulse. When the FPW bit is HIGH, this pin outputs a
244 ns-wide frame pulse. The frame pulse, running at 8 kHz
rate, will have the same format (ST-BUS or GCI-Bus) as the
input frame pulse (FP8i). Output data on both the Backplane
and Local sides (BSTo0-31 and LSTo0-31) will be aligned to
this frame pulse and the accompanying output clock, C8o.
C16o
NA
P10
C16o Output Clock (5 V Tolerant Three-state Output)
This pin outputs a 16.384 MHz clock generated within the
device. The clock falling edge or rising edge is aligned with the
output frame boundary presented on FP16o; this edge polarity
alignment is controlled by the COPOL bit of the Control
Register. Output data on both the Backplane and Local sides
(BSTo0-31 and LSTo0-31) will be aligned to this clock and the
accompanying output frame pulse, FP16o.
Pin Name
Description
Device Timing
10
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Pin Description (continued)
Pin Name
ZL50053
Package
Coordinates
(256 pin
LQFP)
ZL50051
Package
Coordinates
(256 ball
PBGA)
FP16o
NA
P11
Frame Pulse Output (5 V Tolerant Three-state Output)
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin outputs a 61 ns-wide frame
pulse. When the FPW bit is HIGH, this pin outputs a
122 ns-wide frame pulse. The frame pulse, running at 8 kHz
rate, will have the same format (ST-BUS or GCI-Bus) as the
input frame pulse (FP8i). Output data on both the Backplane
and Local sides (BSTo0-31 and LSTo0-31) will be aligned to
this frame pulse and the accompanying output clock, C16o.
228, 229,
230, 231,
232, 233,
234, 235,
236, 238,
237, 240,
239, 242,
241, 244
K1, K2, K3,
K4, L1, L2,
L3, L4, M1,
M2, M3, M4,
N1, N2, N3,
N4
Backplane Serial Input Streams 0 to 15 (5 V Tolerant Inputs with
Internal Pull-downs)
248, 250,
249, 252,
251, 254,
253, 255,
256, 1, 2, 3,
4, 6, 5, 8
N5, P1, P2,
P3, P4, P5,
R1, R2, R3,
R4, R5, T1,
T2, T3, T4, T5
Backplane Serial Input Streams 16 to 31 (5 V Tolerant Inputs with
Internal Pull-downs)
83, 81, 82,
79, 80, 77,
78, 75, 76,
73, 74, 71,
72, 66, 65, 64
K13, K14,
K15, K16,
L13, L14,
L15, L16,
M13, M14,
M15, M16,
N12, N13,
N14, N15
Local Serial Input Streams 0 to 15 (5 V Tolerant Inputs with
Internal Pull-downs)
63, 62, 61,
59, 60, 57,
58, 55, 56,
53, 54, 51,
52, 46, 45, 44
N16, P12,
P13, P14,
P15, P16,
R12, R13,
R14, R15,
R16, T12,
T13, T14,
T15, T16
Local Serial Input Streams 16 to 31 (5 V Tolerant Inputs with
Internal Pull-downs)
Description
Backplane and Local Inputs
BSTi0-15
BSTi16-31
LSTi0-15
LSTi16-31
These pins accept serial TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream), or 8.192 Mbps
(with 128 channels per stream).
These pins accept serial TDM data streams at a data rate of:
8.192 Mbps (with 128 channels per stream).
When the device operates at 16.384 Mbps, these pins are
unused and should be externally connected to a defined logic
level.
These pins accept serial TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream), or 8.192 Mbps
(with 128 channels per stream).
These pins accept serial TDM data streams at a data rate of:
8.192 Mbps (with 128 channels per stream).
When the device operates at 16.384 Mbps, these pins are
unused and should be externally connected to a defined logic
level.
11
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Pin Description (continued)
Pin Name
ZL50053
Package
Coordinates
(256 pin
LQFP)
ZL50051
Package
Coordinates
(256 ball
PBGA)
Description
Backplane and Local Outputs and Control
ODE
149
B10
Output Drive Enable (5 V Tolerant Input with Internal Pull-up)
An asynchronous input providing Output Enable control to the
BSTo0-31 and LSTo0-31 outputs.
When LOW, the BSTo0-31 and LSTo0-31 outputs are driven
HIGH or high impedance (dependent on the BORS and LORS
pin settings respectively).
When HIGH, the outputs BSTo0-31 and LSTo0-31 are
enabled.
BORS
223
D5
Backplane Output Reset State (5 V Tolerant Input with Internal
Pull-down)
When this input is LOW, the device will initialize with the
BSTo0-31 outputs driven high. Following initialization, the
Backplane stream outputs are always active.
When this input is HIGH, the device will initialize with the
BSTo0-31 outputs at high impedance. Following initialization,
the Backplane stream outputs may be set active or high
impedance using the ODE pin or on a per-channel basis with
the BE bit in the Backplane Connection Memory.
BSTo0-15
BSTo16-31
182, 181,
184, 183,
186, 185,
188, 187,
191, 192,
193, 194,
195, 197,
196, 199
B1, B2, B3,
B4, C1, C2,
C3, C4, D1,
D2, D3, D4,
E1, E2, E3,
E4
203, 205,
204, 207,
206, 209,
208, 210,
215, 216,
217, 218,
219, 220,
221, 222
F1, F2, F3,
F4, G1, G2,
G3, G4, H1,
H2, H3, H4,
J1, J2, J3, J4
Backplane Serial Output Streams 0 to 15 (5 V Tolerant,
Three-state Outputs with Slew-Rate Control)
These pins output serial TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream), or 8.192 Mbps
(with 128 channels per stream).
Refer to the descriptions of the BORS and ODE pins for
control of the output HIGH or high impedance state.
Backplane Serial Output Streams 16 to 31 (5 V Tolerant,
Three-state Outputs with Slew-Rate Control)
These pins output serial TDM data streams at a data rate of:
8.192 Mbps (with 128 channels per stream).
When the device operates at 16.384 Mbps, these pins are
unused, and therefore, the value output on these pins (either
driven-HIGH or high impedance) is dependent on the
configuration of the BORS pin.
Refer to the descriptions of the BORS and ODE pins for
control of the output HIGH or high impedance state.
12
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Pin Description (continued)
Pin Name
ZL50053
Package
Coordinates
(256 pin
LQFP)
ZL50051
Package
Coordinates
(256 ball
PBGA)
LORS
84
D12
Description
Local Output Reset State (5 V Tolerant Input with Internal
Pull-down)
When this input is LOW, the device will initialize with the
LSTo0-31 outputs driven high. Following initialization, the
Local stream outputs are always active.
When this input is HIGH, the device will initialize with the
LSTo0-31 outputs at high impedance. Following initialization,
the Local stream outputs may be set active or high impedance
using the ODE pin or on a per-channel basis with the LE bit in
the Local Connection Memory.
LSTo0-15
LSTo16-31
Local Serial Output Streams 0 to 15 (5 V Tolerant Three-state
Outputs with Slew-Rate Control)
130, 129,
128, 127,
126, 125,
121, 118, 119,
116, 117, 114,
115, 113, 108,
107
B13, B14,
B15, B16,
C13, C14,
C15, C16,
D13, D14,
D15, D16,
E13, E14,
E15, E16
106, 105,
104, 103,
102, 101, 98,
97, 96, 95,
94, 93, 92,
91, 86, 85
F13, F14,
F15, F16,
G13, G14,
G15, G16,
H13, H14,
H15, H16,
J13, J14, J15,
J16
These pins output serial TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream), or
8.192 Mbps (with 128 channels per stream).
Refer to the descriptions of the LORS and ODE pins for
control of the output HIGH or high impedance state.
Local Serial Output Streams 16 to 31 (5 V Tolerant Three-state
Outputs with Slew-Rate Control)
These pins output serial TDM data streams at a data rate of:
8.192 Mbps (with 128 channels per stream).
When the device operates at 16.384 Mbps, these pins are
unused, and therefore, the value output on these pins (either
driven-HIGH or high impedance) is dependent on the
configuration of the LORS pin.
Refer to the descriptions of the LORS and ODE pins for
control of the output HIGH or high impedance state.
Microprocessor Port Signals
A0 - A14
D0 - D15
179, 180,
177, 178,
172, 171,
170, 169,
168, 167,
166, 165,
164, 163, 162
A1, A2, A3,
A4, A5, B5,
B6, B7, B8,
B9, C5, C6,
C7, C8, C9
Address 0 - 14 (5 V Tolerant Inputs)
These pins form the 15-bit address bus to the internal
memories and registers.
31, 30, 29,
28, 27, 26,
25, 24, 19,
18, 17, 15,
16, 13, 14, 11
M9, M8, M7,
M6, N9, N8,
N7, N6, P9,
P8, P7, P6,
R9, R8, R7,
R6
Data Bus 0 - 15 (5 V Tolerant Inputs/Outputs with
Slew-Rate Control)
These pins form the 16-bit data bus of the microprocessor
port.
A0 = LSB
D0 = LSB
13
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Pin Description (continued)
Pin Name
ZL50053
Package
Coordinates
(256 pin
LQFP)
ZL50051
Package
Coordinates
(256 ball
PBGA)
CS
151
A8
Chip Select (5 V Tolerant Input)
Active LOW input used by the microprocessor to enable the
microprocessor port access. Note that a minimum of 30 ns
must separate the de-assertion of DTA (to high) and the
assertion of CS and/or DS to initiate the next access.
DS
157
A6
Data Strobe (5 V Tolerant Input)
This active LOW input works in conjunction with CS to enable
the microprocessor port read and write operations. Note that
a minimum of 30 ns must separate the de-assertion of
DTA (to high) and the assertion of CS and/or DS to initiate
the next access.
R/W
152
A7
Read/Write (5 V Tolerant Input)
This input controls the direction of the data bus lines (D0-D15)
during a microprocessor access.
DTA
150
C10
Data Transfer Acknowledgment (5 V Tolerant Three-state
Output)
This active LOW output indicates that a data bus transfer is
complete. A pull-up resistor is required to hold a HIGH level.
Note that a minimum of 30 ns must separate the
de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.
RESET
148
B11
Device Reset (5 V Tolerant Input with Internal Pull-up)
This input (active LOW) asynchronously applies reset and
synchronously releases reset to the device. In the reset state,
the outputs LSTo0-31 and BSTo0-31 are set to a HIGH or high
impedance state, depending on the state of the LORS and
BORS external control pins, respectively. The assertion of this
pin also clears the device registers and internal counters.
Refer to Section 7.3 on page 28 for the timing
requirements regarding this reset signal.
D10
Test Clock (5 V Tolerant Input)
Description
JTAG Control Signals
TCK
143
Provides the clock to the JTAG test logic.
TMS
147
B12
Test Mode Select (5 V Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP
controller.
TDi
145
C11
Test Serial Data In (5 V Tolerant Input with Internal Pull-up)
JTAG serial test instructions and data are shifted in on this pin.
TDo
146
C12
Test Serial Data Out (5 V Tolerant Three-state Output)
JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in a high impedance state when JTAG is
not enabled.
14
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Pin Description (continued)
Pin Name
ZL50053
Package
Coordinates
(256 pin
LQFP)
ZL50051
Package
Coordinates
(256 ball
PBGA)
TRST
144
D11
Description
Test Reset (5 V Tolerant Input with Internal Pull-up)
Asynchronously initializes the JTAG TAP controller to the
Test-Logic-Reset state. This pin must be pulsed LOW during
power-up for JTAG testing. This pin must be held LOW for
normal functional operation of the device.
Power and Ground Pins
VDD_IO
7, 20, 34, 48,
67, 87, 99,
109, 120,
134, 153,
173, 189,
198, 211,
224, 243
E5, E6, E11,
E12, F5, F12,
G5, G12, H5,
H12, L5, L12,
M5, M12
Power Supply for Periphery Circuits: +3.3 V
VDD_CORE
12, 23, 36,
49, 69, 90,
112, 124,
135, 156,
176, 202,
214, 227, 247
E7, E8, E9,
E10, F6, F11,
J5, J12, K5,
K12, L6, L7,
L10, L11
Power Supply for Core Circuits: +1.8 V
VDD_PLL
39
M10
VSS (GND)
9, 10, 21, 22,
35, 38, 40,
47, 50, 68,
70, 88, 89,
100, 110, 111,
122, 123,
133, 136,
154, 155,
174, 175,
190, 200,
201, 212,
213, 225,
226, 245, 246
F7, F8, F9,
F10, G6, G7,
G8, G9, G10,
G11, H6, H7,
H8, H9, H10,
H11, J6, J7,
J8, J9, J10,
J11, K6, K7,
K8, K9, K10,
K11, L8, L9
Power Supply for Analog PLL: +1.8 V
Ground
15
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Pin Description (continued)
Pin Name
ZL50053
Package
Coordinates
(256 pin
LQFP)
ZL50051
Package
Coordinates
(256 ball
PBGA)
Description
Unused Pins
NC
M11
No Connects
These pins are not used and can be tied HIGH, LOW, or left
unconnected.
IC_OPEN
131, 132,
137, 138,
139, 140,
141, 142
A9, A10, A11,
A12, A13,
A14, A15,
A16, N10,
N11
IC_GND
32, 33, 158,
159, 160, 161
D6, D7, D8,
D9, T6, T7,
T8, T9
Internal Connections - OPEN
These pins must be left unconnected.
Internal Connections - GND
These pins must be tied LOW.
16
Zarlink Semiconductor Inc.
ZL50051/3
1.0
Data Sheet
Unidirectional and Bi-directional Switching Applications
The ZL50051/3 has a maximum capacity of 8,192 input channels and 8,192 output channels. This can be
calculated from the two modes of operation:
1. 64 input streams (32 Backplane, 32 Local) at 8.192 Mbps (128 channels per stream), and 64 output streams (32
Backplane, 32 Local) at 8.192 Mbps (128 channels per stream)
2. 32 input streams (32 Backplane, 32 Local) at 16.384 Mbps (256 channels per stream), and 32 output streams
(32 Backplane, 32 Local) at 16.384 Mbps (256 channels per stream)
A typical mode of operation is to separate the input and output streams to form a unidirectional switch, as shown in
Figure 4 below.
BSTi0-31
BSTo0-31
32 streams
32 streams
INPUT
OUTPUT
LSTi0-31
32 streams
LSTo0-31
32 streams
ZL50051/3
Figure 4 - 8,192 x 8,192 Channels (8 Mbps), Unidirectional Switching
In this system, the Backplane and Local input streams are combined, and the Backplane and Local output streams
are combined, so that the switch appears as a 64 input stream by 64 output stream switch. This gives the maximum
8,192 x 8,192 channel capacity.
Often a system design needs to differentiate between a Backplane and a Local side, or it needs to put the switch in
a bi-directional configuration. In this case, the ZL50051/3 can be used as shown in Figure 5 to give 4,096 x 4,096
channel bi-directional capacity.
BSTi0-31
LSTo0-31
32 streams
32 streams
BACKPLANE
LOCAL
BSTo0-31
32 streams
LSTi0-31
32 streams
ZL50051/3
Figure 5 - 4,096 x 4,096 Channels (8 Mbps), Bi-directional Switching
In this system setup, the chip has a capacity of 4,096 input channels and 4,096 output channels on the Backplane
side, as well as 4,096 input channels and 4,096 output channels on the Local side. Note that some or all of the
output channels on one side can come from the other side, e.g., Backplane input to Local output switching.
17
Zarlink Semiconductor Inc.
ZL50051/3
1.1
Data Sheet
Flexible Configuration
The ZL50051/3 can be configured as a 8 K by 8 K non-blocking unidirectional digital switch, a 4 K by 4 K
non-blocking bi-directional digital switch, or as a blocking switch with various switching capacities.
1.1.1
Non-Blocking Unidirectional Configuration (Typical System Configuration)
Because the input and output drivers are synchronous, the user can combine input Backplane streams and input
Local streams as well as output Backplane streams and output Local streams to increase the total number of input
and output streams of the switch in a unidirectional configuration, as shown in Figure 4.
•
8,192 channel x 8,192 channel non-blocking switching from input to output streams
1.1.2
Non-Blocking Bi-directional Configuration
Another typical application is to configure the ZL50051/3 as a non-blocking 4 K by 4 K bi-directional switch, as
shown in Figure 5:
•
4,096 channel x 4,096 channel non-blocking switching from Backplane input to Local output streams
•
4,096 channel x 4,096 channel non-blocking switching from Local input to Backplane output streams
•
4,096 channel x 4,096 channel non-blocking switching from Backplane input to Backplane output streams
•
4,096 channel x 4,096 channel non-blocking switching from Local input to Local output streams
1.1.3
Blocking Bi-directional Configuration
The ZL50051/3 can be configured as a blocking bi-directional switch if it is an application requirement. For
example, it can be configured as a 6 K by 2 K bi-directional blocking switch, as shown in Figure 6:
•
6,144 channel x 2,048 channel blocking switching from Backplane input to Local output streams
•
2,048 channel x 6,144 channel blocking switching from Local input to Backplane output streams
•
6,144 channel x 6,144 channel non-blocking switching from Backplane input to Backplane output streams
•
2,048 channel x 2,048 channel non-blocking switching from Local input to Local output streams
ZL50051/3
BSTi0-31
6 K by 2 K
LSTi0-15
BSTo0-31
6K by 6K
LSTo0-15
LSTi16-31
2K by 2K
LSTo16-31
2 K by 6 K
Total 48 streams input and 48 streams output
Total 16 streams input and 16 streams output
Figure 6 - 6,144 x 2,048 Channels (8 Mbps) Blocking Bi-directional Configuration
18
Zarlink Semiconductor Inc.
ZL50051/3
2.0
Functional Description
2.1
Switching Configuration
Data Sheet
The device supports five switching configurations:
1. Unidirectional sSwitch
2. Backplane-to-Local
3. Local-to-Backplane
4. Backplane-to-Backplane
5. Local-to-Local
The following sections describe the switching paths in detail. Configurations (2) - (5) enable a non-blocking
bi-directional switch with 4,096 Backplane input/output channels and 4,096 Local input/output channels. The
switching paths of configurations (2) to (5) may be operated simultaneously.
2.1.1
Unidirectional Switch
The device can be configured as a 8,192 x 8,192 unidirectional switch by grouping together all input streams and all
output streams. All streams can be operated at a data rate of 16.384 Mbps or 8.192 Mbps.
2.1.2
Backplane-to-Local Path
The device can provide data switching between the Backplane input port and the Local output port. The Local
Connection Memory determines the switching configurations.
2.1.3
Local-to-Backplane Path
The device can provide data switching between the Local input port and the Backplane output port. The Backplane
Connection Memory determines the switching configurations.
2.1.4
Backplane-to-Backplane Path
The device can provide data switching between the Backplane input and output ports. The Backplane Connection
Memory determines the switching configurations.
2.1.5
Local-to-Local Path
The device can provide data switching between the Local input and output ports. The Local Connection Memory
determines the switching configurations.
2.1.6
Port Data Rate Modes and Selection
The Local port has 32 input (LSTi0-31) and 32 output (LSTo0-31) data streams. Similarly, the Backplane port has
32 input (BSTi0-31) and 32 output (BSTo0-31) data streams. The bit rate of all these streams is selected by writing
to the Bit Rate Registers, BRR (see Table 24). All the streams operate at the same bit rate at a time. The device can
operate at 8.192 or 16.384 Mbps. The default operation mode is 8.192 Mbps, in which all the input (LSTi0-31,
BSTi0-31) and output (LSTo0-31, BSTo0-31) streams are available. In 16.384 Mbps mode, only half of the streams
are available. LSTi16-31, BSTi16-31, LSTo16-31, and BSTo16-31 are not used. The timing of the input and output
clocks and frame pulses is shown in Figure 8, “Input and Output Frame Pulse Alignment for Different Data Rates”
on page 21. The input traffic are aligned based on the FP8i and C8i input timing signals, while the output traffic are
aligned based on the FP8o and C8o output timing signals.
19
Zarlink Semiconductor Inc.
ZL50051/3
2.1.6.1
Data Sheet
Local Output Port
Operation of stream data in Connection Mode or Message Mode is determined by the state of the LMM bit of the
Local Connection Memory. The channel high impedance state is controlled by the LE bit of the Local Connection
Memory. The data source (e.g., from the Local or Backplane Data Memory) is determined by the LSRC bit of the
Local Connection Memory. Refer to Section 8.1, “Local Connection Memory”, and Section 11.3, “Local Connection
Memory Bit Definition” for more details.
2.1.6.2
Backplane Output Port
Operation of stream data in Connection Mode or Message Mode is determined by the state of the BMM bit of the
Backplane Connection Memory and the channel high impedance state is controlled by the BE bit of the Backplane
Connection Memory. The data source (e.g., from the Local or Backplane Data Memory) is determined by the BSRC
bit of the Backplane Connection Memory. Refer to Section 8.2, “Backplane Connection Memory” and Section 11.4,
“Backplane Connection Memory Bit Definition” for more details.
2.2
Frame Pulse Input and Master Input Clock Timing
The input frame pulse (FP8i) is an 8 kHz input signal active for 122 ns or 244 ns at the frame boundary. The FPW
bit in the Control Register must be set according to the applied pulse width. See Pin Description and Table 13,
“Control Register Bits” on page 36 for details.
The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 7,
“ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates”. The ZL50051/3 device will automatically
detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The
output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame
pulse. The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL.
Note that the active edge of ST-BUS is falling edge, which is the default mode of the device, while GCI-Bus uses
rising edge as the active edge. Although GCI frame pulse will be automatically detected, to fully conform to
GCI-Bus operation, the device should be set to use C8i rising edge as the active edge (by setting bit C8IPOL HIGH)
when GCI-Bus is used.
For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS
frame pulse format with a single width frame pulse of 122 ns and a falling active clock-edge, unless explicitly stated
otherwise.
In addition, the ZL50051 device provides FP8o, FP16o, C8o and C16o outputs to support external devices which
connect to the output ports. The ZL50053 only provides FP8o and C8o outputs. The generated frame pulses (FP8o,
FP16o) will be provided in the same format as the master frame pulse (FP8i). The polarity of C8o and C16o, at the
frame boundary, can be controlled by the Control Register bit, COPOL. An analog phase lock loop (APLL) is used
to multiply the input clock frequency on C8i to generate an internal clock signal operating at 131.072 MHz.
20
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
FP8i (ST-BUS)
(8 kHz)
C8i (ST-BUS)
(8.192 MHz)
FP8i (GCI-Bus)
(8 kHz)
C8i (GCI-Bus)
(8.192 MHz)
Channel 0
BSTi/LSTi0-15
(16 Mbps) ST-BUS
1
0
7
6
5
Channel 255
3
4
2
1
0
6
5
Channel 0
BSTi/LSTi0-15
(16 Mbps) GCI-Bus
6
7
0
1
2
5
6
7
1
2
Channel 0
BSTi/LSTi0-31
(8 Mbps) ST-BUS
0
7
6
BSTi/LSTi0-31
(8 Mbps) GCI-Bus
7
0
1
3
2
1
0
7
5
6
7
0
Channel 255
4
3
4
3
4
Channel 127
5
4
3
2
3
4
2
1
0
7
7
0
Channel 127
Channel 0
5
6
Figure 7 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates
2.3
Input Frame Pulse and Generated Frame Pulse Alignment
The ZL50051 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are
aligned to the master frame pulse. The ZL50053 only generates one frame pulse output, FP8o. There is a constant
throughput delay for data being switched from the input to the output of the device such that data which is input
during Frame N is output during Frame N+2.
For further details of frame pulse conditions and options, see Section 13.1, “Control Register (CR)”, Figure 16,
“Frame Boundary Conditions, ST-BUS Operation”, and Figure 17, “Frame Boundary Conditions, GCI-Bus
Operation”.
FP8i
C8i
BSTi/LSTi0-31
(8 Mbps)
BSTi/LSTi0-15
(16 Mbps)
CH0
CH
0
CH1
CH
1
CH
2
CH2
CH
3
CH
4
CH3
CH
5
CH
6
CH4
CH
7
CH
8
CH5
CH
9
CH
10
CH6
CH
11
CH
12
CH7
CH
13
CH
14
CH9
CH8
CH
15
CH
16
CH
17
CH
18
CH10
CH
19
CH
20
CH11
CH
21
CH
22
CH
23
tFBOS
FP8o
C8o
BSTo/LSTo0-31
(8 Mbps)
BSTo/LSTo0-15
(16 Mbps)
CH0
CH
0
CH1
CH
1
CH
2
CH2
CH
3
CH
4
CH3
CH
5
CH
6
CH4
CH
7
CH
8
CH5
CH
9
CH
10
CH6
CH
11
CH
12
CH7
CH
13
CH
14
CH8
CH
15
CH
16
CH9
CH CH
17 18
CH
19
CH10
CH
20
CH CH
21 22
Figure 8 - Input and Output Frame Pulse Alignment for Different Data Rates
21
Zarlink Semiconductor Inc.
CH11
CH
23
ZL50051/3
Data Sheet
Figure 8 illustrates the input and output frame pulse alignment. The tFBOS is the offset between the input frame
pulse, FP8i, and the generated output frame pulse, FP8o. Refer to the “AC Electrical Characteristics”, on page 52.
Note that although this figure shows the traditional setups of the frame pulses and clocks for both ST-BUS and
GCI-Bus configurations, the devices can be configured to accept/generate double-width frame pulses (if the FPW
bit in the Control Register is set) as well as to use the opposite clock edge for frame-boundary determination (using
the C8IPOL and COPOL bits in the Control Register). See the timing diagrams in “AC Electrical Characteristics”, on
page 52 for all of the available configurations.
2.4
Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator
To improve the jitter tolerance of the ZL50051/3, a Frame Boundary Discriminator (FBD) circuit was added to the
device. This circuit is enabled by setting the Control Register bit FBDEN to HIGH. By default the FBD is disabled.
The FBD can operate in two modes, as controlled by the FBD_MODE[2:0] bits of the Control Register. When bits
FBD_MODE[2:0] are set to 000B, the FBD is set to handle lower frequency jitter only (<8 kHz). When bits
FBD_MODE[2:0] are set to 111B, the FBD can handle both low frequency and high frequency jitter. All other values
are reserved. These bits are ignored when bit FBDEN is LOW. It is strongly recommended that if bit FBDEN is set
HIGH, bits FBD_MODE[2:0] should be set to 111B to improve the high frequency jitter handling capability.
To achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be
optimized. In most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by
programming all the LIDR and BIDR registers). This will give more allowance for sampling point variations caused
by jitter. There are, however, some cases where data experiences more delay than the timing signals. A common
example occurs when multiple data lines are tied together to form bi-directional buses. The large bus loading may
cause data to be delayed. If this is the case, the optimum sampling point may be 3/4 or 4/4 instead of 1/2. The
optimum sampling point is dependent on the application. The user should optimize the sampling point to achieve
the best jitter tolerance performance.
2.5
Input Clock Jitter Tolerance
Input clock jitter tolerance depends on the data rate. In general, the higher the data rate, the smaller the jitter
tolerance is, because the period of a bit cell is shorter, and the sampling point variation allowance is smaller.
Jitter tolerance can not be accurately represented by just one number. Jitter of the same amplitude but different
frequency spectrum can have different effect on the operation of a device. For example, a device that can tolerate
20 ns of jitter of 10 kHz frequency may only be able to tolerate 10 ns of jitter of 1 MHz frequency. Therefore, jitter
tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the
carrier frequency. In the case of the ZL50051/3, the input clock is 8.192 MHz, and the jitter associated with this
clock can have the highest frequency component at 4.096 MHz.
For the above reasons, jitter tolerance of the ZL50051/3 has been characterized at 16.384 Mbps. The lower data
rate (8.192 Mbps) will have the same or better tolerance than that of the 16.384 Mbps operation. Tolerance of jitter
of different frequencies are shown in the “AC Electrical Characteristics” section, table “Input Clock Jitter Tolerance”
on page 61. The Jitter Tolerance Improvement Circuit was enabled (Control Register, bit FBDEN set HIGH, and bits
FBD_MODE[2:0] set to 111B), and the sampling point was optimized.
3.0
Input and Output Offset Programming
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.
3.1
Input Offsets
Control of the Input Bit Delay allows each input stream to have a different frame boundary with respect to the
master frame pulse, FP8i. Each input stream can be individually delayed by up to 7 3/4 bits with a resolution of 1/4
bit of the bit period.
22
Zarlink Semiconductor Inc.
ZL50051/3
3.1.1
Data Sheet
Input Bit Delay Programming (Backplane and Local Input Streams)
Input Bit Delay Registers LIDR0-31 and BIDR0-31 work in conjunction with the SMPL_MODE bit in the Control
Register to allow users to control input bit fractional delay as well as input bit sample point selection for greater
flexibility when designing switch matrices for high speed operation.
When SMPL_MODE = LOW (input bit fractional delay mode), bits LID[4:0] and BID[4:0] in the LIDR0-31 and
BIDR0-31 registers respectively define the input bit fractional delay of the corresponding Local and Backplane
stream. The total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. When
SMPL_MODE = HIGH (sampling point select mode), bits LID[1:0] and BID[1:0] define the input bit sampling point of
the stream. The sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance
for input jitter. Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a
resolution of 1 bit.
Refer to Figure 9 and Figure 10 for Input Bit Delay Timing at 16 Mbps and 8 Mbps data rates, respectively.
Refer to Figure 10 for Input Sampling Point Selection Timing at 8 Mbps data rates.
SMPL_MODE = LOW
FP8i
C8i
Ch255
BSTi/LSTi0-15
Bit Delay = 0
(Default)
3
2
Ch0
1
7
0
6
5
Ch1
4
3
2
1
0
7
6
5
4
Bit Delay, 1/4
BSTi/LSTi0-15
Bit Delay = 1/4
Ch255
3
Ch0
2
1
7
0
6
5
Ch1
4
3
2
1
0
7
6
5
4
Bit Delay, 1/2
BSTi/LSTi0-15
Bit Delay = 1/2
Ch255
3
Ch0
2
1
7
0
6
5
Ch1
4
3
2
1
0
7
6
5
4
Bit Delay, 3/4
BSTi/LSTi0-15
Bit Delay = 3/4
Ch255
3
Ch0
2
1
7
0
6
5
Ch1
4
3
2
1
0
7
6
5
4
Bit Delay, 1
BSTi/LSTi0-15
Bit Delay = 1
BSTi/LSTi0-15
Bit Delay = 7 1/2
BSTi/LSTi0-15
Bit Delay = 7 3/4
3
2
1
7
0
6
Ch254
2
5
4
3
2
1
0
7
0
6
5
4
Ch254
3
2
1
0
7
6
0
7
6
5
4
6
5
5
4
Bit Delay, 7 3/4
Ch0
Ch255
1
7
Bit Delay, 7 1/2
Ch0
Ch255
1
2
Ch1
Ch0
Ch255
3
2
1
0
7
6
5
4
Please refer to Control Register (Section 13.1) for SMPL_MODE definition.
Figure 9 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps
23
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
SMPL_MODE = LOW
FP8i
C8i
Ch127
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00000B
Bit delay = 0 bit (Default)
Ch0
0
1
6
7
5
3
4
2
sample at 3/4 point
Ch127
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00011B
Bit Delay = 3/4 bit
Ch0
0
1
6
7
5
3
4
2
sample at 3/4 point
SMPL_MODE = HIGH
FP8i
C8i
Ch127
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00000B
3/4 sampling (Default)
Ch0
0
1
6
7
5
4
3
2
5
4
3
2
sample at 3/4 point
Ch127
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00011B
2/4 sampling
1
Ch0
0
6
7
sample at 2/4 point
Please refer to Control Register (Section 13.1) for SMPL_MODE definition.
Figure 10 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for
Data Rate of 8 Mbps
3.2
Output Advancement Programming (Backplane and Local Output Streams)
This feature is used to advance the output channel alignment of individual Local or Backplane output streams with
respect to the frame boundary FP8o. Each output stream has its own advancement value that can be programmed
by the Output Advancement Registers. The output advancement selection is useful in compensating for various
parasitic loading on the serial data output pins.
The Local and Backplane Output Advancement Registers, LOAR0 - LOAR31 and BOAR0 - BOAR31, are used to
control the Local and Backplane output advancement respectively. The advancement is determined with reference
to the internal system clock rate (131.072 MHz). The advancement can be 0, -2 cycles, -4 cycles or -6 cycles, which
converts to approximately 0 ns, -15 ns, -31 ns or -46 ns as shown in Figure 11.
24
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
FP8o
System Clock
131.072 MHz
Bit Advancement, 0
Ch255
BSTo/LSTo0-15
Bit Advancement = 0
(Default)
Bit 1
Bit 0
Bit 7
Bit 1
Bit 0
Bit 5
Ch0
Bit 6
Bit Advancement, -6
Bit 0
Bit 1
Bit 6
Bit 7
Ch255
BSTo/LSTo0-15
Bit Advancement = -6
Ch0
Bit 7
Bit 0
Bit 1
Bit 5
Bit Advancement, -4
Ch255
BSTo/LSTo0-15
Bit Advancement = -4
Bit 6
Bit Advancement, -2
Ch255
BSTo/LSTo0-15
Bit Advancement = -2
Ch0
Bit 7
Bit 4
Bit 5
Ch0
Bit 6
Bit 5
Bit 4
Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16 Mbps
4.0
Port High Impedance Control
The input pins, LORS and BORS, select whether the Local (LSTo0-31) and Backplane (BSTo0-31) output streams,
respectively, are set to high impedance at the output of the device itself, or are always driven (active HIGH or active
LOW).
Setting LORS/BORS to a LOW state will configure the output streams, LSTo0-31/BSTo0-31, to transmit bi-state
channel data.
Setting LORS/BORS to a HIGH state will configure the output streams, LSTo0-31/BSTo0-31, of the device to
invoke a high impedance output on a per-channel basis. The Local/Backplane Output Enable Bit (LE/BE) of the
Local/Backplane Connection Memory has direct per-channel control on the high impedance state of the
Local/Backplane output streams, L/BSTo0-31. Programming a LOW state in the connection memory LE/BE bit will
set the stream output of the device to high impedance for the duration of the channel period. See “Local Connection
Memory Bit Definition”, on page 33 and “Backplane Connection Memory Bit Definition”, on page 34 for
programming details.
The state of the LORS/BORS pin is detected and the device configured accordingly during a RESET operation,
e.g. following power-up. The LORS/BORS pin is an asynchronous input and is expected to be hard-wired for a
particular system application, although it may be driven under logic control if preferred.
The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE.
LE/BE
(Local /
LORS/BORS
Backplane
(input pin)
Connection
Memory bit)
RESET
(input pin)
ODE
(input pin)
OSB
(Control
Register bit)
0
X
X
X
0
HIGH
0
X
X
X
1
HI-Z
1
0
X
X
0
HIGH
1
0
X
X
1
HI-Z
1
1
0
X
0
HIGH
LSTo0-31/
BSTo0-31
Table 1 - Local and Backplane Output Enable Control Priority
25
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
LE/BE
(Local /
LORS/BORS
Backplane
(input pin)
Connection
Memory bit)
RESET
(input pin)
ODE
(input pin)
OSB
(Control
Register bit)
1
1
0
X
1
HI-Z
1
1
1
0
0
HIGH
1
1
1
0
1
HI-Z
1
1
1
1
X
ACTIVE
(HIGH or LOW)
LSTo0-31/
BSTo0-31
Table 1 - Local and Backplane Output Enable Control Priority (continued)
5.0
Data Delay Through the Switching Paths
Serial data which goes into the device is converted into parallel format and written to consecutive locations in the
data memory. Each data memory location corresponds to the input stream and channel number. Channels written
to any of the buffers during Frame N will be read out during Frame N+2. The input bit delay and output bit
advancement have no impact on the overall data throughput delay.
In the following paragraphs, the data throughput delay (T) is represented as a function of ST-BUS frames, input
channel number, (m), and output channel number (n). Table 2 describes the variable range for input streams and
Table 3 describes the variable range for output streams. The data throughput delay under various input channel
and output channel conditions can be summarized as:
T = 2 frames + (n - m)
Input Stream
Data Rate
Input Channel
Number (m)
8 Mbps
0 to 127
16 Mbps
0 to 255
Table 2 - Variable Range for Input Streams
Output Stream
Data Rate
Output Channel
Number (n)
8 Mbps
0 to 127
16 Mbps
0 to 255
Table 3 - Variable Range for Output Streams
The data throughput delay (T) is: T = 2 frames + (n - m). Assuming that m (input channel) and n (output channel)
are equal, we have the figure below, in which the delay between the input data being written and the output data
being read is exactly 2 frames.
26
Zarlink Semiconductor Inc.
ZL50051/3
Frame
Serial Input Data
Frame N
Frame N Data
Frame N+1
Frame N+2
Frame N+1Data
Frame N+3
Data Sheet
Frame N+4
Frame N+5
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
2 Frames + 0
Serial Output Data
Frame N-2 Data
Frame N-1 Data
Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch0
Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay
time between the input channel being written and the output channel being read exceeds 2 frames.
Frame
Serial Input Data
Frame N
Frame N Data
Frame N+1
Frame N+2
Frame N+1Data
Frame N+2 Data
Frame N+3
Frame N+4
Frame N+5
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
2 Frames + (n - m)
Serial Output Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Figure 13 - Data Throughput Delay with Input Ch0 Switched to Output Ch13
Assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time
between the input channel being written and the output channel being read is less than 2 frames.
Frame
Serial Input Data
Frame N
Frame N Data
Frame N+1
Frame N+2
Frame N+1Data
Frame N+2 Data
Frame N+3
Frame N+4
Frame N+5
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
2 Frames + (n - m)
Serial Output Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Figure 14 - Data Throughput Delay with Input Ch13 Switched to Output Ch0
27
Zarlink Semiconductor Inc.
ZL50051/3
6.0
Data Sheet
Microprocessor Port
The 8 K switch family supports non-multiplexed Motorola type microprocessor buses. The microprocessor port
consists of a 16-bit parallel data bus (D0-15), a 15-bit address bus (A0-14) and four control signals (CS, DS, R/W
and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data Memories,
and the Local Connection and Data Memories. Each memory has 4,096 locations. See Table 7, Address Map for
Data and Connection Memory Locations (A14 = 1), for the address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’, in the event of the switch not receiving a master clock, the microprocessor port shall
complete the DTA handshake when accessed, but any data read from the bus will be invalid.
7.0
Device Power-Up, Initialization and Reset
7.1
Power-Up Sequence
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3 V) to be established before the
power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8 V). The VDD_PLL and VDD_CORE supplies may be
powered-up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3 V.
All supplies may be powered-down simultaneously.
7.2
Initialization
Upon power-up, the device should be initialized by applying the following sequence:
1
Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller.
2
Set ODE pin to LOW. This sets the LSTo0-31 outputs to HIGH or high impedance, dependent on the
LORS input value, and sets the BSTo0-31 outputs to HIGH or high impedance, dependent on BORS
input value. Refer to Pin Description for details of the LORS and BORS pins.
3
Reset the device by asserting the RESET pin to zero for at least two cycles of the input clock, C8i. A
delay of an additional 250 µs must also be applied before the first microprocessor access is
performed following the de-assertion of the RESET pin; this delay is required for determination of the
input frame pulse format.
4
Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer
to Section 8.3, “Connection Memory Block Programming”.
5
Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will
not occur at the serial stream outputs.
7.3
Reset
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the device. It is
then synchronized to the internal clock. During the reset period, depending on the state of input pins LORS and
BORS, the output streams LSTo0-31 and BSTo0-31 are set to HIGH or high impedance, and all internal registers
and counters are reset to the default state.
The RESET pin must remain LOW for two input clock cycles (C8i) to guarantee a synchronized reset release. A
delay of an additional 250 µs must also be waited before the first microprocessor access is performed following
the de-assertion of the RESET pin; this delay is required for determination of the frame pulse format.
28
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
In addition, the reset signal must be de-asserted less than 12 µs after the frame boundary or more than 13 µs after
the frame boundary, as illustrated in Figure 15. This can be achieved, for example, by synchronizing the
de-assertion of the reset signal with the input frame pulse FP8i.
FP8i
RESET
(case 1)
RESET
(case 2)
12µs
RESET assertion
13µs
RESET de-assertion
De-assertion of RESET must not fall within this window
Figure 15 - Hardware RESET De-assertion
8.0
Connection Memory
The device includes two connection memories, the Local Connection Memory and the Backplane Connection
Memory.
8.1
Local Connection Memory
The Local Connection Memory (LCM) is a 16-bit wide memory with 4,096 memory locations to support the Local
output port. The most significant bit of each word, bit[15], selects the source stream from either the Backplane
(LSRC = LOW) or the Local (LSRC = HIGH) port and determines the Backplane-to-Local or Local-to-Local data
routing. Bits[14:13] select the control modes of the Local output streams, the per-channel Message Mode and the
per-channel high impedance output control modes. In Connection Mode (bit[14] = LOW), bits[12:0] select the
source stream and channel number as detailed in Table 4. In Message Mode (bit[14] = HIGH), bits[12:8] are unused
and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that
the output channel is not tri-stated.
8.2
Backplane Connection Memory
The Backplane Connection Memory (BCM) is a 16-bit wide memory with 4,096 memory locations to support the
Backplane output port. The most significant bit of each word, bit[15], selects the source stream from either the
Backplane (BSRC = HIGH) or the Local (BSRC = LOW) port and determines the Local-to-Backplane or
Backplane-to-Backplane data routing. Bit[14:13] select the control modes of the Backplane output streams, namely
the per-channel Message Mode and the per-channel high impedance output control mode. In Connection Mode
(bit[14] = LOW), bits[12:0] select the source stream and channel number as detailed in Table 4. In Message Mode
(bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be
HIGH for Message Mode to ensure that the output channel is not tri-stated.
The Control Register bits MS[2:0] must be set to 000 to select the Local Connection Memory for the write and read
operations via the microprocessor port. The Control Register bits MS[2:0] must be set to 001 to select the
Backplane Connection Memory for the write and read operations via the microprocessor port. See Section 6.0,
“Microprocessor Port”, and Section 13.1, “Control Register (CR)” for details on microprocessor port access.
29
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Source Stream Bit Rate
Source Stream No.
Source Channel No.
8 Mbps
Bits[12:8]
legal values 0:31
Bits[7:0]
legal values 0:127
16 Mbps
Bits[12:8]
legal values 0:15
Bits[7:0]
legal values 0:255
Table 4 - Local and Backplane Connection Memory Configuration
8.3
Connection Memory Block Programming
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after
power-up. When the Memory Block Programming mode is enabled, the contents of the Block Programming
Register (BPR) will be loaded into the connection memories. See Table 13 and Table 14 for details of the Control
Register and Block Programming Register values, respectively.
8.3.1
Memory Block Programming Procedure:
•
Set the MBP bit in the Control Register from LOW to HIGH.
•
Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection
Memory. The remaining bit positions are loaded with zeros as shown in Table 5.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBPD2
LBPD1
LBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5 - Local Connection Memory in Block Programming Mode
The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into
bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as
shown in Table 6.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BBPD2
BBPD1
BBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6 - Backplane Connection Memory in Block Programming Mode
The Block Programming Register bit, BPE will be automatically reset LOW within 125 µs, to indicate completion of
memory programming.
The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the
Block Programming Register or the MBP bit of the Control Register.
Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a
device reset, can be used.
During reset, all output channels go HIGH or high impedance, depending on the value of the LORS and BORS
pins, irrespective of the values in bits[14:13] of the connection memory.
30
Zarlink Semiconductor Inc.
ZL50051/3
9.0
Data Sheet
Memory Built-In-Self-Test (BIST) Mode
As operation of the memory BIST will corrupt existing data, this test must only be initiated when the device is placed
“out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (Section 13.7, “Memory BIST Register”).
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register.
10.0
JTAG Port
The ZL50051/3 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit
shall be controlled by an external Test Access Port (TAP) Controller.
10.1
Test Access Port (TAP)
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
•
Test Clock Input (TCK)
TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in
Boundary-Scan Mode.
•
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to VDD_IO when not
driven from an external source.
•
Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in
Section 10.2, “TAP Registers”. The applied input data is sampled at the rising edge of TCK pulses. This pin
is internally pulled to VDD_IO when not driven from an external source.
•
Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo output is
set to a high impedance state.
•
Test Reset (TRST)
TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when
not driven from an external source. This pin MUST be pulled low for normal operation.
10.2
TAP Registers
The ZL50051/3 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an
Instruction Register and three Test Data Registers.
10.2.1
Test Instruction Register
The JTAG interface contains a four bit instruction register. Instructions are serially loaded into the Instruction
Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to
achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to
define the serial Test Data Register path to shift data between TDi and TDo during data register scanning. Please
refer to Figure 27 for JTAG test port timing.
31
Zarlink Semiconductor Inc.
ZL50051/3
10.2.2
Data Sheet
Test Data Registers
10.2.2.1
The Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the
boundary of the ZL50051/3 core logic.
10.2.2.2
The Bypass Register
The Bypass register is a single stage shift register to provide a 1 bit path from TDi to TDo.
10.2.2.3
The Device Identification Register
The JTAG device ID for the ZL50051/3 is 0C38314BH.
Version, Bits <31:28>: 0000
Part No., Bits <27:12>: 1100 0011 1000 0011
Manufacturer ID, Bits <11:1>: 0001 0100 101
Header, Bit <0> (LSB): 1
10.3
Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
11.0
Memory Address Mappings
When the most significant bit, A14, of the address bus is set to ’1’, the microprocessor performs an access to one of
the device’s internal memories. The Control Register bits MS[2:0] indicate which memory (Local Connection, Local
Data, Backplane Connection, or Backplane Data) is being accessed. Address bits A0-A13 indicate which location
within the particular memory is being accessed.
Address Bit
A14
Description
Selects memory or register access (0 = register, 1 = memory)
Note that which memory (Local Connection, Local Data, Backplane Connection, Backplane
Data) is accessed depends on the MS[2:0] bits in the Control Register.
A13-A9
Stream address (0 - 31)
Streams 0 to 31 are used when serial stream is at 8.192 Mbps
Streams 0 to 15 are used when serial stream is at 16.384 Mbps
A8-A0
Channel address (0 - 511)
Channels 0 to 127 are used when serial stream is at 8.192 Mbps
Channels 0 to 255 are used when serial stream is at 16.384 Mbps
Table 7 - Address Map for Data and Connection Memory Locations (A14 = 1)
The device contains two data memory blocks, one for received Backplane data and one for received Local data. For
all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored
sequentially in the relevant data memory.
32
Zarlink Semiconductor Inc.
ZL50051/3
11.1
Data Sheet
Local Data Memory Bit Definition
The 8-bit Local Data Memory (LDM) has 4,096 positions. The locations are associated with the Local input streams
and channels. As explained in the section above, address bits A13-A0 of the microprocessor define the addresses
of the streams and the channels. The LDM is read-only and configured as follows:
Bit
Name
15:8
Reserved
7:0
LDM
Description
Set to a default value of 8’h00.
Local Data Memory - Local Input Channel Data
The LDM[7:0] bits contain the timeslot data from the Local side input TDM
stream. LDM[7] corresponds to the first bit received, e.g., bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 7, “ST-BUS and GCI-Bus Input Timing
Diagram for Different Data Rates” for the arrival order of the bits.
Table 8 - Local Data Memory (LDM) Bits
Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.
11.2
Backplane Data Memory Bit Definition
The 8-bit Backplane Data Memory (BDM) has 4,096 positions. The locations are associated with the Backplane
input streams and channels. As explained previously, address bits A13-A0 of the microprocessor define the
addresses of the streams and the channels. The BDM is read-only and configured as follows:
Bit
Name
15:8
Reserved
7:0
BDM
Description
Set to a default value of 8’h00.
Backplane Data Memory - Backplane Input Channel Data.
The BDM[7:0] bits contain the timeslot data from the Backplane side input TDM
stream. BDM[7] corresponds to the first bit received, e.g., bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 7, “ST-BUS and GCI-Bus Input Timing
Diagram for Different Data Rates” for the arrival order of the bits
Table 9 - Backplane Data Memory (BDM) Bits
Note that the Backplane Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.
11.3
Local Connection Memory Bit Definition
The Local Connection Memory (LCM) has 4,096 addresses of 16-bit words. Each address, accessed through bits
A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit definition
for each 16-bit word is presented in Table 10 for Source-to-Local connections.
The most-significant bit in the memory location, LSRC, selects the switch configuration for Backplane-to-Local or
Local-to-Local. When the per-channel Message Mode is selected (LMM memory bit = HIGH), the lower byte of the
LCM word (LCAB[7:0]) will be transmitted as data on the output stream (LSTo0-31) in place of data defined by the
Source Control, Stream and Channel Address bits.
33
Zarlink Semiconductor Inc.
ZL50051/3
Bit
Name
15
LSRC
Data Sheet
Description
Local Source Control Bit
When LOW, the source is from the Backplane input port (Backplane Data Memory).
When HIGH, the source is from the Local input port (Local Data Memory).
Ignored when LMM is set HIGH.
14
LMM
Local Message Mode Bit
When LOW, the channel is in Connection Mode (data to be output on channel originated in
Local or Backplane Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Local Connection Memory).
13
LE
Local Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the LORS pin.
When HIGH, the channel is active.
12:8
LSAB[4:0]
Source Stream Address Bits
The binary value of these 5 bits represents the input stream number.
Ignored when LMM is set HIGH.
7:0
LCAB[7:0]
Source Channel Address Bits / Message Mode Data
The binary value of these 8 bits represents the input channel number when LMM is set
LOW.
Transmitted as data when LMM is set HIGH.
Note: When LMM is set HIGH, in both ST-BUS and GCI-Bus modes, the LCAB[7:0] bits are
output sequentially to the timeslot with LCAB[7] being output first.
Table 10 - LCM Bits for Source-to-Local Switching
11.4
Backplane Connection Memory Bit Definition
The Backplane Connection Memory (BCM) has 4,096 addresses of 16-bit words. Each address, accessed through
bits A13-A0 of the microprocessor port, is allocated to an individual Backplane output stream and channel. The bit
definition for each 16-bit word is presented in Table 11 for Source-to-Backplane connections.
The most-significant bit in the memory location, BSRC, selects the switch configuration for Local-to-Backplane or
Backplane-to-Backplane. When the per-channel Message Mode is selected (BMM memory bit = HIGH), the lower
byte of the BCM word (BCAB[7:0]) will be transmitted as data on the output stream (BSTo0-31) in place of data
defined by the Source Control, Stream and Channel Address bits.
Bit
Name
15
BSRC
Description
Backplane Source Control Bit
When LOW, the source is from the Local input port (Local Data Memory).
When HIGH, the source is from the Backplane input port (Backplane Data Memory).
Ignored when BMM is set HIGH.
14
BMM
Backplane Message Mode Bit
When LOW, the channel is in Connection Mode (data to be output on channel originated in
Backplane or Local Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Backplane Connection Memory).
Table 11 - BCM Bits for Source-to-Backplane Switching
34
Zarlink Semiconductor Inc.
ZL50051/3
Bit
Name
13
BE
Data Sheet
Description
Backplane Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the BORS pin.
When HIGH, the channel is active.
12:8
BSAB[4:0]
Source Stream Address Bits
The binary value of these 5 bits represents the input stream number.
Ignored when BMM is set HIGH.
7:0
BCAB[7:0]
Source Channel Address Bits / Message Mode Data
The binary value of these 8 bits represents the input channel number when BMM is set
LOW.
Transmitted as data when BMM is set HIGH.
Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits
are output sequentially to the timeslot with BCAB[7] being output first.
Table 11 - BCM Bits for Source-to-Backplane Switching (continued)
12.0
Internal Register Mappings
When the most significant bit, A14, of the address bus is set to ’0’, the microprocessor is performing an access to
one of the device’s internal registers. Address bits A13-A0 indicate which particular register is being accessed.
A14-A0
Register
0000H
Control Register, CR
0001H
Block Programming Register, BPR
0023H - 0042H
Local Input Bit Delay Register 0 - 31, LIDR0 - 31
0063H - 0082H
Backplane Input Bit Delay Register 0 - 31, BIDR0 - 31
0083H - 00A2H
Local Output Advancement Register 0 - 31, LOAR0 - 31
00A3H - 00C2H
Backplane Output Advancement Register 0 - 31, BOAR0 - 31
014DH
Memory BIST Register, MBISTR
1001H
Bit Rate Register, BRR
3FFFH
Device Identification Register, DIR
Table 12 - Address Map for Registers (A14 = 0)
35
Zarlink Semiconductor Inc.
ZL50051/3
13.0
Data Sheet
Detailed Register Descriptions
This section describes the registers that are used in the device.
13.1
Control Register (CR)
Address 0000H.
The Control Register defines which memory is to be accessed. It initiates the memory block programming mode
and selects the Backplane and Local data rate modes. The Control Register (CR) is configured as follows:
Reset
Value
Bit
Name
15:13
FBD_
MODE[2:0]
0
SMPL_
MODE
0
11
Reserved
0
10
FBDEN
0
9
Reserved
0
8
FPW
0
7
Reserved
0
6
C8IPOL
0
5
COPOL
0
12
Description
Frame Boundary Discriminator Mode
When set to 111B, the Frame Boundary Discriminator can handle both low
frequency and high frequency jitter.
When set to 000B, the Frame Boundary Discriminator is set to handle lower
frequency jitter only.
All other values are reserved.
These bits are ignored when FBDEN bit is LOW.
Sample Point Mode
When LOW the input bit sampling point is always at the 3/4 bit location. The input bit
fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value
of the LIDR0 to LIDR31 and BIDR0 to BIDR31 registers.
When HIGH, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit
location as per the value of the LIDR0 to LIDR31 and BIDR0 to BIDR31 registers. In
addition, the incoming data can be delayed by 0 to 7 bits in 1 bit increments.
See Table 15, Table 16, Table 17 and Table 18 for details.
Reserved
Must be set to 0 for normal operation
Frame Boundary Discriminator Enable
When LOW, the frame boundary discriminator function is disabled.
When HIGH, enables frame boundary discriminator function which allows the
device to tolerate inconsistent frame boundaries, hence improving the tolerance to
cycle-to-cycle variation on the input clock.
Reserved
Must be set to 0 for normal operation
Frame Pulse Width
When LOW, the user must apply a 122 ns frame pulse on FP8i; the FP8o pin will
output a 122 ns wide frame pulse; FP16o will output a 61 ns wide frame pulse.
When HIGH, the user must apply a 244 ns frame pulse on FP8i; the FP8o pin will
output a 244 ns wide frame pulse; FP16o will output a 122 ns wide frame pulse.
Reserved
Must be set to 0 for normal operation
8 MHz Input Clock Polarity
The frame boundary is aligned to the falling or rising edge of the input clock.
When LOW, the frame boundary is aligned to the clock falling edge.
When HIGH, the frame boundary is aligned to the clock rising edge.
Output Clock Polarity
When LOW, the output clock has the same polarity as the input clock.
When HIGH, the output clock is inverted.
This applies to both the 8 MHz (C8o) and 16 MHz (C16o) output clocks.
Table 13 - Control Register Bits
36
Zarlink Semiconductor Inc.
ZL50051/3
Bit
Name
Reset
Value
4
MBP
0
3
OSB
0
2
Reserved
0
1:0
MS[1:0]
0
Data Sheet
Description
Memory Block Programming
When LOW, the memory block programming mode is disabled.
When HIGH, the connection memory block programming mode is ready to program
the Local Connection Memory (LCM) and the Backplane Connection Memory
(BCM).
Output Stand By
This bit enables the BSTo0-31 and LSTo0-31 serial outputs.
ODE Pin
OSB bit
BSTo0-31, LSTo0-31
0
1
1
X
0
1
Disabled
Disabled
Enabled
Output Control with ODE pin and OSB bit
When LOW, BSTo0-31 and LSTo0-31 are driven HIGH or high impedance,
dependent on the BORS and LORS pin settings respectively.
When HIGH, BSTo0-31 and LSTo0-31 are enabled.
Reserved
Must be set to 0 for normal operation
Memory Select Bits
These three bits select the connection or data memory for subsequent microport
memory access operations:
00 selects Local Connection Memory (LCM) for read or write operations.
01 selects Backplane Connection Memory (BCM) for read or write operations.
10 selects Local Data Memory (LDM) for read-only operation.
11 selects Backplane Data Memory (BDM) for read-only operation.
Table 13 - Control Register Bits (continued)
37
Zarlink Semiconductor Inc.
ZL50051/3
Frame Boundary
(a) Frame Pulse Width = 122 ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 0
C8i
FP8i
(b) Frame Pulse Width = 122 ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
(c) Frame Pulse Width = 244 ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 0
C8i
FP8i
(d) Frame Pulse Width = 244 ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
Figure 16 - Frame Boundary Conditions, ST-BUS Operation
38
Zarlink Semiconductor Inc.
Data Sheet
ZL50051/3
Frame Boundary
(e) Pulse Width = 122 ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 0
C8i
FP8i
(f) Pulse Width = 122 ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
(g) Pulse Width = 244 ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 0
C8i
FP8i
(h) Pulse Width = 244 ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
Figure 17 - Frame Boundary Conditions, GCI-Bus Operation
39
Zarlink Semiconductor Inc.
Data Sheet
ZL50051/3
13.2
Data Sheet
Block Programming Register (BPR)
Address 0001H.
The Block Programming Register stores the bit patterns to be loaded into the connection memories when the
Memory Block Programming feature is enabled. The BPE, LBPD[2:0] and BBPD[2:0] bits in the BPR register must
be defined in the same write operation.
The BPE bit is set HIGH to commence the block programming operation. Programming is completed in one frame
period and may be initiated at any time within a frame. The BPE bit returns to LOW to indicate that the block
programming function has completed.
When BPE is HIGH, no other bits of the BPR register may be changed for at least a single frame period, except to
abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the
Control Register bit, MBP, to LOW.
The BPR register is configured as follows:
Bit
Name
Reset
Value
15:7
Reserved
0
Reserved
Must be set to 0 for normal operation
6:4
BBPD[2:0]
0
Backplane Block Programming Data
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated.
When the MBP bit in the Control Register (CR) is set HIGH and BPE (in this
register) is set HIGH, the contents of bits BBPD[2:0] are loaded into bits 15-13,
respectively, of the BCM. Bits 12-0 of the BCM are set LOW.
3:1
LBPD[2:0]
0
Local Block Programming Data
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated.
When the MBP bit in the Control Register is set HIGH and BPE (in this register)
is set HIGH, the contents of bits LBPD[2:0] are loaded into bits 15-13,
respectively, of the LCM. Bits 12-0 of the LCM are set LOW.
0
BPE
0
Block Programming Enable
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125 µs, upon completion of programming.
Set LOW to abort the programming operation.
Description
Table 14 - Block Programming Register Bits
40
Zarlink Semiconductor Inc.
ZL50051/3
13.3
Data Sheet
Local Input Bit Delay Registers (LIDR0 to LIDR31)
Addresses 0023H to 0042H.
There are thirty-two Local Input Bit Delay Registers (LIDR0 to LIDR31).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and LIDR0 to LIDR31 define the input bit and fractional bit delay of each Local stream. The possible bit
delay adjustment is up to 7 3/4 bits, in steps of 1/4 bit.
When the SMPL_MODE bit is HIGH, LIDR0 to LIDR31 define the input bit sampling point as well as the integer bit
delay of each Local stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be
adjusted in 1-bit increments from 0 to 7 bits.
The LIDR0 to LIDR31 registers are configured as follows:
Name
Reset
Value
15:5
Reserved
0
Reserved
Must be set to 0 for normal operation
4:0
LID[4:0]
0
Local Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 7 3/4).
When SMPL_MODE = HIGH, the binary value of LID[1:0]
refers to the input bit sampling point (1/4 to 4/4). LID[4:2]
refer to the integer bit delay value (0 to 7 bits).
LIDRn Bit
(where n = 0 to 31)
Description
Table 15 - Local Input Bit Delay Register (LIDRn) Bits
13.3.1
Local Input Delay Bits 4-0 (LID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7 3/4 bit periods forward, with resolution of 1/4 bit
period. The default sampling point is at the 3/4 bit location.
This can be described as: no. of bits delay = LID[4:0] / 4
For example, if LID[4:0] is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4.
When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (1/4 to 4/4). LID[4:2]
refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from 1/4 to 4/4 in 1/4-bit increments.
41
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Table 16 illustrates the bit delay and sampling point selection.
LIDn
SMPL_MODE
= LOW
Input Data
Bit Delay
Input Data
Sampling
Point
0 (Default)
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
LID4
LID3
LID2
LID1
LID0
Input Data
Bit Delay
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 (Default)
1/4
1/2
3/4
1
1 1/4
1 1/2
1 3/4
2
2 1/4
2 1/2
2 3/4
3
3 1/4
3 1/2
3 3/4
4
4 1/4
4 1/2
4 3/4
5
5 1/4
5 1/2
5 3/4
6
6 1/4
6 1/2
6 3/4
7
7 1/4
7 1/2
7 3/4
SMPL_MODE
= HIGH
Table 16 - Local Input Bit Delay and Sampling Point Programming Table
42
Zarlink Semiconductor Inc.
ZL50051/3
13.4
Data Sheet
Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
Addresses 0063H to 0082H
There are thirty-two Backplane Input Bit Delay Registers (BIDR0 to BIDR31).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and BIDR0 to BIDR31 define the input bit and fractional bit delay of each Backplane stream. The possible
bit delay adjustment is up to 7 3/4 bits, in steps of 1/4 bit.
When the SMPL_MODE bit is HIGH, BIDR0 to BIDR31 define the input bit sampling point as well as the integer bit
delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay
can be adjusted in 1-bit increments from 0 to 7 bits.
The BIDR0 to BIDR31 registers are configured as follows:
BIDRn Bit
(where n = 0 to 31)
Name
Reset
Value
15:5
Reserved
0
Reserved
Must be set to 0 for normal operation
4:0
BID[4:0]
0
Backplane Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 7 3/4).
When SMPL_MODE = HIGH, the binary value of BID[1:0]
refers to the input bit sampling point (1/4 to 4/4). BID[4:2]
refer to the integer bit delay value (0 to 7 bits).
Description
Table 17 - Backplane Input Bit Delay Register (BIDRn) Bits
13.4.1
Backplane Input Delay Bits 4-0 (BID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7 3/4 bit periods forward, with resolution of 1/4 bit
period. The default sampling point is at the 3/4 bit location.
This can be described as: no. of bits delay = BID[4:0] / 4
For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4.
When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (1/4 to 4/4). BID[4:2]
refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from 1/4 to 4/4 in 1/4-bit increments.
43
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Table 18 illustrates the bit delay and sampling point selection.
BIDn
SMPL_MODE
= LOW
Input Data
Bit Delay
Input Data
Sampling
Point
0 (Default)
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
BID4
BID3
BID2
BID1
BID0
Input Data
Bit Delay
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 (Default)
1/4
1/2
3/4
1
1 1/4
1 1/2
1 3/4
2
2 1/4
2 1/2
2 3/4
3
3 1/4
3 1/2
3 3/4
4
4 1/4
4 1/2
4 3/4
5
5 1/4
5 1/2
5 3/4
6
6 1/4
6 1/2
6 3/4
7
7 1/4
7 1/2
7 3/4
SMPL_MODE
= HIGH
Table 18 - Backplane Input Bit Delay and Sampling Point Programming Table
44
Zarlink Semiconductor Inc.
ZL50051/3
13.5
Data Sheet
Local Output Advancement Registers (LOAR0 to LOAR31)
Addresses 0083H to 00A2H.
Thirty-two Local Output Advancement Registers (LOAR0 to LOAR31) allow users to program the output
advancement for output data streams LSTo0 to LSTo31. The possible adjustment is -2 (15 ns), -4 (31 ns) or -6
(46 ns) cycles of the internal system clock (131.072 MHz).
The LOAR0 to LOAR31 registers are configured as follows:
LOARn Bit
(where n = 0 to 31)
Name
Reset
Value
15:2
Reserved
0
Reserved
Must be set to 0 for normal operation
1:0
LOA[1:0]
0
Local Output Advancement Value
Description
Table 19 - Local Output Advancement Register (LOAR) Bits
13.5.1
Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
Corresponding
Advancement Bits
Local Output Advancement
Clock Rate 131.072 MHz
LOA1
LOA0
0 (Default)
0
0
-2 cycles (~15 ns)
0
1
-4 cycles (~31 ns)
1
0
-6 cycles (~46 ns)
1
1
Table 20 - Local Output Advancement (LOAR) Programming Table
45
Zarlink Semiconductor Inc.
ZL50051/3
13.6
Data Sheet
Backplane Output Advancement Registers (BOAR0 - BOAR31)
Addresses 00A3H to 00C2H
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR31) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. The possible adjustment is -2 (15 ns), -4 (31 ns) or -6
(46 ns) cycles of the internal system clock (131.072 MHz).
The BOAR0 to BOAR31 registers are configured as follows:
Name
Reset
Value
15:2
Reserved
0
Reserved
Must be set to 0 for normal operation
1:0
BOA[1:0]
0
Backplane Output Advancement Value
BOARn Bit
(where n = 0 to 31)
Description
Table 21 - Backplane Output Advancement Register (BOAR) Bits
13.6.1
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
Backplane Output Advancement
Corresponding
Advancement Bits
Clock Rate 131.072 MHz
BOA1
BOA0
0 (Default)
0
0
-2 cycles (~15 ns)
0
1
-4 cycles (~31 ns)
1
0
-6 cycles (~46 ns)
1
1
Table 22 - Backplane Output Advancement (BOAR) Programming Table
46
Zarlink Semiconductor Inc.
ZL50051/3
13.7
Data Sheet
Memory BIST Register
Address 014DH.
The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to
start MBIST: the first with only Bit 12 (LV_TM) set HIGH (i.e. 1000h); the second with Bit 12 maintained HIGH but
with the required start bit(s) also set HIGH.
The MBISTR register is configured as follows:
Bit
Name
Reset
Value
15:13
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
12
LV_TM
0
MBIST Test Enable
Set HIGH to enable MBIST mode.
Set LOW for normal operation.
11
BISTSDB
0
Backplane Data Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
10
BISTCDB
0
Backplane Data Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Backplane Data
Memory BIST sequence.
9
BISTPDB
0
Backplane Data Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Backplane
Data Memory BIST sequence (indicated by assertion of BISTCDB).
A HIGH indicates Pass, a LOW indicates Fail.
8
BISTSDL
0
Local Data Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
7
BISTCDL
0
Local Data Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Local Data
Memory BIST sequence.
6
BISTPDL
0
Local Data Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Local Data
Memory BIST sequence (indicated by assertion of BISTCDL).
A HIGH indicates Pass, a LOW indicates Fail.
5
BISTSCB
0
Backplane Connection Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
4
BISTCCB
0
Backplane Connection Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Backplane
Connection Memory BIST sequence.
3
BISTPCB
0
Backplane Connection Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Backplane
Connection Memory BIST sequence (indicated by assertion of BISTCCB).
A HIGH indicates Pass, a LOW indicates Fail.
2
BISTSCL
0
Local Connection Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
Table 23 - Memory BIST Register (MBISTR) Bits
47
Zarlink Semiconductor Inc.
ZL50051/3
Bit
Name
Reset
Value
1
BISTCCL
0
Data Sheet
Description
Local Connection Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Local Connection
Memory BIST sequence.
0
BISTPCL
0
Local Connection Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Local
Connection Memory BIST sequence (indicated by assertion of BISTCCL).
A HIGH indicates Pass, a LOW indicates Fail.
Table 23 - Memory BIST Register (MBISTR) Bits (continued)
13.8
Bit Rate Register
Address 1001H
This register allows the bit rate of all the input and output streams to be set to 8.192 or 16.384 Mbps.
The BRR register is configured as follows:
Bit
Name
Reset
Value
15:1
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
0
Reserved
0
Bit Rate Selector
This bit defines the bit rate of all the input and output ST-BUS streams, which can
operate at either 8.192 or 16.384 Mbps.
When LOW, 32 Backplane input/output pairs (BSTi[31:0], BSTo[31:0]) and
32 Local input/output pairs (LSTi[31:0], LSTo[31:0]) operate at 8.192 Mbps.
When HIGH, 16 Backplane input/output pairs (BSTi[15:0], BSTo[15:0]) and
16 Local input/output pairs (LSTi[15:0], LSTo[15:0]) operate at 16.384 Mbps.
Table 24 - Bit Rate Register (BRR) Bits
48
Zarlink Semiconductor Inc.
ZL50051/3
13.9
Data Sheet
Device Identification Register
Address 3FFFH.
The Device Identification Register stores the binary value of the silicon revision number and the Device ID. This
register is read-only. The DIR register is configured as follows:
Bit
Name
Reset Value
15:8
Reserved
0
Description
Reserved
Will read 0 in normal operation
7:4
RC[3:0]
0000
3
Reserved
0
Revision Control Bits
Reserved
Will read 0 in normal operation
2:0
DID[2:0]
100
Device ID
Table 25 - Device Identification Register (DIR) Bits
49
Zarlink Semiconductor Inc.
ZL50051/3
14.0
Data Sheet
DC Electrical Characteristics
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
VDD_CORE
-0.5
2.5
V
1
Core Supply Voltage
2
I/O Supply Voltage
VDD_IO
-0.5
5.0
V
3
PLL Supply Voltage
VDD_PLL
-0.5
2.5
V
4
Input Voltage (non-5 V tolerant inputs)
VI
-0.5
VDD_IO
+0.5
V
5
Input Voltage (5 V tolerant inputs)
VI_5V
-0.5
7.0
V
6
Continuous Current at digital outputs
Io
15
mA
7
Package power dissipation
PD
1.5
W
8
Storage temperature
TS
+125
°C
- 55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions
Characteristics
Sym
Min
Typ
Max
Units
TOP
-40
25
+85
°C
1
Operating Temperature
2
Positive Supply
VDD_IO
3.0
3.3
3.6
V
3
Positive Supply
VDD_CORE
1.71
1.8
1.89
V
4
Positive Supply
VDD_PLL
1.71
1.8
1.89
V
5
Input Voltage
VI
0
VDD_IO
V
0
5.5
V
6
Input Voltage on 5 V Tolerant Inputs
VI_5V
Voltages are with respect to ground (VSS) unless otherwise stated.
50
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
DC Electrical Parameters
Characteristics
1a
Sym.
Min.
Supply Current
IDD_Core
Supply Current
IDD_Core
Supply Current
IDD_IO
Supply Current
IDD_IO
Typ.
Max.
Units
Test Conditions
4
mA
Static IDD_Core and
PLL current
290
mA
Applied clock
C8i = 8.192 MHz
100
µA
Static IDD_IO
18
mA
IAV with all output
streams at max.
data rate unloaded
I
1b
240
N
1c
1d
P
14
U
2
Input High Voltage
VIH
Input Low Voltage
VIL
0.8
V
Input Leakage (input pins)
Input Leakage (bi-directional pins)
IIL
IBL
5
5
µA
µA
0 < V < VDD_IO
Note 1
Weak Pullup Current
IPU
200
µA
Input at 0V
5
Weak Pulldown Current
IPD
200
µA
Input at VDD_IO
6
Input Pin Capacitance
CI
5
pF
T
3
4
7
8
9
10
S
O
U
T
P
U
T
S
2.0
V
V
IOH = 8 mA
0.4
V
IOL = 8 mA
IOZ
5
µA
0 < V0 < VDD_IO
Note 1
CO
5
pF
Output High Voltage
VOH
Output Low Voltage
VOL
High impedance Leakage
Output Pin Capacitance
2.4
Voltages are with respect to ground (Vss) unless otherwise stated.
Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V)
51
Zarlink Semiconductor Inc.
ZL50051/3
15.0
Data Sheet
AC Electrical Characteristics
AC Electrical Characteristics Timing Parameter Measurement: Voltage Levels
Characteristics
Sym.
Level
Units
Conditions
1
CMOS Threshold
VCT
0.5 VDD_IO
V
3.0 V < VDD_IO < 3.6V
2
Rise/Fall Threshold Voltage High
VHM
0.7 VDD_IO
V
3.0 V < VDD_IO < 3.6V
3
Rise/Fall Threshold Voltage Low
VLM
0.3 VDD_IO
V
3.0 V < VDD_IO < 3.6V
Input and Output Clock Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
244
122
350
220
ns
Notes
1
FP8i, Input Frame Pulse Width
tIFPW244
tIFPW122
210
10
2
Input Frame Pulse Setup Time
(before C8i clock falling/rising edge)
tIFPS244
tIfPS122
5
5
110
60
ns
3
Input Frame Pulse Hold Time
(from C8i clock falling/rising edge)
tIFPH244
tIFPH122
0
0
110
60
ns
4
C8i Clock Period (Average value, does not
consider the effects of jitter)
tICP
120
122
124
ns
5
C8i Clock Pulse Width High
tICH
50
61
70
ns
6
C8i Clock Pulse Width Low
tICL
50
61
70
ns
7
C8i Clock Rise/Fall Time
trIC, tfIC
0
2
3
ns
8
C8i Cycle to Cycle Variation
(This values is with respect to the typical C8i
Clock Period, and using mid-bit sampling)
tCCVIC
-8.5
8.5
ns
9
Output Frame Boundary Offset
tOFBOS
7
9.5
ns
10
FP8o Frame Pulse Width
tOFPW8_244
tOFPW8_122
224
117
244
122
264
127
ns
FPW = 1
FPW = 0
CL = 60 pF
11
FP8o Output Delay
(from frame pulse edge to output frame
boundary)
tFPFBF8_244
tFPFBF8_122
117
58
122
61
127
64
ns
FPW = 1
FPW = 0
CL = 60 pF
12
FP8o Output Delay
(from output frame boundary to frame pulse
edge)
tFBFPF8_244
tFBFPF8_122
117
58
122
61
127
64
ns
FPW = 1
FPW = 0
CL = 60 pF
13
C8o Clock Period
tOCP8
117
122
127
ns
14
C8o Clock Pulse Width High
tOCH8
58
61
64
ns
15
C8o Clock Pulse Width Low
tOCL8
58
61
64
ns
16
C8o Clock Rise/Fall Time
trOC8, tfOC8
3
7
ns
17
FP16o Frame Pulse Width
tOFPW16_122
tOFPW16_61
117
58
127
64
ns
52
Zarlink Semiconductor Inc.
122
61
CL = 60 pF
FPW = 1
FPW = 0
CL = 60 pF
ZL50051/3
Data Sheet
Input and Output Clock Timing (continued)
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
18
FP16o Output Delay
(from frame pulse edge to output frame
boundary)
tFPFBF16_122
tFPFBF16_61
58
29
61
31
64
33
ns
FPW = 1
FPW = 0
19
FP16o Output Delay
(from output frame boundary to frame pulse
edge)
tFBFPF16_122
tFBFPF16_61
58
29
61
31
64
33
ns
FPW = 1
FPW = 0
20
C16o Clock Period
tOCP16
58
61
64
ns
21
C16o Clock Pulse Width High
tOCH16
29
31
33
ns
22
C16o Clock Pulse Width Low
tOCL16
29
31
33
ns
23
C16o Clock Rise/Fall Time
trOC16,
tfOC16
3
7
ns
53
Zarlink Semiconductor Inc.
CL = 60 pF
ZL50051/3
Data Sheet
tIFPW244
FP8i
(244 ns)
tIFPS244
tIFPH244
tIFPW122
FP8i
(122 ns)
tIFPS122
tICL
tIFPH122
tICP
tICH
C8i
trIC
tfIC
CK_int *
tOFBOS
tOFPW8_244
FP8o
(244 ns)
tFPFBF8_244
tFBFPF8_244
tOFPW8_122
FP8o
(122 ns)
tFBFPF8_122
tFPFBF8_122
tOCL8
tOCP8
tOCH8
C8o
trOC8
tfOC8
tOFPW16_122
FP16o
(122 ns)
tFPFBF16_122
tFBFPF16_122
tOFPW16_61
FP16o
(61 ns)
tFPFB16_61
tOCL16
tFBFP16_61
tOCH16
tOCP16
C16o
trOC16
tfOC16
Note *: CK_int is the internal clock signal of 131.072 MHz.
Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the
frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the
Control Register.
Figure 18 - Input and Output Clock Timing Diagram for ST-BUS
54
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
tIFPW244
FP8i
(244 ns)
tIFPS244
tIFPH244
tIFPW122
FP8i
(122 ns)
tIFPS122
tICL
tIFPH122
tICP
tICH
C8i
trIC
tfIC
CK_int *
tOFBOS
tOFPW8_244
FP8o
(244 ns)
tFPFBF8_244
tFBFPF8_244
tOFPW8_122
FP8o
(122 ns)
tFBFPF8_122
tFPFBF8_122
C8o
tOCL8
tOCP8
tOCH8
trOC8
tfOC8
tOFPW16_122
FP16o
(122 ns)
tFPFBF16_122
tFBFPF16_122
tOFPW16_61
FP16o
(61 ns)
tFPFB16_61
tOCH16
tFBFP16_61
tOCL16
tOCP16
C16o
tfOC16
trOC16
Note *: CK_int is the internal clock signal of 131.072 MHz.
Note **: Although the figures above show the frame boundary as measured from the rising edge of C8i/C8o/C16o, the
frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the
Control Register.
Figure 19 - Input and Output Clock Timing Diagram for GCI-Bus
55
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Local and Backplane Data Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
Local/Backplane Input Data Sampling Point
tIDS16
tIDS8
43
87
46
92
49
97
ns
With
SMPL_MODE =
0 (3/4-bit
sampling) and
zero offset.
2
Local/Backplane Serial Input Set-up Time
tSIS16
tSIS8
2
2
ns
With respect to
Min. Input Data
Sampling Point
3
Local/Backplane Serial Input Hold Time
tSIH16
tSIH8
2
2
ns
With respect to
Max. Input Data
Sampling Point
4
Output Frame Boundary Offset
tOFBOS
5
Local/Backplane Serial Output Delay
tSOD16
tSOD8
7
9.5
ns
4.5
4.5
ns
CL= 50 pF
These numbers
are referencing
output frame
boundary.
FP8i
C8i
CK_int *
tIDS8
tSIS8
tSIH8
L/BSTi0-31
8.192 Mbps
1
0
7
6
5
4
3
2
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
1
tOFBOS
FP8o
C8o
CK_int *
tSOD8
L/BSTo0-31
8.192 Mbps
Bit1
Ch127
Bit0
Ch127
Bit7
Ch0
Bit6
Ch0
Bit1
Ch0
Note *: CK_int is the internal clock signal of 131.072 MHz
Figure 20 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps)
56
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
FP8i
C8i
CK_int *
tIDS16
tSIS16
tSIH16
L/BSTi0-15
16.384 Mbps
Bit1
Ch255
Bit7
Ch0
Bit0
Ch255
Bit6
Ch0
Bit5
Ch0
tOFBOS
FP8o
C8o
CK_int *
tSOD16
L/BSTo0-15
16.384 Mbps
Bit0
Ch255
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Note *: CK_int is the internal clock signal of 131.072 MHz.
Figure 21 - ST-BUS Local/Backplane Data Timing Diagram (16 Mbps)
57
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
FP8i
C8i
CK_int *
tIDS8
tSIS8
tSIH8
L/BSTi0-31
8.192 Mbps
7
6
0
1
2
3
4
5
6
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit5
Ch0
Bit6
Ch0
tOFBOS
FP8o
C8o
CK_int *
tSOD8
L/BSTo0-31
8.192 Mbps
Bit6
Ch127
Bit7
Ch127
Bit0
Ch0
Note *: CK_int is the internal clock signal of 131.072 MHz.
Figure 22 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps)
58
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
FP8i
C8i
CK_int *
tIDS16
tSIS16
tSIH16
L/BSTi0-15
16.384 Mbps
Bit6
Ch255
Bit0
Ch0
Bit7
Ch255
Bit1
Ch0
Bit2
Ch0
tOFBOS
FP8o
C8o
CK_int *
tSOD16
L/BSTo0-15
16.384 Mbps
Bit7
Ch255
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Note *: CK_int is the internal clock signal of 131.072 MHz.
Figure 23 - GCI-Bus Local/Backplane Data Timing Diagram (16 Mbps)
59
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Local and Backplane Output High Impedance Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
4
4
6
6
ns
ns
RL = 1 k, CL = 50 pF, See Note 1
1
STo delay - Active to High-Z
- High-Z to Active
tDZ
tZD
2
Output Driver Enable (ODE)
Delay to Active Data
Output Driver Enable (ODE)
Delay to high impedance
tODE
14
ns
RL = 1 k, CL = 50 pF, See Note 1
tODZ
14
ns
RL = 1 k, CL = 50 pF, See Note 1
Note 1:
High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge
CL.
VTT
CLK
tDZ
STo
Valid Data
HiZ
VTT
Valid Data
VTT
tZD
HiZ
STo
Figure 24 - Serial Output and External Control
VTT
ODE
tODE
STo
Hi-Z
tODZ
Valid Data
Hi-Z
VTT
Figure 25 - Output Driver Enable (ODE)
60
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Input Clock Jitter Tolerance
Jitter Frequency
16.384 Mbps Data Rate
Jitter Tolerance
Units
1
1 kHz
1200
ns
2
10 kHz
1200
ns
3
50 kHz
150
ns
4
66 kHz
110
ns
5
83 kHz
80
ns
6
95 kHz
70
ns
7
100 kHz
25
ns
8
200 kHz
17
ns
9
300 kHz
17
ns
10
400 kHz
17
ns
11
500 kHz
17
ns
12
1 MHz
17
ns
13
2 MHz
17
ns
14
4 MHz
17
ns
61
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
Non-Multiplexed Microprocessor Port Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
CS setup from DS falling
tCSS
0
ns
2
R/W setup from DS falling
tRWS
9
ns
3
Address setup from DS falling
tADS
9
ns
4
CS hold after DS rising
tCSH
0
ns
5
R/W hold after DS rising
tRWH
9
ns
6
Address hold after DS rising
tADH
9
ns
7
Data setup from DTA Low on Read
tRDS
5
12
ns
ns
Memory Read
Register Read
CL = 60 pF
8
Data hold on read
tRDH
ns
CL = 60 pF,
RL = 1 k
Note 1
9
Data setup on write
tWDS
9
ns
10
Data hold on write
tWDH
9
ns
11
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
tAKD
Acknowledgment Hold Time
tAKH
12
4.5
88
80
ns
ns
CL = 60 pF
CL = 60 pF
11
ns
CL = 60 pF,
RL = 1 k,
Note 1
Note 1:
High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge
CL.
Note 2:
There must be a minimum of 30 ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a
minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next
access).
62
Zarlink Semiconductor Inc.
ZL50051/3
Data Sheet
DS
VTT
tCSH
tCSS
VTT
CS
tRWH
tRWS
VTT
R/W
tADS
tADH
VTT
VALID ADDRESS
A0-A14
tRDH
VTT
VALID READ DATA
D0-D15
READ
tWDH
tWDS
D0-D15
WRITE
VTT
VALID WRITE DATA
tRDS
VTT
DTA
tAKD
Figure 26 - Motorola Non-Multiplexed Bus Timing
63
Zarlink Semiconductor Inc.
tAKH
ZL50051/3
Data Sheet
AC Electrical Characteristics† - JTAG Test Port Timing
Characteristic
Sym
Min
Typ
Max
Units
1
TCK Clock Period
tTCKP
100
ns
2
TCK Clock Pulse Width High
tTCKH
80
ns
3
TCK Clock Pulse Width Low
tTCKL
80
ns
4
TMS Set-up Time
tTMSS
10
ns
5
TMS Hold Time
tTMSH
10
ns
6
TDi Input Set-up Time
tTDIS
20
ns
7
TDi Input Hold Time
tTDIH
60
ns
8
TDo Output Delay
tTDOD
9
TRST pulse width
tTRSTW
30
ns
200
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
tTCKL
tTCKH
tTCKP
TCK
tTMSS
tTMSH
TMS
tTDIS
tTDIH
TDi
tTDOD
TDo
tTRSTW
TRST
Figure 27 - JTAG Test Port Timing Diagram
64
Zarlink Semiconductor Inc.
Notes
CL = 30 pF
b
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
1
ACN
214440
DATE
26June03
APPRD.
Previous package codes
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE