54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description The ’F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Commercial Military Package Number Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features Y Guaranteed 4000V minimum ESD protection Package Description N14A 14-Lead (0.300× Wide) Molded Dual-In-Line J14A 14-Lead Ceramic Dual-In-Line 74F74SC (Note 1) M14A 14-Lead (0.150× Wide) Molded Small Outline, JEDEC 74F74SJ (Note 1) M14D 14-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F74FM (Note 2) W14B 14-Lead Cerpack 54F74LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 74F74PC 54F74DM (Note 2) Note 1: Devices also available in 13× reel. Use Suffix e SCX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols IEEE/IEC TL/F/9469 – 6 TL/F/9469–3 TL/F/9469 – 4 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9469 RRD-B30M75/Printed in U. S. A. 54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop December 1994 Connection Diagrams Pin Assignment for DIP, SOIC, and Flatpak Pin Assignment for LCC TL/F/9469–1 TL/F/9469 – 2 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2 Data Inputs Clock Pulse Inputs (Active Rising Edge) Direct Clear Inputs (Active LOW) Direct Set Inputs (Active LOW) Outputs 1.0/1.0 1.0/1.0 1.0/3.0 1.0/3.0 50/33.3 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b1.8 mA 20 mA/b1.8 mA b 1 mA/20 mA Truth Table Inputs Outputs H (h) e HIGH Voltage Level SD CD CP D Q Q L H L H H H H L L H H H X X X L L L X X X h l X H L H H L Q0 L H H L H Q0 L (l) e LOW Voltage Level X e Immaterial Q0 e Previous Q (Q) before LOW-to-HIGH Clock Transition Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Logic Diagram TL/F/9469 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC IIH Input HIGH Current IBVI Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA IOH e b1 mA 0.5 0.5 V Min IOL e 20 mA IOL e 20 mA 54F 74F 20.0 5.0 mA Max VIN e 2.7V Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.8 mA Max VIN e 0.5V (D, CP) VIN e 0.5V (CD, SD) IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V ICC Power Supply Current 16.0 mA Max 2.5 2.5 2.7 4.75 b 60 10.5 3 Recognized as a LOW Signal AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Max Min Typ fmax Maximum Clock Frequency 100 125 tPLH tPHL Propagation Delay CPn to Qn or Qn 3.8 4.4 5.3 6.2 6.8 8.0 3.8 4.4 8.5 10.5 3.8 4.4 7.8 9.2 ns tPLH tPHL Propagation Delay CDn or SDn to Qn or Qn 3.2 3.5 4.6 7.0 6.1 9.0 3.2 3.5 8.0 11.5 3.2 3.5 7.1 10.5 ns 80 Min Units Max 100 MHz AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max ts(H) ts(L) Setup Time, HIGH or LOW Dn to CPn 2.0 3.0 3.0 4.0 2.0 3.0 th(H) th(L) Hold Time, HIGH or LOW Dn to CPn 1.0 1.0 2.0 2.0 1.0 1.0 tw(H) tw(L) CPn Pulse Width HIGH or LOW 4.0 5.0 4.0 6.0 4.0 5.0 ns tw(L) CDn or SDn Pulse Width LOW 4.0 4.0 4.0 ns trec Recovery Time CDn or SDn to CP 2.0 3.0 2.0 ns 4 ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 74 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13× reel Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak Le Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 5 Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Dual-In-Line Package (D) NS Package Number J14A 14-Lead (0.150× Wide) Molded Small Outline, JEDEC (S) NS Package Number M14A 6 Physical Dimensions inches (millimeters) (Continued) 14-Lead (0.300× Wide) Molded Small Outline, EIAJ (SJ) NS Package Number M14D 14-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N14A 7 54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Flatpak (F) NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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