HS-26C32RH ® Data Sheet August 1, 2008 Radiation Hardened Quad Differential Line Receiver The Intersil HS-26C32RH is a differential line receiver designed for digital data transmission over balanced lines and meets the requirements of EIA Standard RS-422. Radiation hardened CMOS processing assures low power consumption, high speed, and reliable operation in the most severe radiation environments. FN3402.4 Features • Electrically Screened to SMD # 5962-95689 • QML Qualified per MIL-PRF-38535 Requirements • 1.2 Micron Radiation Hardened CMOS - Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (Max) • Latch-up Free • EIA RS-422 Compatible Inputs The HS-26C32RH has an input sensitivity typically of 200mV over the common mode input voltage range of ±7V. The receivers are also equipped with input fail safe circuitry, which causes the outputs to go to a logic “1” when the inputs are open. Enable and Disable functions are common to all four receivers. • CMOS Compatible Outputs • Input Fail Safe Circuitry • High Impedance Inputs when Disabled or Powered Down • Low Power Dissipation 138mW Standby (Max) Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed in the “Ordering Information” table must be used when ordering. • Single 5V Supply Detailed Electrical Specifications for these devices are contained in SMD 5962-95689. A “hot-link” is provided on our homepage for downloading .www.intersil.com/military/ • Line Receiver for MIL-STD-1553 Serial Data Bus • Full -55°C to +125°C Military Temperature Range Applications Logic Diagram ENABLE ENABLE DIN DIN + - DOUT CIN CIN BIN BIN AIN AIN + + + - COUT - BOUT - AOUT Ordering Information ORDERING NUMBER INTERNAL MKT. NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # 5962F9568901QEC HS1-26C32RH-8 Q 5962F95 68901QEC -55 to +125 16 Ld SBDIP 5962F9568901QXC HS9-26C32RH-8 Q 5962F95 68901QXC -55 to +125 16 Ld FLATPACK K16.A 5962F9568901V9A HS0-26C32RH-Q 5962F9568901VEC HS1-26C32RH-Q Q 5962F95 68901VEC -55 to +125 16 Ld SBDIP 5962F9568901VXC HS9-26C32RH-Q Q 5962F95 68901VXC -55 to +125 16 Ld FLATPACK K16.A HS1-26C32RH/PROTO HS1-26C32RH/PROTO HS1- 26C32RH /PROTO -55 to +125 16 Ld SBDIP HS9-26C32RH/PROTO HS9-26C32RH/PROTO HS9- 26C32RH /PROTO -55 to +125 16 Ld FLATPACK K16.A 1 D16.3 -55 to +125 D16.3 D16.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HS-26C32RH Pinouts HS9-26C32RH (16 LD FLATPACK) MIL-STD-1835: CDFP4-F16 TOP VIEW HS1-26C32RH (16 LD SBDIP) MIL-STD-1835: CDIP2-T16 TOP VIEW AIN 1 16 VDD AIN 1 16 VDD AIN 2 15 BIN AIN 2 15 BIN AOUT 3 14 BIN ENABLE 4 13 BOUT COUT 5 12 ENABLE CIN 6 11 DOUT CIN 7 10 DIN GND 8 9 DIN 14 BIN AOUT 3 13 BOUT ENABLE 4 COUT 5 12 ENABLE CIN 6 11 DOUT CIN 7 10 DIN GND 8 9 DIN Propagation Delay Timing Diagram Propagation Delay Load Circuit TEST POINT DUT -VIN +2.5V INPUT 0V +VIN = 0V CL -2.5V RL tPHL tPLH VOH VS = 50% CL = 50pF OUTPUT RL = 1000Ω VOL Three-State Low Timing Diagram Three-State High Timing Diagrams VIH VIH VS VS INPUT INPUT VSS VSS tPZL tPZH tPLZ tPHZ VOH VOZ VT OUTPUT VT VW OUTPUT VW VOZ VOL 2 FN3402.4 August 1, 2008 HS-26C32RH TABLE 1. THREE-STATE LOW VOLTAGE LEVELS PARAMETER HS-26C32RH UNITS VDD 4.50 V VIH 4.50 VS TABLE 2. THREE-STATE HIGH VOLTAGE LEVELS HS-26C32RH UNITS VDD 4.50 V V VIH 4.50 V 2.25 V VS 2.25 V VT 50 % VT 50 % VW VOL + 0.5 V VW VOH - 0.5 V 0 V GND 0 V GND Three-State Low Load Circuit VDD PARAMETER Three-State High Load Circuit TEST POINT DUT RL CL RL TEST POINT DUT CL CL = 50pF RL = 1000Ω CL = 50pF RL = 1000Ω All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 3 FN3402.4 August 1, 2008 HS-26C32RH Die Characteristics DIE DIMENSIONS: Top Metallization: 84 mils x 130 mils (2140µm x 3290µm) M1: Mo/Tiw Thickness: 5800Å M2: Al/Si/Cu Thickness: 5800Å INTERFACE MATERIALS: Glassivation: Worst Case Current Density: Type: SiO2 Thickness: 10kÅ ± 1kÅ <2.0 x 105A/cm2 Bond Pad Size: 110µm x 100µm Metallization Mask Layout HS-26C32RH AIN (1) VDD (16) BIN (15) (14) BIN AIN (2) (13) BOUT AOUT (3) ENAB (4) (12) ENAB COUT (5) (11) DOUT (10) DIN CIN (6) (7) CIN 4 (8) GND (9) DIN FN3402.4 August 1, 2008