TERIDIAN 70P2352-IGT

78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
DATA SHEET
SEPTEMBER 2006
DESCRIPTION
FEATURES
The 78P2352 is Teridian’s second generation Line
Interface Unit (LIU) for 155 Mbps SDH/SONET
(OC-3, STS-3, or STM-1) and 140 Mbps PDH (E4)
telecom interfaces. The device is a dual channel,
single chip solution that includes an integrated CDR
in the transmit path for flexible NRZ to CMI
conversion. The device can interface to 75Ω coaxial
cable using CMI coding or directly to a fiber optics
transceiver module using NRZ coding.
The
78P2352 is compliant with all respective ANSI, ITUT, and Telcordia standards for jitter tolerance,
generation, and transfer.
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APPLICATIONS
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Central Office Interconnects
DSLAMs
Add Drop Multiplexers (ADMs)
Multi Service Switches
Digital Microwave Radios
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ITU-T G.703 compliant cable driver for 139.264
Mbps or 155.52 Mbps CMI-coded coax
transmission
Integrated adaptive CMI equalizer and CDR in
receive path handles over 12.7dB of cable loss
Serial, LVPECL system interface with integrated
CRU in transmit path for flexible NRZ to CMI
conversion.
4-bit parallel CMOS system interface with
master and slave Tx clock modes.
Selectable LVPECL compatible NRZ media
interface for 155.52 Mbps optical transmission.
Configurable via HW control pins or 4-wire serial
port interface
Compliant with ANSI T1.105.03-1994; ITU-T
G.751, G.813, G.823, G.825, G.958; and
Telcordia GR-253-CORE for jitter performance.
Receiver Loss of Signal (LOS) detection
compatible with ITU-T G.783
Operates from a single 3.3V supply
Standard and thermally enhanced 128-pin
JEDEC LQFP package options
BLOCK DIAGRAM
EACH CHANNEL: Tx
Lock Detect
SIxDP/N
ECLxP/N
Tx CDR
FIFO
TXxCKP/N
CMI
Encoder
SIxCKP/N
CMIxP/N
PIxCK
PIx[3:0]D
PMOD, SMOD[1:0], PAR
PTOxCK
SOxCKP/N
SOxDP/N
POx[3:0]D
POxCK
RLBK
CMI
Decoder
Rx CDR
Adaptive
Eq.
RXxP/N
Lock Detect
CMI
LOS Detect
LLBK
EACH CHANNEL: Rx
Page: 1 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
TABLE OF CONTENTS ................................................................................................ 2
FUNCTIONAL DESCRIPTION........................................................................................ 4
MODE SELECTION................................................................................................................................4
REFERENCE CLOCK ............................................................................................................................4
RECEIVER OPERATION .......................................................................................................................4
Receiver Monitor Mode ..................................................................................................................4
Receive Loss of Signal ..................................................................................................................5
Receive Loss of Lock.....................................................................................................................5
TRANSMITTER OPERATION ................................................................................................................5
Synchronous (Re-timing) Tx Serial Modes ..................................................................................5
Plesiochronous Serial Modes .......................................................................................................6
Synchronous Parallel Modes ........................................................................................................6
Transmit FIFO Description ............................................................................................................6
Transmit Driver ...............................................................................................................................7
Clock Synthesizer...........................................................................................................................7
Transmit Backplane Equalizer ......................................................................................................7
Transmit Loss of Lock ...................................................................................................................7
POWER-DOWN FUNCTION .................................................................................................................7
ANALOG LOOPBACK MODES.............................................................................................................7
POWER-ON RESET ..............................................................................................................................7
SERIAL CONTROL INTERFACE .........................................................................................................8
PROGRAMMABLE INTERRUPTS ........................................................................................................8
REGISTER DESCRIPTION............................................................................................. 9
REGISTER ADDRESSING.....................................................................................................................9
REGISTER TABLE.................................................................................................................................9
LEGEND ...............................................................................................................................................10
GLOBAL REGISTERS .........................................................................................................................10
ADDRESS 0-0: MASTER CONTROL REGISTER .......................................................................10
ADDRESS 0-1: INTERRUPT CONTROL REGISTER..................................................................11
PORT-SPECIFIC REGISTERS ............................................................................................................12
ADDRESS N-0: MODE CONTROL REGISTER...........................................................................12
ADDRESS N-1: SIGNAL CONTROL REGISTER ........................................................................13
ADDRESS N-2: ADVANCED TX CONTROL REGISTER 1 ........................................................14
ADDRESS N-3: ADVANCED TX CONTROL REGISTER 0 ........................................................14
ADDRESS N-4: MODE CONTROL REGISTER 2........................................................................14
ADDRESS N-5: STATUS MONITOR REGISTER ........................................................................15
PIN DESCRIPTION ....................................................................................................... 16
LEGEND ...............................................................................................................................................16
TRANSMITTER PINS ...........................................................................................................................16
RECEIVER PINS ..................................................................................................................................17
REFERENCE AND STATUS PINS ......................................................................................................18
CONTROL PINS ..................................................................................................................................19
SERIAL-PORT PINS ............................................................................................................................21
POWER AND GROUND PINS .............................................................................................................21
Page: 2 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
TABLE OF CONTENTS (continued)
ELECTRICAL SPECIFICATIONS ................................................................................. 22
ABSOLUTE MAXIMUM RATINGS..........................................................................................................22
RECOMMENDED OPERATING CONDITIONS ......................................................................................22
DC CHARACTERISTICS.........................................................................................................................22
ANALOG PINS CHARACTERISTICS.....................................................................................................23
DIGITAL I/O CHARACTERISTICS..........................................................................................................23
Pins of type CI, CIU, CID................................................................................................................23
Pins of type CIT ..............................................................................................................................23
Pins of type CIS ..............................................................................................................................23
Pins of type CO and COZ...............................................................................................................24
Pins of type PO...............................................................................................................................24
Pins of type PI.................................................................................................................................24
Pins of type OD...............................................................................................................................24
SERIAL-PORT TIMING CHARACTERISTICS........................................................................................25
TRANSMITTER TIMING CHARACTERISTICS ......................................................................................26
TIMING DIAGRAM: Transmitter Waveforms .......................................................................................26
REFERENCE CLOCK CHARACTERISTICS..........................................................................................27
RECEIVER TIMING CHARACTERISTICS..............................................................................................27
TIMING DIAGRAM: Receive Waveforms ............................................................................................27
TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE .................................................................28
TRANSMITTER OUTPUT JITTER ..........................................................................................................33
RECEIVER SPECIFICATIONS FOR CMI INTERFACE (Transformer-coupled)..................................34
RECEIVER JITTER TOLERANCE ..........................................................................................................35
RECEIVER JITTER TRANSFER FUNCTION .........................................................................................37
CMI MODE LOSS OF SIGNAL CONDITION ..........................................................................................38
APPLICATION INFORMATION .................................................................................... 38
EXTERNAL COMPONENTS ...................................................................................................................38
(CMI) TRANSFORMER SPECIFICATIONS............................................................................................38
THERMAL INFORMATION .....................................................................................................................38
MECHANICAL SPECIFICATIONS ............................................................................... 39
PACKAGE INFORMATION (pinout)................................................................................................ 41
ORDERING INFORMATION ......................................................................................... 41
Revision History ........................................................................................................................................42
Page: 3 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
FUNCTIONAL DESCRIPTION
The 78P2352 contains all the necessary transmit
and receive circuitry for connection between
139.264Mbps and 155.52Mbps line interfaces and
the digital universe. The chip is controllable through
pins or serial port register settings.
In hardware mode (pin control) the SPSL pin
must be low.
In software mode (SPSL pin high), control pins
are disabled and the 78P2352 must be
configured via the 4-wire serial port.
MODE SELECTION
The SDO_E4 pin or E4 register bit determines which
rate the device (both channels) operates in
according to the table below. This control, combined
with CKSL, also selects the global reference clock
frequency.
Rate
E4
STM-1, STS-3, OC-3
SDO_E4 pin
High
Low
E4 bit
1
0
The SEN_CMI pin or CMI register bit enables the
CMI encoder/decoder and selects one of two media
for reception and transmission: 75Ω coaxial cable in
CMI mode or optical fiber in Fiber (NRZ) mode.
Independent channel operation for media type is
available with register controls only.
Media (coding)
75Ω Coax (CMI)
Fiber (NRZ)
SEN_CMI pin
High
Low
CMI bit
1
0
The SDI_PAR pin or PAR register bit selects the
interface to the framer to be 4-bit parallel CMOS or
serial LVPECL.
For each interface there are
different transmit timing modes available. See
TRANSMITTER OPERATION section for more info.
REFERENCE CLOCK
The 78P2352 requires a reference clock supplied to
the CKREFP/N pins. This reference clock is used
for clock recovery in the Rx DLL and Tx DLL. It is
also used for transmit re-timing in the synchronous
transmit modes.
Refer to the TRANSMITTER
OPERATION section for timing requirements during
synchronous (re-timing) transmit modes.
For reference frequencies of 77.76MHz or lower, the
device accepts a single ended CMOS input at
CKREFP (with CKREFN grounded). For reference
frequencies of 139.264 or 155.52MHz, the device
accepts a differential LVPECL clock input at
CKREFP/N.
Page: 4 of 42
The frequency of this reference input is controlled by
the rate selection and the CKSL control pin or
register bit.
CKSL pin
Low
Float
High
CKSL[1:0] bits
00
10
11
Reference Frequency
SDO_E4 low
SDO_E4 high
19.44MHz
77.76MHz
155.52MHz
E4 bit = 0
19.44MHz
77.76MHz
155.52MHz
17.408MHz
N/A
139.264MHz
E4 bit = 1
17.408MHz
N/A
139.264MHz
RECEIVER OPERATION
The receiver accepts serial data, at 155.52Mbps or
139.264Mbps from the RXxP/N inputs. In CMI mode,
the input is differentially terminated with 75Ω and
transformer-coupled to a coaxial connector. In Fiber
(NRZ) mode, the input is differentially terminated
with 100Ω and AC-coupled to an optical transceiver
module. For board designs utilizing both coax and
fiber media options, an analog switch or mechanical
relay is required to switch between the different
terminations and media paths.
The CMI signal first enters an AGC and adaptive
equalizer designed to overcome inter-symbol
interference caused by long cable lengths. The
variable gain differential amplifier automatically
controls the gain to maintain a constant voltage level
output regardless of the input voltage level. Note
that in Fiber (NRZ) mode, the input signals bypass
the adaptive equalizer.
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a Delay Locked Loop (DLL), which
uses a reference frequency derived from the clock
applied to the CKREFP/N pins.
In serial mode, the clock and data are decoded and
transmitted through the LVPECL drivers. In parallel
mode, the data is decoded and converted into four
bit parallel segments before being transmitted
through the CMOS drivers. Note that in Fiber (NRZ)
mode, the CMI decoder is bypassed.
Receiver Monitor Mode
In CMI mode, the SCK_MON pin or MONx register
bit enables the receiver’s monitor mode which adds
approximately 20dB of flat gain to the receive signal
before equalization. Rx Monitor Mode can handle
20dB of flat loss typical of monitoring points with up
to 6dB of cable loss. Note that Loss of Signal
detection is disabled during Rx Monitor Mode.
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Receive Loss of Signal
The 78P2352 includes a Loss of Signal (LOS)
detector. When the peak value of the received CMI
signal is less than approximately 19dB below
nominal for approximately 110 UI, Receive Loss of
Signal is asserted. The Rx LOS signal is cleared
when the received signal is greater than
approximately 18dB below nominal for 110 UI.
In ECL mode, the LOSx signal will be asserted when
there are no transitions for longer than 2.3µs. The
signal is cleared when there are more than 4
transitions in 32 UI. It is generally recommended to
use the LOS status signal from the optical
transceiver module.
During Rx LOS conditions, the receive clock will
remain on the last selected phase tap of the Rx DLL
outputting a stable clock while the receive data
outputs are squelched and held at logic ‘0’.
Note: Rx Loss of Signal detection is disabled
during Local Loopback and Receive Monitor
Modes.
Receive Loss of Lock
The 78P2352 includes an optional Receiver Loss of
Lock detector that will flag if the recovered Rx clock
frequency differs from the reference clock by more
than ±100ppm in an interval greater than 420µs.
This condition is cleared when the frequencies are
less than ±100ppm off for more than 500µs.
Notes:
1. During Rx Loss of Signal (RLOS), the Rx
Loss of Lock indicator is undefined and may
report either status.
2. For reliable operation, the LOLOR bit in the
Signal Control register should be toggled
upon power-up and configuration.
TRANSMITTER OPERATION
At the media interface, the transmit driver generates
an analog signal for transmission through either a
transformer and 75Ω coaxial cable or directly to a
fiber optics transceiver for electrical to optical
conversion.
At the host interface, the 78P2352 provides a
number interface options for compatibility with most
off-the-shelf framers and custom ASICs.
A
selectable 4-bit parallel or nibble interface is
available with both slave or master timing options as
well a serial LVPECL interface with various timing
recovery modes.
Each of the serial NRZ transmit timing modes can be
configured in HW mode or SW mode as shown in
the table below.
Serial Mode
HW Control Pins SW Control Bits
SDI_PAR
CKMODE
PAR
SMOD[1:0]
Synchronous
clock + data
Low
Low
0
00
Synchronous
data only
Low
Floating
0
10
Plesiochronou
s data only
Low
High
0
01
Loop-timing
n/a
n/a
X
11
Synchronous (Re-timing) Tx Serial Modes
In Figure 1, serial NRZ transmit data is input to
SIDxP/N pins at LVPECL levels. By default, the data
is latched in on the rising edge of SICKxP. An
integrated FIFO decouples the on chip and off chip
clocks and re-clocks the data using a clean
synthesized clock generated from the provided
reference clock. As such, the SICKxP/N clock
provided by the framer/mapper IC for both
channels must be source synchronous with the
provided reference clock when the FIFO is used.
System Reference Clock
CKREFP/N
NRZ
CMI
SIxDP/N
CMIxP/N
140 / 155 MHz
SIxCKP/N
Framer/
Mapper
NRZ
SOxCKP/N
140 / 155 MHz
TDK
78P2352
CMI
RXxP/N
SOxDP/N
XFMR
XFMR
Coax
Coax
Figure 1: Synchronous clock and data available
(Tx CDR bypassed, FIFO enabled)
If an off-chip serial transmit clock is not available, as
in Figure 2, the 78P2352 can recover a Tx clock
from the serial NRZ data input and pass the data
through the clock decoupling FIFO. The data is then
re-clocked or re-timed using a clean synthesized
clock generated from the provided reference clock.
In this mode, the NRZ transmit source data for both
channels must be source synchronous with the
reference clock applied at CKREFP/N.
System Reference Clock
CKREFP/N
NRZ
CMI
CMIxP/N
SIxDP/N
Framer/
Mapper
NRZ
140 / 155 MHz
SOxCKP/N
SOxDP/N
TDK
78P2352
XFMR
CMI
RXxP/N
Coax
Coax
XFMR
Figure 2: Synchronous data only
(Tx CDR enabled, FIFO enabled)
Page: 5 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Plesiochronous Tx Serial Mode
Figure 3 represents a common condition where a
serial transmit clock is not available and/or the data
is not source synchronous to the reference clock
input. In this mode, the 78P2352 will recover a
transmit clock from the serial plesiochronous data
and bypass the internal FIFO and re-timing block.
This mode is commonly used for mezzanine cards,
modules, and any application where the reference
clock cannot always be synchronous to the transmit
source clock/data.
Reference
Clock
Reference
Clock
CKREFP/N
4-bit CMOS TTL
Framer/
Mapper
34/39 MHz
4-bit CMOS TTL
34/39 MHz
POx[3:0]D
POxCK
140 / 155 MHz
CMI
CMIxP/N
TDK
78P2352
SOxDP/N
XFMR
Coax
CKREFP/N
NRZ
SOxCKP/N
CMI
RXxP/N
Coax
Figure 4: Slave Parallel Mode
CKREFP
NRZ
TDK
78P2352
XFMR
Reference
Clock
4-bit CMOS TTL
Framer/
Mapper
CMIxP/N
PIxCK
XO
SIxDP/N
CMI
PIx[3:0]D
XFMR
Coax
Framer/
Mapper
34/39 MHz
4-bit CMOS TTL
34/39 MHz
CMI
CMI
PIx[3:0]D
CMIxP/N
PTOxCK
POx[3:0]D
POxCK
TDK
78P2352
XFMR
CMI
RXxP/N
Coax
Coax
XFMR
Coax
XFMR
RXxP/N
Figure 5: Master Parallel Mode
Figure 3: Plesiochronous; data only
(Tx CDR enabled, FIFO bypassed)
Synchronous Parallel Modes
In parallel modes, 4-bit CMOS data segments are
input to the chip with a 34.816MHz (E4 ÷ 4) or
38.88MHz (STM1 ÷ 4) synchronous clock. These
inputs are re-timed in a 4x8 clock decoupling FIFO
and then to a serializer for transmission. Because
the data is passed through the FIFO and re-timed
using a synthesized clock, the transmit nibble clock
and data for both channels must be source
synchronous to the provided reference clock.
For maximum compatibility with legacy ASICs, the
78P2352 can operate in both slave and master clock
modes as shown in Figures 4 and 5 respectively.
Note: A loop-timing mode is also available to
allow external remote loopbacks (i.e. line
loopback in framer). In this mode, the FIFO is
still enabled, but the transmit data will be retimed using the recovered receive clock
HW Control Pins
SW Control Bits
SDI_PAR
CKMODE
PAR
PMODE
Slave
High
Low
1
0
Slave +
*Loop-timing
High
Float
1
0
Master
High
High
1
1
Parallel
Mode
*To enable Loop-timing
SMOD[1:0]=11
Page: 6 of 42
in
software
mode
set
Transmit FIFO Description
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The transmit FIFO allows long-term clock phase drift
between the Tx clock and system reference clock,
not exceeding +/- 25.6ns, to be handled without
transmit error. If the clock wander exceeds the
specified limits, the FIFO will over or under flow, and
the FERRx register signal will be asserted. This
signal can be used to trigger an interrupt. This
interrupt event is automatically cleared when a FIFO
Reset (FRSTx) pulse is applied, and the FIFO is recentered.
Notes:
1) External remote loopbacks (i.e. loopback
within framer) are not possible in
synchronous operation (FIFO enabled)
unless the data is re-justified to be
synchronous to the system reference clock
or the 78P2352 is configured for loop-timing.
2) Most E4 applications will not allow the use of
the dual channel 78P2352 as each channel
is asynchronous to each other. Teridian
recommends using the single channel
78P2351 if one cannot control the E4 timing
reference for each channel.
3) During IC power-up or transmit power-up,
the clocks going to the FIFO may not be
stable and cause the FIFO to overflow or
underflow. As such, the FIFO should be
manually reset using FRST anytime the
transmitter is powered-up.
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Transmit Driver
In CMI (electrical) mode, the CMIxP/N pins are
biased and terminated off-chip. They interface to
75Ω coaxial cable through a 1:1 wideband
transformer and coaxial RF connectors. Reference
application notes for schematic and layout
guidelines.
The transmitter encodes the data using CMI line
coding and shapes an analog signal to meet the
appropriate ITU-T G.703 template. The CMI outputs
are tri-stated during transmit disable and transmit
power-down for redundancy applications and powersavings.
Note: To avoid reflections causing unwanted
board noise, it’s recommended to power-down
unused transmit ports that are not terminated
with cable to an Rx input port.
When the CMI pin is low, the chip is in Fiber
(NRZ pass-through) mode and interfaces directly to
an optical transceiver module. The ECLxP/N pins
are internally biased and output NRZ data at
LVPECL levels. The CMI driver, encoder and
decoder are disabled in Fiber (NRZ) mode.
POWER-DOWN FUNCTION
Power-down controls are provided to allow the
78P2352 to be shut off. Transmit and receive
power-down can be set independently through SW
control. Total power-down is achieved by powering
down both the transmitter and receiver.
Note: The serial interface and configuration
registers are not affected by power-down.
In HW mode, both transmitters can also be globally
powered down using the TXPD control pin.
LOOPBACK MODES
In SW mode, LLBKx and RLBKx bits in the Signal
Control Register are provided to activate the local
and remote loopback modes respectively.
In HW mode, the LPBKx pins can be used to
activate local and remote analog loopback modes as
shown in the table below.
LPBK pin
Low
High
This 2x line rate clock is also available at the
TXCKxP/N pins for downstream synchronization or
system debug.
Transmit Backplane Equalizer
An optional fixed LVPECL equalizer is integrated in
the transmit path for architectures that use LIUs on
active interface cards. The fixed equalizer can
compensate for up to 1.5m of FR4 trace and can be
enabled by the TXOUT1 pin or TXEQ bit as follows:
TXOUT1 pin
Low
Float
TXEQ bit
Tx Equalizer
1
0
Enabled
Disabled
Transmit Loss of Lock
In transmit modes using the integrated CDR, the
78P2352 will declare a loss of lock condition when
there is no valid signal detected at the SIxDP/N data
inputs.
Note: The Tx LOL indicator is invalid and
undefined when the parallel (nibble) interface is
selected.
Normal operation
Remote (analog) Loopback:
Recovered receive clock and data
looped back directly to the transmit
driver. The CMI decoder and most of
transmit path is bypassed.
Local (analog) Loopback:
Transmit clock and data looped back to
receiver at the analog media interface.
Float
Clock Synthesizer
The transmit clock synthesizer is a low-jitter DLL that
generates a 278.528/311.04 MHz clock for the CMI
encoder. It is also used in both the receive and
transmit sides for clock and data recovery.
Analog Loopback Mode
EACH CHANNEL: Tx
Lock Detect
ECLxP/N
Tx CDR
SIxDP/N
FIFO
TXxCKP/N
CMI
Encoder
SIxCKP/N
CMIxP/N
PIxCK
PIx[3:0]D
PMOD, SMOD[1:0], PAR
PTOxCK
RLBK
SOxCKP/N
SOxDP/N
CMI
Decoder
POx[3:0]D
Rx CDR
Adaptive
Eq.
RXxP/N
Lock Detect
POxCK
LOS Detect
CMI
LLBK
EACH CHANNEL: Rx
Figure 6: Local (Analog) Loopback
EACH CHANNEL: Tx
Lock Detect
SIxDP/N
ECLxP/N
Tx CDR
FIFO
TXxCKP/N
CMI
Encoder
SIxCKP/N
CMIxP/N
PIxCK
PIx[3:0]D
PMOD, SMOD[1:0], PAR
PTOxCK
RLBK
SOxCKP/N
SOxDP/N
CMI
Decoder
POx[3:0]D
Rx CDR
Adaptive
Eq.
RXxP/N
Lock Detect
POxCK
CMI
LOS Detect
LLBK
EACH CHANNEL: Rx
Figure 7: Remote (Analog) Loopback
Page: 7 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
In SW mode only, a Full Remote (digital) Loopback
bit FLBK is also available in the Advanced Tx
Control register. This loopback exercises the entire
Rx and Tx paths of the 78P2352 including the Tx
clock recovery unit. As such, the user must enable
either Serial Plesiochronous or Serial Loop-timing
transmit modes to utilize the Full Remote (digital)
Loopback.
EACH CHANNEL: Tx
Lock Detect
SIxDP/N
ECLxP/N
Tx CDR
FIFO
TXxCKP/N
CMI
Encoder
SIxCKP/N
CMIxP/N
PIxCK
PIx[3:0]D
PMOD, SMOD[1:0], PAR
PTOxCK
RLBK
SOxCKP/N
SOxDP/N
CMI
Decoder
POx[3:0]D
Rx CDR
Adaptive
Eq.
RXxP/N
Lock Detect
POxCK
CMI
LOS Detect
LLBK
EACH CHANNEL: Rx
Figure 8: Remote (Digital) Loopback
INTERNAL POWER-ON RESET
Power-On Reset (POR) function is provided on chip.
Roughly 50µs after Vcc reaches 2.4V at power up, a
reset pulse is internally generated. This resets all
registers to their default values as well as all state
machines within the transceiver to known initial
values. The reset signal is also brought out to the
PORB pin. The PORB pin is a special function
analog pin that allows for the following:
•
Override the internal POR signal by driving in
an external active low reset signal;
•
Use the internally generated POR signal to
trigger other resets;
•
Add external capacitor to slow down the
release of power-on reset (approximately 8µs
per nF added).
NOTE: Do not pull-up the PORB pin to Vcc or drive
this pin high during power-up. This will prevent the
internal reset generator from resetting the entire chip
and may result in errors.
Page: 8 of 42
SERIAL CONTROL INTERFACE
The serial port controlled registers allows a generic
controller to interface with the 78P2352. It is used
for mode settings, diagnostics and test, retrieval of
status and performance information, and for on-chip
fuse trimming during production test. The SPSL pin
must be high in order to use the serial port.
The serial interface consists of four pins: Serial Port
Enable (SEN_CMI), Serial Clock (SCK_MON), Serial
Data In (SDI_PAR), and Serial Data Out (SDO_E4).
The SEN_CMI pin initiates the read and write
operations. It can also be used to select a
particular device allowing SCK_MON, SDI_PAR
and SDO_E4 to be bussed together.
SCK_MON is the clock input that times the data
on SDI_PAR and SDO_E4. Data on SDI_PAR
is latched in on the rising-edge of SCK_MON,
and data on SDO_E4 is clocked out using the
falling edge of SCK_MON.
SDI_PAR is used to insert mode, address, and
register data into the chip. Address and Data
information are input least significant bit (LSB)
first. The mode and address bit assignment and
register table are shown in the following section.
SDO_E4 is a tri-state capable output. It is used
to output register data during a read operation.
SDO_E4 output is normally high impedance,
and is enabled only during the duration when
register data is being clocked out. Read data is
clocked out least significant bit (LSB) first.
If SDI_PAR coming out of the micro-controller chip is
also tri-state capable, SDI_PAR and SDO_E4 can
be connected together to simplify connections. The
maximum clock frequency for register access is
20MHz.
PROGRAMMABLE INTERRUPTS
In addition to the receiver LOS and LOL status pins,
the 78P2352 provides a programmable interrupt for
each transmitter.
In HW control mode, the default events that trigger
the Tx interrupt is a transmit Loss of Lock (TXLOL)
or FIFO error (FERR).
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION
REGISTER ADDRESSING
Address Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Port Address
Assignment
PA[3]
PA[2]
Bit 1
Bit 0
Read/
Write
Sub-Address
PA[1]
PA[0]
SA[2]
SA[1]
SA[0]
R/W*
REGISTER TABLE
a) PA[3:0] = 0 : Global Registers
Sub
Addr
0
1
2
Reg.
Name
MSCR
(R/W)
INTC
(R/W)
-(R/W)
Description
Master Control
Interrupt Control
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
E4
<0>
INPOL
<0>
-<X>
-<0>
-<0>
-<X>
PAR
<0>
-<1>
-<X>
CKSL[1]
<X>
-<0>
-<X>
CKSL[0]
<X>
-<0>
-<X>
-<X>
-<X>
-<X>
-<X>
MTLOL
<1>
-<X>
SRST
<0>
MFERR
<1>
-<0>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PDTX
<0>
TCMIINV
<0>
-<0>
-<1>
CMI
<1>
-<X>
PDRX
<0>
RCMIINV
-<0>
-<0>
-<X>
-<X>
PMODE
<X>
LOLOR
<0>
-<0>
-<1>
-<X>
-<X>
MON
<0>
RCLKP
<0>
-<0>
BST[1]
<0>
-<0>
-<X>
-<0>
TCLKP
<0>
TPK
<0>
BST[0]
<0>
-<0>
TXLOL
<X>
-<1>
FRST
<0>
TXEQ
<0>
FLBK
<0>
-<0>
FERR
<X>
--
--
--
--
--
--
b) PA[3:0] = 1, 2 : Port-Specific Registers
Sub
Addr
0
1
2
3
4
5
6-7
Reg.
Name
MDCR
(R/W)
SGCR
(R/W)
ACR1
(R/W)
ACR0
(R/W)
MCR2
(R/W)
STAT
(R/C)
--
Page: 9 of 42
Description
Mode Control
Signal Control
Advanced Tx
Control 1
Advanced Tx
Control 0
Mode Control 2
Status Monitor
Reserved
<0>
SMOD[1] SMOD[0]
<X>
<X>
RLBK
LLBK
<0>
<0>
--<0>
<0>
--<0>
<1>
--<0>
<0>
RXLOS
RXLOL
<X>
<X>
--
2006 Teridian Semiconductor Corporation
--
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION (CONTINUED)
LEGEND
TYPE
DESCRIPTION
R/O
Read only
R/C
Read and Clear
TYPE
R/W
DESCRIPTION
Read or Write
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7
E4
R/W
0
Line Rate Selection:
Selects the line rate of all channels as well as the input clock frequency
at the CKREFP/N pins.
0: OC-3, STS-3, STM-1 (155.52MHz)
1: E4 (139.264MHz)
6
--
R/W
0
Unused
0
Serial/Parallel Interface Selection:
Selects the interface to the framer.
0: Serial LVPECL
1: 4-bit Parallel CMOS
5
PAR
R/W
4:3
CKSL
[1:0]
R/W
XX
Reference Clock Frequency Selection:
Selects the reference clock frequency input at CKREFP/N pins.
11: 155.52MHz / 139.264MHz (differential LVPECL)
10: 77.76MHz / NA (single-ended CMOS)
00: 19.44MHz / 17.408MHz (single-ended CMOS)
Secondary values correspond to E4 frequencies. Default values depend
on the CKSL pin selection upon reset.
2:1
--
R/W
X0
Reserved.
0
SRST
R/W
0
Page: 10 of 42
Register Soft-Reset:
When this bit is set, all registers are reset to their default values. This
register bit is self-clearing.
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION (CONTINUED)
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the interrupt pins to be activated. User may set as many bits as
required.
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
Interrupt Pin Polarity Selection:
7
INPOL
R/W
0
0 : Interrupt output is active-low (default)
1 : Interrupt output is active-high
6:2
--
R/W
01000
1
MTLOL
R/W
1
0
MFERR
R/W
1
Reserved for future use
TXLOL Error Mask (active low):
Gates the TXLOL register bit to the INTTXxB interrupt pin.
0: Mask
1: Pass
FIERR Error Mask (active low):
Gates the respective FIERR register bit to the INTTXxB interrupt pin.
0: Mask
1: Pass
ADDRESS 0-2: RESERVED
BIT
NAME
TYPE
DFLT
VALUE
7:0
--
R/W
XXXXXXX0
Page: 11 of 42
DESCRIPTION
Reserved.
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION (CONTINUED)
PORT-SPECIFIC REGISTERS
For PA[3:0] = 1-2 = N only. Accessing a register with port address greater than 2 constitutes an invalid command,
and the read/write operation will be ignored.
ADDRESS N-0: MODE CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
7
PDTX
R/W
0
6
PDRX
R/W
0
5
PMODE
R/W
X
4
SMOD[1]
R/W
X
3
SMOD[0]
R/W
X
DESCRIPTION
Transmitter Power-Down:
0 : Normal Operation
1 : Power-Down. CMI Transmit output is tri-stated.
Receiver Power-Down:
0 : Normal Operation
1 : Power-Down
Parallel Mode Interface Selection:
When PAR=0, PMODE is invalid and defaults to logic ‘1’;
When PAR=1, (Master Control Register: bit 5), PMODE selects the
source of the transmit parallel clock, either taken from the framer
externally or generated internally. Default value is determined by
CKMODE pin setting upon power up or reset.
0: Slave Timing. PIxCK clock input to the transmitter
1: Master Timing. PTOxCK clock output from the transmitter
Serial Mode Interface Selection:
When PAR=0 (Master Control Register: bit 5), SMOD[1:0] configures
the transmitter’s system interface. Default values determined by
CKMODE pin setting upon power up or reset.
SMOD[1] SMOD[0]
0
0
Synchronous clock and data are passed through a
FIFO. The CDR is bypassed.
1
0
Synchronous data is passed through the CDR and
then through the FIFO.
0
1
Plesiochronous data is passed through the CDR to
recover a clock. FIFO is bypassed because the
data is not synchronous with the reference clock.
1
1
Loop Timing Mode Enable: The recovered receive
clock is used as the reference for the transmit DLL
and FIFO.
When PAR=1 (Master Control Regsiter: bit 5), setting SMOD[1:0] = 11
will enable Loop Timing Mode. Default values are determined by
CKMODE pin setting upon power up or reset as follows:
CKMODE Low
SMOD[1:0] default = 00 (no effect)
CKMODE Float
SMOD[1:0] default = 11 (loop-timing enable)
CKMODE High
SMOD[1:0] default = 01 (no effect)
2
MON
R/W
0
Receive Monitor Mode Enable:
0: Normal Operation
1: Adds 20dB of flat gain to the receive signal before equalization
NOTE: Monitor mode is only available in CMI mode.
1:0
--
R/W
00
Reserved
Page: 12 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION (CONTINUED)
ADDRESS N-1: SIGNAL CONTROL REGISTER
BIT
7
6
5
NAME
TCMIINV
RCMIINV
LOLOR
TYPE
R/W
R/W
R/W
DFLT
VALUE
0
Transmit CMI Inversion:
This bit will flip the polarity of the transmit CMI data outputs at CMIxP/N.
For debug use only.
0: Normal
1: Invert
0
Receive CMI Inversion:
This bit will flip the polarity of the receive CMI data inputs at RXxP/N. For
debug use only.
0: Normal
1: Invert
0
Receive Loss of Lock/Signal Override:
When high, the RXLOL and RXLOS signals will always remain low.
0: Normal
1: Forces LOS and LOL outputs to be low and resets counters
NOTE: For reliable operation of the Rx LOL detection circuitry, one must
manually reset the LOL counter by toggling this bit upon power-up or
initialization.
4
RLBK
R/W
0
3
LLBK
R/W
0
2
1
0
RCLKP
TCLKP
FRST
Page: 13 of 42
R/W
R/W
R/W
DESCRIPTION
Analog Loopback Selection:
RLBK LLBK
0
0
Normal operation
1
0
Remote Loopback Enable: Recovered receive data
is looped back to the transmit driver for retransmission.
0
1
Local Loopback Enable: The transmit data is
looped back and used as the input to the receiver.
0
Receive Clock Inversion Select:
This bit will invert the receive output clock.
0: Normal. Data clocked out on falling edge of receive clock.
1: Invert. Data clocked out on the rising edge of receive clock.
0
Transmit Clock Inversion Select:
This bit will invert the transmit input system clock.
0: Normal. Data is clocked in on rising edge of the transmit clock.
1: Invert. Data is clocked in on the falling edge of the transmit clock.
0
FIFO Reset:
0: Normal operation
1: Reset FIFO pointers to default locations.
This reset should be initiated anytime the transmitter or IC powers up to
ensure the FIFO is centered after internal VCO clocks and external
transmit clocks are stable.
*Not required for Plesiochronous Serial Mode
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION (CONTINUED)
ADDRESS N-2: ADVANCED TRANSMIT CONTROL REGISTER 1
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7:1
--
R/W
0000000
Reserved.
0
TXEQ
R/W
Transmit Fixed Equalizer Enable:
When enabled, compensates for between 0.75m and 1.5m of FR4 trace
to the serial LVPECL data inputs SIxDP/N
0: Normal Operation
1: Enable equalizer
0
ADDRESS N-3: ADVANCED TRANSMIT CONTROL REGISTER 0
BIT
NAME
TYPE
DFLT
VALUE
7:3
--
R/W
10101
2:1
BST[1:0]
R/W
00
0
FLBK
R/W
0
DESCRIPTION
Reserved.
Transmit Driver Amplitude Boost:
Adds roughly 5% or 10% of boost to the CMI output. Limits not tested
during production test.
00 : Normal amplitude
01 : 5% boost
10 : Reserved
11 : 10% boost
Full Remote (digital) Loopback Enable:
When enabled the recovered receive data is decoded and looped back
to the transmit clock recovery unit exercising the entire receive and
transmit paths.
NOTE: Must be used in conjunction with Serial Plesiochronous Mode or
Serial Loop-Timing Mode.
ADDRESS N-4: MODE CONTROL REGISTER 2
BIT
NAME
TYPE
DFLT
VALUE
7
CMI
R/W
1
6:0
--
R/W
XX00000
Page: 14 of 42
DESCRIPTION
Line Interface Mode Selection:
0: Optical fiber (LVPECL, NRZ). CMI ENDEC and line driver are
disabled. Use RXxP/N and ECLxP/N pins for line interface.
1: Coaxial cable (CMI encoded). CMI ENDEC enabled. Optical
(NRZ) interface disabled. Use RXxP/N and CMIxP/N pins for
line interface.
Reserved.
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION (continued)
ADDRESS N-5: STATUS MONITOR REGISTER
BIT
NAME
TYPE
DFLT
VALUE
7:5
--
R/C
XXX
4
RXLOS
R/C
X
Receive Loss of Signal Indication:
0: Normal operation
1: Loss of signal condition detected
DESCRIPTION
Reserved.
3
RXLOL
R/C
X
Receive Loss of Lock Indication:
This status bit is only defined during a valid input signal at RxP/N or
when RXLOS=0
0: Normal operation
1: Recovered receive clock frequency differs from the reference by
more than +/- 100ppm.
2
--
R/C
X
Unused
X
Transmit Loss of Lock Indication:
This status bit is only defined and valid when using one of the serial
transmit modes utilizing the Tx CDR.
0: Valid transmit input signal detected at SIxDP/N
1: No valid signal detected at SIxDP/N
X
Transmit FIFO Error Indication:
This bit is set whenever the internal FERR signal is asserted, indicating
that the FIFO is operating at its depth limit. It is reset to 0 when the
FRST pin is asserted.
0: Normal operation
1: Transmit FIFO phase error
1
0
TXLOL
FERR
R/C
R/C
ADDRESS N-6, N-7: RESERVED
BIT
NAME
TYPE
DFLT
VALUE
7:0
RSVD
R/O
0
Page: 15 of 42
DESCRIPTION
Reserved for test.
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION
LEGEND
TYPE
A
CIT
CI
DESCRIPTION
Analog Pin
TYPE
PO
(Tie unused pins to ground)
3-State CMOS Digital Input
CO
CMOS Digital Input
COZ
(Tie unused pins to ground)
CIU
CMOS Digital Input w/ Pull-up
CID
CMOS Digital Input w/ Pull-down
CIS
PI
OD
CMOS Schmitt Trigger Input
(Tie unused pins to ground)
DESCRIPTION
LVPECL-Compatible Differential Output
(Tie unused pins to supply or leave floating)
CMOS Digital Output
(Leave unused pins floating)
CMOS Tristate Digital Output
(Leave unused pins floating)
Open-drain Digital Output
(Leave unused pins floating)
S
Supply
G
Ground
LVPECL-Compatible Differential Input
(Tie unused pins to ground)
TRANSMITTER PINS
NAME
PIN
PIx0D
PIx1D
PIx2D
PIx3D
31, 66
32, 65
33, 64
34, 63
PIxCK
30, 67
TYPE
CI
DESCRIPTION
Transmit (Parallel Mode) Data Input:
Four-bit CMOS parallel (nibble) inputs. Data is latched in on the rising edge
(default) of the transmit parallel clock and serialized with the MSB (PIx3D)
transmitted first.
CIS
Transmit (Parallel Mode) Clock Input:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock input that must be
source synchronous with the reference clock supplied at the CKREFP/N pins.
Used only in Slave Parallel Mode and Loop-timing Parallel Mode.
PTOxCK
35, 62
CO
Transmit (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output that is
intended to latch in synchronous parallel data. Active during reset. Used only
in Master Parallel Mode (output disabled in all other transmit modes).
SIxDP
SIxDN
10, 87
11, 86
PI
Transmit (Serial Mode) Data Input:
Differential NRZ data input. See Transmitter Operation section for more info
on different clocking/timing modes.
SIxCKP
SIxCKN
7, 90
8, 89
PI
Transmit (Serial Mode) Clock Input:
A 155.52MHz synchronous differential input clock used to clock in the serial
NRZ data. By default, data is clocked in on the rising edge of SIxCKP.
CMIxP
CMIxN
121, 104
122, 103
A
Transmit (Serial Mode) CMI Data Output:
A CMI encoded data signal conforming to the relevant ITU-T G.703 pulse
templates when properly terminated and transformer coupled to 75Ω cable.
Outputs are tri-stated when transmitter is disabled. Active, but undefined
during reset.
TXxCKP
TXxCKN
124, 101
125, 100
PO
Transmit (Serial Mode) Clock Output:
A 2x line rate LVPECL clock output used to clock out the transmit CMI data.
Used for diagnostics or far end re-timing. Active during reset.
ECLxP
ECLxN
127, 98
128, 97
PO
Transmit (Serial Mode) LVPECL Data Output:
Transmit NRZ data outputs used for interfacing with optical transceiver
modules when in Fiber (NRZ) mode.
Page: 16 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION (CONTINUED)
RECEIVER PINS
NAME
PIN
POx0D
POx1D
POx2D
POx3D
46, 51
45, 52
42, 55
41, 56
CO
CO
Receive (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output generated by
dividing down the recovered receive clock. By default, receive data is
clocked out on the falling edge. Active during reset.
Note: During Loss of Signal conditions, the clock will remain on the last
divided down phase selection of the Rx DLL and output a steady clock.
PO
Receive (Serial Mode) Data Output:
Recovered receive serial NRZ data at LVPECL levels. Active, but undefined
during reset.
Note: During Loss of Signal conditions, data outputs are held at logic 0.
25, 72
26, 71
PO
Receive (Serial Mode) Clock Output:
Recovered receive serial clock. By default, recovered serial NRZ data is
clocked out the falling edge of SOxCKP. Active during reset.
Note: During Loss of Signal conditions, the clock will remain on the last
phase selection of the Rx DLL and output a steady clock.
118, 107
119, 106
A/
PI
Receiver CMI or LVPECL Input:
The input is either transformer-coupled to coaxial cable for CMI data or ACcoupled at LVPECL levels to an optical transceiver module for NRZ data.
38, 59
SOxDP
SOxDN
28, 69
29, 68
RXxP
RXxN
Page: 17 of 42
DESCRIPTION
Receive (Parallel Mode) Data Output:
Recovered receive data deserialized into four-bit CMOS parallel (nibble)
outputs. The MSB (POx3D) is received first. Active, but undefined during
reset.
Note: During Loss of Signal conditions, data outputs are held low.
POxCK
SOxCKP
SOxCKN
TYPE
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION (CONTINUED)
REFERENCE AND STATUS PINS
Note: The LOSx, LOLx, and INTxXxB pins are configurable at final test (default open-drain outputs). If CMOS
level outputs are required, please refer to alternate 70Pxxxx ordering numbers at the end of the data sheet.
NAME
PIN
TYPE
DESCRIPTION
Reference Clock Input:
A required reference clock input used for clock/data recovery and frequency
synthesizer. Options include :
CKREFP
CKREFN
111
110
PI/
CI
• 139.264 MHz (E4) or 155.52 MHz (STM1) differential LVPECL clock
input at CKREFP/N
• 17.408 MHz (E4), 19.44 MHz (STM1), or 77.78 MHz (STM1) singleended CMOS clock input at CKREFP. Tie CKREFN to ground when
unused.
LOS1
LOS2
80
19
OD/
CO
Receive Loss of Signal (active-high):
See Receiver Loss of Signal description for conditions.
LOL1
LOL2
79
20
OD/
CO
Receive Loss of Lock (active-high):
This condition is met when the recovered clock frequency differs from the
reference clock frequency by more than +/- 100ppm.
INTTX1B
INTTX2B
88
9
OD/
CO
Transmitter Fault Interrupt Flag (active low):
When a transmitter error event occurs (as defined in the Interrupt Control
Register Description), the INTTXxB pin will change state to indicate an
interrupt. The interrupt is cleared by a read to the STAT Register, an issue
of a FRSTx FIFO reset pulse (if the FIERRx signal caused the interrupt), or
when the TXLOL register bit transitions from high to low.
Note: The default interrupt condition is a loss of lock in the transmitter CDR.
INTRX1B
INTRX2B
70
27
OD/
CO
Receiver Fault Interrupt Flag (active low):
Reserved for future use.
PORB
83
A
Page: 18 of 42
Power-On Reset (active low):
See Power-On Reset description on use of this pin.
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION (CONTINUED)
CONTROL PINS
NAME
PIN
TYPE
DESCRIPTION
FIFO Phase-Initialization Control:
When asserted, the transmit FIFO pointers are reset to the respective
“centered” states. Also resets the FIERR interrupt bit. De-assertion edge of
FRSTx will resume FIFO operation.
FRST
78
CIT
•
Low: Channel 1 FRST assertion
•
Float: Normal operation
• High: Channel 2 FRST assertion
Because the internal VCO clock and off-chip transmit clocks may not be
stable during transmit power-up, it is recommended to always reset the FIFOs
after powering up the IC or the transmitter.
Not valid during Plesiochronous Serial Mode.
Analog Loopback Selection:
LPBKx
17, 18
CIT
•
Low: Normal operation
•
Float: Remote Loopback Enable: Recovered receive data and clock
are looped back to the transmitter for retransmission.
•
High: Local Loopback Enable: The serial transmit data is looped back
and used as the input to the receiver.
Clock Mode Selection:
Selects the method of inputting transmit data into the chip. See
TRANSMITTER OPERATION section for more information.
In PARALLEL mode (SDI_PAR high):
CKMODE
Page: 19 of 42
15
CIT
•
Low: Parallel transmit clock is input to the 78P2352.
•
Float: Parallel transmit clock is input to the 78P2352. Loop-timing
mode enabled.
• High: Parallel transmit clock is output from the 78P2352
In SERIAL mode (SDI_PAR low):
•
Low: Reference clock is synchronous to transmit clock and data.
Data is clocked in with SIxCKP/N and passed through a FIFO
•
Float: Reference clock is synchronous to transmit data. Clock is
recovered with a CDR and data is passed through a FIFO
•
High: Reference clock is plesiochronous to transmit data. Clock is
recovered with a CDR and the FIFO is bypassed
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION (CONTINUED)
CONTROL PINS (continued)
NAME
TXOUT1
PIN
1
TYPE
DESCRIPTION
CIT
Advanced Tx Control 1:
Low: Enables fixed LVPECL equalizer at the transmit inputs SIDP/N for
FR4 trace lengths up to 1.5m.
Float: Normal operation
High: Normal operation
TXOUT0
2
CIT
Advanced Tx Control 0:
Low: Nominal amplitude
Float: 5% amplitude boost
High: 10% amplitude boost
TXPD
14
CID
Transmitter Power Down:
When high, powers down and tr-states the transmitt driver on both channels.
SPSL
77
CID
Serial Port Selection:
When high, chip is software controlled through the serial port.
CKSL
Page: 20 of 42
81
CIT
Reference Clock Frequency Selection:
Selects the reference frequency that is supplied at the CKREFP/N pins. Its
level is read in only at power-up or on the rising edge of a reset signal at the
PORB pin.
•
Low: 19.44MHz or 17.408MHz
•
Float: 77.76MHz
•
High: 155.52MHz or 139.264MHz
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION (CONTINUED)
SERIAL-PORT PINS
NAME
PIN
SEN_CMI
95
SCK_MON
96
SDI_PAR
94
SDO_E4
93
TYPE
DESCRIPTION
CIU
[SPSL=1] Serial-Port Enable:
High during read and write operations. Low disables the serial port.
While SEN is low, SDO remains in high impedance state, and SDI and
SCK activities are ignored.
[SPSL=0] Medium Select:
Low: Fiber (NRZ pass-through) mode
High: CMI mode
CIS
[SPSL=1] Serial Clock:
Controls the timing of SDI and SDO.
[SPSL=0] Receive Monitor Mode Enable:
When high, adds 20dB of flat gain to the incoming signal of both
channels before equalization.
NOTE: Channel specific monitor modes can be enabled through the
serial port. Rx Monitor Mode is only available in CMI mode
CI
[SPSL=1] Serial Data Input:
Inputs mode and address information. Also inputs register data during
a Write operation. Both address and data are input least significant bit
first.
[SPSL=0] Data Width Select:
Selects 4 bit parallel transmit modes (input high) or serial transmit
modes (input low)
COZ/
CI
[SPSL=1] Serial Data Output:
Outputs register information during a Read operation. Data is output
least significant bit first
[SPSL=0] Rate Select:
Selects E4 operation (input high) or STM1/STS3 operation (input low)
POWER AND GROUND PINS
It is recommended that all supply pins be connected to a single power supply plane and all ground pins be
connected to a single ground plane. See application note for decoupling guidelines.
NAME
PIN
TYPE
DESCRIPTION
VCC
5, 12, 21, 74, 85, 92, 99, 105,
109, 116, 120, 126
S
Power Supply
VDD
23, 37, 40, 44, 48, 49, 53, 57, 60
S
CMOS I/O Driver Supply
GND
6, 13, 16, 22, 73, 84, 91, 102,
108, 112, 113, 114, 115, 117,
123
G
Ground
VSS
24, 36, 39, 43, 47, 50, 54, 58, 61
G
CMOS I/O Driver Ground
82
G
Trim Ground
Used during production test. Connect directly to
ground. Do not decouple to supply or PORB.
TGND
Page: 21 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation beyond these limits may permanently damage the device.
PARAMETER
RATING
Supply Voltage (Vdd)
-0.5 to 4.0 VDC
Storage Temperature
-65 to 150 °C
Junction Temperature
-40 to 150 °C
Pin Voltage (CMIxP,CMIxN)
Vdd + 1.5 VDC
Pin Voltage (all other pins)
-0.3 to (Vdd+0.6) VDC
Pin Current
±100 mA
RECOMMENDED OPERATING CONDITIONS
Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges.
PARAMETER
RATING
DC Voltage Supply (Vdd)
3.15 to 3.45 VDC
Ambient Operating Temperature
-40 to 85 °C
Junction Temperature
-40 to 125 °C
DC CHARACTERISTICS:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
325
350
mA
Total Supply Current (CMI)
(including transmitter current
through transformer)
Idd
STM-1 mode;
CMI mode;
Max. cable length
Total Supply Current (NRZ)
Idde
STM-1 mode;
Fiber (NRZ) mode
290
310
mA
Iddr
Transmitter disabled;
STM-1 mode;
CMI mode;
Max. cable length
190
205
mA
Supply Current per Port (CMI)
(including transmitter current
through transformer)
Iddx
STM-1 mode;
CMI mode;
Max. cable length
160
180
mA
Power down Current
Iddq
PDTX = 1, PDRX = 1
7
10
mA
Receive-only Supply Current
Page: 22 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
ANALOG PINS CHARACTERISTICS:
The following table is provided for informative purpose only. Not tested in production.
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Ground Reference
1.9
2.1
2.6
V
RXxP and RXxN
Common-Mode Bias Voltage
Vblin
RXxP and RXxN Differential
Input Impedance
Rilin
20
kΩ
Analog Input/Output
Capacitance
Cin
8
pF
--
5
kΩ
PORB Input Impedance
DIGITAL I/O CHARACTERISTICS:
Pins of type CI, CIU, CID:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
Type CI, CID only
0.8
Type CIU only
0.4
UNIT
Input Voltage Low
Vil
V
Input Voltage High
Vih
2.0
Input Current
Iil, Iih
-1
0
1
µA
Pull-up Resistance
Rpu
Type CIU only
53
70
113
kΩ
Pull-down Resistance
Rpd
Type CID only
40
58
120
kΩ
Input Capacitance
Cin
V
8
pF
Pins of type CIT:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
0.4
V
Input Voltage Low
Vtil
Input Voltage High
Vtih
Vcc-0.6
V
Minimum impedance to be
considered as “float” state
Rtiz
30
kΩ
Pins of type CIS:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Low-to-High Threshold
Vt+
1.3
1.7
V
High-to-Low Threshold
Vt-
0.8
1.2
V
Iil, Iih
-1
1
µA
Input Current
Input Capacitance
Page: 23 of 42
Cin
2006 Teridian Semiconductor Corporation
8
pF
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
Pins of type CO and COZ:
PARAMETER
SYMBOL
CONDITIONS
Output Voltage Low
Vol
Iol = 8mA
Output Voltage High
Voh
Ioh = -8mA
Output Transition Time
Effective Source Impedance
Tri-state Output Leakage
Current
Tt
MIN
MAX
UNIT
0.4
V
2.4
V
CL = 20pF, 10-90%
2
Rscr
Iz
NOM
Ω
30
Type COZ only
-1
ns
1
µA
UNIT
Pins of type PO:
PARAMETER
SYMBOL
Signal Swing
Vpk
Common Mode Level
Vcm
Effective Source Impedance
Reff
CONDITIONS
MIN
NOM
MAX
0.5
0.8
1.1
TXxCKP/N pins
0.35
Vdd referenced
-1.55
0.95
-1.2
-1.1
V
V
Ω
20
Rise Time
Tr
10-90%
0.8
1.2
ns
Fall Time
Tf
10-90%
0.8
1.2
ns
Pins of type PI:
PARAMETER
Signal Swing
Common Mode Level
SYMBOL
Vpki
CONDITIONS
MIN
0.3
NOM
MAX
UNIT
V
Vcm
Vdd referenced
-1.6
-1.2
-0.8
V
SYMBOL
Vol
CONDITIONS
Iol = 8mA
MIN
NOM
MAX
0.4
UNIT
V
1
µA
10
kΩ
Pins of type OD:
PARAMETER
Output Voltage Low
Pull-down Leakage Current
Ipd
Pull-up Resistor
Rpu
Page: 24 of 42
Logic high output
2006 Teridian Semiconductor Corporation
4.7
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
SERIAL-PORT TIMING CHARACTERISTICS:
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
SDI to SCK setup time
tsu
4
ns
SDI to SCK hold time
th
4
ns
SCK to SDO propagation
delay
tprop
10
ns
SCK Frequency
SCK
20
MHz
CS
tsu
th
SCK
tsu th
SDI
X
1
SA0
tprop
SA1
SA2
SDO
PA0
PA1
PA2
PA3
X or Z
Z
D0
D1
D2
D3
D4
D5
D6
D7
Z
Figure 9: Read Operation
CS
tsu
th
SCK
tsu th
SDI
X
0
SDO
SA0
SA1
SA2
PA0
PA1
PA2
PA3
D0
D1
D2
D3
D4
D5
D6
D7
X
Z
Figure 10: Write Operation
Page: 25 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
TRANSMITTER TIMING CHARACTERISTICS:
PARAMETER
SYMBOL
CONDITIONS
MIN
Clock Duty Cycle
TTCF/TTC
PTOxCK
40
NOM
MAX
UNIT
60
%
Setup Time
TPS
Parallel mode
4
ns
Hold Time
TPH
Parallel mode
4
ns
Setup Time
TSS
Serial mode
2
ns
Hold Time
TSH
Serial mode
2
ns
TIMING DIAGRAM: Transmitter Waveforms
SIxCKN
SIxCKP
SIxDP
SIxDN
TSS
TSH
PIxCK
PIxD<0:3>
TPS
TRC = 25.72ns
TPH
TTCT
TRCF = 12.86ns
PTOxCK
PIxD<0:3>
TPS
Page: 26 of 42
2006 Teridian Semiconductor Corporation
TPH
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
REFERENCE CLOCK CHARACTERISTICS:
PARAMETER
SYMBOL
CKREF Duty Cycle
CONDITIONS
MIN
MAX
UNIT
40
60
%
Synchronous mode; E4
-15
+15
Synchronous mode; STM1
-20
+20
Plesiochronous or Loop-timing
mode. (see Note 1)
-75
+75
--
CKREF Frequency Stability
--
NOM
ppm
Note 1: In Plesiochronous mode, the transmit clock/data source (i.e. framer/system reference clock) must still
be of +/-20ppm quality (+/-15ppm for E4) in order to meet the ITU-T (or Telcordia) bit rate requirements.
RECEIVER TIMING CHARACTERISTICS:
PARAMETER
RCLK Duty Cycle
Clock to Q
SYMBOL
CONDITIONS
MIN
TRCF/TRC
NOM
MAX
UNIT
40
60
%
RSCQ
Serial mode
0
1
RPCQ
Parallel mode
-1
2
ns
TIMING DIAGRAM: Receive Waveforms
TRC = 6.43ns
TRCF = 3.215ns
SOxCKN
SOxCKP
SOxDP
SOxDN
RSCQ
TRCT
TRC = 25.72ns
TRCF = 12.86ns
POxCK
POxD<0:3>
RPCQ
Page: 27 of 42
2006 Teridian Semiconductor Corporation
TRCT
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE
Bit Rate: 139.264Mbps ± 15ppm or 155.52Mbps ± 20ppm
Code: Coded Mark Inversion (CMI)
Relevant Specification: ITU-T G.703, Telcordia GR-253, ANSI T1.102
With the coaxial output port driving a 75Ω load, the output pulses conform to the templates in Figures 11, 12,
13, and 14. These specifications are tested during production test. Consult application note for reference
schematic, layout guidelines, and recommended transformers.
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Peak-to-peak Output Voltage
(Fuse-trimmed to nominal target at
final test)
Template, steady state
0.9
1.05
1.1
V
Rise/ Fall Time
10-90%
2
ns
Negative Transitions
Transition Timing Tolerance
Transmit clock frequency stability
(PIxCK or SIxCKP/N )
Positive Transitions at Interval
Boundaries
Positive Transitions at midinterval
With respect to CKREF
-0.1
0.1
-0.5
0.5
-0.35
0.35
0
0
ns
ppm
The following specifications are not tested during production test. They are included for information only.
PARAMETER
CONDITION
Output Impedance
Driver is open drain
Return Loss
7MHz to 240MHz
Page: 28 of 42
2006 Teridian Semiconductor Corporation
MIN
NOM
1
8
15
MAX
UNIT
MΩ
pF
dB
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
V
0.60
0.55
T = 7.18ns
(Note 1)
(Note 1)
0.50
0.45
0.40
1.795 ns
1ns
0.1ns
1ns
0.1ns
-0.05
1.795 ns
1ns
0.1ns
0.35ns
0.05
Nominal
Pulse
0.1ns
0.35ns
Nominal
Zero Level
(Note 2)
-0.40
1ns
-0.45
1ns
1.795 ns
-0.50
-0.55
(Note 1)
-0.60
1ns
1.795 ns
(Note 1)
Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into
the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than
0.05V.
Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of
the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input
signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any
such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again
and verifying that the trace lies with ±0.05V of the nominal zero level of the masks.
Note 3 – Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or
succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish
edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing
signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask,
it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by
several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output
circuits with the same clock signal].
Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed
2ns.
Figure 11 – Mask of a Pulse corresponding to a binary Zero in E4 mode
Page: 29 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
V
0.60
0.55
T = 7.18ns
(Note 1)
(Note 1)
0.50
0.45
0.40
1ns
0.1ns
1ns
0.5ns
0.1ns
0.5ns
Nominal
Pulse
0.05
-0.05
Nominal
Zero Level
(Note 2)
3.59ns
3.59ns
1.35ns
-0.40
1.35ns
1ns
-0.45
1ns
1.795 ns
-0.50
-0.55
1.795 ns
(Note 1)
-0.60
Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into
the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than
0.05V.
Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of
the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input
signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any
such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again
and verifying that the trace lies with ±0.05V of the nominal zero level of the masks.
Note 3 – Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or
succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish
edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing
signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask,
it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by
several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output
circuits with the same clock signal].
Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed
2ns.
Note 5 –The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive
transitions are ± 0.1ns and ±0.5ns respectively.
Figure 12 – Mask of a Pulse corresponding to a binary One in E4 mode.
Page: 30 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
V
0.60
T = 6.43ns
(Note 1)
0.55
(Note 1)
0.50
1.608ns
1ns
0.45
0.1ns
0.40
1ns
0.1ns
1.608ns
1ns
0.1ns
0.35ns
0.05
Nominal
Pulse
0.1ns
0.35ns
Nominal
Zero Level
(Note 2)
-0.05
-0.40
1ns
-0.45
1ns
1.608ns
-0.50
-0.55
1.608ns
(Note 1)
-0.60
1ns
(Note 1)
Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into
the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than
0.05V.
Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of
the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input
signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any
such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again
and verifying that the trace lies with ±0.05V of the nominal zero level of the masks.
Note 3 – Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or
succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish
edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing
signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask,
it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by
several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output
circuits with the same clock signal].
Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed
2ns.
Figure 13 – Mask of a Pulse corresponding to a binary Zero in STS-3/STM-1 mode.
Page: 31 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
V
0.60
0.55
6.43ns
(Note 1)
(Note 1)
0.50
0.45
0.40
1ns
0.1ns
1ns
0.5ns
0.1ns
0.5ns
Nominal
Pulse
0.05
-0.05
Nominal
Zero Level
(Note 2)
3.215ns
3.215ns
1.2ns
-0.40
-0.45
-0.50
1.2ns
1ns
1ns
1.608ns
-0.55
-0.60
1.608ns
(Note 1)
Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into
the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than
0.05V.
Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of
the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input
signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any
such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again
and verifying that the trace lies with ±0.05V of the nominal zero level of the masks.
Note 3 – Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or
succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish
edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing
signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask,
it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by
several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output
circuits with the same clock signal].
Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed
2ns.
Note 5 –The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive
transitions are ± 0.1ns and ±0.5ns respectively.
Figure 14 – Mask of a Pulse corresponding to a binary One in STS-3/STM-1 mode
Page: 32 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
TRANSMITTER OUTPUT JITTER
The transmit jitter specification ensures compliance with ITU-T G.813, G.823, G.825 and G.958; ANSI T1.1021993 and T1.105.03-1994; and GR-253-CORE for all supported rates. Transmit output jitter is not tested during
production test.
Jitter
Detector
Measured Jitter
Amplitude
20dB/decade
Transmitter
Output
f1
PARAMETER
Transmitter Output Jitter
Page: 33 of 42
f2
CONDITION
MAX
UNIT
CMI Mode;
200 Hz to 3.5 MHz, measured
with respect to CKREF for 60s
0.075
UIpp
NRZ (optical) Mode;
12 kHz to 1.3 MHz, measured
with respect to CKREF
0.01
UIrms
2006 Teridian Semiconductor Corporation
MIN
NOM
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER SPECIFICATIONS FOR CMI INTERFACE (Transformer-coupled)
Consult application note for reference schematic, layout guidelines, and recommended transformers.
PARAMETER
CONDITION
Peak Differential Input
Amplitude, RXxP and RXxN
CMI mode; MON=0;
12.7dB of cable loss
CMI mode; MON=1;
20dB flat loss w/ 6dB of cable loss
CMI mode; MON=0;
All valid cable lengths.
STM-1 mode; CMI mode;
12.7 dB cable loss
a) Normal receive mode
b) Remote loopback mode
Peak Differential Input
Amplitude, RXxP and RXxN
Flat-loss Tolerance
Receive Clock Jitter
MIN
MAX
UNIT
70
550
mVpk
25
80
mVpk
-2
6
dB
0.1
0.07
10
10
UIpp
UIpp
UI
µs
Latency
PLL Lock Time
TYP
5
1
Return Loss
7MHz to 240MHz
15
dB
The input signal is assumed compliant with ITU-T G.703 and can be attenuated by the dispersive loss of a
cable. The minimum cable loss is 0dB and the maximum is –12.7dB at 78MHz.
The “Worst Case” line corresponds to the ITU-T G.703 recommendation. The “Typical” line corresponds to a
typical installation referred to in ANSI T1.102-1993. The receiver is tested using the cable model. It is a lumped
element approximation of the “Worst Case” line.
30
Attenuation (dB)
25
20
15
10
5
0
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1.00E+09
Frequency (Hz)
Worst Case
Typical
Figure 15: Typical and worst-case Cable attenuation
Page: 34 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER JITTER TOLERANCE
The 78P2352 exceeds all relevant jitter tolerance specifications shown in Figures 16, 17. STS-3/OC-3 jitter
tolerance specifications are in ANSI T1.105.03-1994 and Telcordia GR-253-CORE. STM-1 (optical) jitter
tolerance specifications are in ITU-T G.813, G.825, and G.958. STM-1e (electrical) jitter tolerance
specifications are in ITU-T G.825. E4 specifications are found in ITU-T G.823. Receive jitter tolerance is not
tested during production test.
100
Electrical (CMI) Interfaces
G.825 - STM-1e Tolerance
(for 2048 kbps networks)
G.825 - STM-1e Tolerance
(for 1544 kbps networks)
10
Jitter Tolerance ( UIpp )
G.823 - E4 Tolerance
1
0.1
0.01
1.E+00
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
Jitter Frequency
Figure 16: Jitter Tolerance - electrical (CMI) interfaces
PARAMETER
E4 Jitter Tolerance
CONDITION
MIN
200Hz to 500Hz
1.5
500Hz to 10kHz
UNIT
µs
10kHz to 3.5MHz
0.075
UIpp
10Hz to 19.3Hz
38.9
UIpp
500Hz to 6.5kHz
750 f-1
1.5
6.5kHz to 65kHz
65kHz to 1.3MHz
Page: 35 of 42
MAX
UIpp
750 f-1
19.3Hz to 500Hz
STM-1e Jitter Tolerance
NOM
UIpp
9800 f-1
0.15
2006 Teridian Semiconductor Corporation
µs
µs
UIpp
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
100
Optical (NRZ) Interfaces
G.813, G.958, T1.105.03, GR-253
STM-1 / STS-3 / OC-3 Tolerance
G.825 - STM-1 Tolerance
Jitter Tolerance ( UIpp )
10
1
0.1
0.01
1.E+00
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
Jitter Frequency
Figure 17: Jitter Tolerance - optical (NRZ) interfaces
PARAMETER
CONDITION
MIN
10Hz to 19.3Hz
38.9
19.3Hz to 68.7Hz
OC-3/STS-3/STM-1 (optical)
Jitter Tolerance
68.7Hz to 6.5kHz
Page: 36 of 42
1.5
2006 Teridian Semiconductor Corporation
UNIT
µs
UIpp
9800 f-1
0.15
MAX
UIpp
750 f-1
6.5kHz to 65kHz
65kHz to 1.3MHz
NOM
µs
UIpp
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER JITTER TRANSFER FUNCTION
The receiver clock recovery loop filter characteristics such that the receiver has the following transfer function.
The corner frequency of the Rx DLL is approximately 120 kHz. Receiver jitter transfer function is not tested
during production test.
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
1.00E+03
1.00E+04
1.00E+05
1.00E+06
1.00E+07
Figure 18: Jitter Transfer
PARAMETER
CONDITION
Receiver Jitter transfer function
below 120 kHz
Jitter transfer function roll-off
Page: 37 of 42
MIN
NOM
20
2006 Teridian Semiconductor Corporation
MAX
UNIT
0.1
dB
dB per
decade
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
ELECTRICAL SPECIFICATIONS (continued)
CMI MODE LOSS OF SIGNAL CONDITION
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
LOS threshold
Combination of cable loss at 78MHz
and flat loss
-35
-19
-15
dB
10
110
255
UI
LOS timing
Nominal value
Maximum
cable loss
3 dB
15dB
Loss of Signal must be cleared
Tolerance range
LOS can be detected or cleared
35dB
Loss of Signal must be declared
APPLICATION INFORMATION
EXTERNAL COMPONENTS:
COMPONENT
Receiver Termination Resistor, CMI Mode
Transmitter Termination Resistor, CMI Mode
PIN(S)
RXxP
RXxN
CMIxP
CMIxN
VALUE
UNITS
TOLERANCE
75
Ω
1%
75
Ω
1%
VALUE
UNITS
TOLERANCE
(CMI) TRANSFORMER SPECIFICATIONS:
COMPONENT
Turns Ratio for the Receiver
1:1
Turns Ratio for the Transmitter (center-tapped)
Suggested Manufacturers: Halo, Tamura, MiniCircuits, Belfuse
1:1CT
THERMAL INFORMATION:
PACKAGE
CONDITIONS
Standard 128-pin JEDEC LQFP (78P2352-IGT)
No forced air;
4-layer JEDEC test board
(Recommended) Thernally enhanced
Exposed Pad 128-pin JEDEC LQFP (78P2352-IEL)
No forced air;
4-layer JEDEC test board;
Die attach pad soldered to PCB
ΘJA ( ˚C/W)
46
24.8
SCHEMATICS
For reference schematics, layout guidelines, recommended transformer part numbers, etc. please check Teridian
Semiconductor's website or contact your local sales representative for the latest application note(s) and/or demo
board manuals.
Page: 38 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
MECHANICAL SPECIFICATIONS
16.000 +/- 0.200
14.000 +/- 0.100
12.400 REF.
128
16.000 +/- 0.200
5.00 REF.
14.000 +/- 0.100
1
MAX.
EXPOSED
PAD AREA
5.00 REF.
13.950 +/- 0.100
MAX. 1.600
1.400 +/- 0.050
0.180 +/- 0.050
0.400
0.100 +/- 0.050
0.600 +/- 0.150
78P2352-IEL
128-pin Exposed Pad JEDEC LQFP
(Bottom View)
Page: 39 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
MECHANICAL SPECIFICATIONS
15.8 (0.622)
16.2 (0.637)
15.8 (0.622)
16.2 (0.637)
Top View
13.8 (0.543)
14.2 (0.559)
0.05 (0.002)
0.15 (0.006)
0.40 Typ. .
(0.015)
0.60 Typ.
(0.024)
1.60 Max
(0.063)
0.13 (0.005)
0.23 (0.009)
Side View
78P2352-IGT
128-pin Standard JEDEC LQFP (Top View)
Page: 40 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PACKAGE INFORMATION
1
2
96
95
3
4
5
94
93
92
6
91
7
8
90
89
9
10
11
88
87
86
12
85
13
14
15
16
17
84
83
82
81
80
78P2352
73
72
71
27
70
28
29
30
69
68
67
31
66
32
65
62
63
64
24
25
26
52
53
54
55
56
57
58
59
60
61
75
74
43
44
45
46
47
48
49
50
51
22
23
39
40
41
42
78
77
76
37
38
79
19
20
21
33
34
35
36
18
SCK_MON
SEN_CMI
SDI_PAR
SDO_E4
VCC
GND
SI2CKP
SI2CKN
INTTX1B
SI2DP
SI2DN
VCC
GND
PORB
TGND
CKSL
LOS1
LOL1
FRST
SPSL
N/C
N/C
VCC
GND
SO2CKP
SO2CKN
INTRX1B
SO2DP
SO2DN
PI2CK
PI20D
PI21D
PI12D
PI13D
PTO1CK
VSS
VDD
PO1CK
VSS
VDD
PO13D
PO12D
VSS
VDD
PO11D
PO10D
VSS
VDD
VDD
VSS
PO20D
PO21D
VDD
VSS
PO22D
PO23D
VDD
VSS
PO2CK
VDD
VSS
PTO2CK
PI23D
PI22D
TXOUT1
TXOUT0
N/C
N/C
VCC
GND
SI1CKP
SI1CKN
INTTX2B
SI1DP
SI1DN
VCC
GND
TXPD
CKMODE
GND
LPBK1
LPBK2
LOS2
LOL2
VCC
GND
VDD
VSS
SO1CKP
SO1CKN
INTRX2B
SO1DP
SO1DN
PI1CK
PI10D
PI11D
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
ECL1N
ECL1P
VCC
TX1CKN
TX1CKP
GND
CMI1N
CMI1P
VCC
RX1N
RX1P
GND
VCC
GND
GND
GND
GND
CKREFP
CKREFN
VCC
GND
RX2P
RX2N
VCC
CMI2P
CMI2N
GND
TX2CKP
TX2CKN
VCC
ECL2P
ECL2N
(Top View)
ORDERING INFORMATION
PART DESCRIPTION
128-pin LQFP,
Open-drain outputs for LOSx, LOLx, INTTRx
ORDER NUMBER
78P2352-IGT
PACKAGE MARK
78P2352-IGT
xxxxxxxxxxP6
128-pin LQFP,
CMOS type outputs for LOSx, LOLx, INTTRx
70P2352-IGT
70P2352-IGT
xxxxxxxxxxP6
128-pin LQFP w/ Exposed Solder Pad,
Open-drain outputs for LOSx, LOLx, INTTRx
78P2352-IEL
78P2352-IEL
xxxxxxxxxxP6
Tape & Reel option
append ‘R’
Lead-free option
append ‘/F’
Page: 41 of 42
2006 Teridian Semiconductor Corporation
n/a
xxxxxxx-xxx
xxxxxxxxxxP6F
Rev. 2.4
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
-v2-0
v2-2
v2-3
v2-4
Revison History
Contact Teridian for revision history of earlier releases
March 14, 2005: Final Datasheet Release
Updated Ordering Numbers to reflect production silicon revision A06
Improved/modified Functional Descriptions for:
o Reference Clock, Rx LOS & LOL detectors, Synchronous (Re-Timing) Transmit
Modes, Tx FIFO, Tx Driver, Tx LOL detector, and Power-on Reset description
Improved/modified Register Descriptions for:
o xCMIINV invert bits, FRST, RxLOL, and TxLOL
Improved/modified Pin Descriptions for:
o PTOCK, FRST, SEN_CMI, GND pin 63
Updated Electrical Specification min/max limits for:
o DC Characteristics,
o CID, CIU, CIT, and PO pin types
o CMI Loss of Signal Conditions
August 12, 2005:
Changed name and logo from TDK to Teridian
Updated Rx and Tx Loss of Lock descriptions
Added Full Remote (digital) Loopback and updated Remote (analog) Loopback descriptions
August 15, 2006
Updated Ordering Numbers to remove silicon revision A06
Updated Package Mark from C6 to P6
September 20, 2006
Corrected several typos in the mechanical drawing of IGT package
If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. Teridian Semiconductor Corporation
(TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a
data sheet is current before placing orders. TSC assumes no liability for applications assistance.
Teridian Semiconductor Corp., 6440 Oak Canyon, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridiansemiconductor.com
Page: 42 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4