54ABT/74ABT373 Octal Transparent Latch with TRI-STATEÉ Outputs Y General Description Y The ’ABT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. Features Y Y Y Y Y Y Y Y TRI-STATE outputs for bus interfacing Output sink capability of 64 mA, source capability of 32 mA Commercial Military Guaranteed output skew Guaranteed multiple output switching specifications Output switching specified for both 50 pF and 250 pF loads Guaranteed simultaneous switching, noise level and dynamic threshold performance Guaranteed latchup protection High impedance glitch free bus loading during entire power up and power down Nondestructive hot insertion capability Standard Military Drawing (SMD) 5962-9321801 Package Number Package Description 20-Lead (0.300× Wide) Molded Small Outline, JEDEC 74ABT373CSC (Note 1) M20B 74ABT373CSJ (Note 1) M20D 20-Lead (0.300× Wide) Molded Small Outline, EIAJ 74ABT373CPC N20B 20-Lead (0.300× Wide) Molded Dual-In-Line 54ABT373J/883 J20A 20-Lead Ceramic Dual-In-Line MSA20 20-Lead Molded Shrink Small Outline, EIAJ Type II 54ABT373W/883 W20A 20-Lead Cerpack 54ABT373E/883 E20A 20-Lead Ceramic Leadless Chip Carrier, Type C MTC20 20-Lead Molded Thin Shrink Small Outline, JEDEC 74ABT373CMSA (Note 1) 74ABT373CMTC (Notes 1, 2) Note 1: Devices also available in 13× reel. Use suffix e SCX, SJX, MSAX, and MTCX. Note 2: Contact factory for package availability. Connection Diagrams Pin Assignment for DIP, SOIC, SSOP and Flatpak Pin Assignment for LCC Pin Names D0 –D7 LE OE O0 –O7 Description Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) TRI-STATE Latch Outputs TL/F/11547 – 2 TL/F/11547–1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/11547 RRD-B30M115/Printed in U. S. A. 54ABT/74ABT373 Octal Transparent Latch with TRI-STATE Outputs September 1995 Functional Description Truth Table The ’ABT373 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Output LE OE Dn On H H L X L L L H H L X X H L On (no change) Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance State Logic Diagram TL/F/11547 – 3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) b 150 mA DC Latchup Source Current: OE Pin (Across Comm Operating Range) Other Pins b500 mA If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Ceramic Plastic b 55§ C to a 125§ C Over Voltage Latchup (I/O) Note 2: Either voltage limit or current limit is sufficient to protect inputs. b 55§ C to a 175§ C b 55§ C to a 150§ C VCC Pin Potential to Ground Pin Recommended Operating Conditions b 0.5V to a 7.0V Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial Minimum Input Edge Rate Data Input Enable Input b 0.5V to a 7.0V b 30 mA to a 5.0 mA b 0.5V to a 5.5V b 0.5V to VCC Current Applied to Output in LOW State (Max) 10V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. twice the rated IOL (mA) b 55§ C to a 125§ C b 40§ C to a 85§ C a 4.5V to a 5.5V a 4.5V to a 5.5V (DV/Dt) 50 mV/ns 20 mV/ns DC Electrical Characteristics Symbol ABT373 Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage Min Typ Max 2.0 54ABT/74ABT 54ABT 74ABT VCC Conditions V Recognized HIGH Signal 0.8 V Recognized LOW Signal b 1.2 V Min IIN e b18 mA V Min IOH e b3 mA IOH e b24 mA IOH e b32 mA 0.55 0.55 V Min IOL e 48 mA IOL e 64 mA 5 5 mA Max VIN e 2.7V (Note 2) VIN e VCC 7 mA Max VIN e 7.0V mA Max VIN e 0.5V (Note 2) VIN e 0.0V V 0.0 IID e 1.9 mA All Other Pins Grounded 2.5 2.0 2.0 VOL Output LOW Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test IIL Input LOW Current VID Input Leakage Test IOZH Output Leakage Current 50 mA 0 b 5.5V VOUT e 2.7V; OE e 2.0V IOZL Output Leakage Current b 50 mA 0 b 5.5V VOUT e 0.5V; OE e 2.0V IOS Output Short-Circuit Current b 275 mA Max VOUT e 0.0V ICEX Output High Leakage Current 50 mA Max IZZ Bus Drainage Test 100 mA 0.0 VOUT e VCC VOUT e 5.5V; All Others GND ICCH Power Supply Current 50 mA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current Max OE e VCC All Others at VCC or GND ICCT Additional ICC/Input Max VI e VCC b 2.1V Enable Input VI e VCC b 2.1V Data Input VI e VCC b 2.1V All Others at VCC or GND Max Outputs Open, LE e VCC OE e GND, (Note 1) One Bit Toggling, 50% Duty Cycle ICCD Dynamic ICC (Note 2) 54ABT 74ABT Units b5 b5 4.75 b 100 Outputs Enabled Outputs TRI-STATE Outputs TRI-STATE 50 mA 2.5 2.5 2.5 mA mA mA 0.12 mA/ MHz No Load Note 1: For 8 bits toggling, ICCD k 0.8 mA/MHz. Note 2: Guaranteed, but not tested. 3 DC Electrical Characteristics Symbol (SOIC Package) (Continued) Parameter Min Typ Max Units VCC Conditions CL e 50 pF, RL e 500X 0.4 0.8 V 5.0 TA e 25§ C (Note 1) b 1.2 b 0.8 V 5.0 TA e 25§ C (Note 1) VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VOHV Minimum High Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA e 25§ C (Note 3) VIHD Minimum High Level Dynamic Input Voltage 2.0 1.7 V 5.0 TA e 25§ C (Note 2) VILD Maximum Low Level Dynamic Input Voltage V 5.0 TA e 25§ C (Note 2) 0.9 0.6 Note 1: Max number of outputs defined as (n). n b 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. Note 2: Max number of data inputs (n) switching. n b 1 inputs switching 0V to 3V. Input-under-test switching: 3V to theshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 3: Max number of outputs defined as (n). n b 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter 74ABT 54ABT 74ABT TA e a 25§ C VCC e a 5.0V CL e 50 pF TA e b55§ C to a 125§ C VCC e 4.5V to 5.5V CL e 50 pF TA e b40§ C to a 85§ C VCC e 4.5V to 5.5V CL e 50 pF Units Min Typ Max Min Max Min Max tPLH tPHL Propagation Delay Dn to On 1.9 1.9 2.7 2.8 4.5 4.5 1.0 1.0 6.8 7.0 1.9 1.9 4.5 4.5 ns tPLH tPHL Propagation Delay LE to On 2.0 2.0 3.1 3.0 5.0 5.0 1.0 1.5 7.7 7.7 2.0 2.0 5.0 5.0 ns tPZH tPZL Output Enable Time 1.5 1.5 3.1 3.1 5.3 5.3 1.0 1.5 6.7 7.2 1.5 1.5 5.3 5.3 ns tPHZ tPLZ Output Disable Time 2.0 2.0 3.6 3.4 5.4 5.4 1.7 1.0 8.0 7.0 2.0 2.0 5.4 5.4 ns AC Operating Requirements Symbol Parameter Min 74ABT 54ABT 74ABT TA e a 25§ C VCC e a 5.0V CL e 50 pF TA e b55§ C to a 125§ C VCC e 4.5V to 5.5V CL e 50 pF TA e b40§ C to a 85§ C VCC e 4.5V to 5.5V CL e 50 pF Typ 100 Max Min Max Min 100 Units Max ftoggle Max Toggle Frequency ts(H) ts(L) Setup Time, HIGH or LOW Dn to LE 1.5 1.5 2.5 2.5 1.5 1.5 ns th(H) th(L) Hold Time, HIGH or LOW Dn to LE 1.0 1.0 2.5 2.5 1.0 1.0 ns tw(H) Pulse Width, LE HIGH 3.0 3.3 3.0 ns 4 MHz Extended AC Electrical Characteristics (SOIC package) 74ABT Symbol 74ABT TA e b40§ C to a 85§ C VCC e 4.5V to 5.5V CL e 50 pF Parameter 8 Outputs Switching (Note 4) 74ABT TA e b40§ C to a 85§ C VCC e 4.5V to 5.5V CL e 250 pF (Note 5) TA e b40§ C to a 85§ C VCC e 4.5V to 5.5V CL e 250 pF Units 8 Outputs Switching (Note 6) Min Max Min Max Min Max tPLH tPHL Propagation Delay Dn to On 1.5 1.5 5.2 5.2 2.0 2.0 6.8 6.8 2.0 2.0 9.0 9.0 ns tPLH tPHL Propagation Delay LE to On 1.5 1.5 5.5 5.5 2.0 2.0 7.5 7.5 2.0 2.0 9.5 9.5 ns tPZH tPZL Output Enable Time 1.5 1.5 6.2 6.2 2.0 2.0 8.0 8.0 2.0 2.0 10.5 10.5 ns tPHZ tPZL Output Disable Time 1.0 1.0 5.5 5.5 (Note 7) (Note 7) ns Note 4: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 5: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in plce of the 50 pF load capacitors in the standard AC load. This specificaiton pertains to single output switching only. Note 6: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 7: The TRI-STATE delay times are dominated by the RC network (500X, 250 pF) on the output and has been excluded from the datasheet. Skew Symbol Parameter 74ABT 74ABT TA e b40§ C to a 85§ C VCC e 4.5V–5.5V CL e 50 pF 8 Outputs Switching (Note 3) TA e b40§ C to a 85§ C VCC e 4.5V–5.5V CL e 250 pF 8 Outputs Switching (Note 4) Units Max Max tOSHL (Note 1) Pin to Pin Skew HL Transitions 1.0 1.5 ns tOSLH (Note 1) Pin to Pin Skew LH Transitions 1.0 1.5 ns tPS (Note 5) Duty Cycle LH–HL Skew 1.4 3.5 ns tOST (Note 1) Pin to Pin Skew LH/HL Transitions 1.5 3.9 ns tPV (Note 2) Device to Device Skew LH/HL Transitions 2.0 4.0 ns Note 1: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to LOW (tOST). This specification is guaranteed but not tested. Note 2: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 4: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 5: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. 5 Capacitance Symbol Parameter Typ Units Conditions (TA e 25§ C) CIN Input Capacitance 5 pF VCC e 0V COUT (Note 1) Output Capacitance 9 pF VCC e 5.0V Note 1: COUT is measured at frequency f e 1 MHz, per MIL-STD-883B, Method 3012. tPLH vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to Output tPHL vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to Output TL/F/11547–11 TL/F/11547 – 12 tPZH vs Temperature (TA) CL e 50 pF, 1 Output Switching OE to Output tPZL vs Temperature (TA) CL e 50 pF, 1 Output Switching OE to Output TL/F/11547–13 TL/F/11547 – 14 tPHZ vs Temperature (TA) CL e 50 pF, 1 Output Switching OE to Output tPLZ vs Temperature (TA) CL e 50 pF, 1 Output Switching OE to Output TL/F/11547–15 TL/F/11547 – 16 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 6 tSET LOW vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to LE tSET HIGH vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to LE TL/F/11547 – 17 TL/F/11547 – 18 tHOLD HIGH vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to LE tHOLD LOW vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to LE TL/F/11547 – 19 TL/F/11547 – 20 tPLH vs Temperature (TA) CL e 50 pF, 8 Outputs Switching Data to Output tPHL vs Temperature (TA) CL e 50 pF, 8 Outputs Switching Data to Output TL/F/11547 – 21 TL/F/11547 – 22 tPZH vs Temperature (TA) CL e 50 pF, 8 Outputs Switching OE to Output tPZL vs Temperature (TA) CL e 50 pF, 8 Outputs Switching OE to Output TL/F/11547 – 23 TL/F/11547 – 24 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 7 tPHZ vs Temperature (TA) CL e 50 pF, 8 Outputs Switching OE to Output tPLZ vs Temperature (TA) CL e 50 pF, 8 Outputs Switching OE to Output TL/F/11547–25 TL/F/11547 – 26 tPLH vs Load Capacitance TA e 25§ C, 1 Output Switching Data to Output tPHL vs Load Capacitance TA e 25§ C, 1 Output Switching Data to Output TL/F/11547–27 TL/F/11547 – 28 tPLH vs Load Capacitance TA e 25§ C, 8 Outputs Switching Data to Output tPHL vs Load Capacitance TA e 25§ C, 8 Outputs Switching Data to Output TL/F/11547–29 TL/F/11547 – 30 tPZH vs Load Capacitance TA e 25§ C, 8 Outputs Switching OE to Output tPZL vs Load Capacitance TA e 25§ C, 8 Outputs Switching OE to Output TL/F/11547–31 TL/F/11547 – 32 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 8 tPLH vs Temperature (TA) CL e 50 pF, 1 Output Switching LE to Output tPHL vs Temperature (TA) CL e 50 pF, 1 Output Switching LE to Output TL/F/11547 – 35 TL/F/11547 – 36 tPLH vs Temperature (TA) CL e 50 pF, 8 Outputs Switching LE to Output tPHL vs Temperature (TA) CL e 50 pF, 8 Outputs Switching LE to Output TL/F/11547 – 37 TL/F/11547 – 38 Typical ICC vs Output Switching Frequency CL e 0 pF, VCC e VIH e 5.5V, LE e GND, 1 Output Switching at 50% Duty Cycle Data to Output, Transparent Mode with Unused Data Inputs e VIH tPLH and tPHL vs Number Outputs Switching CL e 50 pF, TA e 25§ C, VCC e 5.0V, Outputs In Phase Data to Output TL/F/11547 – 33 TL/F/11547 – 34 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 9 AC Loading TL/F/11547–4 *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load TL/F/11547 – 5 FIGURE 4. Propagation Delay, Pulse Width Waveforms TL/F/11547–6 TL/F/11547 – 7 FIGURE 2a. Test Input Signal Levels FIGURE 5. TRI-STATE Output HIGH and LOW Enable and Disable Times Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 2b. Test Input Signal Requirements TL/F/11547 – 9 FIGURE 6. Setup Time, Hold Time and Recovery Time Waveforms TL/F/11547–8 FIGURE 3. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 10 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: TL/F/11547 – 39 11 Physical Dimensions inches (millimeters) 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A 12 Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A 20-Lead Small Outline Integrated Circuit JEDEC (S) NS Package Number M20B 13 Physical Dimensions inches (millimeters) (Continued) 20-Lead Small Outline Integrated Circuit EIAJ (SJ) NS Package Number M20D 20-Lead Plastic EIAJ SSOP (MSA) NS Package Number MSA20 14 Physical Dimensions inches (millimeters) (Continued) All dimensions are in millimeters. 20-Lead Molded Thin Shrink Small Outline Package JEDEC (MTC) NS Package Number MTC20 20-Lead Plastic Dual-In-Line Package (P) NS Package Number N20B 15 54ABT/74ABT373 Octal Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.