74ACT374 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 260 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The ACT374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. These 8 bit D-Type flip-flops are controlled by a clock input (CK) and an output enable input (OE). B M (Plastic Package) (Micro Package) ORDER CODES : 74ACT374B 74ACT374M On the positive transition of the clock, the Q outputs will be set to logic state that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The output control does not affect the internal operation of flip flop; that is, the old data can be retained or the new data can be entered even while the outputs are off. The device is designed to interface directly High Speed CMOS system with TTL and NMOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/10 74ACT374 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE NAME AND F UNCTIO N 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 3 State Outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data Inputs 11 CLOCK Clock Input (LOW to HIGH, edge triggered) 10 GND Ground (0V) 20 VCC Positive Supply Voltage 3 State Output Enable Input (Active LOW) TRUTH TABLE INPUT S CK D H X X Z X NO CHANGE L Q L L L L H H X: DON’T CARE Z: HIGH IMPEDANCE LOGIC DIAGRAMS 2/10 OUT PUT S OE 74ACT374 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 400 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o C 300 o C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol Valu e Unit Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC VCC Top dt/dv Parameter Operating Temperature: Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) -40 to +85 8 V o C ns/V 1) VIN from 0.8 V to 2.0 V 3/10 74ACT374 DC SPECIFICATIONS Symbol Parameter Test Con dition s VIH High Level Input Voltage 4.5 5.5 VIL Low Level Input Voltage 4.5 5.5 VOH High Level Output Voltage Low Level Output Voltage VO = 0.1 V or VCC - 0.1 V Unit -40 to 85 o C Min. Typ. 2.0 1.5 2.0 2.0 1.5 2.0 VO = 0.1 V or VCC - 0.1 V Max. Min . 0.8 0.8 0.8 0.8 4.4 4.49 4.4 5.4 5.49 5.4 IO=-24 mA 3.86 5.5 IO=-24 mA 4.86 4.5 IO=50 µA 0.001 IO=50 mA 0.001 5.5 4.5 (*) VI = V IH or V IL V I (*) = V IH or V IL V 1.5 IO=-50 µA 5.5 Max. 1.5 IO=-50 µA 4.5 4.5 VOL Value T A = 25 oC V CC (V) V V 3.76 4.76 0.1 0.1 0.1 0.1 IO=24 mA 0.36 0.44 IO=24 mA V 0.36 0.44 5.5 VI = VCC or GND ±0.1 ±1 µA 3 State Output Leakage Current 5.5 VI = VIH or VIL VO = VCC or GND ±0.5 ±5 µA ICCT Max ICC /Input 5.5 VI = VCC -2.1 V 1.5 mA ICC Quiescent Supply Current 5.5 VI = VCC or GND 80 µA IOLD Dynamic Output Current (note 1, 2) 5.5 VOLD = 1.65 V max 75 mA VOHD = 3.85 V min -75 mA 5.5 Input Leakage Current IOZ II IOHD 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω. (*) All outputs loaded. 4/10 0.6 8 74ACT374 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = t f =3 ns) Symbol Parameter T est Cond ition V CC (V) Unit (*) 5.0 10.0 11.0 ns (*) 6.0 10.0 11.0 ns (*) 6.5 10.0 11.0 ns (*) 1.5 5.0 5.0 ns 5.0 (*) 0.5 5.0 5.0 ns Hold Time Q to CK HIGH or LOW 5.0(*) -0.5 2.0 2.0 ns Maximim Clock Frequency 5.0 tPLH tPHL Propagation Delay Time CK to Q 5.0 tPZL tPZH Output Enable Time 5.0 tPLZ tPHZ Output Disable Time 5.0 tw CK Pulse Width, HIGH or LOW 5.0 ts Setup Time Q to CK HIGH or LOW th fMAX Value T A = 25 oC -40 to 85 o C Min. Typ. Max. Min . Max. (*) 100 260 85 MHz (*) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symbol Parameter Test Con dition s V CC (V) Value T A = 25 oC Min. Typ. Max. Unit -40 to 85 o C Min . Max. Output Capacitance 5.0 8 pF CIN Input Capacitance 5.0 4 pF C PD Power Dissipation Capacitance (note 1) 5.0 25 pF C OUT 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit) 5/10 74ACT374 TEST CIRCUIT TEST t PLH, tPHL SWITCH Open t PZL, tPLZ 2VCC t PZH, tPHZ Open CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT =ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74ACT374 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PULSE WIDTH 7/10 74ACT374 Plastic DIP20 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 3.3 0.130 1.34 0.053 P001J 8/10 74ACT374 SO20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8° (max.) P013L 9/10 74ACT374 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1997 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A . 10/10