Revised May 2005
74ACTQ16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
Features
The ACTQ16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is low, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state. The ACTQ16373 utilizes Fairchild’s Quiet
Series¥ technology to guarantee quiet output switching
and improved dynamic threshold performance. FACT Quiet
Series¥ features GTO¥ output control for superior performance.
■ Utilizes Fairchild FACT Quiet Series technology
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin output skew
■ Separate control logic for each byte
■ 16-bit version of the ACTQ373
■ Outputs source/sink 24 mA
■ Additional specs for Multiple Output Switching
■ Output Loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
Package Number
74ACTQ16373SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Description
74ACTQ16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
LEn
Latch Enable Input
I0–I15
Inputs
O0–O15
Outputs
FACT¥, Quiet Series¥, FACT Quiet Series¥, and GTO¥ are trademarks of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS010934
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74ACTQ16373 16-Bit Transparent Latch with 3-STATE Outputs
June 1991
74ACTQ16373
Functional Description
Truth Tables
The ACTQ16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the Dn enters the latches. In this condition the latches are
transparent, i.e., a latch output will change states each time
its D input changes. When LEn is LOW, the latches store
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Inputs
Outputs
LE1
OE1
I0–I7
O0–O7
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
(Previous)
Inputs
Outputs
LE2
OE2
I8–I15
O8–O15
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
(Previous)
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Previous previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
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2
Recommended Operating
Conditions
0.5V to 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
0.5V
VCC 0.5V
VI
VI
Supply Voltage (VCC)
20 mA
20 mA
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
20 mA
20 mA
0.5V to VCC 0.5V
50 mA
50 mA
Minimum Input Edge Rate ('V/'t)
125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
140qC
65qC to150qC
Storage Temperature
0V to VCC
40qC to 85qC
Operating Temperature (TA)
per Output Pin
Junction Temperature
0V to VCC
Output Voltage (VO)
DC Output Diode Current (IOK)
VO
4.5V to 5.5V
Input Voltage (VI)
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
IOZ
Parameter
Typ
TA
40qC to 85qC
1.5
2.0
2.0
5.5
1.5
2.0
2.0
Maximum LOW
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
4.5
3.86
3.76
5.5
4.86
4.76
Maximum LOW
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
Maximum 3-STATE
Maximum Input Leakage Current
V
0.1V
or VCC 0.1V
VOUT
0.1V
or VCC 0.1V
IOUT
50 PA
VIN
VIL or VIH
IOH
24 mA
IOH
24 mA (Note 2)
V
V
50 PA
IOUT
VIN
VIL or VIH
IOL
24 mA
V
IOL
VI
24 mA (Note 2)
VIL, VIH
PA
5.5
r 0.1
r 1.0
PA
1.5
8.0
80.0
75
mA
VOLD
1.65V Max
75
mA
VOHD
3.85V Min
5.5
IOLD
Minimum Dynamic
5.5
IOHD
Output Current (Note 3)
VOLP
Quiet Output
Maximum Overshoot
V
VOUT
r 5.0
5.5
Minimum Dynamic VOL
V
r 0.5
Maximum ICC/Input
Quiet Output
Conditions
5.5
Max Quiescent Supply Current
Maximum Dynamic VOL
Units
Guaranteed Limits
4.5
ICCT
VOHP
25qC
Minimum HIGH
ICC
VOLV
TA
(V)
Input Voltage
Leakage Current
IIN
VCC
0.6
VO
VCC, GND
VI
VCC, GND
mA
VI
VCC 2.1V
PA
VIN
5.0
0.5
0.8
V
5.0
0.5
1.0
V
5.0
VOH 1.0 VOH 1.5
V
VCC or GND
Figures 1, 2
(Note 5)(Note 6)
Figures 1, 2
(Note 5)(Note 6)
Figures 1, 2
(Note 4)(Note 6)
VOHV
Minimum VCC Droop
5.0
VOH 1.0 VOH 1.8
V
Figures 1, 2
(Note 4)(Note 6)
VIHD
Minimum HIGH Dynamic Input Voltage Level
5.0
1.7
2.0
V
(Note 4)(Note 7)
VILD
Maximum LOW Dynamic Input Voltage Level
5.0
1.2
0.8
V
(Note 4)(Note 7)
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package
Note 5: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched HIGH and one output held HIGH.
Note 7: Max number of data inputs (n) switching, (n 1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD)
3
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74ACTQ16373
Absolute Maximum Ratings(Note 1)
74ACTQ16373
AC Electrical Characteristics
Symbol
Parameter
VCC
TA
25qC
(V)
CL
50 pF
(Note 8)
tPLH
Propagation Delay
tPHL
Dn to On
tPLH
Propagation Delay
tPHL
LE to On
tPZH
Output Enable
tPZL
Delay
tPHZ
Output Disable
tPLZ
Delay
5.0
5.0
5.0
5.0
Min
Typ
40qC to 85qC
TA
CL
Max
50 pF
Min
Units
Max
3.1
5.3
7.9
3.1
8.4
2.6
4.6
7.3
2.6
7.8
3.1
5.4
7.9
3.2
8.4
2.8
4.9
7.3
2.8
7.8
2.5
4.7
7.4
2.5
7.9
2.7
4.8
7.5
2.7
8.0
2.1
5.1
7.9
2.1
8.2
2.0
4.5
7.4
2.0
7.9
ns
ns
ns
ns
Note 8: Voltage Range 5.0 is 5.0V r 0.5V.
Extended AC Electrical Characteristics
TA
VCC
Symbol
Parameter
tPLH
Propagation Delay
tPHL
Data to Output
tPLH
Propagation Delay
tPHL
Latch Enable to Output
tPZH
Output Enable
tPZL
Time
tPHZ
Output Disable
tPLZ
Time
tOSHL
Pin-to-Pin Skew
(Note 14)
HL Data to Output
tOSLH
Pin-to-Pin Skew
(Note 14)
LH Data to Output
tOST
Pin-to-Pin Skew
(Note 14)
LH/HL Data to Output
40qC to 85qC
CL
50 pF
CL
(V)
16 Outputs Switching
(Note 9)
(Note 10)
5.0V
5.0V
5.0V
5.0V
40qC to 85qC
TA
250 pF
(Note 11)
Units
Min
Max
Min
4.7
12.7
6.6
15.7
4.6
10.6
6.4
14.5
4.6
13.3
6.3
15.3
4.1
10.4
5.8
13.6
3.5
10.4
3.6
10.9
3.4
8.5
3.1
8.1
Max
ns
ns
(Note 12)
ns
(Note 13)
ns
5.0V
1.3
ns
5.0V
2.1
ns
5.0V
4.0
ns
Note 9: Voltage Range 5.0 is 5.0V r 0.5V.
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 13: The Output Disable Time is dominated by the RC Network (500:, 250 pF) on the output and has been excluded from the datasheet.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST).
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4
Symbol
Parameter
VCC
TA
25qC
(V)
CL
50 pF
(Note 15)
tS
Setup Time, HIGH or LOW,
Input to Clock
Hold Time, HIGH or LOW
tH
Input to Clock
tW
CS Pulse Width,
HIGH or LOW
TA
40qC to 85qC
CL
Units
50 pF
Guaranteed Minimum
5.0
3.0
3.0
ns
5.0
1.5
1.5
ns
5.0
4.0
4.0
ns
Note 15: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC
5.0V
CPD
Power Dissipation Capacitance
30
pF
VCC
5.0V
5
Conditions
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74ACTQ16373
AC Operating Requirements
74ACTQ16373
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/V OHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50: coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
• Measure VOLP and VOLVon the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
VILD and VIHD:
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500:.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
• Monitor one of the switching outputs using a 50: coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the
correct voltage.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
• Next decrease the input HIGH voltage level, VIH until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as V IHD.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
Note A: VOHV and VOLP are measured with respect to ground reference.
Note B: Input pulses have the following characteristics: f
tf 3 ns, skew 150 ps.
1 MHz, tr
3 ns,
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ16373
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
7
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74ACTQ16373 16-Bit Transparent Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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