ETC 74ACQ245SJX

Revised November 1999
74ACQ245 • 74ACTQ245
Quiet Series Octal Bidirectional Transceiver
with 3-STATE Inputs/Outputs
General Description
Features
The ACQ/ACTQ245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for busoriented applications. Current sinking capability is 24 mA at
both the A and B ports. The Transmit/Receive (T/R) input
determines the direction of data flow through the bidirectional transceiver. Transmit (active-HIGH) enables data
from A Ports to B Ports; Receive (active-LOW) enables
data from B Ports to A Ports. The Output Enable input,
when HIGH, disables both A and B ports by placing them in
a HIGH Z condition.
■ ICC and IOZ reduced by 50%
The ACQ/ACTQ utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24 mA
■ Faster prop delays than the standard ACT245
Ordering Code:
Order Number
Package Number
Package Description
74ACQ245SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACQ245SJ
M20D
20-Lead Small Outline Package (SOP) EIAJ TYPE II, 5.3mm Wide
74ACQ245PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACTQ245SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
M20D
20-Lead Small Outline Package (SOP) EIAJ TYPE II, 5.3mm Wide
74ACTQ245SJ
74ACTQ245QSC
MQA20
74ACTQ245MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ245PC
N20A
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010236
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74ACQ245 • 74ACTQ245 Quiet Series Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
July 1989
74ACQ245 • 74ACTQ245
Connection Diagram
Pin Descriptions
Pin Names
Description
OE
Output Enable Input
T/R
Transmit/Receive Input
A0–A7
Side A 3-STATE Inputs or 3-STATE Outputs
B0–B7
Side B 3-STATE Inputs or 3-STATE Outputs
Truth Table
Inputs
Outputs
OE
Logic Symbols
T/R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
HIGH-Z State
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
IEEE/IEC
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2
Supply Voltage (VCC)
Recommended Operating
Conditions
−0.5V to +7.0V
DC Input Diode Current (IIK)
VI = −0.5V
−20 mA
VI = VCC + 0.5V
+20 mA
DC Input Voltage (VI)
Supply Voltage (VCC)
−0.5V to VCC + 0.5V
VO = VCC + 0.5V
+20 mA
0V to VCC
−40°C to +85°C
Minimum Input Edge Rate ∆V/∆t
ACQ Devices
DC Output Source
VIN from 30% to 70% of VCC
±50 mA
VCC @ 3.0V, 4.5V, 5.5V
125 mV/ ns
Minimum Input Edge Rate ∆V/∆t
DC VCC or Ground Current
±50 mA
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
0V to VCC
Operating Temperature (TA)
−0.5V to VCC + 0.5V
or Sink Current (IO)
4.5V to 5.5V
Output Voltage (VO)
−20 mA
DC Output Voltage (VO)
2.0V to 6.0V
ACTQ
Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
ACQ
ACTQ Devices
−65°C to +150°C
VIN from 0.8V to 2.0V
DC Latch-Up Source or
VCC @ 4.5V, 5.5V
±300 mA
Sink Current
Junction Temperature (TJ)
PDIP
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
140°C
DC Electrical Characteristics for ACQ
Symbol
VIH
Parameter
Minimum HIGH Level
Input Voltage
VIL
VOH
VCC
TA = +25°C
(V)
Typ
3.0
1.5
TA = −40°C to +85°C
Guaranteed Limits
2.1
Units
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
Conditions
VOUT = 0.1V
2.1
V
or VCC − 0.1V
VOUT = 0.1V
V
or VCC − 0.1V
V
IOUT = −50 µA
VIN = VIL or VIH
VOL
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
±0.1
IOH = −12 mA
V
IOH = −24 mA
IOH = −24 mA (Note 2)
V
IOUT = 50 µA
VIN = VIL or VIH
IIN
Maximum Input
IOL = 12 mA
V
IOL = 24 mA
IOL = 24 mA (Note 2)
(Note 4)
Leakage Current
±1.0
µA
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 3)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent
(Note 4)
Supply Current
IOZT
Maximum I/O
Leakage Current
5.5
4.0
40.0
µA
5.5
±0.3
±3.0
µA
VI = VCC, GND
VIN = VCC
or GND
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
3
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74ACQ245 • 74ACTQ245
Absolute Maximum Ratings(Note 1)
74ACQ245 • 74ACTQ245
DC Electrical Characteristics for ACQ
Symbol
VOLP
Parameter
Quiet Output
Maximum Dynamic VOL
VOLV
Quiet Output
Minimum Dynamic VOL
VIHD
Minimum HIGH Level
Dynamic Input Voltage
VILD
Maximum LOW Level
Dynamic Input Voltage
(Continued)
TA = +25°C
VCC
TA = −40°C to +85°C
Units
Conditions
(V)
Typ
Guaranteed Limits
5.0
1.1
1.5
V
5.0
−0.6
−1.2
V
5.0
3.1
3.5
V
(Note 5)(Note 7)
5.0
1.9
1.5
V
(Note 5)(Note 7)
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 5)(Note 6)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Note 5: DIP package.
Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V; one output @ GND.
Note 7: Max number of Data Inputs (n) switching. (n−1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
DC Electrical Characteristics for ACTQ
Symbol
VIH
VIL
VOH
Parameter
TA = +25°C
VCC
(V)
Typ
TA = −40°C to +85°C
Guaranteed Limits
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
4.5
3.86
3.76
5.5
4.86
4.76
Units
V
V
V
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
IOUT = −50 µA
VIN = VIL or VIH
VOL
V
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
±0.1
±1.0
µA
5.5
±0.3
±3.0
µA
V
IOH = −24 mA
IOH = −24 mA (Note 8)
IOUT = 50 µA
VIN = VIL or VIH
IIN
Maximum Input Leakage Current
IOZT
Maximum 3-STATE
Leakage Current
IOL = 24 mA
IOL = 24 mA (Note 8)
VI = VCC, GND
VI = VIL, V IH
VO = VCC, GND
VI = VCC − 2.1V
ICCT
Maximum ICC/Input
5.5
1.5
mA
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 9)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent Supply Current
5.5
40.0
µA
VIN = VCC or GND
VOLP
Quiet Output
Maximum Dynamic VOL
VOLV
Quiet Output
Minimum Dynamic VOL
0.6
V
4.0
5.0
1.1
1.5
V
5.0
−0.6
−1.2
V
Figure 1, Figure 2
(Note 10)(Note 11)
Figure 1, Figure 2
(Note 10)(Note 11)
VIHD
Minimum HIGH Level Dynamic Input Voltage
5.0
1.9
2.2
V
(Note 10)(Note 12)
VILD
Maximum LOW Level Dynamic Input Voltage
5.0
1.2
0.8
V
(Note 10)(Note 12)
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: DIP package.
Note 11: Max number of outputs defined as (n). n−1 Data Inputs are driven 0V to 3V; one output @ GND.
Note 12: Max number of Data Inputs (n) switching. (n−1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD) f = 1 MHz.
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4
Symbol
Parameter
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
(Note 13)
Min
Typ
Max
Units
Min
Max
tPHL
Propagation Delay
3.3
2.0
7.5
10.0
2.0
10.5
tPLH
Data to Output
5.0
1.5
5.0
6.5
1.5
7.0
tPZL
Output Enable Time
3.3
3.0
8.5
13.0
3.0
13.5
5.0
2.0
6.0
8.5
2.0
9.0
3.3
1.0
8.5
14.5
1.0
15.0
5.0
1.0
7.5
9.5
1.0
10.0
tPZH
Output Disable Time
tPHZ
tPLZ
tOSHL
Output to Output Skew (Note 14)
3.3
1.0
1.5
1.5
tOSLH
Data to Output
5.0
0.5
1.0
1.0
ns
ns
ns
ns
Note 13: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Electrical Characteristics for ACTQ
Symbol
Parameter
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
(Note 15)
Min
Typ
Max
Min
Max
5.0
1.5
5.5
7.0
1.5
7.5
Units
tPHL
Propagation Delay
tPLH
Data to Output
tPZL, tPZH
Output Enable Time
5.0
2.0
7.0
9.0
2.0
9.5
ns
tPHZ, tPLZ
Output Disable Time
5.0
1.0
8.0
10.0
1.0
10.5
ns
tOSHL
Output to Output Skew (Note 16)
tOSLH
Data to Output
0.5
1.0
1.0
ns
5.0
ns
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
Note 16: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
CIN
Input Capacitance
CI/O
Input/Output Capacitance
CPD
Power Dissipation Capacitance
Typ
Units
4.5
pF
Conditions
VCC = OPEN
15
pF
VCC = 5.0V
80.0
pF
VCC = 5.0V
5
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74ACQ245 • 74ACTQ245
AC Electrical Characteristics for ACQ
74ACQ245 • 74ACTQ245
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
• Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
VILD and VIHD:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the
correct voltage.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as V ILD.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
• Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as V IHD.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 17: VOHV and VOLP are measured with respect to ground reference.
Note 18: Input pulses have the following characteristics: f = 1 MHz, tr =
3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACQ245 • 74ACTQ245
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
7
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74ACQ245 • 74ACTQ245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
74ACQ245 • 74ACTQ245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Package Number MQA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
9
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74ACQ245 • 74ACTQ245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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10
20-Lead Plastic Dual-In-Line (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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74ACQ245 • 74ACTQ245 Quiet Series Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)