Revised November 1999 74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The ACQ/ACTQ374 is a high-speed, low-power octal Dtype flip-flop featuring separate D-type inputs for each flipflop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. ■ ICC and IOZ reduced by 50% The ACQ/ACTQ374 utilizes FACT Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Improved latch-up immunity ■ Buffered positive edge-triggered clock ■ 3-STATE outputs drive bus lines or buffer memory address registers ■ Outputs source/sink 24 mA ■ Faster prop delays than the standard AC/ACT374 Ordering Code: Order Number Package Number Package Description 74ACQ374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACQ374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACQ374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACTQ374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACTQ374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ374QSC 74ACTQ374PC MQA20 N20A 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010238 www.fairchildsemi.com 74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs July 1989 74ACQ374 • 74ACTQ374 Logic Symbols Functional Description The ACQ/ACTQ374 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. IEEE/IEC Truth Table Inputs Dn H L X CP Outputs OE On L H L L X H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Input Voltage (VI) VO = VCC + 0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate ∆V/∆t ACQ Devices DC Output Source VIN from 30% to 70% of VCC ±50 mA VCC @ 3.0V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate ∆V/∆t DC VCC or Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to VCC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACTQ Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V ACQ ACTQ devices −65°C to +150°C VIN from 0.8V to 2.0V ±300 mA DC Latch-Up Source or Sink Current VCC @ 4.5V, 5.5V Junction Temperature (TJ) PDIP 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. 140°C DC Electrical Characteristics for ACQ Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH VCC TA = +25°C (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA V IOL = 24 mA IOL = 12 mA IOL = 24 mA (Note 2) 5.5 0.36 0.44 IIN (Note 4) Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µA IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC (Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µA VIN = VCC or GND Leakage Current 5.5 ±0.25 ±2.5 µA VI = VCC, GND Quiet Output 5.0 IOZ VI = VCC, GND VI (OE) = VIL, VIH Maximum 3-STATE VO = VCC, GND VOLP 1.1 1.5 Maximum Dynamic VOL V Figure 1, Figure 2 (Note 5)(Note 6) 3 www.fairchildsemi.com 74ACQ374 • 74ACTQ374 Absolute Maximum Ratings(Note 1) 74ACQ374 • 74ACTQ374 DC Electrical Characteristics for ACQ Symbol VOLV Parameter Quiet Output (Continued) TA = +25°C VCC (V) Typ 5.0 −0.6 TA = −40°C to +85°C Units −1.2 V Minimum HIGH Level Dynamic Input Voltage VILD Maximum LOW Level Dynamic Input Voltage Figure 1, Figure 2 (Note 5)(Note 6) Minimum Dynamic VOL VIHD Conditions Guaranteed Limits 5.0 3.1 3.5 V (Note 5)(Note 7) 5.0 1.9 1.5 V (Note 5)(Note 7) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 5: DIP Package. Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND. Note 7: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. DC Electrical Characteristics for ACTQ Symbol VIH VIL VOH Parameter TA = +25°C VCC (V) Typ TA = −40°C to +85°C Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 IOH = −24 mA (Note 8) V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN (Note 4) Maximum Input Leakage Current IOZ Maximum 3-STATE Current IOL = 24 mA (Note 8) 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.25 ±2.5 µA 1.5 mA VI = VCC, GND VI = VIL, V IH VO = VCC, GND ICCT Maximum IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 8) 5.5 −75 mA VOHD = 3.85V Min 40.0 µA ICC/Input (Note 4) ICC Maximum Quiescent (Note 4) Supply Current VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL 5.5 0.6 5.5 4.0 5.0 1.1 1.5 V 5.0 −0.6 −1.2 V VI = VCC − 2.1V VIN = VCC or GND Figure 1, Figure 2 (Note 10)(Note 11) Figure 1, Figure 2 (Note 10)(Note 11) VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 10)(Note 12) VILD Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 10)(Note 12) Note 8: All outputs loaded; thresholds on input associated with output under test. Note 9: Maximum test duration 2.0 ms, one output loaded at a time. Note 10: DIP package. Note 11: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND Note 12: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 4 Symbol fMAX Parameter VCC TA = +25°C (V) CL = 50 pF Typ TA = −40°C to +85°C CL = 50 pF (Note 13) Min Max Min Maximum Clock 3.3 75 70 Frequency 5.0 90 85 MHz tPLH Propagation Delay 3.3 3.0 9.5 13.0 3.0 13.5 tPHL CP to On 5.0 2.0 6.5 8.5 2.0 9.0 tPZL Output Enable Time 3.3 3.0 9.5 13.0 3.0 13.5 5.0 2.0 6.5 8.5 2.0 9.0 3.3 1.0 9.5 14.5 1.0 15.0 5.0 1.0 8.0 9.5 1.0 10.0 tPZH tPHZ Output Disable Time tPLZ Units Max tOSHL Output to Output Skew (Note 14) 3.3 1.0 1.5 1.5 tOSLH CP to On 5.0 0.5 1.0 1.0 ns ns ns ns Note 13: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements for ACQ Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 15) tS tH tW Typ TA = −40°C to +85°C CL = 50 pF Units Guaranteed Minimum Setup Time, HIGH or LOW 3.3 0 3.0 3.0 Dn to CP 5.0 0 3.0 3.0 Hold Time, HIGH or LOW 3.3 0 1.5 1.5 Dn to CP 5.0 2.0 1.5 1.5 CP Pulse Width, 3.3 2.0 4.0 4.0 HIGH or LOW 5.0 2.0 4.0 4.0 ns ns ns Note 15: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V AC Electrical Characteristics for ACTQ Symbol fMAX Parameter Maximum Clock Frequency VCC TA = +25°C (V) CL = 50 pF (Note 16) Min Typ 5.0 85 5.0 2.0 7.0 TA = −40°C to +85°C CL = 50 pF Max Min Units Max 80 MHz tPLH Propagation Delay tPHL CP to On tPZL tPZH Output Enable Time 5.0 2.0 7.5 9.0 2.0 9.5 ns tPHZ tPLZ Output Disable Time 5.0 1.0 8.0 10.0 1.0 10.5 ns tOSHL Output to Output Skew (Note 17) tOSLH CP to On 0.5 1.0 1.0 ns 5.0 9.0 2.0 9.5 ns Note 16: Voltage Range 5.0 is 5.0V ± 0.5V Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. 5 www.fairchildsemi.com 74ACQ374 • 74ACTQ374 AC Electrical Characteristics for ACQ 74ACQ374 • 74ACTQ374 AC Operating Requirements for ACTQ Symbol tS Parameter Setup Time, HIGH or LOW Dn to CP tH Hold Time, HIGH or LOW Dn to CP CP Pulse Width, tH HIGH or LOW VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum 5.0 0 3.0 3.0 ns 5.0 0 1.5 1.5 ns 5.0 2.0 4.0 4.0 ns Note 18: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 42.0 pF VCC = 5.0V www.fairchildsemi.com Units (Note 18) 6 Conditions The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. Note 19: VOHV and VOLP are measured with respect to ground reference. Note 20: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms FIGURE 2. Simultaneous Switching Test Circuit 7 www.fairchildsemi.com 74ACQ374 • 74ACTQ374 FACT Noise Characteristics 74ACQ374 • 74ACTQ374 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B www.fairchildsemi.com 8 74ACQ374 • 74ACTQ374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 9 www.fairchildsemi.com 74ACQ374 • 74ACTQ374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide Package Number MQA20 www.fairchildsemi.com 10 74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com