Revised August 1999 74F323 Octal Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins General Description Features The 74F323 is an 8-bit universal shift/storage register with 3-STATE outputs. Its function is similar to the 74F299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right and parallel load. ■ Common parallel I/O for reduced pin count ■ Additional serial inputs and outputs for expansion ■ Four operating modes: shift left, shift right, load and store ■ 3-STATE outputs for bus-oriented applications Ordering Code: Order Number Package Number Package Description 74F323SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F323PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009517 www.fairchildsemi.com 74F323 Octal Universal Shift/Storage Register April 1988 74F323 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA DS0 Serial Data Input for Right Shift 1.0/1.0 20 µA/−0.6 mA DS7 Serial Data Input for Left Shift 1.0/1.0 20 µA/−0.6 mA S0, S1 Mode Select Inputs 1.0/2.0 20 µA/−1.2 mA SR Synchronous Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA OE1, OE2 3-STATE Output Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA I/O0–I/O7 Multiplexed Parallel Data Inputs 3.5/1.083 70 µA/−0.65 mA 3-STATE Parallel Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) Q0, Q7 Serial Outputs 50/33.3 −1 mA/20 mA Logic Diagram Functional Description The 74F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE 1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. Mode Select Table Inputs SR S1 Response S0 CP L X X H H H H L H H H L H L L X Synchronous Reset; Q0–Q7 = LOW Parallel Load; I/On → Qn Shift Right; DS0 → Q0, Q0 → Q1, etc. Shift Left; DS7 → Q7, Q7 → Q6, etc. Hold H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH transition Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 5% VCC 2.7 5% VCC 2.7 VOL 2.0 Units VIH V 0.5 Voltage 10% VCC 0.5 Input HIGH Current Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown (I/O) ICEX Output HIGH Leakage Current VID Input Leakage Test IOD IIN = −18 mA Min IOH = −3 mA (I/On) IOH = −1 mA (Q0, Q7) Output Leakage Input LOW Current −60 V Min IOL = 20 mA (Q0, Q7) IOL = 24 mA (I/On) 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V (Non I/O Inputs) 0.5 mA Max VIN = 5.5V (I/O Inputs) 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V (CP, DS0, DS7, SR, OE1, OE2) −1.2 mA Max VIN = 0.5V (S0, S1) −150 mA Max VOUT = 0V 4.75 Circuit Current IIL Recognized as a LOW Signal Min IOH = −3 mA (I/On) 10% VCC IBVI Conditions Recognized as a HIGH Signal IOH = −1 mA (Q0, Q7) Output LOW IIH VCC V IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded IOS Output Short-Circuit Current IZZ Bus Drainage Test 500 µA 0.0V VOUT = 5.25V ICCH Power Supply Current 68 95 mA Max VO = HIGH ICCL Power Supply Current 68 95 mA Max VO = LOW ICCZ Power Supply Current 68 95 mA Max VO = HIGH Z 3 www.fairchildsemi.com 74F323 Absolute Maximum Ratings(Note 1) 74F323 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Input Frequency 70 100 tPLH Propagation Delay 4.0 7.0 tPHL CP to Q0 or Q7 4.5 6.5 8.0 4.5 8.5 tPLH Propagation Delay 3.5 7.0 9.0 3.5 10.0 tPHL CP to I/On 4.0 8.5 9.0 4.0 10.0 tPZH Output Enable Time 3.5 6.0 8.0 3.5 9.0 4.0 7.0 10.0 4.0 11.0 Output Disable Time 2.0 4.5 6.0 2.0 7.0 1.0 4.0 5.5 1.0 6.5 tPZH Output Enable Time 3.5 9.0 3.5 10.0 tPZL Sn to I/On 4.0 10.0 4.0 11.0 tPHZ Output Disable Time 2.5 6.0 2.5 7.0 tPLZ Sn to I/On 1.0 5.5 1.5 6.5 tPZL tPHZ tPLZ Max Min Max 70 8.0 4.0 Units MHz 8.5 ns ns ns ns AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 8.5 8.5 tS(L) S0 or S1 to CP 8.5 8.5 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) S0 or S1 to CP 0 0 tS(H) Setup Time, HIGH or LOW 5.0 5.0 tS(L) I/On, DS0, DS 7 to CP 5.0 5.0 tH(H) Hold Time, HIGH or LOW 2.0 2.0 tH(L) I/On, DS0, DS 7 to CP 2.0 2.0 tS(H) Setup Time, HIGH or LOW 10.0 10.0 tS(L) SR to CP 10.0 10.0 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) SR to CP 0 0 tW(H) CP Pulse Width 5.0 5.0 tW(L) HIGH or LOW 5.0 5.0 www.fairchildsemi.com 4 Units Max ns ns ns ns 74F323 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com 74F323 Octal Universal Shift/Storage Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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