INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC4050 Hex high-to-low level shifter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Hex high-to-low level shifter 74HC4050 therefore be used. This feature enables the non-inverting buffers to be used as logic level translators, which will convert high level logic to low level logic, while operating from a low voltage power supply. For example 15 V logic (“4000B series”) can be converted down to 2 V logic. FEATURES • Output capability: standard • ICC category: SSI GENERAL DESCRIPTION The actual input switch level remains related to the VCC and is the same as mentioned in the family characteristics. The 74HC4050 is a high-speed Si-gate CMOS device and is pin compatible with the “4050” of the “4000B” series. It is specified in compliance with JEDEC standard no. 7A. APPLICATIONS • Converting 15 V logic (“4000B” series) down to 2 V logic. The 74HC4050 provides six non-inverting buffers with a modified input protection structure, which has no diode connected to VCC. Input voltages of up to 15 V may QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL / tPLH propagation delay nA to nY CI input capacitance CPD power dissipation capacitance per buffer CL = 15 pF; VCC = 5 V note 1 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 7 ns 3.5 pF 14 pF Philips Semiconductors Product specification Hex high-to-low level shifter 74HC4050 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 VCC positive supply voltage 2, 4, 6, 10, 12, 15 1Y to 6Y data outputs 3, 5, 7, 9, 11, 14 1A to 6A data inputs 8 GND ground (0 V) 13, 16 n.c. not connected Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Hex high-to-low level shifter 74HC4050 Fig.5 Fig.4 Functional diagram. Fig.6 Logic diagram (one level shifter). FUNCTION TABLE (1) INPUT OUTPUT nA nY L H L H Note 1. H = HIGH voltage level L = LOW voltage level December 1990 4 Input protection for HC4050. Single sided thick oxide field effect metal gate transistor as input protection. Philips Semiconductors Product specification Hex high-to-low level shifter 74HC4050 RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER MIN. MAX. UNIT VCC DC supply voltage −0.5 +7 V VIK DC input voltage range −0.5 +16 V −IIK DC input diode current 20 mA ±IOK DC output diode current 20 mA ±IO DC output source or sink current - standard outputs ±ICC; ±IGND DC VCC or GND current for types with: - standard outputs Tstg storage temperature range CONDITIONS for VI < −0.5 V for VO < −0.5 V or VO > VCC + 0.5 V for −0.5 V < VO < VCC + 0.5 V −65 25 mA 50 mA +150 °C for temperature range: −40 to +125 °C 74HC power dissipation per package Ptot plastic DIL 750 mW above +70 °C: derate linearly with 12 mW/K plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K RECOMMENDED OPERATING CONDITIONS 74HC SYMBOL PARAMETER UNIT min. typ. VCC DC supply voltage 2.0 5.0 6.0 V GND − VI DC input voltage range 15 V Tamb operating ambient temperature range −40 +85 °C Tamb operating ambient temperature range −40 +125 °C input rise and fall times 1000 500 400 650 1000 tr, tf December 1990 6.0 5 CONDITIONS max. ns see DC and AC characteristics VCC = 2.0 V; VIN = 2.0 V VCC = 4.5 V; VIN = 4.5 V VCC = 6.0 V; VIN = 6.0 V VCC = 6.0 V; VIN = 10.0 V VCC = 6.0 V; VIN = 15.0 V Philips Semiconductors Product specification Hex high-to-low level shifter 74HC4050 DC CHARACTERISTICS FOR 74HC Voltages are referenced to GND (ground = 0 V) Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER −40 to +85 +25 −40 to +125 min. typ. max. min. max. min. VIH HIGH level input voltage 1.5 1.3 3.15 2.4 4.2 3.1 1.5 3.15 4.2 VIL LOW level input voltage 0.7 1.8 2.3 VOH HIGH level output voltage - all outputs 1.9 4.4 5.9 VOH HIGH level output voltage - standard outputs 3.98 5.48 VOL LOW level output voltage - all outputs 0.1 0.1 0.1 0.1 0.1 0.1 VOL LOW level output voltage - standard outputs 0.26 0.26 ± II input leakage current 0.1 0.5 1.35 1.8 2.0 4.5 6.0 0.5 1.35 1.8 V 2.0 4.5 6.0 V 2.0 4.5 6.0 quiescent supply current December 1990 OTHER 1.9 4.4 5.9 1.9 4.4 5.9 V 2.0 4.5 6.0 VIH or VIL −IO = 20 µA −IO = 20 µA −IO = 20 µA 3.84 5.34 3.7 5.2 V 4.5 6.0 VIH or VIL −IO = 4.0 mA −IO = 5.2 mA 0.1 0.1 0.1 V 2.0 4.5 6.0 VIH or VIL IO = 20 µA IO = 20 µA IO = 20 µA 0.33 0.33 0.4 0.4 V 4.5 6.0 VIH or VIL IO = 4.0 mA IO = 5.2 mA 1.0 1.0 µA 6.0 ICC VI max. 1.5 3.15 4.2 0.5 1.35 1.8 UNIT V CC (V) VCC or GND 0.5 5.0 5.0 µA 2.0 to 6.0 15 V 2.0 20.0 40.0 µA 6.0 15 V or GND 6 Philips Semiconductors Product specification Hex high-to-low level shifter 74HC4050 AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS UNIT 74HC SYMBOL PARAMETER −40 to +85 +25 min. typ. max. min. max. VCC WAVEFORMS (V) −40 to +125 min. max. tPHL/ tPLH propagation delay nA to nY 25 9 7 85 17 14 105 21 18 130 26 22 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.7 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7