INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT583 4-bit full adder with fast carry Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Mar 31 Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 The “583” generates the decimal sum outputs (∑0 to ∑3) and a carry output (Cn+4) if the sum is greater than 9. FEATURES • Adds two decimal numbers If an addition of two BCD numbers produce a number greater than 9, a valid BCD number and a carry will result. For input values larger than 9, the number is converted from binary to BCD. Binary to BCD conversion occurs by grounding one set of inputs, An or Bn and applying a 4-bit binary number to the other set of inputs. If the input is between 0 and 9, a BCD number occurs at the output. If the binary input falls between 10 and 15, a carry term is generated. Both the carry term and the sum are the BCD equivalent of the binary input. Converting binary numbers greater than 16 may be achieved by cascading “583s”. • Full internal look-ahead • Fast ripple carry for economical expansion • Output capability: standard driver • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT583 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JECEC standard no. 7A. See the “283” for the binary version. The 74HC/HCT583 are high-speed 4-bit BCD full adders with internal carry look-ahead. They accept two 4-bit decimal numbers (A0 to A3 and B0 to B3) and a carry input (CIN). QUICK REFERENCE DATA GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V CIN to Cn+4 20 23 ns An, Bn to Cn+4 23 27 ns 3.5 3.5 pF 116 120 pF CI input capacitance CPD power dissipation capacitance per package notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V 1998 Mar 31 HCT 2 Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION 74HC583 DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HC583 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT583 DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HCT583 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 5 CIN carry input 6 Cn+4 carry output 8 GND ground (0 V) 11, 10, 7, 9 ∑0 to ∑3 12, 1, 2, 3 handbook, halfpage B1 1 16 VCC B2 2 15 A2 sum outputs B3 3 14 A1 B0 to B3 B operand inputs A3 4 13, 14, 15, 4 A0 to A3 A operand inputs CIN 5 12 B0 16 VCC positive supply voltage Cn + 4 6 11 ∑0 ∑2 7 10 ∑1 13 A0 583 GND 8 ∑3 9 MGM851 Fig.1 Pin configuration. handbook, halfpage 13 0 14 handbook, halfpage A0 13 CIN B0 12 A1 14 A2 B1 1 15 A3 B2 2 4 5 4 Cn + 4 12 10 3 ∑ ∑0 10 ∑1 7 ∑2 3 9 ∑3 3 5 9 Q 2 MGM852 7 0 1 11 11 0 3 6 P 15 B3 ∑ (BCD) 3 C1 C0 6 MGM853 Fig.2 Logic symbol. 1998 Mar 31 Fig.3 IEC logic symbol. 3 Philips Semiconductors Product specification 4-bit full adder with fast carry handbook, halfpage 74HC/HCT583 A0 13 B0 A1 B1 A2 12 14 1 15 B2 A3 B3 2 4 3 CIN 5 6 Cn + 4 11 10 7 9 ∑0 ∑1 ∑2 ∑3 Fig.4 Functional diagram. 1998 Mar 31 4 MGM854 Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 handbook, full pagewidth S0 B0 A0 S1 B1 A1 B2 S2 A2 B3 S3 A3 CIN Cn + 4 MGM856 Fig.5 Logic diagram. 1998 Mar 31 5 Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH 1998 Mar 31 propagation delay CIN to ∑0 propagation delay CIN to ∑1 propagation delay CIN to ∑2 propagation delay CIN to ∑3 propagation delay An or Bn to ∑0 propagation delay An or Bn to ∑1 propagation delay An or Bn to ∑2 propagation delay An or Bn to ∑3 propagation delay CIN to Cn+4 propagation delay An to Cn+4 typ. max. −40 to +85 −40 to +125 min. min. max. UNIT V WAVEFORMS CC (V) max. 50 155 195 235 18 31 39 47 4.5 14 26 33 40 6.0 113 350 440 525 41 70 88 105 4.5 33 60 75 90 6.0 100 305 380 460 36 61 76 92 4.5 29 52 65 78 6.0 110 340 425 510 40 68 85 102 4.5 32 58 72 87 6.0 50 155 195 235 18 31 39 47 4.5 14 26 33 40 6.0 120 365 455 550 43 73 91 110 4.5 34 62 77 94 6.0 105 325 405 490 38 65 81 98 4.5 30 55 69 83 6.0 116 355 445 535 42 71 89 107 34 60 76 91 63 195 245 295 23 39 49 59 18 33 42 50 72 220 275 330 26 44 55 66 4.5 21 37 47 56 6.0 6 ns ns ns ns ns ns ns ns 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 4.5 6.0 ns 2.0 Fig.6 4.5 6.0 ns 2.0 Fig.6 Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH tTHL/ tTLH propagation delay Bn to Cn+4 output transition time standard outputs typ. max. −40 to +85 −40 to +125 min. min. max. WAVEFORMS UNIT V CC (V) max. 74 230 290 345 27 46 58 69 ns 4.5 22 39 49 59 6.0 19 75 95 110 7 15 19 22 4.5 6 13 16 19 6.0 ns 2.0 2.0 Fig.6 Fig.6 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT An, Bn 0.4 CIN 1.5 1998 Mar 31 7 Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. typ. max. −40 to +85 −40 to +125 min. min. max. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay CIN to ∑0 20 34 43 51 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CIN to ∑1 40 68 85 102 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CIN to ∑2 38 65 81 98 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CIN to ∑3 38 65 81 98 ns 4.5 Fig.6 tPHL/ tPLH propagation delay An or Bn to ∑0 22 37 46 56 ns 4.5 Fig.6 tPHL/ tPLH propagation delay An or Bn to ∑1 43 73 91 110 ns 4.5 Fig.6 tPHL/ tPLH propagation delay An or Bn to ∑2 40 68 85 102 ns 4.5 Fig.6 tPHL/ tPLH propagation delay An or Bn to ∑3 41 70 88 105 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CIN to Cn+4 27 46 58 69 ns 4.5 Fig.6 tPHL/ tPLH propagation delay An to Cn+4 31 53 66 80 ns 4.5 Fig.6 tPHL/ tPLH propagation delay Bn to Cn+4 30 51 64 77 ns 4.5 Fig.6 tTHL/ tTLH output transition time standard outputs 7 15 19 22 ns 4.5 Fig.6 1998 Mar 31 8 Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 AC WAVEFORMS book, full pagewidth CIN, An, Bn INPUT VM(1) tPHL ∑n, Cn + 4 tPLH VM(1) OUTPUT tTHL (1) tTLH MGM855 HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the inputs (CIN, An, Bn) to the outputs (∑n, Cn+4) propagation delays and the output transition times. 1998 Mar 31 9 Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.7 1.40 1.14 0.53 0.38 0.32 0.23 21.8 21.4 6.48 6.20 2.54 7.62 3.9 3.4 8.25 7.80 9.5 8.3 0.254 2.2 inches 0.19 0.020 0.15 0.055 0.045 0.021 0.015 0.013 0.009 0.86 0.84 0.26 0.24 0.10 0.30 0.15 0.13 0.32 0.31 0.37 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT38-1 050G09 MO-001AE 1998 Mar 31 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-10-02 95-01-19 10 Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.050 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 inches 0.244 0.041 0.228 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07S MS-012AC 1998 Mar 31 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 11 o 8 0o Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP • The longitudinal axis of the package footprint must be parallel to the solder flow. SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1998 Mar 31 12 Philips Semiconductors Product specification 4-bit full adder with fast carry 74HC/HCT583 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Mar 31 13